hw/misc: Add npcm7xx random number generator
[qemu.git] / hw / arm / npcm7xx.c
1 /*
2 * Nuvoton NPCM7xx SoC family.
3 *
4 * Copyright 2020 Google LLC
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 */
16
17 #include "qemu/osdep.h"
18
19 #include "exec/address-spaces.h"
20 #include "hw/arm/boot.h"
21 #include "hw/arm/npcm7xx.h"
22 #include "hw/char/serial.h"
23 #include "hw/loader.h"
24 #include "hw/misc/unimp.h"
25 #include "hw/qdev-properties.h"
26 #include "qapi/error.h"
27 #include "qemu/units.h"
28 #include "sysemu/sysemu.h"
29
30 /*
31 * This covers the whole MMIO space. We'll use this to catch any MMIO accesses
32 * that aren't handled by any device.
33 */
34 #define NPCM7XX_MMIO_BA (0x80000000)
35 #define NPCM7XX_MMIO_SZ (0x7ffd0000)
36
37 /* OTP key storage and fuse strap array */
38 #define NPCM7XX_OTP1_BA (0xf0189000)
39 #define NPCM7XX_OTP2_BA (0xf018a000)
40
41 /* Core system modules. */
42 #define NPCM7XX_L2C_BA (0xf03fc000)
43 #define NPCM7XX_CPUP_BA (0xf03fe000)
44 #define NPCM7XX_GCR_BA (0xf0800000)
45 #define NPCM7XX_CLK_BA (0xf0801000)
46 #define NPCM7XX_MC_BA (0xf0824000)
47 #define NPCM7XX_RNG_BA (0xf000b000)
48
49 /* Internal AHB SRAM */
50 #define NPCM7XX_RAM3_BA (0xc0008000)
51 #define NPCM7XX_RAM3_SZ (4 * KiB)
52
53 /* Memory blocks at the end of the address space */
54 #define NPCM7XX_RAM2_BA (0xfffd0000)
55 #define NPCM7XX_RAM2_SZ (128 * KiB)
56 #define NPCM7XX_ROM_BA (0xffff0000)
57 #define NPCM7XX_ROM_SZ (64 * KiB)
58
59 /* Clock configuration values to be fixed up when bypassing bootloader */
60
61 /* Run PLL1 at 1600 MHz */
62 #define NPCM7XX_PLLCON1_FIXUP_VAL (0x00402101)
63 /* Run the CPU from PLL1 and UART from PLL2 */
64 #define NPCM7XX_CLKSEL_FIXUP_VAL (0x004aaba9)
65
66 /*
67 * Interrupt lines going into the GIC. This does not include internal Cortex-A9
68 * interrupts.
69 */
70 enum NPCM7xxInterrupt {
71 NPCM7XX_UART0_IRQ = 2,
72 NPCM7XX_UART1_IRQ,
73 NPCM7XX_UART2_IRQ,
74 NPCM7XX_UART3_IRQ,
75 NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */
76 NPCM7XX_TIMER1_IRQ,
77 NPCM7XX_TIMER2_IRQ,
78 NPCM7XX_TIMER3_IRQ,
79 NPCM7XX_TIMER4_IRQ,
80 NPCM7XX_TIMER5_IRQ, /* Timer Module 1 */
81 NPCM7XX_TIMER6_IRQ,
82 NPCM7XX_TIMER7_IRQ,
83 NPCM7XX_TIMER8_IRQ,
84 NPCM7XX_TIMER9_IRQ,
85 NPCM7XX_TIMER10_IRQ, /* Timer Module 2 */
86 NPCM7XX_TIMER11_IRQ,
87 NPCM7XX_TIMER12_IRQ,
88 NPCM7XX_TIMER13_IRQ,
89 NPCM7XX_TIMER14_IRQ,
90 NPCM7XX_WDG0_IRQ = 47, /* Timer Module 0 Watchdog */
91 NPCM7XX_WDG1_IRQ, /* Timer Module 1 Watchdog */
92 NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */
93 };
94
95 /* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */
96 #define NPCM7XX_NUM_IRQ (160)
97
98 /* Register base address for each Timer Module */
99 static const hwaddr npcm7xx_tim_addr[] = {
100 0xf0008000,
101 0xf0009000,
102 0xf000a000,
103 };
104
105 /* Register base address for each 16550 UART */
106 static const hwaddr npcm7xx_uart_addr[] = {
107 0xf0001000,
108 0xf0002000,
109 0xf0003000,
110 0xf0004000,
111 };
112
113 /* Direct memory-mapped access to SPI0 CS0-1. */
114 static const hwaddr npcm7xx_fiu0_flash_addr[] = {
115 0x80000000, /* CS0 */
116 0x88000000, /* CS1 */
117 };
118
119 /* Direct memory-mapped access to SPI3 CS0-3. */
120 static const hwaddr npcm7xx_fiu3_flash_addr[] = {
121 0xa0000000, /* CS0 */
122 0xa8000000, /* CS1 */
123 0xb0000000, /* CS2 */
124 0xb8000000, /* CS3 */
125 };
126
127 static const struct {
128 const char *name;
129 hwaddr regs_addr;
130 int cs_count;
131 const hwaddr *flash_addr;
132 } npcm7xx_fiu[] = {
133 {
134 .name = "fiu0",
135 .regs_addr = 0xfb000000,
136 .cs_count = ARRAY_SIZE(npcm7xx_fiu0_flash_addr),
137 .flash_addr = npcm7xx_fiu0_flash_addr,
138 }, {
139 .name = "fiu3",
140 .regs_addr = 0xc0000000,
141 .cs_count = ARRAY_SIZE(npcm7xx_fiu3_flash_addr),
142 .flash_addr = npcm7xx_fiu3_flash_addr,
143 },
144 };
145
146 static void npcm7xx_write_board_setup(ARMCPU *cpu,
147 const struct arm_boot_info *info)
148 {
149 uint32_t board_setup[] = {
150 0xe59f0010, /* ldr r0, clk_base_addr */
151 0xe59f1010, /* ldr r1, pllcon1_value */
152 0xe5801010, /* str r1, [r0, #16] */
153 0xe59f100c, /* ldr r1, clksel_value */
154 0xe5801004, /* str r1, [r0, #4] */
155 0xe12fff1e, /* bx lr */
156 NPCM7XX_CLK_BA,
157 NPCM7XX_PLLCON1_FIXUP_VAL,
158 NPCM7XX_CLKSEL_FIXUP_VAL,
159 };
160 int i;
161
162 for (i = 0; i < ARRAY_SIZE(board_setup); i++) {
163 board_setup[i] = tswap32(board_setup[i]);
164 }
165 rom_add_blob_fixed("board-setup", board_setup, sizeof(board_setup),
166 info->board_setup_addr);
167 }
168
169 static void npcm7xx_write_secondary_boot(ARMCPU *cpu,
170 const struct arm_boot_info *info)
171 {
172 /*
173 * The default smpboot stub halts the secondary CPU with a 'wfi'
174 * instruction, but the arch/arm/mach-npcm/platsmp.c in the Linux kernel
175 * does not send an IPI to wake it up, so the second CPU fails to boot. So
176 * we need to provide our own smpboot stub that can not use 'wfi', it has
177 * to spin the secondary CPU until the first CPU writes to the SCRPAD reg.
178 */
179 uint32_t smpboot[] = {
180 0xe59f2018, /* ldr r2, bootreg_addr */
181 0xe3a00000, /* mov r0, #0 */
182 0xe5820000, /* str r0, [r2] */
183 0xe320f002, /* wfe */
184 0xe5921000, /* ldr r1, [r2] */
185 0xe1110001, /* tst r1, r1 */
186 0x0afffffb, /* beq <wfe> */
187 0xe12fff11, /* bx r1 */
188 NPCM7XX_SMP_BOOTREG_ADDR,
189 };
190 int i;
191
192 for (i = 0; i < ARRAY_SIZE(smpboot); i++) {
193 smpboot[i] = tswap32(smpboot[i]);
194 }
195
196 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
197 NPCM7XX_SMP_LOADER_START);
198 }
199
200 static struct arm_boot_info npcm7xx_binfo = {
201 .loader_start = NPCM7XX_LOADER_START,
202 .smp_loader_start = NPCM7XX_SMP_LOADER_START,
203 .smp_bootreg_addr = NPCM7XX_SMP_BOOTREG_ADDR,
204 .gic_cpu_if_addr = NPCM7XX_GIC_CPU_IF_ADDR,
205 .write_secondary_boot = npcm7xx_write_secondary_boot,
206 .board_id = -1,
207 .board_setup_addr = NPCM7XX_BOARD_SETUP_ADDR,
208 .write_board_setup = npcm7xx_write_board_setup,
209 };
210
211 void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc)
212 {
213 NPCM7xxClass *sc = NPCM7XX_GET_CLASS(soc);
214
215 npcm7xx_binfo.ram_size = machine->ram_size;
216 npcm7xx_binfo.nb_cpus = sc->num_cpus;
217
218 arm_load_kernel(&soc->cpu[0], machine, &npcm7xx_binfo);
219 }
220
221 static void npcm7xx_init_fuses(NPCM7xxState *s)
222 {
223 NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s);
224 uint32_t value;
225
226 /*
227 * The initial mask of disabled modules indicates the chip derivative (e.g.
228 * NPCM750 or NPCM730).
229 */
230 value = tswap32(nc->disabled_modules);
231 npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE,
232 sizeof(value));
233 }
234
235 static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
236 {
237 return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
238 }
239
240 static void npcm7xx_init(Object *obj)
241 {
242 NPCM7xxState *s = NPCM7XX(obj);
243 int i;
244
245 for (i = 0; i < NPCM7XX_MAX_NUM_CPUS; i++) {
246 object_initialize_child(obj, "cpu[*]", &s->cpu[i],
247 ARM_CPU_TYPE_NAME("cortex-a9"));
248 }
249
250 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
251 object_initialize_child(obj, "gcr", &s->gcr, TYPE_NPCM7XX_GCR);
252 object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr),
253 "power-on-straps");
254 object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK);
255 object_initialize_child(obj, "otp1", &s->key_storage,
256 TYPE_NPCM7XX_KEY_STORAGE);
257 object_initialize_child(obj, "otp2", &s->fuse_array,
258 TYPE_NPCM7XX_FUSE_ARRAY);
259 object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
260 object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG);
261
262 for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
263 object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
264 }
265
266 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu));
267 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) {
268 object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],
269 TYPE_NPCM7XX_FIU);
270 }
271 }
272
273 static void npcm7xx_realize(DeviceState *dev, Error **errp)
274 {
275 NPCM7xxState *s = NPCM7XX(dev);
276 NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s);
277 int i;
278
279 if (memory_region_size(s->dram) > NPCM7XX_DRAM_SZ) {
280 error_setg(errp, "%s: NPCM7xx cannot address more than %" PRIu64
281 " MiB of DRAM", __func__, NPCM7XX_DRAM_SZ / MiB);
282 return;
283 }
284
285 /* CPUs */
286 for (i = 0; i < nc->num_cpus; i++) {
287 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
288 arm_cpu_mp_affinity(i, NPCM7XX_MAX_NUM_CPUS),
289 &error_abort);
290 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
291 NPCM7XX_GIC_CPU_IF_ADDR, &error_abort);
292 object_property_set_bool(OBJECT(&s->cpu[i]), "reset-hivecs", true,
293 &error_abort);
294
295 /* Disable security extensions. */
296 object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", false,
297 &error_abort);
298
299 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
300 return;
301 }
302 }
303
304 /* A9MPCORE peripherals. Can only fail if we pass bad parameters here. */
305 object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", nc->num_cpus,
306 &error_abort);
307 object_property_set_int(OBJECT(&s->a9mpcore), "num-irq", NPCM7XX_NUM_IRQ,
308 &error_abort);
309 sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), &error_abort);
310 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, NPCM7XX_CPUP_BA);
311
312 for (i = 0; i < nc->num_cpus; i++) {
313 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i,
314 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
315 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + nc->num_cpus,
316 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
317 }
318
319 /* L2 cache controller */
320 sysbus_create_simple("l2x0", NPCM7XX_L2C_BA, NULL);
321
322 /* System Global Control Registers (GCR). Can fail due to user input. */
323 object_property_set_int(OBJECT(&s->gcr), "disabled-modules",
324 nc->disabled_modules, &error_abort);
325 object_property_add_const_link(OBJECT(&s->gcr), "dram-mr", OBJECT(s->dram));
326 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) {
327 return;
328 }
329 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gcr), 0, NPCM7XX_GCR_BA);
330
331 /* Clock Control Registers (CLK). Cannot fail. */
332 sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_abort);
333 sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM7XX_CLK_BA);
334
335 /* OTP key storage and fuse strap array. Cannot fail. */
336 sysbus_realize(SYS_BUS_DEVICE(&s->key_storage), &error_abort);
337 sysbus_mmio_map(SYS_BUS_DEVICE(&s->key_storage), 0, NPCM7XX_OTP1_BA);
338 sysbus_realize(SYS_BUS_DEVICE(&s->fuse_array), &error_abort);
339 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM7XX_OTP2_BA);
340 npcm7xx_init_fuses(s);
341
342 /* Fake Memory Controller (MC). Cannot fail. */
343 sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort);
344 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA);
345
346 /* Timer Modules (TIM). Cannot fail. */
347 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
348 for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
349 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->tim[i]);
350 int first_irq;
351 int j;
352
353 sysbus_realize(sbd, &error_abort);
354 sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);
355
356 first_irq = NPCM7XX_TIMER0_IRQ + i * NPCM7XX_TIMERS_PER_CTRL;
357 for (j = 0; j < NPCM7XX_TIMERS_PER_CTRL; j++) {
358 qemu_irq irq = npcm7xx_irq(s, first_irq + j);
359 sysbus_connect_irq(sbd, j, irq);
360 }
361
362 /* IRQ for watchdogs */
363 sysbus_connect_irq(sbd, NPCM7XX_TIMERS_PER_CTRL,
364 npcm7xx_irq(s, NPCM7XX_WDG0_IRQ + i));
365 /* GPIO that connects clk module with watchdog */
366 qdev_connect_gpio_out_named(DEVICE(&s->tim[i]),
367 NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 0,
368 qdev_get_gpio_in_named(DEVICE(&s->clk),
369 NPCM7XX_WATCHDOG_RESET_GPIO_IN, i));
370 }
371
372 /* UART0..3 (16550 compatible) */
373 for (i = 0; i < ARRAY_SIZE(npcm7xx_uart_addr); i++) {
374 serial_mm_init(get_system_memory(), npcm7xx_uart_addr[i], 2,
375 npcm7xx_irq(s, NPCM7XX_UART0_IRQ + i), 115200,
376 serial_hd(i), DEVICE_LITTLE_ENDIAN);
377 }
378
379 /* Random Number Generator. Cannot fail. */
380 sysbus_realize(SYS_BUS_DEVICE(&s->rng), &error_abort);
381 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM7XX_RNG_BA);
382
383 /*
384 * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
385 * specified, but this is a programming error.
386 */
387 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu));
388 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) {
389 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->fiu[i]);
390 int j;
391
392 object_property_set_int(OBJECT(sbd), "cs-count",
393 npcm7xx_fiu[i].cs_count, &error_abort);
394 sysbus_realize(sbd, &error_abort);
395
396 sysbus_mmio_map(sbd, 0, npcm7xx_fiu[i].regs_addr);
397 for (j = 0; j < npcm7xx_fiu[i].cs_count; j++) {
398 sysbus_mmio_map(sbd, j + 1, npcm7xx_fiu[i].flash_addr[j]);
399 }
400 }
401
402 /* RAM2 (SRAM) */
403 memory_region_init_ram(&s->sram, OBJECT(dev), "ram2",
404 NPCM7XX_RAM2_SZ, &error_abort);
405 memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM2_BA, &s->sram);
406
407 /* RAM3 (SRAM) */
408 memory_region_init_ram(&s->ram3, OBJECT(dev), "ram3",
409 NPCM7XX_RAM3_SZ, &error_abort);
410 memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM3_BA, &s->ram3);
411
412 /* Internal ROM */
413 memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM7XX_ROM_SZ,
414 &error_abort);
415 memory_region_add_subregion(get_system_memory(), NPCM7XX_ROM_BA, &s->irom);
416
417 create_unimplemented_device("npcm7xx.shm", 0xc0001000, 4 * KiB);
418 create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB);
419 create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB);
420 create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB);
421 create_unimplemented_device("npcm7xx.adc", 0xf000c000, 4 * KiB);
422 create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB);
423 create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * KiB);
424 create_unimplemented_device("npcm7xx.gpio[1]", 0xf0011000, 4 * KiB);
425 create_unimplemented_device("npcm7xx.gpio[2]", 0xf0012000, 4 * KiB);
426 create_unimplemented_device("npcm7xx.gpio[3]", 0xf0013000, 4 * KiB);
427 create_unimplemented_device("npcm7xx.gpio[4]", 0xf0014000, 4 * KiB);
428 create_unimplemented_device("npcm7xx.gpio[5]", 0xf0015000, 4 * KiB);
429 create_unimplemented_device("npcm7xx.gpio[6]", 0xf0016000, 4 * KiB);
430 create_unimplemented_device("npcm7xx.gpio[7]", 0xf0017000, 4 * KiB);
431 create_unimplemented_device("npcm7xx.smbus[0]", 0xf0080000, 4 * KiB);
432 create_unimplemented_device("npcm7xx.smbus[1]", 0xf0081000, 4 * KiB);
433 create_unimplemented_device("npcm7xx.smbus[2]", 0xf0082000, 4 * KiB);
434 create_unimplemented_device("npcm7xx.smbus[3]", 0xf0083000, 4 * KiB);
435 create_unimplemented_device("npcm7xx.smbus[4]", 0xf0084000, 4 * KiB);
436 create_unimplemented_device("npcm7xx.smbus[5]", 0xf0085000, 4 * KiB);
437 create_unimplemented_device("npcm7xx.smbus[6]", 0xf0086000, 4 * KiB);
438 create_unimplemented_device("npcm7xx.smbus[7]", 0xf0087000, 4 * KiB);
439 create_unimplemented_device("npcm7xx.smbus[8]", 0xf0088000, 4 * KiB);
440 create_unimplemented_device("npcm7xx.smbus[9]", 0xf0089000, 4 * KiB);
441 create_unimplemented_device("npcm7xx.smbus[10]", 0xf008a000, 4 * KiB);
442 create_unimplemented_device("npcm7xx.smbus[11]", 0xf008b000, 4 * KiB);
443 create_unimplemented_device("npcm7xx.smbus[12]", 0xf008c000, 4 * KiB);
444 create_unimplemented_device("npcm7xx.smbus[13]", 0xf008d000, 4 * KiB);
445 create_unimplemented_device("npcm7xx.smbus[14]", 0xf008e000, 4 * KiB);
446 create_unimplemented_device("npcm7xx.smbus[15]", 0xf008f000, 4 * KiB);
447 create_unimplemented_device("npcm7xx.espi", 0xf009f000, 4 * KiB);
448 create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB);
449 create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB);
450 create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB);
451 create_unimplemented_device("npcm7xx.pwm[0]", 0xf0103000, 4 * KiB);
452 create_unimplemented_device("npcm7xx.pwm[1]", 0xf0104000, 4 * KiB);
453 create_unimplemented_device("npcm7xx.mft[0]", 0xf0180000, 4 * KiB);
454 create_unimplemented_device("npcm7xx.mft[1]", 0xf0181000, 4 * KiB);
455 create_unimplemented_device("npcm7xx.mft[2]", 0xf0182000, 4 * KiB);
456 create_unimplemented_device("npcm7xx.mft[3]", 0xf0183000, 4 * KiB);
457 create_unimplemented_device("npcm7xx.mft[4]", 0xf0184000, 4 * KiB);
458 create_unimplemented_device("npcm7xx.mft[5]", 0xf0185000, 4 * KiB);
459 create_unimplemented_device("npcm7xx.mft[6]", 0xf0186000, 4 * KiB);
460 create_unimplemented_device("npcm7xx.mft[7]", 0xf0187000, 4 * KiB);
461 create_unimplemented_device("npcm7xx.pspi1", 0xf0200000, 4 * KiB);
462 create_unimplemented_device("npcm7xx.pspi2", 0xf0201000, 4 * KiB);
463 create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * MiB);
464 create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB);
465 create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * KiB);
466 create_unimplemented_device("npcm7xx.gmac2", 0xf0804000, 8 * KiB);
467 create_unimplemented_device("npcm7xx.ehci", 0xf0806000, 4 * KiB);
468 create_unimplemented_device("npcm7xx.ohci", 0xf0807000, 4 * KiB);
469 create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * KiB);
470 create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * KiB);
471 create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * KiB);
472 create_unimplemented_device("npcm7xx.emc1", 0xf0825000, 4 * KiB);
473 create_unimplemented_device("npcm7xx.emc2", 0xf0826000, 4 * KiB);
474 create_unimplemented_device("npcm7xx.usbd[0]", 0xf0830000, 4 * KiB);
475 create_unimplemented_device("npcm7xx.usbd[1]", 0xf0831000, 4 * KiB);
476 create_unimplemented_device("npcm7xx.usbd[2]", 0xf0832000, 4 * KiB);
477 create_unimplemented_device("npcm7xx.usbd[3]", 0xf0833000, 4 * KiB);
478 create_unimplemented_device("npcm7xx.usbd[4]", 0xf0834000, 4 * KiB);
479 create_unimplemented_device("npcm7xx.usbd[5]", 0xf0835000, 4 * KiB);
480 create_unimplemented_device("npcm7xx.usbd[6]", 0xf0836000, 4 * KiB);
481 create_unimplemented_device("npcm7xx.usbd[7]", 0xf0837000, 4 * KiB);
482 create_unimplemented_device("npcm7xx.usbd[8]", 0xf0838000, 4 * KiB);
483 create_unimplemented_device("npcm7xx.usbd[9]", 0xf0839000, 4 * KiB);
484 create_unimplemented_device("npcm7xx.sd", 0xf0840000, 8 * KiB);
485 create_unimplemented_device("npcm7xx.mmc", 0xf0842000, 8 * KiB);
486 create_unimplemented_device("npcm7xx.pcimbx", 0xf0848000, 512 * KiB);
487 create_unimplemented_device("npcm7xx.aes", 0xf0858000, 4 * KiB);
488 create_unimplemented_device("npcm7xx.des", 0xf0859000, 4 * KiB);
489 create_unimplemented_device("npcm7xx.sha", 0xf085a000, 4 * KiB);
490 create_unimplemented_device("npcm7xx.secacc", 0xf085b000, 4 * KiB);
491 create_unimplemented_device("npcm7xx.spixcs0", 0xf8000000, 16 * MiB);
492 create_unimplemented_device("npcm7xx.spixcs1", 0xf9000000, 16 * MiB);
493 create_unimplemented_device("npcm7xx.spix", 0xfb001000, 4 * KiB);
494 }
495
496 static Property npcm7xx_properties[] = {
497 DEFINE_PROP_LINK("dram-mr", NPCM7xxState, dram, TYPE_MEMORY_REGION,
498 MemoryRegion *),
499 DEFINE_PROP_END_OF_LIST(),
500 };
501
502 static void npcm7xx_class_init(ObjectClass *oc, void *data)
503 {
504 DeviceClass *dc = DEVICE_CLASS(oc);
505
506 dc->realize = npcm7xx_realize;
507 dc->user_creatable = false;
508 device_class_set_props(dc, npcm7xx_properties);
509 }
510
511 static void npcm730_class_init(ObjectClass *oc, void *data)
512 {
513 NPCM7xxClass *nc = NPCM7XX_CLASS(oc);
514
515 /* NPCM730 is optimized for data center use, so no graphics, etc. */
516 nc->disabled_modules = 0x00300395;
517 nc->num_cpus = 2;
518 }
519
520 static void npcm750_class_init(ObjectClass *oc, void *data)
521 {
522 NPCM7xxClass *nc = NPCM7XX_CLASS(oc);
523
524 /* NPCM750 has 2 cores and a full set of peripherals */
525 nc->disabled_modules = 0x00000000;
526 nc->num_cpus = 2;
527 }
528
529 static const TypeInfo npcm7xx_soc_types[] = {
530 {
531 .name = TYPE_NPCM7XX,
532 .parent = TYPE_DEVICE,
533 .instance_size = sizeof(NPCM7xxState),
534 .instance_init = npcm7xx_init,
535 .class_size = sizeof(NPCM7xxClass),
536 .class_init = npcm7xx_class_init,
537 .abstract = true,
538 }, {
539 .name = TYPE_NPCM730,
540 .parent = TYPE_NPCM7XX,
541 .class_init = npcm730_class_init,
542 }, {
543 .name = TYPE_NPCM750,
544 .parent = TYPE_NPCM7XX,
545 .class_init = npcm750_class_init,
546 },
547 };
548
549 DEFINE_TYPES(npcm7xx_soc_types);