cpu: Move halted and interrupt_request fields to CPUState
[qemu.git] / hw / arm / pxa2xx_gpio.c
1 /*
2 * Intel XScale PXA255/270 GPIO controller emulation.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GPL.
8 */
9
10 #include "hw/hw.h"
11 #include "hw/sysbus.h"
12 #include "hw/pxa.h"
13
14 #define PXA2XX_GPIO_BANKS 4
15
16 typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
17 struct PXA2xxGPIOInfo {
18 SysBusDevice busdev;
19 MemoryRegion iomem;
20 qemu_irq irq0, irq1, irqX;
21 int lines;
22 int ncpu;
23 ARMCPU *cpu;
24
25 /* XXX: GNU C vectors are more suitable */
26 uint32_t ilevel[PXA2XX_GPIO_BANKS];
27 uint32_t olevel[PXA2XX_GPIO_BANKS];
28 uint32_t dir[PXA2XX_GPIO_BANKS];
29 uint32_t rising[PXA2XX_GPIO_BANKS];
30 uint32_t falling[PXA2XX_GPIO_BANKS];
31 uint32_t status[PXA2XX_GPIO_BANKS];
32 uint32_t gpsr[PXA2XX_GPIO_BANKS];
33 uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
34
35 uint32_t prev_level[PXA2XX_GPIO_BANKS];
36 qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
37 qemu_irq read_notify;
38 };
39
40 static struct {
41 enum {
42 GPIO_NONE,
43 GPLR,
44 GPSR,
45 GPCR,
46 GPDR,
47 GRER,
48 GFER,
49 GEDR,
50 GAFR_L,
51 GAFR_U,
52 } reg;
53 int bank;
54 } pxa2xx_gpio_regs[0x200] = {
55 [0 ... 0x1ff] = { GPIO_NONE, 0 },
56 #define PXA2XX_REG(reg, a0, a1, a2, a3) \
57 [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
58
59 PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
60 PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
61 PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
62 PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
63 PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
64 PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
65 PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
66 PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
67 PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
68 };
69
70 static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
71 {
72 if (s->status[0] & (1 << 0))
73 qemu_irq_raise(s->irq0);
74 else
75 qemu_irq_lower(s->irq0);
76
77 if (s->status[0] & (1 << 1))
78 qemu_irq_raise(s->irq1);
79 else
80 qemu_irq_lower(s->irq1);
81
82 if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3])
83 qemu_irq_raise(s->irqX);
84 else
85 qemu_irq_lower(s->irqX);
86 }
87
88 /* Bitmap of pins used as standby and sleep wake-up sources. */
89 static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
90 0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
91 };
92
93 static void pxa2xx_gpio_set(void *opaque, int line, int level)
94 {
95 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
96 CPUState *cpu = CPU(s->cpu);
97 int bank;
98 uint32_t mask;
99
100 if (line >= s->lines) {
101 printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
102 return;
103 }
104
105 bank = line >> 5;
106 mask = 1 << (line & 31);
107
108 if (level) {
109 s->status[bank] |= s->rising[bank] & mask &
110 ~s->ilevel[bank] & ~s->dir[bank];
111 s->ilevel[bank] |= mask;
112 } else {
113 s->status[bank] |= s->falling[bank] & mask &
114 s->ilevel[bank] & ~s->dir[bank];
115 s->ilevel[bank] &= ~mask;
116 }
117
118 if (s->status[bank] & mask)
119 pxa2xx_gpio_irq_update(s);
120
121 /* Wake-up GPIOs */
122 if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
123 cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_EXITTB);
124 }
125 }
126
127 static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
128 uint32_t level, diff;
129 int i, bit, line;
130 for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
131 level = s->olevel[i] & s->dir[i];
132
133 for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
134 bit = ffs(diff) - 1;
135 line = bit + 32 * i;
136 qemu_set_irq(s->handler[line], (level >> bit) & 1);
137 }
138
139 s->prev_level[i] = level;
140 }
141 }
142
143 static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
144 unsigned size)
145 {
146 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
147 uint32_t ret;
148 int bank;
149 if (offset >= 0x200)
150 return 0;
151
152 bank = pxa2xx_gpio_regs[offset].bank;
153 switch (pxa2xx_gpio_regs[offset].reg) {
154 case GPDR: /* GPIO Pin-Direction registers */
155 return s->dir[bank];
156
157 case GPSR: /* GPIO Pin-Output Set registers */
158 printf("%s: Read from a write-only register " REG_FMT "\n",
159 __FUNCTION__, offset);
160 return s->gpsr[bank]; /* Return last written value. */
161
162 case GPCR: /* GPIO Pin-Output Clear registers */
163 printf("%s: Read from a write-only register " REG_FMT "\n",
164 __FUNCTION__, offset);
165 return 31337; /* Specified as unpredictable in the docs. */
166
167 case GRER: /* GPIO Rising-Edge Detect Enable registers */
168 return s->rising[bank];
169
170 case GFER: /* GPIO Falling-Edge Detect Enable registers */
171 return s->falling[bank];
172
173 case GAFR_L: /* GPIO Alternate Function registers */
174 return s->gafr[bank * 2];
175
176 case GAFR_U: /* GPIO Alternate Function registers */
177 return s->gafr[bank * 2 + 1];
178
179 case GPLR: /* GPIO Pin-Level registers */
180 ret = (s->olevel[bank] & s->dir[bank]) |
181 (s->ilevel[bank] & ~s->dir[bank]);
182 qemu_irq_raise(s->read_notify);
183 return ret;
184
185 case GEDR: /* GPIO Edge Detect Status registers */
186 return s->status[bank];
187
188 default:
189 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
190 }
191
192 return 0;
193 }
194
195 static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
196 uint64_t value, unsigned size)
197 {
198 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
199 int bank;
200 if (offset >= 0x200)
201 return;
202
203 bank = pxa2xx_gpio_regs[offset].bank;
204 switch (pxa2xx_gpio_regs[offset].reg) {
205 case GPDR: /* GPIO Pin-Direction registers */
206 s->dir[bank] = value;
207 pxa2xx_gpio_handler_update(s);
208 break;
209
210 case GPSR: /* GPIO Pin-Output Set registers */
211 s->olevel[bank] |= value;
212 pxa2xx_gpio_handler_update(s);
213 s->gpsr[bank] = value;
214 break;
215
216 case GPCR: /* GPIO Pin-Output Clear registers */
217 s->olevel[bank] &= ~value;
218 pxa2xx_gpio_handler_update(s);
219 break;
220
221 case GRER: /* GPIO Rising-Edge Detect Enable registers */
222 s->rising[bank] = value;
223 break;
224
225 case GFER: /* GPIO Falling-Edge Detect Enable registers */
226 s->falling[bank] = value;
227 break;
228
229 case GAFR_L: /* GPIO Alternate Function registers */
230 s->gafr[bank * 2] = value;
231 break;
232
233 case GAFR_U: /* GPIO Alternate Function registers */
234 s->gafr[bank * 2 + 1] = value;
235 break;
236
237 case GEDR: /* GPIO Edge Detect Status registers */
238 s->status[bank] &= ~value;
239 pxa2xx_gpio_irq_update(s);
240 break;
241
242 default:
243 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
244 }
245 }
246
247 static const MemoryRegionOps pxa_gpio_ops = {
248 .read = pxa2xx_gpio_read,
249 .write = pxa2xx_gpio_write,
250 .endianness = DEVICE_NATIVE_ENDIAN,
251 };
252
253 DeviceState *pxa2xx_gpio_init(hwaddr base,
254 ARMCPU *cpu, DeviceState *pic, int lines)
255 {
256 CPUState *cs = CPU(cpu);
257 DeviceState *dev;
258
259 dev = qdev_create(NULL, "pxa2xx-gpio");
260 qdev_prop_set_int32(dev, "lines", lines);
261 qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
262 qdev_init_nofail(dev);
263
264 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
265 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
266 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
267 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1,
268 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
269 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2,
270 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));
271
272 return dev;
273 }
274
275 static int pxa2xx_gpio_initfn(SysBusDevice *dev)
276 {
277 PXA2xxGPIOInfo *s;
278
279 s = FROM_SYSBUS(PXA2xxGPIOInfo, dev);
280
281 s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu));
282
283 qdev_init_gpio_in(&dev->qdev, pxa2xx_gpio_set, s->lines);
284 qdev_init_gpio_out(&dev->qdev, s->handler, s->lines);
285
286 memory_region_init_io(&s->iomem, &pxa_gpio_ops, s, "pxa2xx-gpio", 0x1000);
287 sysbus_init_mmio(dev, &s->iomem);
288 sysbus_init_irq(dev, &s->irq0);
289 sysbus_init_irq(dev, &s->irq1);
290 sysbus_init_irq(dev, &s->irqX);
291
292 return 0;
293 }
294
295 /*
296 * Registers a callback to notify on GPLR reads. This normally
297 * shouldn't be needed but it is used for the hack on Spitz machines.
298 */
299 void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
300 {
301 PXA2xxGPIOInfo *s = FROM_SYSBUS(PXA2xxGPIOInfo, SYS_BUS_DEVICE(dev));
302 s->read_notify = handler;
303 }
304
305 static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
306 .name = "pxa2xx-gpio",
307 .version_id = 1,
308 .minimum_version_id = 1,
309 .minimum_version_id_old = 1,
310 .fields = (VMStateField []) {
311 VMSTATE_INT32(lines, PXA2xxGPIOInfo),
312 VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
313 VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
314 VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
315 VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
316 VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
317 VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
318 VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
319 VMSTATE_END_OF_LIST(),
320 },
321 };
322
323 static Property pxa2xx_gpio_properties[] = {
324 DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
325 DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0),
326 DEFINE_PROP_END_OF_LIST(),
327 };
328
329 static void pxa2xx_gpio_class_init(ObjectClass *klass, void *data)
330 {
331 DeviceClass *dc = DEVICE_CLASS(klass);
332 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
333
334 k->init = pxa2xx_gpio_initfn;
335 dc->desc = "PXA2xx GPIO controller";
336 dc->props = pxa2xx_gpio_properties;
337 }
338
339 static const TypeInfo pxa2xx_gpio_info = {
340 .name = "pxa2xx-gpio",
341 .parent = TYPE_SYS_BUS_DEVICE,
342 .instance_size = sizeof(PXA2xxGPIOInfo),
343 .class_init = pxa2xx_gpio_class_init,
344 };
345
346 static void pxa2xx_gpio_register_types(void)
347 {
348 type_register_static(&pxa2xx_gpio_info);
349 }
350
351 type_init(pxa2xx_gpio_register_types)