hw/arm/raspi: Move arm_boot_info structure to RaspiMachineState
[qemu.git] / hw / arm / raspi.c
1 /*
2 * Raspberry Pi emulation (c) 2012 Gregory Estrade
3 * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
4 *
5 * Rasperry Pi 2 emulation Copyright (c) 2015, Microsoft
6 * Written by Andrew Baumann
7 *
8 * Raspberry Pi 3 emulation Copyright (c) 2018 Zoltán Baldaszti
9 * Upstream code cleanup (c) 2018 Pekka Enberg
10 *
11 * This work is licensed under the terms of the GNU GPL, version 2 or later.
12 * See the COPYING file in the top-level directory.
13 */
14
15 #include "qemu/osdep.h"
16 #include "qemu/units.h"
17 #include "qemu/cutils.h"
18 #include "qapi/error.h"
19 #include "cpu.h"
20 #include "hw/arm/bcm2836.h"
21 #include "hw/registerfields.h"
22 #include "qemu/error-report.h"
23 #include "hw/boards.h"
24 #include "hw/loader.h"
25 #include "hw/arm/boot.h"
26 #include "sysemu/sysemu.h"
27 #include "qom/object.h"
28
29 #define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS */
30 #define MVBAR_ADDR 0x400 /* secure vectors */
31 #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
32 #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
33 #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
34 #define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */
35
36 /* Registered machine type (matches RPi Foundation bootloader and U-Boot) */
37 #define MACH_TYPE_BCM2708 3138
38
39 struct RaspiMachineState {
40 /*< private >*/
41 MachineState parent_obj;
42 /*< public >*/
43 BCM283XState soc;
44 struct arm_boot_info binfo;
45 };
46 typedef struct RaspiMachineState RaspiMachineState;
47
48 struct RaspiMachineClass {
49 /*< private >*/
50 MachineClass parent_obj;
51 /*< public >*/
52 uint32_t board_rev;
53 };
54 typedef struct RaspiMachineClass RaspiMachineClass;
55
56 #define TYPE_RASPI_MACHINE MACHINE_TYPE_NAME("raspi-common")
57 DECLARE_OBJ_CHECKERS(RaspiMachineState, RaspiMachineClass,
58 RASPI_MACHINE, TYPE_RASPI_MACHINE)
59
60
61 /*
62 * Board revision codes:
63 * www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/
64 */
65 FIELD(REV_CODE, REVISION, 0, 4);
66 FIELD(REV_CODE, TYPE, 4, 8);
67 FIELD(REV_CODE, PROCESSOR, 12, 4);
68 FIELD(REV_CODE, MANUFACTURER, 16, 4);
69 FIELD(REV_CODE, MEMORY_SIZE, 20, 3);
70 FIELD(REV_CODE, STYLE, 23, 1);
71
72 static uint64_t board_ram_size(uint32_t board_rev)
73 {
74 assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */
75 return 256 * MiB << FIELD_EX32(board_rev, REV_CODE, MEMORY_SIZE);
76 }
77
78 static int board_processor_id(uint32_t board_rev)
79 {
80 assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */
81 return FIELD_EX32(board_rev, REV_CODE, PROCESSOR);
82 }
83
84 static int board_version(uint32_t board_rev)
85 {
86 return board_processor_id(board_rev) + 1;
87 }
88
89 static const char *board_soc_type(uint32_t board_rev)
90 {
91 static const char *soc_types[] = {
92 NULL, TYPE_BCM2836, TYPE_BCM2837,
93 };
94 int proc_id = board_processor_id(board_rev);
95
96 if (proc_id >= ARRAY_SIZE(soc_types) || !soc_types[proc_id]) {
97 error_report("Unsupported processor id '%d' (board revision: 0x%x)",
98 proc_id, board_rev);
99 exit(1);
100 }
101 return soc_types[proc_id];
102 }
103
104 static int cores_count(uint32_t board_rev)
105 {
106 static const int soc_cores_count[] = {
107 0, BCM283X_NCPUS, BCM283X_NCPUS,
108 };
109 int proc_id = board_processor_id(board_rev);
110
111 if (proc_id >= ARRAY_SIZE(soc_cores_count) || !soc_cores_count[proc_id]) {
112 error_report("Unsupported processor id '%d' (board revision: 0x%x)",
113 proc_id, board_rev);
114 exit(1);
115 }
116 return soc_cores_count[proc_id];
117 }
118
119 static const char *board_type(uint32_t board_rev)
120 {
121 static const char *types[] = {
122 "A", "B", "A+", "B+", "2B", "Alpha", "CM1", NULL, "3B", "Zero",
123 "CM3", NULL, "Zero W", "3B+", "3A+", NULL, "CM3+", "4B",
124 };
125 assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */
126 int bt = FIELD_EX32(board_rev, REV_CODE, TYPE);
127 if (bt >= ARRAY_SIZE(types) || !types[bt]) {
128 return "Unknown";
129 }
130 return types[bt];
131 }
132
133 static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info)
134 {
135 static const uint32_t smpboot[] = {
136 0xe1a0e00f, /* mov lr, pc */
137 0xe3a0fe00 + (BOARDSETUP_ADDR >> 4), /* mov pc, BOARDSETUP_ADDR */
138 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5;get core ID */
139 0xe7e10050, /* ubfx r0, r0, #0, #2 ;extract LSB */
140 0xe59f5014, /* ldr r5, =0x400000CC ;load mbox base */
141 0xe320f001, /* 1: yield */
142 0xe7953200, /* ldr r3, [r5, r0, lsl #4] ;read mbox for our core*/
143 0xe3530000, /* cmp r3, #0 ;spin while zero */
144 0x0afffffb, /* beq 1b */
145 0xe7853200, /* str r3, [r5, r0, lsl #4] ;clear mbox */
146 0xe12fff13, /* bx r3 ;jump to target */
147 0x400000cc, /* (constant: mailbox 3 read/clear base) */
148 };
149
150 /* check that we don't overrun board setup vectors */
151 QEMU_BUILD_BUG_ON(SMPBOOT_ADDR + sizeof(smpboot) > MVBAR_ADDR);
152 /* check that board setup address is correctly relocated */
153 QEMU_BUILD_BUG_ON((BOARDSETUP_ADDR & 0xf) != 0
154 || (BOARDSETUP_ADDR >> 4) >= 0x100);
155
156 rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot),
157 info->smp_loader_start,
158 arm_boot_address_space(cpu, info));
159 }
160
161 static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info)
162 {
163 AddressSpace *as = arm_boot_address_space(cpu, info);
164 /* Unlike the AArch32 version we don't need to call the board setup hook.
165 * The mechanism for doing the spin-table is also entirely different.
166 * We must have four 64-bit fields at absolute addresses
167 * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for
168 * our CPUs, and which we must ensure are zero initialized before
169 * the primary CPU goes into the kernel. We put these variables inside
170 * a rom blob, so that the reset for ROM contents zeroes them for us.
171 */
172 static const uint32_t smpboot[] = {
173 0xd2801b05, /* mov x5, 0xd8 */
174 0xd53800a6, /* mrs x6, mpidr_el1 */
175 0x924004c6, /* and x6, x6, #0x3 */
176 0xd503205f, /* spin: wfe */
177 0xf86678a4, /* ldr x4, [x5,x6,lsl #3] */
178 0xb4ffffc4, /* cbz x4, spin */
179 0xd2800000, /* mov x0, #0x0 */
180 0xd2800001, /* mov x1, #0x0 */
181 0xd2800002, /* mov x2, #0x0 */
182 0xd2800003, /* mov x3, #0x0 */
183 0xd61f0080, /* br x4 */
184 };
185
186 static const uint64_t spintables[] = {
187 0, 0, 0, 0
188 };
189
190 rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot),
191 info->smp_loader_start, as);
192 rom_add_blob_fixed_as("raspi_spintables", spintables, sizeof(spintables),
193 SPINTABLE_ADDR, as);
194 }
195
196 static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info)
197 {
198 arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
199 }
200
201 static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
202 {
203 CPUState *cs = CPU(cpu);
204 cpu_set_pc(cs, info->smp_loader_start);
205 }
206
207 static void setup_boot(MachineState *machine, int version, size_t ram_size)
208 {
209 RaspiMachineState *s = RASPI_MACHINE(machine);
210 int r;
211
212 s->binfo.board_id = MACH_TYPE_BCM2708;
213 s->binfo.ram_size = ram_size;
214 s->binfo.nb_cpus = machine->smp.cpus;
215
216 if (version <= 2) {
217 /* The rpi1 and 2 require some custom setup code to run in Secure
218 * mode before booting a kernel (to set up the SMC vectors so
219 * that we get a no-op SMC; this is used by Linux to call the
220 * firmware for some cache maintenance operations.
221 * The rpi3 doesn't need this.
222 */
223 s->binfo.board_setup_addr = BOARDSETUP_ADDR;
224 s->binfo.write_board_setup = write_board_setup;
225 s->binfo.secure_board_setup = true;
226 s->binfo.secure_boot = true;
227 }
228
229 /* Pi2 and Pi3 requires SMP setup */
230 if (version >= 2) {
231 s->binfo.smp_loader_start = SMPBOOT_ADDR;
232 if (version == 2) {
233 s->binfo.write_secondary_boot = write_smpboot;
234 } else {
235 s->binfo.write_secondary_boot = write_smpboot64;
236 }
237 s->binfo.secondary_cpu_reset_hook = reset_secondary;
238 }
239
240 /* If the user specified a "firmware" image (e.g. UEFI), we bypass
241 * the normal Linux boot process
242 */
243 if (machine->firmware) {
244 hwaddr firmware_addr = version == 3 ? FIRMWARE_ADDR_3 : FIRMWARE_ADDR_2;
245 /* load the firmware image (typically kernel.img) */
246 r = load_image_targphys(machine->firmware, firmware_addr,
247 ram_size - firmware_addr);
248 if (r < 0) {
249 error_report("Failed to load firmware from %s", machine->firmware);
250 exit(1);
251 }
252
253 s->binfo.entry = firmware_addr;
254 s->binfo.firmware_loaded = true;
255 }
256
257 arm_load_kernel(&s->soc.cpu[0].core, machine, &s->binfo);
258 }
259
260 static void raspi_machine_init(MachineState *machine)
261 {
262 RaspiMachineClass *mc = RASPI_MACHINE_GET_CLASS(machine);
263 RaspiMachineState *s = RASPI_MACHINE(machine);
264 uint32_t board_rev = mc->board_rev;
265 int version = board_version(board_rev);
266 uint64_t ram_size = board_ram_size(board_rev);
267 uint32_t vcram_size;
268 DriveInfo *di;
269 BlockBackend *blk;
270 BusState *bus;
271 DeviceState *carddev;
272
273 if (machine->ram_size != ram_size) {
274 char *size_str = size_to_str(ram_size);
275 error_report("Invalid RAM size, should be %s", size_str);
276 g_free(size_str);
277 exit(1);
278 }
279
280 /* FIXME: Remove when we have custom CPU address space support */
281 memory_region_add_subregion_overlap(get_system_memory(), 0,
282 machine->ram, 0);
283
284 /* Setup the SOC */
285 object_initialize_child(OBJECT(machine), "soc", &s->soc,
286 board_soc_type(board_rev));
287 object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(machine->ram));
288 object_property_set_int(OBJECT(&s->soc), "board-rev", board_rev,
289 &error_abort);
290 qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
291
292 /* Create and plug in the SD cards */
293 di = drive_get_next(IF_SD);
294 blk = di ? blk_by_legacy_dinfo(di) : NULL;
295 bus = qdev_get_child_bus(DEVICE(&s->soc), "sd-bus");
296 if (bus == NULL) {
297 error_report("No SD bus found in SOC object");
298 exit(1);
299 }
300 carddev = qdev_new(TYPE_SD_CARD);
301 qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal);
302 qdev_realize_and_unref(carddev, bus, &error_fatal);
303
304 vcram_size = object_property_get_uint(OBJECT(&s->soc), "vcram-size",
305 &error_abort);
306 setup_boot(machine, version, machine->ram_size - vcram_size);
307 }
308
309 static void raspi_machine_class_init(ObjectClass *oc, void *data)
310 {
311 MachineClass *mc = MACHINE_CLASS(oc);
312 RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
313 uint32_t board_rev = (uint32_t)(uintptr_t)data;
314
315 rmc->board_rev = board_rev;
316 mc->desc = g_strdup_printf("Raspberry Pi %s (revision 1.%u)",
317 board_type(board_rev),
318 FIELD_EX32(board_rev, REV_CODE, REVISION));
319 mc->init = raspi_machine_init;
320 mc->block_default_type = IF_SD;
321 mc->no_parallel = 1;
322 mc->no_floppy = 1;
323 mc->no_cdrom = 1;
324 mc->default_cpus = mc->min_cpus = mc->max_cpus = cores_count(board_rev);
325 mc->default_ram_size = board_ram_size(board_rev);
326 mc->default_ram_id = "ram";
327 };
328
329 static const TypeInfo raspi_machine_types[] = {
330 {
331 .name = MACHINE_TYPE_NAME("raspi2"),
332 .parent = TYPE_RASPI_MACHINE,
333 .class_init = raspi_machine_class_init,
334 .class_data = (void *)0xa21041,
335 #ifdef TARGET_AARCH64
336 }, {
337 .name = MACHINE_TYPE_NAME("raspi3"),
338 .parent = TYPE_RASPI_MACHINE,
339 .class_init = raspi_machine_class_init,
340 .class_data = (void *)0xa02082,
341 #endif
342 }, {
343 .name = TYPE_RASPI_MACHINE,
344 .parent = TYPE_MACHINE,
345 .instance_size = sizeof(RaspiMachineState),
346 .class_size = sizeof(RaspiMachineClass),
347 .abstract = true,
348 }
349 };
350
351 DEFINE_TYPES(raspi_machine_types)