Merge remote-tracking branch 'remotes/philmd-gitlab/tags/renesas-20201027' into staging
[qemu.git] / hw / arm / sabrelite.c
1 /*
2 * SABRELITE Board System emulation.
3 *
4 * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
5 *
6 * This code is licensed under the GPL, version 2 or later.
7 * See the file `COPYING' in the top level directory.
8 *
9 * It (partially) emulates a sabrelite board, with a Freescale
10 * i.MX6 SoC
11 */
12
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "hw/arm/fsl-imx6.h"
16 #include "hw/boards.h"
17 #include "hw/qdev-properties.h"
18 #include "sysemu/sysemu.h"
19 #include "qemu/error-report.h"
20 #include "sysemu/qtest.h"
21
22 static struct arm_boot_info sabrelite_binfo = {
23 /* DDR memory start */
24 .loader_start = FSL_IMX6_MMDC_ADDR,
25 /* No board ID, we boot from DT tree */
26 .board_id = -1,
27 };
28
29 /* No need to do any particular setup for secondary boot */
30 static void sabrelite_write_secondary(ARMCPU *cpu,
31 const struct arm_boot_info *info)
32 {
33 }
34
35 /* Secondary cores are reset through SRC device */
36 static void sabrelite_reset_secondary(ARMCPU *cpu,
37 const struct arm_boot_info *info)
38 {
39 }
40
41 static void sabrelite_init(MachineState *machine)
42 {
43 FslIMX6State *s;
44
45 /* Check the amount of memory is compatible with the SOC */
46 if (machine->ram_size > FSL_IMX6_MMDC_SIZE) {
47 error_report("RAM size " RAM_ADDR_FMT " above max supported (%08x)",
48 machine->ram_size, FSL_IMX6_MMDC_SIZE);
49 exit(1);
50 }
51
52 s = FSL_IMX6(object_new(TYPE_FSL_IMX6));
53 object_property_add_child(OBJECT(machine), "soc", OBJECT(s));
54 qdev_realize(DEVICE(s), NULL, &error_fatal);
55
56 memory_region_add_subregion(get_system_memory(), FSL_IMX6_MMDC_ADDR,
57 machine->ram);
58
59 {
60 /*
61 * TODO: Ideally we would expose the chip select and spi bus on the
62 * SoC object using alias properties; then we would not need to
63 * directly access the underlying spi device object.
64 */
65 /* Add the sst25vf016b NOR FLASH memory to first SPI */
66 Object *spi_dev;
67
68 spi_dev = object_resolve_path_component(OBJECT(s), "spi1");
69 if (spi_dev) {
70 SSIBus *spi_bus;
71
72 spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(spi_dev), "spi");
73 if (spi_bus) {
74 DeviceState *flash_dev;
75 qemu_irq cs_line;
76 DriveInfo *dinfo = drive_get_next(IF_MTD);
77
78 flash_dev = qdev_new("sst25vf016b");
79 if (dinfo) {
80 qdev_prop_set_drive_err(flash_dev, "drive",
81 blk_by_legacy_dinfo(dinfo),
82 &error_fatal);
83 }
84 qdev_realize_and_unref(flash_dev, BUS(spi_bus), &error_fatal);
85
86 cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
87 sysbus_connect_irq(SYS_BUS_DEVICE(spi_dev), 1, cs_line);
88 }
89 }
90 }
91
92 sabrelite_binfo.ram_size = machine->ram_size;
93 sabrelite_binfo.nb_cpus = machine->smp.cpus;
94 sabrelite_binfo.secure_boot = true;
95 sabrelite_binfo.write_secondary_boot = sabrelite_write_secondary;
96 sabrelite_binfo.secondary_cpu_reset_hook = sabrelite_reset_secondary;
97
98 if (!qtest_enabled()) {
99 arm_load_kernel(&s->cpu[0], machine, &sabrelite_binfo);
100 }
101 }
102
103 static void sabrelite_machine_init(MachineClass *mc)
104 {
105 mc->desc = "Freescale i.MX6 Quad SABRE Lite Board (Cortex A9)";
106 mc->init = sabrelite_init;
107 mc->max_cpus = FSL_IMX6_NUM_CPUS;
108 mc->ignore_memory_transaction_failures = true;
109 mc->default_ram_id = "sabrelite.ram";
110 }
111
112 DEFINE_MACHINE("sabrelite", sabrelite_machine_init)