hw/arm/sbsa-ref : Add embedded controller in secure memory
[qemu.git] / hw / arm / sbsa-ref.c
1 /*
2 * ARM SBSA Reference Platform emulation
3 *
4 * Copyright (c) 2018 Linaro Limited
5 * Written by Hongbo Zhang <hongbo.zhang@linaro.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qapi/error.h"
23 #include "qemu/error-report.h"
24 #include "qemu/units.h"
25 #include "sysemu/device_tree.h"
26 #include "sysemu/numa.h"
27 #include "sysemu/runstate.h"
28 #include "sysemu/sysemu.h"
29 #include "exec/address-spaces.h"
30 #include "exec/hwaddr.h"
31 #include "kvm_arm.h"
32 #include "hw/arm/boot.h"
33 #include "hw/block/flash.h"
34 #include "hw/boards.h"
35 #include "hw/ide/internal.h"
36 #include "hw/ide/ahci_internal.h"
37 #include "hw/intc/arm_gicv3_common.h"
38 #include "hw/loader.h"
39 #include "hw/pci-host/gpex.h"
40 #include "hw/qdev-properties.h"
41 #include "hw/usb.h"
42 #include "hw/char/pl011.h"
43 #include "net/net.h"
44
45 #define RAMLIMIT_GB 8192
46 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB)
47
48 #define NUM_IRQS 256
49 #define NUM_SMMU_IRQS 4
50 #define NUM_SATA_PORTS 6
51
52 #define VIRTUAL_PMU_IRQ 7
53 #define ARCH_GIC_MAINT_IRQ 9
54 #define ARCH_TIMER_VIRT_IRQ 11
55 #define ARCH_TIMER_S_EL1_IRQ 13
56 #define ARCH_TIMER_NS_EL1_IRQ 14
57 #define ARCH_TIMER_NS_EL2_IRQ 10
58
59 enum {
60 SBSA_FLASH,
61 SBSA_MEM,
62 SBSA_CPUPERIPHS,
63 SBSA_GIC_DIST,
64 SBSA_GIC_REDIST,
65 SBSA_SECURE_EC,
66 SBSA_SMMU,
67 SBSA_UART,
68 SBSA_RTC,
69 SBSA_PCIE,
70 SBSA_PCIE_MMIO,
71 SBSA_PCIE_MMIO_HIGH,
72 SBSA_PCIE_PIO,
73 SBSA_PCIE_ECAM,
74 SBSA_GPIO,
75 SBSA_SECURE_UART,
76 SBSA_SECURE_UART_MM,
77 SBSA_SECURE_MEM,
78 SBSA_AHCI,
79 SBSA_EHCI,
80 };
81
82 typedef struct MemMapEntry {
83 hwaddr base;
84 hwaddr size;
85 } MemMapEntry;
86
87 typedef struct {
88 MachineState parent;
89 struct arm_boot_info bootinfo;
90 int smp_cpus;
91 void *fdt;
92 int fdt_size;
93 int psci_conduit;
94 DeviceState *gic;
95 PFlashCFI01 *flash[2];
96 } SBSAMachineState;
97
98 #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref")
99 #define SBSA_MACHINE(obj) \
100 OBJECT_CHECK(SBSAMachineState, (obj), TYPE_SBSA_MACHINE)
101
102 static const MemMapEntry sbsa_ref_memmap[] = {
103 /* 512M boot ROM */
104 [SBSA_FLASH] = { 0, 0x20000000 },
105 /* 512M secure memory */
106 [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 },
107 /* Space reserved for CPU peripheral devices */
108 [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 },
109 [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 },
110 [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 },
111 [SBSA_SECURE_EC] = { 0x50000000, 0x00001000 },
112 [SBSA_UART] = { 0x60000000, 0x00001000 },
113 [SBSA_RTC] = { 0x60010000, 0x00001000 },
114 [SBSA_GPIO] = { 0x60020000, 0x00001000 },
115 [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 },
116 [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 },
117 [SBSA_SMMU] = { 0x60050000, 0x00020000 },
118 /* Space here reserved for more SMMUs */
119 [SBSA_AHCI] = { 0x60100000, 0x00010000 },
120 [SBSA_EHCI] = { 0x60110000, 0x00010000 },
121 /* Space here reserved for other devices */
122 [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 },
123 /* 32-bit address PCIE MMIO space */
124 [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 },
125 /* 256M PCIE ECAM space */
126 [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 },
127 /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */
128 [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL },
129 [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES },
130 };
131
132 static const int sbsa_ref_irqmap[] = {
133 [SBSA_UART] = 1,
134 [SBSA_RTC] = 2,
135 [SBSA_PCIE] = 3, /* ... to 6 */
136 [SBSA_GPIO] = 7,
137 [SBSA_SECURE_UART] = 8,
138 [SBSA_SECURE_UART_MM] = 9,
139 [SBSA_AHCI] = 10,
140 [SBSA_EHCI] = 11,
141 };
142
143 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
144 {
145 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
146 return arm_cpu_mp_affinity(idx, clustersz);
147 }
148
149 /*
150 * Firmware on this machine only uses ACPI table to load OS, these limited
151 * device tree nodes are just to let firmware know the info which varies from
152 * command line parameters, so it is not necessary to be fully compatible
153 * with the kernel CPU and NUMA binding rules.
154 */
155 static void create_fdt(SBSAMachineState *sms)
156 {
157 void *fdt = create_device_tree(&sms->fdt_size);
158 const MachineState *ms = MACHINE(sms);
159 int nb_numa_nodes = ms->numa_state->num_nodes;
160 int cpu;
161
162 if (!fdt) {
163 error_report("create_device_tree() failed");
164 exit(1);
165 }
166
167 sms->fdt = fdt;
168
169 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref");
170 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
171 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
172
173 if (ms->numa_state->have_numa_distance) {
174 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
175 uint32_t *matrix = g_malloc0(size);
176 int idx, i, j;
177
178 for (i = 0; i < nb_numa_nodes; i++) {
179 for (j = 0; j < nb_numa_nodes; j++) {
180 idx = (i * nb_numa_nodes + j) * 3;
181 matrix[idx + 0] = cpu_to_be32(i);
182 matrix[idx + 1] = cpu_to_be32(j);
183 matrix[idx + 2] =
184 cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
185 }
186 }
187
188 qemu_fdt_add_subnode(fdt, "/distance-map");
189 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
190 matrix, size);
191 g_free(matrix);
192 }
193
194 /*
195 * From Documentation/devicetree/bindings/arm/cpus.yaml
196 * On ARM v8 64-bit systems this property is required
197 * and matches the MPIDR_EL1 register affinity bits.
198 *
199 * * If cpus node's #address-cells property is set to 2
200 *
201 * The first reg cell bits [7:0] must be set to
202 * bits [39:32] of MPIDR_EL1.
203 *
204 * The second reg cell bits [23:0] must be set to
205 * bits [23:0] of MPIDR_EL1.
206 */
207 qemu_fdt_add_subnode(sms->fdt, "/cpus");
208 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#address-cells", 2);
209 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#size-cells", 0x0);
210
211 for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) {
212 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
213 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
214 CPUState *cs = CPU(armcpu);
215 uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu);
216
217 qemu_fdt_add_subnode(sms->fdt, nodename);
218 qemu_fdt_setprop_u64(sms->fdt, nodename, "reg", mpidr);
219
220 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
221 qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id",
222 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
223 }
224
225 g_free(nodename);
226 }
227 }
228
229 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB)
230
231 static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms,
232 const char *name,
233 const char *alias_prop_name)
234 {
235 /*
236 * Create a single flash device. We use the same parameters as
237 * the flash devices on the Versatile Express board.
238 */
239 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
240
241 qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE);
242 qdev_prop_set_uint8(dev, "width", 4);
243 qdev_prop_set_uint8(dev, "device-width", 2);
244 qdev_prop_set_bit(dev, "big-endian", false);
245 qdev_prop_set_uint16(dev, "id0", 0x89);
246 qdev_prop_set_uint16(dev, "id1", 0x18);
247 qdev_prop_set_uint16(dev, "id2", 0x00);
248 qdev_prop_set_uint16(dev, "id3", 0x00);
249 qdev_prop_set_string(dev, "name", name);
250 object_property_add_child(OBJECT(sms), name, OBJECT(dev));
251 object_property_add_alias(OBJECT(sms), alias_prop_name,
252 OBJECT(dev), "drive");
253 return PFLASH_CFI01(dev);
254 }
255
256 static void sbsa_flash_create(SBSAMachineState *sms)
257 {
258 sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0");
259 sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1");
260 }
261
262 static void sbsa_flash_map1(PFlashCFI01 *flash,
263 hwaddr base, hwaddr size,
264 MemoryRegion *sysmem)
265 {
266 DeviceState *dev = DEVICE(flash);
267
268 assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE));
269 assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX);
270 qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE);
271 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
272
273 memory_region_add_subregion(sysmem, base,
274 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
275 0));
276 }
277
278 static void sbsa_flash_map(SBSAMachineState *sms,
279 MemoryRegion *sysmem,
280 MemoryRegion *secure_sysmem)
281 {
282 /*
283 * Map two flash devices to fill the SBSA_FLASH space in the memmap.
284 * sysmem is the system memory space. secure_sysmem is the secure view
285 * of the system, and the first flash device should be made visible only
286 * there. The second flash device is visible to both secure and nonsecure.
287 */
288 hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2;
289 hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base;
290
291 sbsa_flash_map1(sms->flash[0], flashbase, flashsize,
292 secure_sysmem);
293 sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize,
294 sysmem);
295 }
296
297 static bool sbsa_firmware_init(SBSAMachineState *sms,
298 MemoryRegion *sysmem,
299 MemoryRegion *secure_sysmem)
300 {
301 int i;
302 BlockBackend *pflash_blk0;
303
304 /* Map legacy -drive if=pflash to machine properties */
305 for (i = 0; i < ARRAY_SIZE(sms->flash); i++) {
306 pflash_cfi01_legacy_drive(sms->flash[i],
307 drive_get(IF_PFLASH, 0, i));
308 }
309
310 sbsa_flash_map(sms, sysmem, secure_sysmem);
311
312 pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]);
313
314 if (bios_name) {
315 char *fname;
316 MemoryRegion *mr;
317 int image_size;
318
319 if (pflash_blk0) {
320 error_report("The contents of the first flash device may be "
321 "specified with -bios or with -drive if=pflash... "
322 "but you cannot use both options at once");
323 exit(1);
324 }
325
326 /* Fall back to -bios */
327
328 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
329 if (!fname) {
330 error_report("Could not find ROM image '%s'", bios_name);
331 exit(1);
332 }
333 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0);
334 image_size = load_image_mr(fname, mr);
335 g_free(fname);
336 if (image_size < 0) {
337 error_report("Could not load ROM image '%s'", bios_name);
338 exit(1);
339 }
340 }
341
342 return pflash_blk0 || bios_name;
343 }
344
345 static void create_secure_ram(SBSAMachineState *sms,
346 MemoryRegion *secure_sysmem)
347 {
348 MemoryRegion *secram = g_new(MemoryRegion, 1);
349 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base;
350 hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size;
351
352 memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size,
353 &error_fatal);
354 memory_region_add_subregion(secure_sysmem, base, secram);
355 }
356
357 static void create_gic(SBSAMachineState *sms)
358 {
359 unsigned int smp_cpus = MACHINE(sms)->smp.cpus;
360 SysBusDevice *gicbusdev;
361 const char *gictype;
362 uint32_t redist0_capacity, redist0_count;
363 int i;
364
365 gictype = gicv3_class_name();
366
367 sms->gic = qdev_new(gictype);
368 qdev_prop_set_uint32(sms->gic, "revision", 3);
369 qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus);
370 /*
371 * Note that the num-irq property counts both internal and external
372 * interrupts; there are always 32 of the former (mandated by GIC spec).
373 */
374 qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32);
375 qdev_prop_set_bit(sms->gic, "has-security-extensions", true);
376
377 redist0_capacity =
378 sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE;
379 redist0_count = MIN(smp_cpus, redist0_capacity);
380
381 qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1);
382 qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count);
383
384 gicbusdev = SYS_BUS_DEVICE(sms->gic);
385 sysbus_realize_and_unref(gicbusdev, &error_fatal);
386 sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base);
387 sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base);
388
389 /*
390 * Wire the outputs from each CPU's generic timer and the GICv3
391 * maintenance interrupt signal to the appropriate GIC PPI inputs,
392 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
393 */
394 for (i = 0; i < smp_cpus; i++) {
395 DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
396 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
397 int irq;
398 /*
399 * Mapping from the output timer irq lines from the CPU to the
400 * GIC PPI inputs used for this board.
401 */
402 const int timer_irq[] = {
403 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
404 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
405 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
406 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
407 };
408
409 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
410 qdev_connect_gpio_out(cpudev, irq,
411 qdev_get_gpio_in(sms->gic,
412 ppibase + timer_irq[irq]));
413 }
414
415 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
416 qdev_get_gpio_in(sms->gic, ppibase
417 + ARCH_GIC_MAINT_IRQ));
418 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
419 qdev_get_gpio_in(sms->gic, ppibase
420 + VIRTUAL_PMU_IRQ));
421
422 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
423 sysbus_connect_irq(gicbusdev, i + smp_cpus,
424 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
425 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
426 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
427 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
428 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
429 }
430 }
431
432 static void create_uart(const SBSAMachineState *sms, int uart,
433 MemoryRegion *mem, Chardev *chr)
434 {
435 hwaddr base = sbsa_ref_memmap[uart].base;
436 int irq = sbsa_ref_irqmap[uart];
437 DeviceState *dev = qdev_new(TYPE_PL011);
438 SysBusDevice *s = SYS_BUS_DEVICE(dev);
439
440 qdev_prop_set_chr(dev, "chardev", chr);
441 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
442 memory_region_add_subregion(mem, base,
443 sysbus_mmio_get_region(s, 0));
444 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq));
445 }
446
447 static void create_rtc(const SBSAMachineState *sms)
448 {
449 hwaddr base = sbsa_ref_memmap[SBSA_RTC].base;
450 int irq = sbsa_ref_irqmap[SBSA_RTC];
451
452 sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq));
453 }
454
455 static DeviceState *gpio_key_dev;
456 static void sbsa_ref_powerdown_req(Notifier *n, void *opaque)
457 {
458 /* use gpio Pin 3 for power button event */
459 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
460 }
461
462 static Notifier sbsa_ref_powerdown_notifier = {
463 .notify = sbsa_ref_powerdown_req
464 };
465
466 static void create_gpio(const SBSAMachineState *sms)
467 {
468 DeviceState *pl061_dev;
469 hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base;
470 int irq = sbsa_ref_irqmap[SBSA_GPIO];
471
472 pl061_dev = sysbus_create_simple("pl061", base,
473 qdev_get_gpio_in(sms->gic, irq));
474
475 gpio_key_dev = sysbus_create_simple("gpio-key", -1,
476 qdev_get_gpio_in(pl061_dev, 3));
477
478 /* connect powerdown request */
479 qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier);
480 }
481
482 static void create_ahci(const SBSAMachineState *sms)
483 {
484 hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base;
485 int irq = sbsa_ref_irqmap[SBSA_AHCI];
486 DeviceState *dev;
487 DriveInfo *hd[NUM_SATA_PORTS];
488 SysbusAHCIState *sysahci;
489 AHCIState *ahci;
490 int i;
491
492 dev = qdev_new("sysbus-ahci");
493 qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS);
494 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
495 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
496 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq));
497
498 sysahci = SYSBUS_AHCI(dev);
499 ahci = &sysahci->ahci;
500 ide_drive_get(hd, ARRAY_SIZE(hd));
501 for (i = 0; i < ahci->ports; i++) {
502 if (hd[i] == NULL) {
503 continue;
504 }
505 ide_create_drive(&ahci->dev[i].port, 0, hd[i]);
506 }
507 }
508
509 static void create_ehci(const SBSAMachineState *sms)
510 {
511 hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base;
512 int irq = sbsa_ref_irqmap[SBSA_EHCI];
513
514 sysbus_create_simple("platform-ehci-usb", base,
515 qdev_get_gpio_in(sms->gic, irq));
516 }
517
518 static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
519 {
520 hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base;
521 int irq = sbsa_ref_irqmap[SBSA_SMMU];
522 DeviceState *dev;
523 int i;
524
525 dev = qdev_new("arm-smmuv3");
526
527 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
528 &error_abort);
529 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
530 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
531 for (i = 0; i < NUM_SMMU_IRQS; i++) {
532 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
533 qdev_get_gpio_in(sms->gic, irq + 1));
534 }
535 }
536
537 static void create_pcie(SBSAMachineState *sms)
538 {
539 hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base;
540 hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size;
541 hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base;
542 hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size;
543 hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base;
544 hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size;
545 hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base;
546 int irq = sbsa_ref_irqmap[SBSA_PCIE];
547 MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg;
548 MemoryRegion *ecam_alias, *ecam_reg;
549 DeviceState *dev;
550 PCIHostState *pci;
551 int i;
552
553 dev = qdev_new(TYPE_GPEX_HOST);
554 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
555
556 /* Map ECAM space */
557 ecam_alias = g_new0(MemoryRegion, 1);
558 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
559 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
560 ecam_reg, 0, size_ecam);
561 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
562
563 /* Map the MMIO space */
564 mmio_alias = g_new0(MemoryRegion, 1);
565 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
566 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
567 mmio_reg, base_mmio, size_mmio);
568 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
569
570 /* Map the MMIO_HIGH space */
571 mmio_alias_high = g_new0(MemoryRegion, 1);
572 memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high",
573 mmio_reg, base_mmio_high, size_mmio_high);
574 memory_region_add_subregion(get_system_memory(), base_mmio_high,
575 mmio_alias_high);
576
577 /* Map IO port space */
578 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
579
580 for (i = 0; i < GPEX_NUM_IRQS; i++) {
581 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
582 qdev_get_gpio_in(sms->gic, irq + i));
583 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
584 }
585
586 pci = PCI_HOST_BRIDGE(dev);
587 if (pci->bus) {
588 for (i = 0; i < nb_nics; i++) {
589 NICInfo *nd = &nd_table[i];
590
591 if (!nd->model) {
592 nd->model = g_strdup("e1000e");
593 }
594
595 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
596 }
597 }
598
599 pci_create_simple(pci->bus, -1, "VGA");
600
601 create_smmu(sms, pci->bus);
602 }
603
604 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size)
605 {
606 const SBSAMachineState *board = container_of(binfo, SBSAMachineState,
607 bootinfo);
608
609 *fdt_size = board->fdt_size;
610 return board->fdt;
611 }
612
613 static void create_secure_ec(MemoryRegion *mem)
614 {
615 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_EC].base;
616 DeviceState *dev = qdev_new("sbsa-ec");
617 SysBusDevice *s = SYS_BUS_DEVICE(dev);
618
619 memory_region_add_subregion(mem, base,
620 sysbus_mmio_get_region(s, 0));
621 }
622
623 static void sbsa_ref_init(MachineState *machine)
624 {
625 unsigned int smp_cpus = machine->smp.cpus;
626 unsigned int max_cpus = machine->smp.max_cpus;
627 SBSAMachineState *sms = SBSA_MACHINE(machine);
628 MachineClass *mc = MACHINE_GET_CLASS(machine);
629 MemoryRegion *sysmem = get_system_memory();
630 MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1);
631 bool firmware_loaded;
632 const CPUArchIdList *possible_cpus;
633 int n, sbsa_max_cpus;
634
635 if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) {
636 error_report("sbsa-ref: CPU type other than the built-in "
637 "cortex-a57 not supported");
638 exit(1);
639 }
640
641 if (kvm_enabled()) {
642 error_report("sbsa-ref: KVM is not supported for this machine");
643 exit(1);
644 }
645
646 /*
647 * The Secure view of the world is the same as the NonSecure,
648 * but with a few extra devices. Create it as a container region
649 * containing the system memory at low priority; any secure-only
650 * devices go in at higher priority and take precedence.
651 */
652 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
653 UINT64_MAX);
654 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
655
656 firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem);
657
658 if (machine->kernel_filename && firmware_loaded) {
659 error_report("sbsa-ref: No fw_cfg device on this machine, "
660 "so -kernel option is not supported when firmware loaded, "
661 "please load OS from hard disk instead");
662 exit(1);
663 }
664
665 /*
666 * This machine has EL3 enabled, external firmware should supply PSCI
667 * implementation, so the QEMU's internal PSCI is disabled.
668 */
669 sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
670
671 sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE;
672
673 if (max_cpus > sbsa_max_cpus) {
674 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
675 "supported by machine 'sbsa-ref' (%d)",
676 max_cpus, sbsa_max_cpus);
677 exit(1);
678 }
679
680 sms->smp_cpus = smp_cpus;
681
682 if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) {
683 error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB);
684 exit(1);
685 }
686
687 possible_cpus = mc->possible_cpu_arch_ids(machine);
688 for (n = 0; n < possible_cpus->len; n++) {
689 Object *cpuobj;
690 CPUState *cs;
691
692 if (n >= smp_cpus) {
693 break;
694 }
695
696 cpuobj = object_new(possible_cpus->cpus[n].type);
697 object_property_set_int(cpuobj, "mp-affinity",
698 possible_cpus->cpus[n].arch_id, NULL);
699
700 cs = CPU(cpuobj);
701 cs->cpu_index = n;
702
703 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
704 &error_fatal);
705
706 if (object_property_find(cpuobj, "reset-cbar", NULL)) {
707 object_property_set_int(cpuobj, "reset-cbar",
708 sbsa_ref_memmap[SBSA_CPUPERIPHS].base,
709 &error_abort);
710 }
711
712 object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
713 &error_abort);
714
715 object_property_set_link(cpuobj, "secure-memory",
716 OBJECT(secure_sysmem), &error_abort);
717
718 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
719 object_unref(cpuobj);
720 }
721
722 memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base,
723 machine->ram);
724
725 create_fdt(sms);
726
727 create_secure_ram(sms, secure_sysmem);
728
729 create_gic(sms);
730
731 create_uart(sms, SBSA_UART, sysmem, serial_hd(0));
732 create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1));
733 /* Second secure UART for RAS and MM from EL0 */
734 create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2));
735
736 create_rtc(sms);
737
738 create_gpio(sms);
739
740 create_ahci(sms);
741
742 create_ehci(sms);
743
744 create_pcie(sms);
745
746 create_secure_ec(secure_sysmem);
747
748 sms->bootinfo.ram_size = machine->ram_size;
749 sms->bootinfo.nb_cpus = smp_cpus;
750 sms->bootinfo.board_id = -1;
751 sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base;
752 sms->bootinfo.get_dtb = sbsa_ref_dtb;
753 sms->bootinfo.firmware_loaded = firmware_loaded;
754 arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo);
755 }
756
757 static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms)
758 {
759 unsigned int max_cpus = ms->smp.max_cpus;
760 SBSAMachineState *sms = SBSA_MACHINE(ms);
761 int n;
762
763 if (ms->possible_cpus) {
764 assert(ms->possible_cpus->len == max_cpus);
765 return ms->possible_cpus;
766 }
767
768 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
769 sizeof(CPUArchId) * max_cpus);
770 ms->possible_cpus->len = max_cpus;
771 for (n = 0; n < ms->possible_cpus->len; n++) {
772 ms->possible_cpus->cpus[n].type = ms->cpu_type;
773 ms->possible_cpus->cpus[n].arch_id =
774 sbsa_ref_cpu_mp_affinity(sms, n);
775 ms->possible_cpus->cpus[n].props.has_thread_id = true;
776 ms->possible_cpus->cpus[n].props.thread_id = n;
777 }
778 return ms->possible_cpus;
779 }
780
781 static CpuInstanceProperties
782 sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
783 {
784 MachineClass *mc = MACHINE_GET_CLASS(ms);
785 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
786
787 assert(cpu_index < possible_cpus->len);
788 return possible_cpus->cpus[cpu_index].props;
789 }
790
791 static int64_t
792 sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx)
793 {
794 return idx % ms->numa_state->num_nodes;
795 }
796
797 static void sbsa_ref_instance_init(Object *obj)
798 {
799 SBSAMachineState *sms = SBSA_MACHINE(obj);
800
801 sbsa_flash_create(sms);
802 }
803
804 static void sbsa_ref_class_init(ObjectClass *oc, void *data)
805 {
806 MachineClass *mc = MACHINE_CLASS(oc);
807
808 mc->init = sbsa_ref_init;
809 mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine";
810 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a57");
811 mc->max_cpus = 512;
812 mc->pci_allow_0_address = true;
813 mc->minimum_page_bits = 12;
814 mc->block_default_type = IF_IDE;
815 mc->no_cdrom = 1;
816 mc->default_ram_size = 1 * GiB;
817 mc->default_ram_id = "sbsa-ref.ram";
818 mc->default_cpus = 4;
819 mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids;
820 mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props;
821 mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id;
822 }
823
824 static const TypeInfo sbsa_ref_info = {
825 .name = TYPE_SBSA_MACHINE,
826 .parent = TYPE_MACHINE,
827 .instance_init = sbsa_ref_instance_init,
828 .class_init = sbsa_ref_class_init,
829 .instance_size = sizeof(SBSAMachineState),
830 };
831
832 static void sbsa_ref_machine_init(void)
833 {
834 type_register_static(&sbsa_ref_info);
835 }
836
837 type_init(sbsa_ref_machine_init);