arm/stm32f405: Fix realization of "stm32f2xx-adc" devices
[qemu.git] / hw / arm / stm32f405_soc.c
1 /*
2 * STM32F405 SoC
3 *
4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qapi/error.h"
27 #include "qemu-common.h"
28 #include "exec/address-spaces.h"
29 #include "sysemu/sysemu.h"
30 #include "hw/arm/stm32f405_soc.h"
31 #include "hw/misc/unimp.h"
32
33 #define SYSCFG_ADD 0x40013800
34 static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800,
35 0x40004C00, 0x40005000, 0x40011400,
36 0x40007800, 0x40007C00 };
37 /* At the moment only Timer 2 to 5 are modelled */
38 static const uint32_t timer_addr[] = { 0x40000000, 0x40000400,
39 0x40000800, 0x40000C00 };
40 static const uint32_t adc_addr[] = { 0x40012000, 0x40012100, 0x40012200,
41 0x40012300, 0x40012400, 0x40012500 };
42 static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00,
43 0x40013400, 0x40015000, 0x40015400 };
44 #define EXTI_ADDR 0x40013C00
45
46 #define SYSCFG_IRQ 71
47 static const int usart_irq[] = { 37, 38, 39, 52, 53, 71, 82, 83 };
48 static const int timer_irq[] = { 28, 29, 30, 50 };
49 #define ADC_IRQ 18
50 static const int spi_irq[] = { 35, 36, 51, 0, 0, 0 };
51 static const int exti_irq[] = { 6, 7, 8, 9, 10, 23, 23, 23, 23, 23, 40,
52 40, 40, 40, 40, 40} ;
53
54
55 static void stm32f405_soc_initfn(Object *obj)
56 {
57 STM32F405State *s = STM32F405_SOC(obj);
58 int i;
59
60 sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m),
61 TYPE_ARMV7M);
62
63 sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg),
64 TYPE_STM32F4XX_SYSCFG);
65
66 for (i = 0; i < STM_NUM_USARTS; i++) {
67 sysbus_init_child_obj(obj, "usart[*]", &s->usart[i],
68 sizeof(s->usart[i]), TYPE_STM32F2XX_USART);
69 }
70
71 for (i = 0; i < STM_NUM_TIMERS; i++) {
72 sysbus_init_child_obj(obj, "timer[*]", &s->timer[i],
73 sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER);
74 }
75
76 for (i = 0; i < STM_NUM_ADCS; i++) {
77 sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]),
78 TYPE_STM32F2XX_ADC);
79 }
80
81 for (i = 0; i < STM_NUM_SPIS; i++) {
82 sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
83 TYPE_STM32F2XX_SPI);
84 }
85
86 sysbus_init_child_obj(obj, "exti", &s->exti, sizeof(s->exti),
87 TYPE_STM32F4XX_EXTI);
88 }
89
90 static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
91 {
92 STM32F405State *s = STM32F405_SOC(dev_soc);
93 MemoryRegion *system_memory = get_system_memory();
94 DeviceState *dev, *armv7m;
95 SysBusDevice *busdev;
96 Error *err = NULL;
97 int i;
98
99 memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F405.flash",
100 FLASH_SIZE, &err);
101 if (err != NULL) {
102 error_propagate(errp, err);
103 return;
104 }
105 memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
106 "STM32F405.flash.alias", &s->flash, 0,
107 FLASH_SIZE);
108
109 memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);
110 memory_region_add_subregion(system_memory, 0, &s->flash_alias);
111
112 memory_region_init_ram(&s->sram, NULL, "STM32F405.sram", SRAM_SIZE,
113 &err);
114 if (err != NULL) {
115 error_propagate(errp, err);
116 return;
117 }
118 memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
119
120 armv7m = DEVICE(&s->armv7m);
121 qdev_prop_set_uint32(armv7m, "num-irq", 96);
122 qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
123 qdev_prop_set_bit(armv7m, "enable-bitband", true);
124 object_property_set_link(OBJECT(&s->armv7m), OBJECT(system_memory),
125 "memory", &error_abort);
126 object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
127 if (err != NULL) {
128 error_propagate(errp, err);
129 return;
130 }
131
132 /* System configuration controller */
133 dev = DEVICE(&s->syscfg);
134 object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
135 if (err != NULL) {
136 error_propagate(errp, err);
137 return;
138 }
139 busdev = SYS_BUS_DEVICE(dev);
140 sysbus_mmio_map(busdev, 0, SYSCFG_ADD);
141 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, SYSCFG_IRQ));
142
143 /* Attach UART (uses USART registers) and USART controllers */
144 for (i = 0; i < STM_NUM_USARTS; i++) {
145 dev = DEVICE(&(s->usart[i]));
146 qdev_prop_set_chr(dev, "chardev", serial_hd(i));
147 object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
148 if (err != NULL) {
149 error_propagate(errp, err);
150 return;
151 }
152 busdev = SYS_BUS_DEVICE(dev);
153 sysbus_mmio_map(busdev, 0, usart_addr[i]);
154 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
155 }
156
157 /* Timer 2 to 5 */
158 for (i = 0; i < STM_NUM_TIMERS; i++) {
159 dev = DEVICE(&(s->timer[i]));
160 qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
161 object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
162 if (err != NULL) {
163 error_propagate(errp, err);
164 return;
165 }
166 busdev = SYS_BUS_DEVICE(dev);
167 sysbus_mmio_map(busdev, 0, timer_addr[i]);
168 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
169 }
170
171 /* ADC device, the IRQs are ORed together */
172 object_initialize_child(OBJECT(s), "adc-orirq", &s->adc_irqs,
173 sizeof(s->adc_irqs), TYPE_OR_IRQ,
174 &err, NULL);
175 if (err != NULL) {
176 error_propagate(errp, err);
177 return;
178 }
179 object_property_set_int(OBJECT(&s->adc_irqs), STM_NUM_ADCS,
180 "num-lines", &err);
181 object_property_set_bool(OBJECT(&s->adc_irqs), true, "realized", &err);
182 if (err != NULL) {
183 error_propagate(errp, err);
184 return;
185 }
186 qdev_connect_gpio_out(DEVICE(&s->adc_irqs), 0,
187 qdev_get_gpio_in(armv7m, ADC_IRQ));
188
189 for (i = 0; i < STM_NUM_ADCS; i++) {
190 dev = DEVICE(&(s->adc[i]));
191 object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
192 if (err != NULL) {
193 error_propagate(errp, err);
194 return;
195 }
196 busdev = SYS_BUS_DEVICE(dev);
197 sysbus_mmio_map(busdev, 0, adc_addr[i]);
198 sysbus_connect_irq(busdev, 0,
199 qdev_get_gpio_in(DEVICE(&s->adc_irqs), i));
200 }
201
202 /* SPI devices */
203 for (i = 0; i < STM_NUM_SPIS; i++) {
204 dev = DEVICE(&(s->spi[i]));
205 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
206 if (err != NULL) {
207 error_propagate(errp, err);
208 return;
209 }
210 busdev = SYS_BUS_DEVICE(dev);
211 sysbus_mmio_map(busdev, 0, spi_addr[i]);
212 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
213 }
214
215 /* EXTI device */
216 dev = DEVICE(&s->exti);
217 object_property_set_bool(OBJECT(&s->exti), true, "realized", &err);
218 if (err != NULL) {
219 error_propagate(errp, err);
220 return;
221 }
222 busdev = SYS_BUS_DEVICE(dev);
223 sysbus_mmio_map(busdev, 0, EXTI_ADDR);
224 for (i = 0; i < 16; i++) {
225 sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i]));
226 }
227 for (i = 0; i < 16; i++) {
228 qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(dev, i));
229 }
230
231 create_unimplemented_device("timer[7]", 0x40001400, 0x400);
232 create_unimplemented_device("timer[12]", 0x40001800, 0x400);
233 create_unimplemented_device("timer[6]", 0x40001000, 0x400);
234 create_unimplemented_device("timer[13]", 0x40001C00, 0x400);
235 create_unimplemented_device("timer[14]", 0x40002000, 0x400);
236 create_unimplemented_device("RTC and BKP", 0x40002800, 0x400);
237 create_unimplemented_device("WWDG", 0x40002C00, 0x400);
238 create_unimplemented_device("IWDG", 0x40003000, 0x400);
239 create_unimplemented_device("I2S2ext", 0x40003000, 0x400);
240 create_unimplemented_device("I2S3ext", 0x40004000, 0x400);
241 create_unimplemented_device("I2C1", 0x40005400, 0x400);
242 create_unimplemented_device("I2C2", 0x40005800, 0x400);
243 create_unimplemented_device("I2C3", 0x40005C00, 0x400);
244 create_unimplemented_device("CAN1", 0x40006400, 0x400);
245 create_unimplemented_device("CAN2", 0x40006800, 0x400);
246 create_unimplemented_device("PWR", 0x40007000, 0x400);
247 create_unimplemented_device("DAC", 0x40007400, 0x400);
248 create_unimplemented_device("timer[1]", 0x40010000, 0x400);
249 create_unimplemented_device("timer[8]", 0x40010400, 0x400);
250 create_unimplemented_device("SDIO", 0x40012C00, 0x400);
251 create_unimplemented_device("timer[9]", 0x40014000, 0x400);
252 create_unimplemented_device("timer[10]", 0x40014400, 0x400);
253 create_unimplemented_device("timer[11]", 0x40014800, 0x400);
254 create_unimplemented_device("GPIOA", 0x40020000, 0x400);
255 create_unimplemented_device("GPIOB", 0x40020400, 0x400);
256 create_unimplemented_device("GPIOC", 0x40020800, 0x400);
257 create_unimplemented_device("GPIOD", 0x40020C00, 0x400);
258 create_unimplemented_device("GPIOE", 0x40021000, 0x400);
259 create_unimplemented_device("GPIOF", 0x40021400, 0x400);
260 create_unimplemented_device("GPIOG", 0x40021800, 0x400);
261 create_unimplemented_device("GPIOH", 0x40021C00, 0x400);
262 create_unimplemented_device("GPIOI", 0x40022000, 0x400);
263 create_unimplemented_device("CRC", 0x40023000, 0x400);
264 create_unimplemented_device("RCC", 0x40023800, 0x400);
265 create_unimplemented_device("Flash Int", 0x40023C00, 0x400);
266 create_unimplemented_device("BKPSRAM", 0x40024000, 0x400);
267 create_unimplemented_device("DMA1", 0x40026000, 0x400);
268 create_unimplemented_device("DMA2", 0x40026400, 0x400);
269 create_unimplemented_device("Ethernet", 0x40028000, 0x1400);
270 create_unimplemented_device("USB OTG HS", 0x40040000, 0x30000);
271 create_unimplemented_device("USB OTG FS", 0x50000000, 0x31000);
272 create_unimplemented_device("DCMI", 0x50050000, 0x400);
273 create_unimplemented_device("RNG", 0x50060800, 0x400);
274 }
275
276 static Property stm32f405_soc_properties[] = {
277 DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type),
278 DEFINE_PROP_END_OF_LIST(),
279 };
280
281 static void stm32f405_soc_class_init(ObjectClass *klass, void *data)
282 {
283 DeviceClass *dc = DEVICE_CLASS(klass);
284
285 dc->realize = stm32f405_soc_realize;
286 device_class_set_props(dc, stm32f405_soc_properties);
287 /* No vmstate or reset required: device has no internal state */
288 }
289
290 static const TypeInfo stm32f405_soc_info = {
291 .name = TYPE_STM32F405_SOC,
292 .parent = TYPE_SYS_BUS_DEVICE,
293 .instance_size = sizeof(STM32F405State),
294 .instance_init = stm32f405_soc_initfn,
295 .class_init = stm32f405_soc_class_init,
296 };
297
298 static void stm32f405_soc_types(void)
299 {
300 type_register_static(&stm32f405_soc_info);
301 }
302
303 type_init(stm32f405_soc_types)