Merge remote-tracking branch 'remotes/philmd-gitlab/tags/renesas-20201027' into staging
[qemu.git] / hw / arm / stm32f405_soc.c
1 /*
2 * STM32F405 SoC
3 *
4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qapi/error.h"
27 #include "qemu-common.h"
28 #include "exec/address-spaces.h"
29 #include "sysemu/sysemu.h"
30 #include "hw/arm/stm32f405_soc.h"
31 #include "hw/misc/unimp.h"
32
33 #define SYSCFG_ADD 0x40013800
34 static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800,
35 0x40004C00, 0x40005000, 0x40011400,
36 0x40007800, 0x40007C00 };
37 /* At the moment only Timer 2 to 5 are modelled */
38 static const uint32_t timer_addr[] = { 0x40000000, 0x40000400,
39 0x40000800, 0x40000C00 };
40 static const uint32_t adc_addr[] = { 0x40012000, 0x40012100, 0x40012200,
41 0x40012300, 0x40012400, 0x40012500 };
42 static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00,
43 0x40013400, 0x40015000, 0x40015400 };
44 #define EXTI_ADDR 0x40013C00
45
46 #define SYSCFG_IRQ 71
47 static const int usart_irq[] = { 37, 38, 39, 52, 53, 71, 82, 83 };
48 static const int timer_irq[] = { 28, 29, 30, 50 };
49 #define ADC_IRQ 18
50 static const int spi_irq[] = { 35, 36, 51, 0, 0, 0 };
51 static const int exti_irq[] = { 6, 7, 8, 9, 10, 23, 23, 23, 23, 23, 40,
52 40, 40, 40, 40, 40} ;
53
54
55 static void stm32f405_soc_initfn(Object *obj)
56 {
57 STM32F405State *s = STM32F405_SOC(obj);
58 int i;
59
60 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
61
62 object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F4XX_SYSCFG);
63
64 for (i = 0; i < STM_NUM_USARTS; i++) {
65 object_initialize_child(obj, "usart[*]", &s->usart[i],
66 TYPE_STM32F2XX_USART);
67 }
68
69 for (i = 0; i < STM_NUM_TIMERS; i++) {
70 object_initialize_child(obj, "timer[*]", &s->timer[i],
71 TYPE_STM32F2XX_TIMER);
72 }
73
74 for (i = 0; i < STM_NUM_ADCS; i++) {
75 object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC);
76 }
77
78 for (i = 0; i < STM_NUM_SPIS; i++) {
79 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
80 }
81
82 object_initialize_child(obj, "exti", &s->exti, TYPE_STM32F4XX_EXTI);
83 }
84
85 static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
86 {
87 STM32F405State *s = STM32F405_SOC(dev_soc);
88 MemoryRegion *system_memory = get_system_memory();
89 DeviceState *dev, *armv7m;
90 SysBusDevice *busdev;
91 Error *err = NULL;
92 int i;
93
94 memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F405.flash",
95 FLASH_SIZE, &err);
96 if (err != NULL) {
97 error_propagate(errp, err);
98 return;
99 }
100 memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
101 "STM32F405.flash.alias", &s->flash, 0,
102 FLASH_SIZE);
103
104 memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);
105 memory_region_add_subregion(system_memory, 0, &s->flash_alias);
106
107 memory_region_init_ram(&s->sram, NULL, "STM32F405.sram", SRAM_SIZE,
108 &err);
109 if (err != NULL) {
110 error_propagate(errp, err);
111 return;
112 }
113 memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
114
115 armv7m = DEVICE(&s->armv7m);
116 qdev_prop_set_uint32(armv7m, "num-irq", 96);
117 qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
118 qdev_prop_set_bit(armv7m, "enable-bitband", true);
119 object_property_set_link(OBJECT(&s->armv7m), "memory",
120 OBJECT(system_memory), &error_abort);
121 if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
122 return;
123 }
124
125 /* System configuration controller */
126 dev = DEVICE(&s->syscfg);
127 if (!sysbus_realize(SYS_BUS_DEVICE(&s->syscfg), errp)) {
128 return;
129 }
130 busdev = SYS_BUS_DEVICE(dev);
131 sysbus_mmio_map(busdev, 0, SYSCFG_ADD);
132 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, SYSCFG_IRQ));
133
134 /* Attach UART (uses USART registers) and USART controllers */
135 for (i = 0; i < STM_NUM_USARTS; i++) {
136 dev = DEVICE(&(s->usart[i]));
137 qdev_prop_set_chr(dev, "chardev", serial_hd(i));
138 if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) {
139 return;
140 }
141 busdev = SYS_BUS_DEVICE(dev);
142 sysbus_mmio_map(busdev, 0, usart_addr[i]);
143 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
144 }
145
146 /* Timer 2 to 5 */
147 for (i = 0; i < STM_NUM_TIMERS; i++) {
148 dev = DEVICE(&(s->timer[i]));
149 qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
150 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), errp)) {
151 return;
152 }
153 busdev = SYS_BUS_DEVICE(dev);
154 sysbus_mmio_map(busdev, 0, timer_addr[i]);
155 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
156 }
157
158 /* ADC device, the IRQs are ORed together */
159 if (!object_initialize_child_with_props(OBJECT(s), "adc-orirq",
160 &s->adc_irqs, sizeof(s->adc_irqs),
161 TYPE_OR_IRQ, errp, NULL)) {
162 return;
163 }
164 object_property_set_int(OBJECT(&s->adc_irqs), "num-lines", STM_NUM_ADCS,
165 &error_abort);
166 if (!qdev_realize(DEVICE(&s->adc_irqs), NULL, errp)) {
167 return;
168 }
169 qdev_connect_gpio_out(DEVICE(&s->adc_irqs), 0,
170 qdev_get_gpio_in(armv7m, ADC_IRQ));
171
172 for (i = 0; i < STM_NUM_ADCS; i++) {
173 dev = DEVICE(&(s->adc[i]));
174 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc[i]), errp)) {
175 return;
176 }
177 busdev = SYS_BUS_DEVICE(dev);
178 sysbus_mmio_map(busdev, 0, adc_addr[i]);
179 sysbus_connect_irq(busdev, 0,
180 qdev_get_gpio_in(DEVICE(&s->adc_irqs), i));
181 }
182
183 /* SPI devices */
184 for (i = 0; i < STM_NUM_SPIS; i++) {
185 dev = DEVICE(&(s->spi[i]));
186 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
187 return;
188 }
189 busdev = SYS_BUS_DEVICE(dev);
190 sysbus_mmio_map(busdev, 0, spi_addr[i]);
191 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
192 }
193
194 /* EXTI device */
195 dev = DEVICE(&s->exti);
196 if (!sysbus_realize(SYS_BUS_DEVICE(&s->exti), errp)) {
197 return;
198 }
199 busdev = SYS_BUS_DEVICE(dev);
200 sysbus_mmio_map(busdev, 0, EXTI_ADDR);
201 for (i = 0; i < 16; i++) {
202 sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i]));
203 }
204 for (i = 0; i < 16; i++) {
205 qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(dev, i));
206 }
207
208 create_unimplemented_device("timer[7]", 0x40001400, 0x400);
209 create_unimplemented_device("timer[12]", 0x40001800, 0x400);
210 create_unimplemented_device("timer[6]", 0x40001000, 0x400);
211 create_unimplemented_device("timer[13]", 0x40001C00, 0x400);
212 create_unimplemented_device("timer[14]", 0x40002000, 0x400);
213 create_unimplemented_device("RTC and BKP", 0x40002800, 0x400);
214 create_unimplemented_device("WWDG", 0x40002C00, 0x400);
215 create_unimplemented_device("IWDG", 0x40003000, 0x400);
216 create_unimplemented_device("I2S2ext", 0x40003000, 0x400);
217 create_unimplemented_device("I2S3ext", 0x40004000, 0x400);
218 create_unimplemented_device("I2C1", 0x40005400, 0x400);
219 create_unimplemented_device("I2C2", 0x40005800, 0x400);
220 create_unimplemented_device("I2C3", 0x40005C00, 0x400);
221 create_unimplemented_device("CAN1", 0x40006400, 0x400);
222 create_unimplemented_device("CAN2", 0x40006800, 0x400);
223 create_unimplemented_device("PWR", 0x40007000, 0x400);
224 create_unimplemented_device("DAC", 0x40007400, 0x400);
225 create_unimplemented_device("timer[1]", 0x40010000, 0x400);
226 create_unimplemented_device("timer[8]", 0x40010400, 0x400);
227 create_unimplemented_device("SDIO", 0x40012C00, 0x400);
228 create_unimplemented_device("timer[9]", 0x40014000, 0x400);
229 create_unimplemented_device("timer[10]", 0x40014400, 0x400);
230 create_unimplemented_device("timer[11]", 0x40014800, 0x400);
231 create_unimplemented_device("GPIOA", 0x40020000, 0x400);
232 create_unimplemented_device("GPIOB", 0x40020400, 0x400);
233 create_unimplemented_device("GPIOC", 0x40020800, 0x400);
234 create_unimplemented_device("GPIOD", 0x40020C00, 0x400);
235 create_unimplemented_device("GPIOE", 0x40021000, 0x400);
236 create_unimplemented_device("GPIOF", 0x40021400, 0x400);
237 create_unimplemented_device("GPIOG", 0x40021800, 0x400);
238 create_unimplemented_device("GPIOH", 0x40021C00, 0x400);
239 create_unimplemented_device("GPIOI", 0x40022000, 0x400);
240 create_unimplemented_device("CRC", 0x40023000, 0x400);
241 create_unimplemented_device("RCC", 0x40023800, 0x400);
242 create_unimplemented_device("Flash Int", 0x40023C00, 0x400);
243 create_unimplemented_device("BKPSRAM", 0x40024000, 0x400);
244 create_unimplemented_device("DMA1", 0x40026000, 0x400);
245 create_unimplemented_device("DMA2", 0x40026400, 0x400);
246 create_unimplemented_device("Ethernet", 0x40028000, 0x1400);
247 create_unimplemented_device("USB OTG HS", 0x40040000, 0x30000);
248 create_unimplemented_device("USB OTG FS", 0x50000000, 0x31000);
249 create_unimplemented_device("DCMI", 0x50050000, 0x400);
250 create_unimplemented_device("RNG", 0x50060800, 0x400);
251 }
252
253 static Property stm32f405_soc_properties[] = {
254 DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type),
255 DEFINE_PROP_END_OF_LIST(),
256 };
257
258 static void stm32f405_soc_class_init(ObjectClass *klass, void *data)
259 {
260 DeviceClass *dc = DEVICE_CLASS(klass);
261
262 dc->realize = stm32f405_soc_realize;
263 device_class_set_props(dc, stm32f405_soc_properties);
264 /* No vmstate or reset required: device has no internal state */
265 }
266
267 static const TypeInfo stm32f405_soc_info = {
268 .name = TYPE_STM32F405_SOC,
269 .parent = TYPE_SYS_BUS_DEVICE,
270 .instance_size = sizeof(STM32F405State),
271 .instance_init = stm32f405_soc_initfn,
272 .class_init = stm32f405_soc_class_init,
273 };
274
275 static void stm32f405_soc_types(void)
276 {
277 type_register_static(&stm32f405_soc_info);
278 }
279
280 type_init(stm32f405_soc_types)