Merge remote-tracking branch 'remotes/ericb/tags/pull-bitmaps-2020-09-21' into staging
[qemu.git] / hw / arm / vexpress.c
1 /*
2 * ARM Versatile Express emulation.
3 *
4 * Copyright (c) 2010 - 2011 B Labs Ltd.
5 * Copyright (c) 2011 Linaro Limited
6 * Written by Bahadir Balban, Amit Mahajan, Peter Maydell
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 *
20 * Contributions after 2012-01-13 are licensed under the terms of the
21 * GNU GPL, version 2 or (at your option) any later version.
22 */
23
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
26 #include "qemu-common.h"
27 #include "cpu.h"
28 #include "hw/sysbus.h"
29 #include "hw/arm/boot.h"
30 #include "hw/arm/primecell.h"
31 #include "hw/net/lan9118.h"
32 #include "hw/i2c/i2c.h"
33 #include "net/net.h"
34 #include "sysemu/sysemu.h"
35 #include "hw/boards.h"
36 #include "hw/loader.h"
37 #include "exec/address-spaces.h"
38 #include "hw/block/flash.h"
39 #include "sysemu/device_tree.h"
40 #include "qemu/error-report.h"
41 #include <libfdt.h>
42 #include "hw/char/pl011.h"
43 #include "hw/cpu/a9mpcore.h"
44 #include "hw/cpu/a15mpcore.h"
45 #include "hw/i2c/arm_sbcon_i2c.h"
46 #include "hw/sd/sd.h"
47 #include "qom/object.h"
48
49 #define VEXPRESS_BOARD_ID 0x8e0
50 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
51 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024)
52
53 /* Number of virtio transports to create (0..8; limited by
54 * number of available IRQ lines).
55 */
56 #define NUM_VIRTIO_TRANSPORTS 4
57
58 /* Address maps for peripherals:
59 * the Versatile Express motherboard has two possible maps,
60 * the "legacy" one (used for A9) and the "Cortex-A Series"
61 * map (used for newer cores).
62 * Individual daughterboards can also have different maps for
63 * their peripherals.
64 */
65
66 enum {
67 VE_SYSREGS,
68 VE_SP810,
69 VE_SERIALPCI,
70 VE_PL041,
71 VE_MMCI,
72 VE_KMI0,
73 VE_KMI1,
74 VE_UART0,
75 VE_UART1,
76 VE_UART2,
77 VE_UART3,
78 VE_WDT,
79 VE_TIMER01,
80 VE_TIMER23,
81 VE_SERIALDVI,
82 VE_RTC,
83 VE_COMPACTFLASH,
84 VE_CLCD,
85 VE_NORFLASH0,
86 VE_NORFLASH1,
87 VE_NORFLASHALIAS,
88 VE_SRAM,
89 VE_VIDEORAM,
90 VE_ETHERNET,
91 VE_USB,
92 VE_DAPROM,
93 VE_VIRTIO,
94 };
95
96 static hwaddr motherboard_legacy_map[] = {
97 [VE_NORFLASHALIAS] = 0,
98 /* CS7: 0x10000000 .. 0x10020000 */
99 [VE_SYSREGS] = 0x10000000,
100 [VE_SP810] = 0x10001000,
101 [VE_SERIALPCI] = 0x10002000,
102 [VE_PL041] = 0x10004000,
103 [VE_MMCI] = 0x10005000,
104 [VE_KMI0] = 0x10006000,
105 [VE_KMI1] = 0x10007000,
106 [VE_UART0] = 0x10009000,
107 [VE_UART1] = 0x1000a000,
108 [VE_UART2] = 0x1000b000,
109 [VE_UART3] = 0x1000c000,
110 [VE_WDT] = 0x1000f000,
111 [VE_TIMER01] = 0x10011000,
112 [VE_TIMER23] = 0x10012000,
113 [VE_VIRTIO] = 0x10013000,
114 [VE_SERIALDVI] = 0x10016000,
115 [VE_RTC] = 0x10017000,
116 [VE_COMPACTFLASH] = 0x1001a000,
117 [VE_CLCD] = 0x1001f000,
118 /* CS0: 0x40000000 .. 0x44000000 */
119 [VE_NORFLASH0] = 0x40000000,
120 /* CS1: 0x44000000 .. 0x48000000 */
121 [VE_NORFLASH1] = 0x44000000,
122 /* CS2: 0x48000000 .. 0x4a000000 */
123 [VE_SRAM] = 0x48000000,
124 /* CS3: 0x4c000000 .. 0x50000000 */
125 [VE_VIDEORAM] = 0x4c000000,
126 [VE_ETHERNET] = 0x4e000000,
127 [VE_USB] = 0x4f000000,
128 };
129
130 static hwaddr motherboard_aseries_map[] = {
131 [VE_NORFLASHALIAS] = 0,
132 /* CS0: 0x08000000 .. 0x0c000000 */
133 [VE_NORFLASH0] = 0x08000000,
134 /* CS4: 0x0c000000 .. 0x10000000 */
135 [VE_NORFLASH1] = 0x0c000000,
136 /* CS5: 0x10000000 .. 0x14000000 */
137 /* CS1: 0x14000000 .. 0x18000000 */
138 [VE_SRAM] = 0x14000000,
139 /* CS2: 0x18000000 .. 0x1c000000 */
140 [VE_VIDEORAM] = 0x18000000,
141 [VE_ETHERNET] = 0x1a000000,
142 [VE_USB] = 0x1b000000,
143 /* CS3: 0x1c000000 .. 0x20000000 */
144 [VE_DAPROM] = 0x1c000000,
145 [VE_SYSREGS] = 0x1c010000,
146 [VE_SP810] = 0x1c020000,
147 [VE_SERIALPCI] = 0x1c030000,
148 [VE_PL041] = 0x1c040000,
149 [VE_MMCI] = 0x1c050000,
150 [VE_KMI0] = 0x1c060000,
151 [VE_KMI1] = 0x1c070000,
152 [VE_UART0] = 0x1c090000,
153 [VE_UART1] = 0x1c0a0000,
154 [VE_UART2] = 0x1c0b0000,
155 [VE_UART3] = 0x1c0c0000,
156 [VE_WDT] = 0x1c0f0000,
157 [VE_TIMER01] = 0x1c110000,
158 [VE_TIMER23] = 0x1c120000,
159 [VE_VIRTIO] = 0x1c130000,
160 [VE_SERIALDVI] = 0x1c160000,
161 [VE_RTC] = 0x1c170000,
162 [VE_COMPACTFLASH] = 0x1c1a0000,
163 [VE_CLCD] = 0x1c1f0000,
164 };
165
166 /* Structure defining the peculiarities of a specific daughterboard */
167
168 typedef struct VEDBoardInfo VEDBoardInfo;
169
170 struct VexpressMachineClass {
171 MachineClass parent;
172 VEDBoardInfo *daughterboard;
173 };
174
175 struct VexpressMachineState {
176 MachineState parent;
177 bool secure;
178 bool virt;
179 };
180
181 #define TYPE_VEXPRESS_MACHINE "vexpress"
182 #define TYPE_VEXPRESS_A9_MACHINE MACHINE_TYPE_NAME("vexpress-a9")
183 #define TYPE_VEXPRESS_A15_MACHINE MACHINE_TYPE_NAME("vexpress-a15")
184 OBJECT_DECLARE_TYPE(VexpressMachineState, VexpressMachineClass, VEXPRESS_MACHINE)
185
186 typedef void DBoardInitFn(const VexpressMachineState *machine,
187 ram_addr_t ram_size,
188 const char *cpu_type,
189 qemu_irq *pic);
190
191 struct VEDBoardInfo {
192 struct arm_boot_info bootinfo;
193 const hwaddr *motherboard_map;
194 hwaddr loader_start;
195 const hwaddr gic_cpu_if_addr;
196 uint32_t proc_id;
197 uint32_t num_voltage_sensors;
198 const uint32_t *voltages;
199 uint32_t num_clocks;
200 const uint32_t *clocks;
201 DBoardInitFn *init;
202 };
203
204 static void init_cpus(MachineState *ms, const char *cpu_type,
205 const char *privdev, hwaddr periphbase,
206 qemu_irq *pic, bool secure, bool virt)
207 {
208 DeviceState *dev;
209 SysBusDevice *busdev;
210 int n;
211 unsigned int smp_cpus = ms->smp.cpus;
212
213 /* Create the actual CPUs */
214 for (n = 0; n < smp_cpus; n++) {
215 Object *cpuobj = object_new(cpu_type);
216
217 if (!secure) {
218 object_property_set_bool(cpuobj, "has_el3", false, NULL);
219 }
220 if (!virt) {
221 if (object_property_find(cpuobj, "has_el2", NULL)) {
222 object_property_set_bool(cpuobj, "has_el2", false, NULL);
223 }
224 }
225
226 if (object_property_find(cpuobj, "reset-cbar", NULL)) {
227 object_property_set_int(cpuobj, "reset-cbar", periphbase,
228 &error_abort);
229 }
230 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
231 }
232
233 /* Create the private peripheral devices (including the GIC);
234 * this must happen after the CPUs are created because a15mpcore_priv
235 * wires itself up to the CPU's generic_timer gpio out lines.
236 */
237 dev = qdev_new(privdev);
238 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
239 busdev = SYS_BUS_DEVICE(dev);
240 sysbus_realize_and_unref(busdev, &error_fatal);
241 sysbus_mmio_map(busdev, 0, periphbase);
242
243 /* Interrupts [42:0] are from the motherboard;
244 * [47:43] are reserved; [63:48] are daughterboard
245 * peripherals. Note that some documentation numbers
246 * external interrupts starting from 32 (because there
247 * are internal interrupts 0..31).
248 */
249 for (n = 0; n < 64; n++) {
250 pic[n] = qdev_get_gpio_in(dev, n);
251 }
252
253 /* Connect the CPUs to the GIC */
254 for (n = 0; n < smp_cpus; n++) {
255 DeviceState *cpudev = DEVICE(qemu_get_cpu(n));
256
257 sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
258 sysbus_connect_irq(busdev, n + smp_cpus,
259 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
260 sysbus_connect_irq(busdev, n + 2 * smp_cpus,
261 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
262 sysbus_connect_irq(busdev, n + 3 * smp_cpus,
263 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
264 }
265 }
266
267 static void a9_daughterboard_init(const VexpressMachineState *vms,
268 ram_addr_t ram_size,
269 const char *cpu_type,
270 qemu_irq *pic)
271 {
272 MachineState *machine = MACHINE(vms);
273 MemoryRegion *sysmem = get_system_memory();
274 MemoryRegion *lowram = g_new(MemoryRegion, 1);
275 ram_addr_t low_ram_size;
276
277 if (ram_size > 0x40000000) {
278 /* 1GB is the maximum the address space permits */
279 error_report("vexpress-a9: cannot model more than 1GB RAM");
280 exit(1);
281 }
282
283 low_ram_size = ram_size;
284 if (low_ram_size > 0x4000000) {
285 low_ram_size = 0x4000000;
286 }
287 /* RAM is from 0x60000000 upwards. The bottom 64MB of the
288 * address space should in theory be remappable to various
289 * things including ROM or RAM; we always map the RAM there.
290 */
291 memory_region_init_alias(lowram, NULL, "vexpress.lowmem", machine->ram,
292 0, low_ram_size);
293 memory_region_add_subregion(sysmem, 0x0, lowram);
294 memory_region_add_subregion(sysmem, 0x60000000, machine->ram);
295
296 /* 0x1e000000 A9MPCore (SCU) private memory region */
297 init_cpus(machine, cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic,
298 vms->secure, vms->virt);
299
300 /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
301
302 /* 0x10020000 PL111 CLCD (daughterboard) */
303 sysbus_create_simple("pl111", 0x10020000, pic[44]);
304
305 /* 0x10060000 AXI RAM */
306 /* 0x100e0000 PL341 Dynamic Memory Controller */
307 /* 0x100e1000 PL354 Static Memory Controller */
308 /* 0x100e2000 System Configuration Controller */
309
310 sysbus_create_simple("sp804", 0x100e4000, pic[48]);
311 /* 0x100e5000 SP805 Watchdog module */
312 /* 0x100e6000 BP147 TrustZone Protection Controller */
313 /* 0x100e9000 PL301 'Fast' AXI matrix */
314 /* 0x100ea000 PL301 'Slow' AXI matrix */
315 /* 0x100ec000 TrustZone Address Space Controller */
316 /* 0x10200000 CoreSight debug APB */
317 /* 0x1e00a000 PL310 L2 Cache Controller */
318 sysbus_create_varargs("l2x0", 0x1e00a000, NULL);
319 }
320
321 /* Voltage values for SYS_CFG_VOLT daughterboard registers;
322 * values are in microvolts.
323 */
324 static const uint32_t a9_voltages[] = {
325 1000000, /* VD10 : 1.0V : SoC internal logic voltage */
326 1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */
327 1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */
328 1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */
329 900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */
330 3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */
331 };
332
333 /* Reset values for daughterboard oscillators (in Hz) */
334 static const uint32_t a9_clocks[] = {
335 45000000, /* AMBA AXI ACLK: 45MHz */
336 23750000, /* daughterboard CLCD clock: 23.75MHz */
337 66670000, /* Test chip reference clock: 66.67MHz */
338 };
339
340 static VEDBoardInfo a9_daughterboard = {
341 .motherboard_map = motherboard_legacy_map,
342 .loader_start = 0x60000000,
343 .gic_cpu_if_addr = 0x1e000100,
344 .proc_id = 0x0c000191,
345 .num_voltage_sensors = ARRAY_SIZE(a9_voltages),
346 .voltages = a9_voltages,
347 .num_clocks = ARRAY_SIZE(a9_clocks),
348 .clocks = a9_clocks,
349 .init = a9_daughterboard_init,
350 };
351
352 static void a15_daughterboard_init(const VexpressMachineState *vms,
353 ram_addr_t ram_size,
354 const char *cpu_type,
355 qemu_irq *pic)
356 {
357 MachineState *machine = MACHINE(vms);
358 MemoryRegion *sysmem = get_system_memory();
359 MemoryRegion *sram = g_new(MemoryRegion, 1);
360
361 {
362 /* We have to use a separate 64 bit variable here to avoid the gcc
363 * "comparison is always false due to limited range of data type"
364 * warning if we are on a host where ram_addr_t is 32 bits.
365 */
366 uint64_t rsz = ram_size;
367 if (rsz > (30ULL * 1024 * 1024 * 1024)) {
368 error_report("vexpress-a15: cannot model more than 30GB RAM");
369 exit(1);
370 }
371 }
372
373 /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */
374 memory_region_add_subregion(sysmem, 0x80000000, machine->ram);
375
376 /* 0x2c000000 A15MPCore private memory region (GIC) */
377 init_cpus(machine, cpu_type, TYPE_A15MPCORE_PRIV,
378 0x2c000000, pic, vms->secure, vms->virt);
379
380 /* A15 daughterboard peripherals: */
381
382 /* 0x20000000: CoreSight interfaces: not modelled */
383 /* 0x2a000000: PL301 AXI interconnect: not modelled */
384 /* 0x2a420000: SCC: not modelled */
385 /* 0x2a430000: system counter: not modelled */
386 /* 0x2b000000: HDLCD controller: not modelled */
387 /* 0x2b060000: SP805 watchdog: not modelled */
388 /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */
389 /* 0x2e000000: system SRAM */
390 memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000,
391 &error_fatal);
392 memory_region_add_subregion(sysmem, 0x2e000000, sram);
393
394 /* 0x7ffb0000: DMA330 DMA controller: not modelled */
395 /* 0x7ffd0000: PL354 static memory controller: not modelled */
396 }
397
398 static const uint32_t a15_voltages[] = {
399 900000, /* Vcore: 0.9V : CPU core voltage */
400 };
401
402 static const uint32_t a15_clocks[] = {
403 60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */
404 0, /* OSCCLK1: reserved */
405 0, /* OSCCLK2: reserved */
406 0, /* OSCCLK3: reserved */
407 40000000, /* OSCCLK4: 40MHz : external AXI master clock */
408 23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */
409 50000000, /* OSCCLK6: 50MHz : static memory controller clock */
410 60000000, /* OSCCLK7: 60MHz : SYSCLK reference */
411 40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */
412 };
413
414 static VEDBoardInfo a15_daughterboard = {
415 .motherboard_map = motherboard_aseries_map,
416 .loader_start = 0x80000000,
417 .gic_cpu_if_addr = 0x2c002000,
418 .proc_id = 0x14000237,
419 .num_voltage_sensors = ARRAY_SIZE(a15_voltages),
420 .voltages = a15_voltages,
421 .num_clocks = ARRAY_SIZE(a15_clocks),
422 .clocks = a15_clocks,
423 .init = a15_daughterboard_init,
424 };
425
426 static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells,
427 hwaddr addr, hwaddr size, uint32_t intc,
428 int irq)
429 {
430 /* Add a virtio_mmio node to the device tree blob:
431 * virtio_mmio@ADDRESS {
432 * compatible = "virtio,mmio";
433 * reg = <ADDRESS, SIZE>;
434 * interrupt-parent = <&intc>;
435 * interrupts = <0, irq, 1>;
436 * }
437 * (Note that the format of the interrupts property is dependent on the
438 * interrupt controller that interrupt-parent points to; these are for
439 * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.)
440 */
441 int rc;
442 char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr);
443
444 rc = qemu_fdt_add_subnode(fdt, nodename);
445 rc |= qemu_fdt_setprop_string(fdt, nodename,
446 "compatible", "virtio,mmio");
447 rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg",
448 acells, addr, scells, size);
449 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc);
450 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1);
451 qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
452 g_free(nodename);
453 if (rc) {
454 return -1;
455 }
456 return 0;
457 }
458
459 static uint32_t find_int_controller(void *fdt)
460 {
461 /* Find the FDT node corresponding to the interrupt controller
462 * for virtio-mmio devices. We do this by scanning the fdt for
463 * a node with the right compatibility, since we know there is
464 * only one GIC on a vexpress board.
465 * We return the phandle of the node, or 0 if none was found.
466 */
467 const char *compat = "arm,cortex-a9-gic";
468 int offset;
469
470 offset = fdt_node_offset_by_compatible(fdt, -1, compat);
471 if (offset >= 0) {
472 return fdt_get_phandle(fdt, offset);
473 }
474 return 0;
475 }
476
477 static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt)
478 {
479 uint32_t acells, scells, intc;
480 const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info;
481
482 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells",
483 NULL, &error_fatal);
484 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells",
485 NULL, &error_fatal);
486 intc = find_int_controller(fdt);
487 if (!intc) {
488 /* Not fatal, we just won't provide virtio. This will
489 * happen with older device tree blobs.
490 */
491 warn_report("couldn't find interrupt controller in "
492 "dtb; will not include virtio-mmio devices in the dtb");
493 } else {
494 int i;
495 const hwaddr *map = daughterboard->motherboard_map;
496
497 /* We iterate backwards here because adding nodes
498 * to the dtb puts them in last-first.
499 */
500 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
501 add_virtio_mmio_node(fdt, acells, scells,
502 map[VE_VIRTIO] + 0x200 * i,
503 0x200, intc, 40 + i);
504 }
505 }
506 }
507
508
509 /* Open code a private version of pflash registration since we
510 * need to set non-default device width for VExpress platform.
511 */
512 static PFlashCFI01 *ve_pflash_cfi01_register(hwaddr base, const char *name,
513 DriveInfo *di)
514 {
515 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
516
517 if (di) {
518 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di));
519 }
520
521 qdev_prop_set_uint32(dev, "num-blocks",
522 VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE);
523 qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE);
524 qdev_prop_set_uint8(dev, "width", 4);
525 qdev_prop_set_uint8(dev, "device-width", 2);
526 qdev_prop_set_bit(dev, "big-endian", false);
527 qdev_prop_set_uint16(dev, "id0", 0x89);
528 qdev_prop_set_uint16(dev, "id1", 0x18);
529 qdev_prop_set_uint16(dev, "id2", 0x00);
530 qdev_prop_set_uint16(dev, "id3", 0x00);
531 qdev_prop_set_string(dev, "name", name);
532 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
533
534 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
535 return PFLASH_CFI01(dev);
536 }
537
538 static void vexpress_common_init(MachineState *machine)
539 {
540 VexpressMachineState *vms = VEXPRESS_MACHINE(machine);
541 VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine);
542 VEDBoardInfo *daughterboard = vmc->daughterboard;
543 DeviceState *dev, *sysctl, *pl041;
544 qemu_irq pic[64];
545 uint32_t sys_id;
546 DriveInfo *dinfo;
547 PFlashCFI01 *pflash0;
548 I2CBus *i2c;
549 ram_addr_t vram_size, sram_size;
550 MemoryRegion *sysmem = get_system_memory();
551 MemoryRegion *vram = g_new(MemoryRegion, 1);
552 MemoryRegion *sram = g_new(MemoryRegion, 1);
553 MemoryRegion *flashalias = g_new(MemoryRegion, 1);
554 MemoryRegion *flash0mem;
555 const hwaddr *map = daughterboard->motherboard_map;
556 int i;
557
558 daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic);
559
560 /*
561 * If a bios file was provided, attempt to map it into memory
562 */
563 if (bios_name) {
564 char *fn;
565 int image_size;
566
567 if (drive_get(IF_PFLASH, 0, 0)) {
568 error_report("The contents of the first flash device may be "
569 "specified with -bios or with -drive if=pflash... "
570 "but you cannot use both options at once");
571 exit(1);
572 }
573 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
574 if (!fn) {
575 error_report("Could not find ROM image '%s'", bios_name);
576 exit(1);
577 }
578 image_size = load_image_targphys(fn, map[VE_NORFLASH0],
579 VEXPRESS_FLASH_SIZE);
580 g_free(fn);
581 if (image_size < 0) {
582 error_report("Could not load ROM image '%s'", bios_name);
583 exit(1);
584 }
585 }
586
587 /* Motherboard peripherals: the wiring is the same but the
588 * addresses vary between the legacy and A-Series memory maps.
589 */
590
591 sys_id = 0x1190f500;
592
593 sysctl = qdev_new("realview_sysctl");
594 qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
595 qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id);
596 qdev_prop_set_uint32(sysctl, "len-db-voltage",
597 daughterboard->num_voltage_sensors);
598 for (i = 0; i < daughterboard->num_voltage_sensors; i++) {
599 char *propname = g_strdup_printf("db-voltage[%d]", i);
600 qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]);
601 g_free(propname);
602 }
603 qdev_prop_set_uint32(sysctl, "len-db-clock",
604 daughterboard->num_clocks);
605 for (i = 0; i < daughterboard->num_clocks; i++) {
606 char *propname = g_strdup_printf("db-clock[%d]", i);
607 qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]);
608 g_free(propname);
609 }
610 sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal);
611 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
612
613 /* VE_SP810: not modelled */
614 /* VE_SERIALPCI: not modelled */
615
616 pl041 = qdev_new("pl041");
617 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
618 sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal);
619 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]);
620 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]);
621
622 dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL);
623 /* Wire up MMC card detect and read-only signals */
624 qdev_connect_gpio_out_named(dev, "card-read-only", 0,
625 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
626 qdev_connect_gpio_out_named(dev, "card-inserted", 0,
627 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN));
628 dinfo = drive_get_next(IF_SD);
629 if (dinfo) {
630 DeviceState *card;
631
632 card = qdev_new(TYPE_SD_CARD);
633 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
634 &error_fatal);
635 qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"),
636 &error_fatal);
637 }
638
639 sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]);
640 sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]);
641
642 pl011_create(map[VE_UART0], pic[5], serial_hd(0));
643 pl011_create(map[VE_UART1], pic[6], serial_hd(1));
644 pl011_create(map[VE_UART2], pic[7], serial_hd(2));
645 pl011_create(map[VE_UART3], pic[8], serial_hd(3));
646
647 sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
648 sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
649
650 dev = sysbus_create_simple(TYPE_VERSATILE_I2C, map[VE_SERIALDVI], NULL);
651 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
652 i2c_slave_create_simple(i2c, "sii9022", 0x39);
653
654 sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */
655
656 /* VE_COMPACTFLASH: not modelled */
657
658 sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
659
660 dinfo = drive_get_next(IF_PFLASH);
661 pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0",
662 dinfo);
663 if (!pflash0) {
664 error_report("vexpress: error registering flash 0");
665 exit(1);
666 }
667
668 if (map[VE_NORFLASHALIAS] != -1) {
669 /* Map flash 0 as an alias into low memory */
670 flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0);
671 memory_region_init_alias(flashalias, NULL, "vexpress.flashalias",
672 flash0mem, 0, VEXPRESS_FLASH_SIZE);
673 memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias);
674 }
675
676 dinfo = drive_get_next(IF_PFLASH);
677 if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1",
678 dinfo)) {
679 error_report("vexpress: error registering flash 1");
680 exit(1);
681 }
682
683 sram_size = 0x2000000;
684 memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size,
685 &error_fatal);
686 memory_region_add_subregion(sysmem, map[VE_SRAM], sram);
687
688 vram_size = 0x800000;
689 memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size,
690 &error_fatal);
691 memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram);
692
693 /* 0x4e000000 LAN9118 Ethernet */
694 if (nd_table[0].used) {
695 lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]);
696 }
697
698 /* VE_USB: not modelled */
699
700 /* VE_DAPROM: not modelled */
701
702 /* Create mmio transports, so the user can create virtio backends
703 * (which will be automatically plugged in to the transports). If
704 * no backend is created the transport will just sit harmlessly idle.
705 */
706 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
707 sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i,
708 pic[40 + i]);
709 }
710
711 daughterboard->bootinfo.ram_size = machine->ram_size;
712 daughterboard->bootinfo.nb_cpus = machine->smp.cpus;
713 daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID;
714 daughterboard->bootinfo.loader_start = daughterboard->loader_start;
715 daughterboard->bootinfo.smp_loader_start = map[VE_SRAM];
716 daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;
717 daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr;
718 daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb;
719 /* When booting Linux we should be in secure state if the CPU has one. */
720 daughterboard->bootinfo.secure_boot = vms->secure;
721 arm_load_kernel(ARM_CPU(first_cpu), machine, &daughterboard->bootinfo);
722 }
723
724 static bool vexpress_get_secure(Object *obj, Error **errp)
725 {
726 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
727
728 return vms->secure;
729 }
730
731 static void vexpress_set_secure(Object *obj, bool value, Error **errp)
732 {
733 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
734
735 vms->secure = value;
736 }
737
738 static bool vexpress_get_virt(Object *obj, Error **errp)
739 {
740 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
741
742 return vms->virt;
743 }
744
745 static void vexpress_set_virt(Object *obj, bool value, Error **errp)
746 {
747 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
748
749 vms->virt = value;
750 }
751
752 static void vexpress_instance_init(Object *obj)
753 {
754 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
755
756 /* EL3 is enabled by default on vexpress */
757 vms->secure = true;
758 object_property_add_bool(obj, "secure", vexpress_get_secure,
759 vexpress_set_secure);
760 object_property_set_description(obj, "secure",
761 "Set on/off to enable/disable the ARM "
762 "Security Extensions (TrustZone)");
763 }
764
765 static void vexpress_a15_instance_init(Object *obj)
766 {
767 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
768
769 /*
770 * For the vexpress-a15, EL2 is by default enabled if EL3 is,
771 * but can also be specifically set to on or off.
772 */
773 vms->virt = true;
774 object_property_add_bool(obj, "virtualization", vexpress_get_virt,
775 vexpress_set_virt);
776 object_property_set_description(obj, "virtualization",
777 "Set on/off to enable/disable the ARM "
778 "Virtualization Extensions "
779 "(defaults to same as 'secure')");
780 }
781
782 static void vexpress_a9_instance_init(Object *obj)
783 {
784 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
785
786 /* The A9 doesn't have the virt extensions */
787 vms->virt = false;
788 }
789
790 static void vexpress_class_init(ObjectClass *oc, void *data)
791 {
792 MachineClass *mc = MACHINE_CLASS(oc);
793
794 mc->desc = "ARM Versatile Express";
795 mc->init = vexpress_common_init;
796 mc->max_cpus = 4;
797 mc->ignore_memory_transaction_failures = true;
798 mc->default_ram_id = "vexpress.highmem";
799 }
800
801 static void vexpress_a9_class_init(ObjectClass *oc, void *data)
802 {
803 MachineClass *mc = MACHINE_CLASS(oc);
804 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
805
806 mc->desc = "ARM Versatile Express for Cortex-A9";
807 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
808
809 vmc->daughterboard = &a9_daughterboard;
810 }
811
812 static void vexpress_a15_class_init(ObjectClass *oc, void *data)
813 {
814 MachineClass *mc = MACHINE_CLASS(oc);
815 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
816
817 mc->desc = "ARM Versatile Express for Cortex-A15";
818 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
819
820 vmc->daughterboard = &a15_daughterboard;
821 }
822
823 static const TypeInfo vexpress_info = {
824 .name = TYPE_VEXPRESS_MACHINE,
825 .parent = TYPE_MACHINE,
826 .abstract = true,
827 .instance_size = sizeof(VexpressMachineState),
828 .instance_init = vexpress_instance_init,
829 .class_size = sizeof(VexpressMachineClass),
830 .class_init = vexpress_class_init,
831 };
832
833 static const TypeInfo vexpress_a9_info = {
834 .name = TYPE_VEXPRESS_A9_MACHINE,
835 .parent = TYPE_VEXPRESS_MACHINE,
836 .class_init = vexpress_a9_class_init,
837 .instance_init = vexpress_a9_instance_init,
838 };
839
840 static const TypeInfo vexpress_a15_info = {
841 .name = TYPE_VEXPRESS_A15_MACHINE,
842 .parent = TYPE_VEXPRESS_MACHINE,
843 .class_init = vexpress_a15_class_init,
844 .instance_init = vexpress_a15_instance_init,
845 };
846
847 static void vexpress_machine_init(void)
848 {
849 type_register_static(&vexpress_info);
850 type_register_static(&vexpress_a9_info);
851 type_register_static(&vexpress_a15_info);
852 }
853
854 type_init(vexpress_machine_init);