Update version for v6.2.0-rc4 release
[qemu.git] / hw / arm / virt.c
1 /*
2 * ARM mach-virt emulation
3 *
4 * Copyright (c) 2013 Linaro Limited
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
29 */
30
31 #include "qemu/osdep.h"
32 #include "qemu-common.h"
33 #include "qemu/datadir.h"
34 #include "qemu/units.h"
35 #include "qemu/option.h"
36 #include "monitor/qdev.h"
37 #include "qapi/error.h"
38 #include "hw/sysbus.h"
39 #include "hw/arm/boot.h"
40 #include "hw/arm/primecell.h"
41 #include "hw/arm/virt.h"
42 #include "hw/block/flash.h"
43 #include "hw/vfio/vfio-calxeda-xgmac.h"
44 #include "hw/vfio/vfio-amd-xgbe.h"
45 #include "hw/display/ramfb.h"
46 #include "net/net.h"
47 #include "sysemu/device_tree.h"
48 #include "sysemu/numa.h"
49 #include "sysemu/runstate.h"
50 #include "sysemu/tpm.h"
51 #include "sysemu/kvm.h"
52 #include "hw/loader.h"
53 #include "qapi/error.h"
54 #include "qemu/bitops.h"
55 #include "qemu/error-report.h"
56 #include "qemu/module.h"
57 #include "hw/pci-host/gpex.h"
58 #include "hw/virtio/virtio-pci.h"
59 #include "hw/arm/sysbus-fdt.h"
60 #include "hw/platform-bus.h"
61 #include "hw/qdev-properties.h"
62 #include "hw/arm/fdt.h"
63 #include "hw/intc/arm_gic.h"
64 #include "hw/intc/arm_gicv3_common.h"
65 #include "hw/irq.h"
66 #include "kvm_arm.h"
67 #include "hw/firmware/smbios.h"
68 #include "qapi/visitor.h"
69 #include "qapi/qapi-visit-common.h"
70 #include "standard-headers/linux/input.h"
71 #include "hw/arm/smmuv3.h"
72 #include "hw/acpi/acpi.h"
73 #include "target/arm/internals.h"
74 #include "hw/mem/pc-dimm.h"
75 #include "hw/mem/nvdimm.h"
76 #include "hw/acpi/generic_event_device.h"
77 #include "hw/virtio/virtio-iommu.h"
78 #include "hw/char/pl011.h"
79 #include "qemu/guest-random.h"
80
81 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
82 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
83 void *data) \
84 { \
85 MachineClass *mc = MACHINE_CLASS(oc); \
86 virt_machine_##major##_##minor##_options(mc); \
87 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
88 if (latest) { \
89 mc->alias = "virt"; \
90 } \
91 } \
92 static const TypeInfo machvirt_##major##_##minor##_info = { \
93 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
94 .parent = TYPE_VIRT_MACHINE, \
95 .class_init = virt_##major##_##minor##_class_init, \
96 }; \
97 static void machvirt_machine_##major##_##minor##_init(void) \
98 { \
99 type_register_static(&machvirt_##major##_##minor##_info); \
100 } \
101 type_init(machvirt_machine_##major##_##minor##_init);
102
103 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
104 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
105 #define DEFINE_VIRT_MACHINE(major, minor) \
106 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
107
108
109 /* Number of external interrupt lines to configure the GIC with */
110 #define NUM_IRQS 256
111
112 #define PLATFORM_BUS_NUM_IRQS 64
113
114 /* Legacy RAM limit in GB (< version 4.0) */
115 #define LEGACY_RAMLIMIT_GB 255
116 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
117
118 /* Addresses and sizes of our components.
119 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
120 * 128MB..256MB is used for miscellaneous device I/O.
121 * 256MB..1GB is reserved for possible future PCI support (ie where the
122 * PCI memory window will go if we add a PCI host controller).
123 * 1GB and up is RAM (which may happily spill over into the
124 * high memory region beyond 4GB).
125 * This represents a compromise between how much RAM can be given to
126 * a 32 bit VM and leaving space for expansion and in particular for PCI.
127 * Note that devices should generally be placed at multiples of 0x10000,
128 * to accommodate guests using 64K pages.
129 */
130 static const MemMapEntry base_memmap[] = {
131 /* Space up to 0x8000000 is reserved for a boot ROM */
132 [VIRT_FLASH] = { 0, 0x08000000 },
133 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 },
134 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
135 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 },
136 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 },
137 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 },
138 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 },
139 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 },
140 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
141 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 },
142 /* This redistributor space allows up to 2*64kB*123 CPUs */
143 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },
144 [VIRT_UART] = { 0x09000000, 0x00001000 },
145 [VIRT_RTC] = { 0x09010000, 0x00001000 },
146 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
147 [VIRT_GPIO] = { 0x09030000, 0x00001000 },
148 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 },
149 [VIRT_SMMU] = { 0x09050000, 0x00020000 },
150 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN },
151 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN },
152 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN},
153 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 },
154 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 },
155 [VIRT_MMIO] = { 0x0a000000, 0x00000200 },
156 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
157 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
158 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 },
159 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
160 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
161 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
162 /* Actual RAM size depends on initial RAM and device memory settings */
163 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES },
164 };
165
166 /*
167 * Highmem IO Regions: This memory map is floating, located after the RAM.
168 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
169 * top of the RAM, so that its base get the same alignment as the size,
170 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
171 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
172 * Note the extended_memmap is sized so that it eventually also includes the
173 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
174 * index of base_memmap).
175 */
176 static MemMapEntry extended_memmap[] = {
177 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
178 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB },
179 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB },
180 /* Second PCIe window */
181 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB },
182 };
183
184 static const int a15irqmap[] = {
185 [VIRT_UART] = 1,
186 [VIRT_RTC] = 2,
187 [VIRT_PCIE] = 3, /* ... to 6 */
188 [VIRT_GPIO] = 7,
189 [VIRT_SECURE_UART] = 8,
190 [VIRT_ACPI_GED] = 9,
191 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
192 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
193 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
194 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
195 };
196
197 static const char *valid_cpus[] = {
198 ARM_CPU_TYPE_NAME("cortex-a7"),
199 ARM_CPU_TYPE_NAME("cortex-a15"),
200 ARM_CPU_TYPE_NAME("cortex-a53"),
201 ARM_CPU_TYPE_NAME("cortex-a57"),
202 ARM_CPU_TYPE_NAME("cortex-a72"),
203 ARM_CPU_TYPE_NAME("a64fx"),
204 ARM_CPU_TYPE_NAME("host"),
205 ARM_CPU_TYPE_NAME("max"),
206 };
207
208 static bool cpu_type_valid(const char *cpu)
209 {
210 int i;
211
212 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
213 if (strcmp(cpu, valid_cpus[i]) == 0) {
214 return true;
215 }
216 }
217 return false;
218 }
219
220 static void create_kaslr_seed(MachineState *ms, const char *node)
221 {
222 uint64_t seed;
223
224 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) {
225 return;
226 }
227 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed);
228 }
229
230 static void create_fdt(VirtMachineState *vms)
231 {
232 MachineState *ms = MACHINE(vms);
233 int nb_numa_nodes = ms->numa_state->num_nodes;
234 void *fdt = create_device_tree(&vms->fdt_size);
235
236 if (!fdt) {
237 error_report("create_device_tree() failed");
238 exit(1);
239 }
240
241 ms->fdt = fdt;
242
243 /* Header */
244 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
245 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
246 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
247
248 /* /chosen must exist for load_dtb to fill in necessary properties later */
249 qemu_fdt_add_subnode(fdt, "/chosen");
250 create_kaslr_seed(ms, "/chosen");
251
252 if (vms->secure) {
253 qemu_fdt_add_subnode(fdt, "/secure-chosen");
254 create_kaslr_seed(ms, "/secure-chosen");
255 }
256
257 /* Clock node, for the benefit of the UART. The kernel device tree
258 * binding documentation claims the PL011 node clock properties are
259 * optional but in practice if you omit them the kernel refuses to
260 * probe for the device.
261 */
262 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
263 qemu_fdt_add_subnode(fdt, "/apb-pclk");
264 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
265 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
266 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
267 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
268 "clk24mhz");
269 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
270
271 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) {
272 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
273 uint32_t *matrix = g_malloc0(size);
274 int idx, i, j;
275
276 for (i = 0; i < nb_numa_nodes; i++) {
277 for (j = 0; j < nb_numa_nodes; j++) {
278 idx = (i * nb_numa_nodes + j) * 3;
279 matrix[idx + 0] = cpu_to_be32(i);
280 matrix[idx + 1] = cpu_to_be32(j);
281 matrix[idx + 2] =
282 cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
283 }
284 }
285
286 qemu_fdt_add_subnode(fdt, "/distance-map");
287 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
288 "numa-distance-map-v1");
289 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
290 matrix, size);
291 g_free(matrix);
292 }
293 }
294
295 static void fdt_add_timer_nodes(const VirtMachineState *vms)
296 {
297 /* On real hardware these interrupts are level-triggered.
298 * On KVM they were edge-triggered before host kernel version 4.4,
299 * and level-triggered afterwards.
300 * On emulated QEMU they are level-triggered.
301 *
302 * Getting the DTB info about them wrong is awkward for some
303 * guest kernels:
304 * pre-4.8 ignore the DT and leave the interrupt configured
305 * with whatever the GIC reset value (or the bootloader) left it at
306 * 4.8 before rc6 honour the incorrect data by programming it back
307 * into the GIC, causing problems
308 * 4.8rc6 and later ignore the DT and always write "level triggered"
309 * into the GIC
310 *
311 * For backwards-compatibility, virt-2.8 and earlier will continue
312 * to say these are edge-triggered, but later machines will report
313 * the correct information.
314 */
315 ARMCPU *armcpu;
316 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
317 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
318 MachineState *ms = MACHINE(vms);
319
320 if (vmc->claim_edge_triggered_timers) {
321 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
322 }
323
324 if (vms->gic_version == VIRT_GIC_VERSION_2) {
325 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
326 GIC_FDT_IRQ_PPI_CPU_WIDTH,
327 (1 << MACHINE(vms)->smp.cpus) - 1);
328 }
329
330 qemu_fdt_add_subnode(ms->fdt, "/timer");
331
332 armcpu = ARM_CPU(qemu_get_cpu(0));
333 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
334 const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
335 qemu_fdt_setprop(ms->fdt, "/timer", "compatible",
336 compat, sizeof(compat));
337 } else {
338 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible",
339 "arm,armv7-timer");
340 }
341 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
342 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
343 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
344 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
345 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
346 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
347 }
348
349 static void fdt_add_cpu_nodes(const VirtMachineState *vms)
350 {
351 int cpu;
352 int addr_cells = 1;
353 const MachineState *ms = MACHINE(vms);
354 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
355 int smp_cpus = ms->smp.cpus;
356
357 /*
358 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml
359 * On ARM v8 64-bit systems value should be set to 2,
360 * that corresponds to the MPIDR_EL1 register size.
361 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
362 * in the system, #address-cells can be set to 1, since
363 * MPIDR_EL1[63:32] bits are not used for CPUs
364 * identification.
365 *
366 * Here we actually don't know whether our system is 32- or 64-bit one.
367 * The simplest way to go is to examine affinity IDs of all our CPUs. If
368 * at least one of them has Aff3 populated, we set #address-cells to 2.
369 */
370 for (cpu = 0; cpu < smp_cpus; cpu++) {
371 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
372
373 if (armcpu->mp_affinity & ARM_AFF3_MASK) {
374 addr_cells = 2;
375 break;
376 }
377 }
378
379 qemu_fdt_add_subnode(ms->fdt, "/cpus");
380 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells);
381 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
382
383 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
384 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
385 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
386 CPUState *cs = CPU(armcpu);
387
388 qemu_fdt_add_subnode(ms->fdt, nodename);
389 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
390 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
391 armcpu->dtb_compatible);
392
393 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) {
394 qemu_fdt_setprop_string(ms->fdt, nodename,
395 "enable-method", "psci");
396 }
397
398 if (addr_cells == 2) {
399 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg",
400 armcpu->mp_affinity);
401 } else {
402 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg",
403 armcpu->mp_affinity);
404 }
405
406 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
407 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",
408 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
409 }
410
411 if (!vmc->no_cpu_topology) {
412 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle",
413 qemu_fdt_alloc_phandle(ms->fdt));
414 }
415
416 g_free(nodename);
417 }
418
419 if (!vmc->no_cpu_topology) {
420 /*
421 * Add vCPU topology description through fdt node cpu-map.
422 *
423 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt
424 * In a SMP system, the hierarchy of CPUs can be defined through
425 * four entities that are used to describe the layout of CPUs in
426 * the system: socket/cluster/core/thread.
427 *
428 * A socket node represents the boundary of system physical package
429 * and its child nodes must be one or more cluster nodes. A system
430 * can contain several layers of clustering within a single physical
431 * package and cluster nodes can be contained in parent cluster nodes.
432 *
433 * Given that cluster is not yet supported in the vCPU topology,
434 * we currently generate one cluster node within each socket node
435 * by default.
436 */
437 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
438
439 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
440 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu);
441 char *map_path;
442
443 if (ms->smp.threads > 1) {
444 map_path = g_strdup_printf(
445 "/cpus/cpu-map/socket%d/cluster0/core%d/thread%d",
446 cpu / (ms->smp.cores * ms->smp.threads),
447 (cpu / ms->smp.threads) % ms->smp.cores,
448 cpu % ms->smp.threads);
449 } else {
450 map_path = g_strdup_printf(
451 "/cpus/cpu-map/socket%d/cluster0/core%d",
452 cpu / ms->smp.cores,
453 cpu % ms->smp.cores);
454 }
455 qemu_fdt_add_path(ms->fdt, map_path);
456 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path);
457
458 g_free(map_path);
459 g_free(cpu_path);
460 }
461 }
462 }
463
464 static void fdt_add_its_gic_node(VirtMachineState *vms)
465 {
466 char *nodename;
467 MachineState *ms = MACHINE(vms);
468
469 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
470 nodename = g_strdup_printf("/intc/its@%" PRIx64,
471 vms->memmap[VIRT_GIC_ITS].base);
472 qemu_fdt_add_subnode(ms->fdt, nodename);
473 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
474 "arm,gic-v3-its");
475 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
476 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
477 2, vms->memmap[VIRT_GIC_ITS].base,
478 2, vms->memmap[VIRT_GIC_ITS].size);
479 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
480 g_free(nodename);
481 }
482
483 static void fdt_add_v2m_gic_node(VirtMachineState *vms)
484 {
485 MachineState *ms = MACHINE(vms);
486 char *nodename;
487
488 nodename = g_strdup_printf("/intc/v2m@%" PRIx64,
489 vms->memmap[VIRT_GIC_V2M].base);
490 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
491 qemu_fdt_add_subnode(ms->fdt, nodename);
492 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
493 "arm,gic-v2m-frame");
494 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
495 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
496 2, vms->memmap[VIRT_GIC_V2M].base,
497 2, vms->memmap[VIRT_GIC_V2M].size);
498 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
499 g_free(nodename);
500 }
501
502 static void fdt_add_gic_node(VirtMachineState *vms)
503 {
504 MachineState *ms = MACHINE(vms);
505 char *nodename;
506
507 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt);
508 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle);
509
510 nodename = g_strdup_printf("/intc@%" PRIx64,
511 vms->memmap[VIRT_GIC_DIST].base);
512 qemu_fdt_add_subnode(ms->fdt, nodename);
513 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3);
514 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
515 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2);
516 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2);
517 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0);
518 if (vms->gic_version == VIRT_GIC_VERSION_3) {
519 int nb_redist_regions = virt_gicv3_redist_region_count(vms);
520
521 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
522 "arm,gic-v3");
523
524 qemu_fdt_setprop_cell(ms->fdt, nodename,
525 "#redistributor-regions", nb_redist_regions);
526
527 if (nb_redist_regions == 1) {
528 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
529 2, vms->memmap[VIRT_GIC_DIST].base,
530 2, vms->memmap[VIRT_GIC_DIST].size,
531 2, vms->memmap[VIRT_GIC_REDIST].base,
532 2, vms->memmap[VIRT_GIC_REDIST].size);
533 } else {
534 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
535 2, vms->memmap[VIRT_GIC_DIST].base,
536 2, vms->memmap[VIRT_GIC_DIST].size,
537 2, vms->memmap[VIRT_GIC_REDIST].base,
538 2, vms->memmap[VIRT_GIC_REDIST].size,
539 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base,
540 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size);
541 }
542
543 if (vms->virt) {
544 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
545 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
546 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
547 }
548 } else {
549 /* 'cortex-a15-gic' means 'GIC v2' */
550 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
551 "arm,cortex-a15-gic");
552 if (!vms->virt) {
553 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
554 2, vms->memmap[VIRT_GIC_DIST].base,
555 2, vms->memmap[VIRT_GIC_DIST].size,
556 2, vms->memmap[VIRT_GIC_CPU].base,
557 2, vms->memmap[VIRT_GIC_CPU].size);
558 } else {
559 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
560 2, vms->memmap[VIRT_GIC_DIST].base,
561 2, vms->memmap[VIRT_GIC_DIST].size,
562 2, vms->memmap[VIRT_GIC_CPU].base,
563 2, vms->memmap[VIRT_GIC_CPU].size,
564 2, vms->memmap[VIRT_GIC_HYP].base,
565 2, vms->memmap[VIRT_GIC_HYP].size,
566 2, vms->memmap[VIRT_GIC_VCPU].base,
567 2, vms->memmap[VIRT_GIC_VCPU].size);
568 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
569 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
570 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
571 }
572 }
573
574 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle);
575 g_free(nodename);
576 }
577
578 static void fdt_add_pmu_nodes(const VirtMachineState *vms)
579 {
580 ARMCPU *armcpu = ARM_CPU(first_cpu);
581 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
582 MachineState *ms = MACHINE(vms);
583
584 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
585 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL));
586 return;
587 }
588
589 if (vms->gic_version == VIRT_GIC_VERSION_2) {
590 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
591 GIC_FDT_IRQ_PPI_CPU_WIDTH,
592 (1 << MACHINE(vms)->smp.cpus) - 1);
593 }
594
595 qemu_fdt_add_subnode(ms->fdt, "/pmu");
596 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
597 const char compat[] = "arm,armv8-pmuv3";
598 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible",
599 compat, sizeof(compat));
600 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts",
601 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags);
602 }
603 }
604
605 static inline DeviceState *create_acpi_ged(VirtMachineState *vms)
606 {
607 DeviceState *dev;
608 MachineState *ms = MACHINE(vms);
609 int irq = vms->irqmap[VIRT_ACPI_GED];
610 uint32_t event = ACPI_GED_PWR_DOWN_EVT;
611
612 if (ms->ram_slots) {
613 event |= ACPI_GED_MEM_HOTPLUG_EVT;
614 }
615
616 if (ms->nvdimms_state->is_enabled) {
617 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT;
618 }
619
620 dev = qdev_new(TYPE_ACPI_GED);
621 qdev_prop_set_uint32(dev, "ged-event", event);
622
623 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base);
624 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base);
625 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq));
626
627 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
628
629 return dev;
630 }
631
632 static void create_its(VirtMachineState *vms)
633 {
634 const char *itsclass = its_class_name();
635 DeviceState *dev;
636
637 if (!strcmp(itsclass, "arm-gicv3-its")) {
638 if (!vms->tcg_its) {
639 itsclass = NULL;
640 }
641 }
642
643 if (!itsclass) {
644 /* Do nothing if not supported */
645 return;
646 }
647
648 dev = qdev_new(itsclass);
649
650 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic),
651 &error_abort);
652 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
653 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
654
655 fdt_add_its_gic_node(vms);
656 vms->msi_controller = VIRT_MSI_CTRL_ITS;
657 }
658
659 static void create_v2m(VirtMachineState *vms)
660 {
661 int i;
662 int irq = vms->irqmap[VIRT_GIC_V2M];
663 DeviceState *dev;
664
665 dev = qdev_new("arm-gicv2m");
666 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
667 qdev_prop_set_uint32(dev, "base-spi", irq);
668 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
669 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
670
671 for (i = 0; i < NUM_GICV2M_SPIS; i++) {
672 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
673 qdev_get_gpio_in(vms->gic, irq + i));
674 }
675
676 fdt_add_v2m_gic_node(vms);
677 vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
678 }
679
680 static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
681 {
682 MachineState *ms = MACHINE(vms);
683 /* We create a standalone GIC */
684 SysBusDevice *gicbusdev;
685 const char *gictype;
686 int type = vms->gic_version, i;
687 unsigned int smp_cpus = ms->smp.cpus;
688 uint32_t nb_redist_regions = 0;
689
690 gictype = (type == 3) ? gicv3_class_name() : gic_class_name();
691
692 vms->gic = qdev_new(gictype);
693 qdev_prop_set_uint32(vms->gic, "revision", type);
694 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus);
695 /* Note that the num-irq property counts both internal and external
696 * interrupts; there are always 32 of the former (mandated by GIC spec).
697 */
698 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32);
699 if (!kvm_irqchip_in_kernel()) {
700 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure);
701 }
702
703 if (type == 3) {
704 uint32_t redist0_capacity =
705 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
706 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
707
708 nb_redist_regions = virt_gicv3_redist_region_count(vms);
709
710 qdev_prop_set_uint32(vms->gic, "len-redist-region-count",
711 nb_redist_regions);
712 qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count);
713
714 if (!kvm_irqchip_in_kernel()) {
715 if (vms->tcg_its) {
716 object_property_set_link(OBJECT(vms->gic), "sysmem",
717 OBJECT(mem), &error_fatal);
718 qdev_prop_set_bit(vms->gic, "has-lpi", true);
719 }
720 }
721
722 if (nb_redist_regions == 2) {
723 uint32_t redist1_capacity =
724 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
725
726 qdev_prop_set_uint32(vms->gic, "redist-region-count[1]",
727 MIN(smp_cpus - redist0_count, redist1_capacity));
728 }
729 } else {
730 if (!kvm_irqchip_in_kernel()) {
731 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions",
732 vms->virt);
733 }
734 }
735 gicbusdev = SYS_BUS_DEVICE(vms->gic);
736 sysbus_realize_and_unref(gicbusdev, &error_fatal);
737 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
738 if (type == 3) {
739 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
740 if (nb_redist_regions == 2) {
741 sysbus_mmio_map(gicbusdev, 2,
742 vms->memmap[VIRT_HIGH_GIC_REDIST2].base);
743 }
744 } else {
745 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
746 if (vms->virt) {
747 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);
748 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);
749 }
750 }
751
752 /* Wire the outputs from each CPU's generic timer and the GICv3
753 * maintenance interrupt signal to the appropriate GIC PPI inputs,
754 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
755 */
756 for (i = 0; i < smp_cpus; i++) {
757 DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
758 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
759 int irq;
760 /* Mapping from the output timer irq lines from the CPU to the
761 * GIC PPI inputs we use for the virt board.
762 */
763 const int timer_irq[] = {
764 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
765 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
766 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
767 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
768 };
769
770 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
771 qdev_connect_gpio_out(cpudev, irq,
772 qdev_get_gpio_in(vms->gic,
773 ppibase + timer_irq[irq]));
774 }
775
776 if (type == 3) {
777 qemu_irq irq = qdev_get_gpio_in(vms->gic,
778 ppibase + ARCH_GIC_MAINT_IRQ);
779 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
780 0, irq);
781 } else if (vms->virt) {
782 qemu_irq irq = qdev_get_gpio_in(vms->gic,
783 ppibase + ARCH_GIC_MAINT_IRQ);
784 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
785 }
786
787 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
788 qdev_get_gpio_in(vms->gic, ppibase
789 + VIRTUAL_PMU_IRQ));
790
791 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
792 sysbus_connect_irq(gicbusdev, i + smp_cpus,
793 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
794 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
795 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
796 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
797 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
798 }
799
800 fdt_add_gic_node(vms);
801
802 if (type == 3 && vms->its) {
803 create_its(vms);
804 } else if (type == 2) {
805 create_v2m(vms);
806 }
807 }
808
809 static void create_uart(const VirtMachineState *vms, int uart,
810 MemoryRegion *mem, Chardev *chr)
811 {
812 char *nodename;
813 hwaddr base = vms->memmap[uart].base;
814 hwaddr size = vms->memmap[uart].size;
815 int irq = vms->irqmap[uart];
816 const char compat[] = "arm,pl011\0arm,primecell";
817 const char clocknames[] = "uartclk\0apb_pclk";
818 DeviceState *dev = qdev_new(TYPE_PL011);
819 SysBusDevice *s = SYS_BUS_DEVICE(dev);
820 MachineState *ms = MACHINE(vms);
821
822 qdev_prop_set_chr(dev, "chardev", chr);
823 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
824 memory_region_add_subregion(mem, base,
825 sysbus_mmio_get_region(s, 0));
826 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
827
828 nodename = g_strdup_printf("/pl011@%" PRIx64, base);
829 qemu_fdt_add_subnode(ms->fdt, nodename);
830 /* Note that we can't use setprop_string because of the embedded NUL */
831 qemu_fdt_setprop(ms->fdt, nodename, "compatible",
832 compat, sizeof(compat));
833 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
834 2, base, 2, size);
835 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
836 GIC_FDT_IRQ_TYPE_SPI, irq,
837 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
838 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks",
839 vms->clock_phandle, vms->clock_phandle);
840 qemu_fdt_setprop(ms->fdt, nodename, "clock-names",
841 clocknames, sizeof(clocknames));
842
843 if (uart == VIRT_UART) {
844 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename);
845 } else {
846 /* Mark as not usable by the normal world */
847 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
848 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
849
850 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path",
851 nodename);
852 }
853
854 g_free(nodename);
855 }
856
857 static void create_rtc(const VirtMachineState *vms)
858 {
859 char *nodename;
860 hwaddr base = vms->memmap[VIRT_RTC].base;
861 hwaddr size = vms->memmap[VIRT_RTC].size;
862 int irq = vms->irqmap[VIRT_RTC];
863 const char compat[] = "arm,pl031\0arm,primecell";
864 MachineState *ms = MACHINE(vms);
865
866 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq));
867
868 nodename = g_strdup_printf("/pl031@%" PRIx64, base);
869 qemu_fdt_add_subnode(ms->fdt, nodename);
870 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
871 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
872 2, base, 2, size);
873 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
874 GIC_FDT_IRQ_TYPE_SPI, irq,
875 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
876 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
877 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
878 g_free(nodename);
879 }
880
881 static DeviceState *gpio_key_dev;
882 static void virt_powerdown_req(Notifier *n, void *opaque)
883 {
884 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier);
885
886 if (s->acpi_dev) {
887 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS);
888 } else {
889 /* use gpio Pin 3 for power button event */
890 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
891 }
892 }
893
894 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev,
895 uint32_t phandle)
896 {
897 gpio_key_dev = sysbus_create_simple("gpio-key", -1,
898 qdev_get_gpio_in(pl061_dev, 3));
899
900 qemu_fdt_add_subnode(fdt, "/gpio-keys");
901 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys");
902 qemu_fdt_setprop_cell(fdt, "/gpio-keys", "#size-cells", 0);
903 qemu_fdt_setprop_cell(fdt, "/gpio-keys", "#address-cells", 1);
904
905 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff");
906 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff",
907 "label", "GPIO Key Poweroff");
908 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code",
909 KEY_POWER);
910 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff",
911 "gpios", phandle, 3, 0);
912 }
913
914 #define SECURE_GPIO_POWEROFF 0
915 #define SECURE_GPIO_RESET 1
916
917 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev,
918 uint32_t phandle)
919 {
920 DeviceState *gpio_pwr_dev;
921
922 /* gpio-pwr */
923 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL);
924
925 /* connect secure pl061 to gpio-pwr */
926 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET,
927 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0));
928 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF,
929 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0));
930
931 qemu_fdt_add_subnode(fdt, "/gpio-poweroff");
932 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible",
933 "gpio-poweroff");
934 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff",
935 "gpios", phandle, SECURE_GPIO_POWEROFF, 0);
936 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled");
937 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status",
938 "okay");
939
940 qemu_fdt_add_subnode(fdt, "/gpio-restart");
941 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible",
942 "gpio-restart");
943 qemu_fdt_setprop_cells(fdt, "/gpio-restart",
944 "gpios", phandle, SECURE_GPIO_RESET, 0);
945 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled");
946 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status",
947 "okay");
948 }
949
950 static void create_gpio_devices(const VirtMachineState *vms, int gpio,
951 MemoryRegion *mem)
952 {
953 char *nodename;
954 DeviceState *pl061_dev;
955 hwaddr base = vms->memmap[gpio].base;
956 hwaddr size = vms->memmap[gpio].size;
957 int irq = vms->irqmap[gpio];
958 const char compat[] = "arm,pl061\0arm,primecell";
959 SysBusDevice *s;
960 MachineState *ms = MACHINE(vms);
961
962 pl061_dev = qdev_new("pl061");
963 /* Pull lines down to 0 if not driven by the PL061 */
964 qdev_prop_set_uint32(pl061_dev, "pullups", 0);
965 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff);
966 s = SYS_BUS_DEVICE(pl061_dev);
967 sysbus_realize_and_unref(s, &error_fatal);
968 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0));
969 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
970
971 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt);
972 nodename = g_strdup_printf("/pl061@%" PRIx64, base);
973 qemu_fdt_add_subnode(ms->fdt, nodename);
974 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
975 2, base, 2, size);
976 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
977 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2);
978 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0);
979 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
980 GIC_FDT_IRQ_TYPE_SPI, irq,
981 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
982 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
983 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
984 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle);
985
986 if (gpio != VIRT_GPIO) {
987 /* Mark as not usable by the normal world */
988 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
989 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
990 }
991 g_free(nodename);
992
993 /* Child gpio devices */
994 if (gpio == VIRT_GPIO) {
995 create_gpio_keys(ms->fdt, pl061_dev, phandle);
996 } else {
997 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle);
998 }
999 }
1000
1001 static void create_virtio_devices(const VirtMachineState *vms)
1002 {
1003 int i;
1004 hwaddr size = vms->memmap[VIRT_MMIO].size;
1005 MachineState *ms = MACHINE(vms);
1006
1007 /* We create the transports in forwards order. Since qbus_realize()
1008 * prepends (not appends) new child buses, the incrementing loop below will
1009 * create a list of virtio-mmio buses with decreasing base addresses.
1010 *
1011 * When a -device option is processed from the command line,
1012 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
1013 * order. The upshot is that -device options in increasing command line
1014 * order are mapped to virtio-mmio buses with decreasing base addresses.
1015 *
1016 * When this code was originally written, that arrangement ensured that the
1017 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
1018 * the first -device on the command line. (The end-to-end order is a
1019 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
1020 * guest kernel's name-to-address assignment strategy.)
1021 *
1022 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
1023 * the message, if not necessarily the code, of commit 70161ff336.
1024 * Therefore the loop now establishes the inverse of the original intent.
1025 *
1026 * Unfortunately, we can't counteract the kernel change by reversing the
1027 * loop; it would break existing command lines.
1028 *
1029 * In any case, the kernel makes no guarantee about the stability of
1030 * enumeration order of virtio devices (as demonstrated by it changing
1031 * between kernel versions). For reliable and stable identification
1032 * of disks users must use UUIDs or similar mechanisms.
1033 */
1034 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
1035 int irq = vms->irqmap[VIRT_MMIO] + i;
1036 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1037
1038 sysbus_create_simple("virtio-mmio", base,
1039 qdev_get_gpio_in(vms->gic, irq));
1040 }
1041
1042 /* We add dtb nodes in reverse order so that they appear in the finished
1043 * device tree lowest address first.
1044 *
1045 * Note that this mapping is independent of the loop above. The previous
1046 * loop influences virtio device to virtio transport assignment, whereas
1047 * this loop controls how virtio transports are laid out in the dtb.
1048 */
1049 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
1050 char *nodename;
1051 int irq = vms->irqmap[VIRT_MMIO] + i;
1052 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1053
1054 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
1055 qemu_fdt_add_subnode(ms->fdt, nodename);
1056 qemu_fdt_setprop_string(ms->fdt, nodename,
1057 "compatible", "virtio,mmio");
1058 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1059 2, base, 2, size);
1060 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1061 GIC_FDT_IRQ_TYPE_SPI, irq,
1062 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1063 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1064 g_free(nodename);
1065 }
1066 }
1067
1068 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
1069
1070 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms,
1071 const char *name,
1072 const char *alias_prop_name)
1073 {
1074 /*
1075 * Create a single flash device. We use the same parameters as
1076 * the flash devices on the Versatile Express board.
1077 */
1078 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
1079
1080 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
1081 qdev_prop_set_uint8(dev, "width", 4);
1082 qdev_prop_set_uint8(dev, "device-width", 2);
1083 qdev_prop_set_bit(dev, "big-endian", false);
1084 qdev_prop_set_uint16(dev, "id0", 0x89);
1085 qdev_prop_set_uint16(dev, "id1", 0x18);
1086 qdev_prop_set_uint16(dev, "id2", 0x00);
1087 qdev_prop_set_uint16(dev, "id3", 0x00);
1088 qdev_prop_set_string(dev, "name", name);
1089 object_property_add_child(OBJECT(vms), name, OBJECT(dev));
1090 object_property_add_alias(OBJECT(vms), alias_prop_name,
1091 OBJECT(dev), "drive");
1092 return PFLASH_CFI01(dev);
1093 }
1094
1095 static void virt_flash_create(VirtMachineState *vms)
1096 {
1097 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0");
1098 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1");
1099 }
1100
1101 static void virt_flash_map1(PFlashCFI01 *flash,
1102 hwaddr base, hwaddr size,
1103 MemoryRegion *sysmem)
1104 {
1105 DeviceState *dev = DEVICE(flash);
1106
1107 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
1108 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
1109 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
1110 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1111
1112 memory_region_add_subregion(sysmem, base,
1113 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
1114 0));
1115 }
1116
1117 static void virt_flash_map(VirtMachineState *vms,
1118 MemoryRegion *sysmem,
1119 MemoryRegion *secure_sysmem)
1120 {
1121 /*
1122 * Map two flash devices to fill the VIRT_FLASH space in the memmap.
1123 * sysmem is the system memory space. secure_sysmem is the secure view
1124 * of the system, and the first flash device should be made visible only
1125 * there. The second flash device is visible to both secure and nonsecure.
1126 * If sysmem == secure_sysmem this means there is no separate Secure
1127 * address space and both flash devices are generally visible.
1128 */
1129 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1130 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1131
1132 virt_flash_map1(vms->flash[0], flashbase, flashsize,
1133 secure_sysmem);
1134 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize,
1135 sysmem);
1136 }
1137
1138 static void virt_flash_fdt(VirtMachineState *vms,
1139 MemoryRegion *sysmem,
1140 MemoryRegion *secure_sysmem)
1141 {
1142 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1143 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1144 MachineState *ms = MACHINE(vms);
1145 char *nodename;
1146
1147 if (sysmem == secure_sysmem) {
1148 /* Report both flash devices as a single node in the DT */
1149 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
1150 qemu_fdt_add_subnode(ms->fdt, nodename);
1151 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1152 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1153 2, flashbase, 2, flashsize,
1154 2, flashbase + flashsize, 2, flashsize);
1155 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1156 g_free(nodename);
1157 } else {
1158 /*
1159 * Report the devices as separate nodes so we can mark one as
1160 * only visible to the secure world.
1161 */
1162 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
1163 qemu_fdt_add_subnode(ms->fdt, nodename);
1164 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1165 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1166 2, flashbase, 2, flashsize);
1167 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1168 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1169 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1170 g_free(nodename);
1171
1172 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
1173 qemu_fdt_add_subnode(ms->fdt, nodename);
1174 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1175 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1176 2, flashbase + flashsize, 2, flashsize);
1177 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1178 g_free(nodename);
1179 }
1180 }
1181
1182 static bool virt_firmware_init(VirtMachineState *vms,
1183 MemoryRegion *sysmem,
1184 MemoryRegion *secure_sysmem)
1185 {
1186 int i;
1187 const char *bios_name;
1188 BlockBackend *pflash_blk0;
1189
1190 /* Map legacy -drive if=pflash to machine properties */
1191 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) {
1192 pflash_cfi01_legacy_drive(vms->flash[i],
1193 drive_get(IF_PFLASH, 0, i));
1194 }
1195
1196 virt_flash_map(vms, sysmem, secure_sysmem);
1197
1198 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]);
1199
1200 bios_name = MACHINE(vms)->firmware;
1201 if (bios_name) {
1202 char *fname;
1203 MemoryRegion *mr;
1204 int image_size;
1205
1206 if (pflash_blk0) {
1207 error_report("The contents of the first flash device may be "
1208 "specified with -bios or with -drive if=pflash... "
1209 "but you cannot use both options at once");
1210 exit(1);
1211 }
1212
1213 /* Fall back to -bios */
1214
1215 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1216 if (!fname) {
1217 error_report("Could not find ROM image '%s'", bios_name);
1218 exit(1);
1219 }
1220 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0);
1221 image_size = load_image_mr(fname, mr);
1222 g_free(fname);
1223 if (image_size < 0) {
1224 error_report("Could not load ROM image '%s'", bios_name);
1225 exit(1);
1226 }
1227 }
1228
1229 return pflash_blk0 || bios_name;
1230 }
1231
1232 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
1233 {
1234 MachineState *ms = MACHINE(vms);
1235 hwaddr base = vms->memmap[VIRT_FW_CFG].base;
1236 hwaddr size = vms->memmap[VIRT_FW_CFG].size;
1237 FWCfgState *fw_cfg;
1238 char *nodename;
1239
1240 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
1241 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
1242
1243 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
1244 qemu_fdt_add_subnode(ms->fdt, nodename);
1245 qemu_fdt_setprop_string(ms->fdt, nodename,
1246 "compatible", "qemu,fw-cfg-mmio");
1247 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1248 2, base, 2, size);
1249 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1250 g_free(nodename);
1251 return fw_cfg;
1252 }
1253
1254 static void create_pcie_irq_map(const MachineState *ms,
1255 uint32_t gic_phandle,
1256 int first_irq, const char *nodename)
1257 {
1258 int devfn, pin;
1259 uint32_t full_irq_map[4 * 4 * 10] = { 0 };
1260 uint32_t *irq_map = full_irq_map;
1261
1262 for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
1263 for (pin = 0; pin < 4; pin++) {
1264 int irq_type = GIC_FDT_IRQ_TYPE_SPI;
1265 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
1266 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
1267 int i;
1268
1269 uint32_t map[] = {
1270 devfn << 8, 0, 0, /* devfn */
1271 pin + 1, /* PCI pin */
1272 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */
1273
1274 /* Convert map to big endian */
1275 for (i = 0; i < 10; i++) {
1276 irq_map[i] = cpu_to_be32(map[i]);
1277 }
1278 irq_map += 10;
1279 }
1280 }
1281
1282 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map",
1283 full_irq_map, sizeof(full_irq_map));
1284
1285 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask",
1286 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */
1287 0, 0,
1288 0x7 /* PCI irq */);
1289 }
1290
1291 static void create_smmu(const VirtMachineState *vms,
1292 PCIBus *bus)
1293 {
1294 char *node;
1295 const char compat[] = "arm,smmu-v3";
1296 int irq = vms->irqmap[VIRT_SMMU];
1297 int i;
1298 hwaddr base = vms->memmap[VIRT_SMMU].base;
1299 hwaddr size = vms->memmap[VIRT_SMMU].size;
1300 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
1301 DeviceState *dev;
1302 MachineState *ms = MACHINE(vms);
1303
1304 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
1305 return;
1306 }
1307
1308 dev = qdev_new("arm-smmuv3");
1309
1310 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
1311 &error_abort);
1312 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1313 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1314 for (i = 0; i < NUM_SMMU_IRQS; i++) {
1315 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1316 qdev_get_gpio_in(vms->gic, irq + i));
1317 }
1318
1319 node = g_strdup_printf("/smmuv3@%" PRIx64, base);
1320 qemu_fdt_add_subnode(ms->fdt, node);
1321 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1322 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size);
1323
1324 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts",
1325 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1326 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1327 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1328 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1329
1330 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,
1331 sizeof(irq_names));
1332
1333 qemu_fdt_setprop_cell(ms->fdt, node, "clocks", vms->clock_phandle);
1334 qemu_fdt_setprop_string(ms->fdt, node, "clock-names", "apb_pclk");
1335 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);
1336
1337 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1338
1339 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1340 g_free(node);
1341 }
1342
1343 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms)
1344 {
1345 const char compat[] = "virtio,pci-iommu";
1346 uint16_t bdf = vms->virtio_iommu_bdf;
1347 MachineState *ms = MACHINE(vms);
1348 char *node;
1349
1350 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1351
1352 node = g_strdup_printf("%s/virtio_iommu@%d", vms->pciehb_nodename, bdf);
1353 qemu_fdt_add_subnode(ms->fdt, node);
1354 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1355 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg",
1356 1, bdf << 8, 1, 0, 1, 0,
1357 1, 0, 1, 0);
1358
1359 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1360 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1361 g_free(node);
1362
1363 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map",
1364 0x0, vms->iommu_phandle, 0x0, bdf,
1365 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf);
1366 }
1367
1368 static void create_pcie(VirtMachineState *vms)
1369 {
1370 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
1371 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
1372 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base;
1373 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size;
1374 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
1375 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
1376 hwaddr base_ecam, size_ecam;
1377 hwaddr base = base_mmio;
1378 int nr_pcie_buses;
1379 int irq = vms->irqmap[VIRT_PCIE];
1380 MemoryRegion *mmio_alias;
1381 MemoryRegion *mmio_reg;
1382 MemoryRegion *ecam_alias;
1383 MemoryRegion *ecam_reg;
1384 DeviceState *dev;
1385 char *nodename;
1386 int i, ecam_id;
1387 PCIHostState *pci;
1388 MachineState *ms = MACHINE(vms);
1389
1390 dev = qdev_new(TYPE_GPEX_HOST);
1391 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1392
1393 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
1394 base_ecam = vms->memmap[ecam_id].base;
1395 size_ecam = vms->memmap[ecam_id].size;
1396 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
1397 /* Map only the first size_ecam bytes of ECAM space */
1398 ecam_alias = g_new0(MemoryRegion, 1);
1399 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1400 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1401 ecam_reg, 0, size_ecam);
1402 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
1403
1404 /* Map the MMIO window into system address space so as to expose
1405 * the section of PCI MMIO space which starts at the same base address
1406 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1407 * the window).
1408 */
1409 mmio_alias = g_new0(MemoryRegion, 1);
1410 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1411 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1412 mmio_reg, base_mmio, size_mmio);
1413 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
1414
1415 if (vms->highmem) {
1416 /* Map high MMIO space */
1417 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
1418
1419 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1420 mmio_reg, base_mmio_high, size_mmio_high);
1421 memory_region_add_subregion(get_system_memory(), base_mmio_high,
1422 high_mmio_alias);
1423 }
1424
1425 /* Map IO port space */
1426 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
1427
1428 for (i = 0; i < GPEX_NUM_IRQS; i++) {
1429 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1430 qdev_get_gpio_in(vms->gic, irq + i));
1431 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
1432 }
1433
1434 pci = PCI_HOST_BRIDGE(dev);
1435 pci->bypass_iommu = vms->default_bus_bypass_iommu;
1436 vms->bus = pci->bus;
1437 if (vms->bus) {
1438 for (i = 0; i < nb_nics; i++) {
1439 NICInfo *nd = &nd_table[i];
1440
1441 if (!nd->model) {
1442 nd->model = g_strdup("virtio");
1443 }
1444
1445 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
1446 }
1447 }
1448
1449 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base);
1450 qemu_fdt_add_subnode(ms->fdt, nodename);
1451 qemu_fdt_setprop_string(ms->fdt, nodename,
1452 "compatible", "pci-host-ecam-generic");
1453 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci");
1454 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3);
1455 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2);
1456 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0);
1457 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0,
1458 nr_pcie_buses - 1);
1459 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1460
1461 if (vms->msi_phandle) {
1462 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-parent",
1463 vms->msi_phandle);
1464 }
1465
1466 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1467 2, base_ecam, 2, size_ecam);
1468
1469 if (vms->highmem) {
1470 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1471 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1472 2, base_pio, 2, size_pio,
1473 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1474 2, base_mmio, 2, size_mmio,
1475 1, FDT_PCI_RANGE_MMIO_64BIT,
1476 2, base_mmio_high,
1477 2, base_mmio_high, 2, size_mmio_high);
1478 } else {
1479 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1480 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1481 2, base_pio, 2, size_pio,
1482 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1483 2, base_mmio, 2, size_mmio);
1484 }
1485
1486 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
1487 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename);
1488
1489 if (vms->iommu) {
1490 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1491
1492 switch (vms->iommu) {
1493 case VIRT_IOMMU_SMMUV3:
1494 create_smmu(vms, vms->bus);
1495 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map",
1496 0x0, vms->iommu_phandle, 0x0, 0x10000);
1497 break;
1498 default:
1499 g_assert_not_reached();
1500 }
1501 }
1502 }
1503
1504 static void create_platform_bus(VirtMachineState *vms)
1505 {
1506 DeviceState *dev;
1507 SysBusDevice *s;
1508 int i;
1509 MemoryRegion *sysmem = get_system_memory();
1510
1511 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
1512 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
1513 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
1514 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
1515 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1516 vms->platform_bus_dev = dev;
1517
1518 s = SYS_BUS_DEVICE(dev);
1519 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) {
1520 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i;
1521 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq));
1522 }
1523
1524 memory_region_add_subregion(sysmem,
1525 vms->memmap[VIRT_PLATFORM_BUS].base,
1526 sysbus_mmio_get_region(s, 0));
1527 }
1528
1529 static void create_tag_ram(MemoryRegion *tag_sysmem,
1530 hwaddr base, hwaddr size,
1531 const char *name)
1532 {
1533 MemoryRegion *tagram = g_new(MemoryRegion, 1);
1534
1535 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal);
1536 memory_region_add_subregion(tag_sysmem, base / 32, tagram);
1537 }
1538
1539 static void create_secure_ram(VirtMachineState *vms,
1540 MemoryRegion *secure_sysmem,
1541 MemoryRegion *secure_tag_sysmem)
1542 {
1543 MemoryRegion *secram = g_new(MemoryRegion, 1);
1544 char *nodename;
1545 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
1546 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
1547 MachineState *ms = MACHINE(vms);
1548
1549 memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
1550 &error_fatal);
1551 memory_region_add_subregion(secure_sysmem, base, secram);
1552
1553 nodename = g_strdup_printf("/secram@%" PRIx64, base);
1554 qemu_fdt_add_subnode(ms->fdt, nodename);
1555 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");
1556 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
1557 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1558 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1559
1560 if (secure_tag_sysmem) {
1561 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag");
1562 }
1563
1564 g_free(nodename);
1565 }
1566
1567 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
1568 {
1569 const VirtMachineState *board = container_of(binfo, VirtMachineState,
1570 bootinfo);
1571 MachineState *ms = MACHINE(board);
1572
1573
1574 *fdt_size = board->fdt_size;
1575 return ms->fdt;
1576 }
1577
1578 static void virt_build_smbios(VirtMachineState *vms)
1579 {
1580 MachineClass *mc = MACHINE_GET_CLASS(vms);
1581 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1582 uint8_t *smbios_tables, *smbios_anchor;
1583 size_t smbios_tables_len, smbios_anchor_len;
1584 const char *product = "QEMU Virtual Machine";
1585
1586 if (kvm_enabled()) {
1587 product = "KVM Virtual Machine";
1588 }
1589
1590 smbios_set_defaults("QEMU", product,
1591 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false,
1592 true, SMBIOS_ENTRY_POINT_30);
1593
1594 smbios_get_tables(MACHINE(vms), NULL, 0,
1595 &smbios_tables, &smbios_tables_len,
1596 &smbios_anchor, &smbios_anchor_len,
1597 &error_fatal);
1598
1599 if (smbios_anchor) {
1600 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
1601 smbios_tables, smbios_tables_len);
1602 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
1603 smbios_anchor, smbios_anchor_len);
1604 }
1605 }
1606
1607 static
1608 void virt_machine_done(Notifier *notifier, void *data)
1609 {
1610 VirtMachineState *vms = container_of(notifier, VirtMachineState,
1611 machine_done);
1612 MachineState *ms = MACHINE(vms);
1613 ARMCPU *cpu = ARM_CPU(first_cpu);
1614 struct arm_boot_info *info = &vms->bootinfo;
1615 AddressSpace *as = arm_boot_address_space(cpu, info);
1616
1617 /*
1618 * If the user provided a dtb, we assume the dynamic sysbus nodes
1619 * already are integrated there. This corresponds to a use case where
1620 * the dynamic sysbus nodes are complex and their generation is not yet
1621 * supported. In that case the user can take charge of the guest dt
1622 * while qemu takes charge of the qom stuff.
1623 */
1624 if (info->dtb_filename == NULL) {
1625 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc",
1626 vms->memmap[VIRT_PLATFORM_BUS].base,
1627 vms->memmap[VIRT_PLATFORM_BUS].size,
1628 vms->irqmap[VIRT_PLATFORM_BUS]);
1629 }
1630 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) {
1631 exit(1);
1632 }
1633
1634 fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg);
1635
1636 virt_acpi_setup(vms);
1637 virt_build_smbios(vms);
1638 }
1639
1640 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
1641 {
1642 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
1643 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1644
1645 if (!vmc->disallow_affinity_adjustment) {
1646 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1647 * GIC's target-list limitations. 32-bit KVM hosts currently
1648 * always create clusters of 4 CPUs, but that is expected to
1649 * change when they gain support for gicv3. When KVM is enabled
1650 * it will override the changes we make here, therefore our
1651 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1652 * and to improve SGI efficiency.
1653 */
1654 if (vms->gic_version == VIRT_GIC_VERSION_3) {
1655 clustersz = GICV3_TARGETLIST_BITS;
1656 } else {
1657 clustersz = GIC_TARGETLIST_BITS;
1658 }
1659 }
1660 return arm_cpu_mp_affinity(idx, clustersz);
1661 }
1662
1663 static void virt_set_memmap(VirtMachineState *vms)
1664 {
1665 MachineState *ms = MACHINE(vms);
1666 hwaddr base, device_memory_base, device_memory_size;
1667 int i;
1668
1669 vms->memmap = extended_memmap;
1670
1671 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) {
1672 vms->memmap[i] = base_memmap[i];
1673 }
1674
1675 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) {
1676 error_report("unsupported number of memory slots: %"PRIu64,
1677 ms->ram_slots);
1678 exit(EXIT_FAILURE);
1679 }
1680
1681 /*
1682 * We compute the base of the high IO region depending on the
1683 * amount of initial and device memory. The device memory start/size
1684 * is aligned on 1GiB. We never put the high IO region below 256GiB
1685 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1686 * The device region size assumes 1GiB page max alignment per slot.
1687 */
1688 device_memory_base =
1689 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);
1690 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;
1691
1692 /* Base address of the high IO region */
1693 base = device_memory_base + ROUND_UP(device_memory_size, GiB);
1694 if (base < device_memory_base) {
1695 error_report("maxmem/slots too huge");
1696 exit(EXIT_FAILURE);
1697 }
1698 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
1699 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
1700 }
1701
1702 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
1703 hwaddr size = extended_memmap[i].size;
1704
1705 base = ROUND_UP(base, size);
1706 vms->memmap[i].base = base;
1707 vms->memmap[i].size = size;
1708 base += size;
1709 }
1710 vms->highest_gpa = base - 1;
1711 if (device_memory_size > 0) {
1712 ms->device_memory = g_malloc0(sizeof(*ms->device_memory));
1713 ms->device_memory->base = device_memory_base;
1714 memory_region_init(&ms->device_memory->mr, OBJECT(vms),
1715 "device-memory", device_memory_size);
1716 }
1717 }
1718
1719 /*
1720 * finalize_gic_version - Determines the final gic_version
1721 * according to the gic-version property
1722 *
1723 * Default GIC type is v2
1724 */
1725 static void finalize_gic_version(VirtMachineState *vms)
1726 {
1727 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
1728
1729 if (kvm_enabled()) {
1730 int probe_bitmap;
1731
1732 if (!kvm_irqchip_in_kernel()) {
1733 switch (vms->gic_version) {
1734 case VIRT_GIC_VERSION_HOST:
1735 warn_report(
1736 "gic-version=host not relevant with kernel-irqchip=off "
1737 "as only userspace GICv2 is supported. Using v2 ...");
1738 return;
1739 case VIRT_GIC_VERSION_MAX:
1740 case VIRT_GIC_VERSION_NOSEL:
1741 vms->gic_version = VIRT_GIC_VERSION_2;
1742 return;
1743 case VIRT_GIC_VERSION_2:
1744 return;
1745 case VIRT_GIC_VERSION_3:
1746 error_report(
1747 "gic-version=3 is not supported with kernel-irqchip=off");
1748 exit(1);
1749 }
1750 }
1751
1752 probe_bitmap = kvm_arm_vgic_probe();
1753 if (!probe_bitmap) {
1754 error_report("Unable to determine GIC version supported by host");
1755 exit(1);
1756 }
1757
1758 switch (vms->gic_version) {
1759 case VIRT_GIC_VERSION_HOST:
1760 case VIRT_GIC_VERSION_MAX:
1761 if (probe_bitmap & KVM_ARM_VGIC_V3) {
1762 vms->gic_version = VIRT_GIC_VERSION_3;
1763 } else {
1764 vms->gic_version = VIRT_GIC_VERSION_2;
1765 }
1766 return;
1767 case VIRT_GIC_VERSION_NOSEL:
1768 if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) {
1769 vms->gic_version = VIRT_GIC_VERSION_2;
1770 } else if (probe_bitmap & KVM_ARM_VGIC_V3) {
1771 /*
1772 * in case the host does not support v2 in-kernel emulation or
1773 * the end-user requested more than 8 VCPUs we now default
1774 * to v3. In any case defaulting to v2 would be broken.
1775 */
1776 vms->gic_version = VIRT_GIC_VERSION_3;
1777 } else if (max_cpus > GIC_NCPU) {
1778 error_report("host only supports in-kernel GICv2 emulation "
1779 "but more than 8 vcpus are requested");
1780 exit(1);
1781 }
1782 break;
1783 case VIRT_GIC_VERSION_2:
1784 case VIRT_GIC_VERSION_3:
1785 break;
1786 }
1787
1788 /* Check chosen version is effectively supported by the host */
1789 if (vms->gic_version == VIRT_GIC_VERSION_2 &&
1790 !(probe_bitmap & KVM_ARM_VGIC_V2)) {
1791 error_report("host does not support in-kernel GICv2 emulation");
1792 exit(1);
1793 } else if (vms->gic_version == VIRT_GIC_VERSION_3 &&
1794 !(probe_bitmap & KVM_ARM_VGIC_V3)) {
1795 error_report("host does not support in-kernel GICv3 emulation");
1796 exit(1);
1797 }
1798 return;
1799 }
1800
1801 /* TCG mode */
1802 switch (vms->gic_version) {
1803 case VIRT_GIC_VERSION_NOSEL:
1804 vms->gic_version = VIRT_GIC_VERSION_2;
1805 break;
1806 case VIRT_GIC_VERSION_MAX:
1807 vms->gic_version = VIRT_GIC_VERSION_3;
1808 break;
1809 case VIRT_GIC_VERSION_HOST:
1810 error_report("gic-version=host requires KVM");
1811 exit(1);
1812 case VIRT_GIC_VERSION_2:
1813 case VIRT_GIC_VERSION_3:
1814 break;
1815 }
1816 }
1817
1818 /*
1819 * virt_cpu_post_init() must be called after the CPUs have
1820 * been realized and the GIC has been created.
1821 */
1822 static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem)
1823 {
1824 int max_cpus = MACHINE(vms)->smp.max_cpus;
1825 bool aarch64, pmu, steal_time;
1826 CPUState *cpu;
1827
1828 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
1829 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
1830 steal_time = object_property_get_bool(OBJECT(first_cpu),
1831 "kvm-steal-time", NULL);
1832
1833 if (kvm_enabled()) {
1834 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base;
1835 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size;
1836
1837 if (steal_time) {
1838 MemoryRegion *pvtime = g_new(MemoryRegion, 1);
1839 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU;
1840
1841 /* The memory region size must be a multiple of host page size. */
1842 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size);
1843
1844 if (pvtime_size > pvtime_reg_size) {
1845 error_report("pvtime requires a %" HWADDR_PRId
1846 " byte memory region for %d CPUs,"
1847 " but only %" HWADDR_PRId " has been reserved",
1848 pvtime_size, max_cpus, pvtime_reg_size);
1849 exit(1);
1850 }
1851
1852 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL);
1853 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime);
1854 }
1855
1856 CPU_FOREACH(cpu) {
1857 if (pmu) {
1858 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
1859 if (kvm_irqchip_in_kernel()) {
1860 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
1861 }
1862 kvm_arm_pmu_init(cpu);
1863 }
1864 if (steal_time) {
1865 kvm_arm_pvtime_init(cpu, pvtime_reg_base +
1866 cpu->cpu_index * PVTIME_SIZE_PER_CPU);
1867 }
1868 }
1869 } else {
1870 if (aarch64 && vms->highmem) {
1871 int requested_pa_size = 64 - clz64(vms->highest_gpa);
1872 int pamax = arm_pamax(ARM_CPU(first_cpu));
1873
1874 if (pamax < requested_pa_size) {
1875 error_report("VCPU supports less PA bits (%d) than "
1876 "requested by the memory map (%d)",
1877 pamax, requested_pa_size);
1878 exit(1);
1879 }
1880 }
1881 }
1882 }
1883
1884 static void machvirt_init(MachineState *machine)
1885 {
1886 VirtMachineState *vms = VIRT_MACHINE(machine);
1887 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
1888 MachineClass *mc = MACHINE_GET_CLASS(machine);
1889 const CPUArchIdList *possible_cpus;
1890 MemoryRegion *sysmem = get_system_memory();
1891 MemoryRegion *secure_sysmem = NULL;
1892 MemoryRegion *tag_sysmem = NULL;
1893 MemoryRegion *secure_tag_sysmem = NULL;
1894 int n, virt_max_cpus;
1895 bool firmware_loaded;
1896 bool aarch64 = true;
1897 bool has_ged = !vmc->no_ged;
1898 unsigned int smp_cpus = machine->smp.cpus;
1899 unsigned int max_cpus = machine->smp.max_cpus;
1900
1901 /*
1902 * In accelerated mode, the memory map is computed earlier in kvm_type()
1903 * to create a VM with the right number of IPA bits.
1904 */
1905 if (!vms->memmap) {
1906 virt_set_memmap(vms);
1907 }
1908
1909 /* We can probe only here because during property set
1910 * KVM is not available yet
1911 */
1912 finalize_gic_version(vms);
1913
1914 if (!cpu_type_valid(machine->cpu_type)) {
1915 error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
1916 exit(1);
1917 }
1918
1919 if (vms->secure) {
1920 /*
1921 * The Secure view of the world is the same as the NonSecure,
1922 * but with a few extra devices. Create it as a container region
1923 * containing the system memory at low priority; any secure-only
1924 * devices go in at higher priority and take precedence.
1925 */
1926 secure_sysmem = g_new(MemoryRegion, 1);
1927 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
1928 UINT64_MAX);
1929 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
1930 }
1931
1932 firmware_loaded = virt_firmware_init(vms, sysmem,
1933 secure_sysmem ?: sysmem);
1934
1935 /* If we have an EL3 boot ROM then the assumption is that it will
1936 * implement PSCI itself, so disable QEMU's internal implementation
1937 * so it doesn't get in the way. Instead of starting secondary
1938 * CPUs in PSCI powerdown state we will start them all running and
1939 * let the boot ROM sort them out.
1940 * The usual case is that we do use QEMU's PSCI implementation;
1941 * if the guest has EL2 then we will use SMC as the conduit,
1942 * and otherwise we will use HVC (for backwards compatibility and
1943 * because if we're using KVM then we must use HVC).
1944 */
1945 if (vms->secure && firmware_loaded) {
1946 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
1947 } else if (vms->virt) {
1948 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
1949 } else {
1950 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
1951 }
1952
1953 /* The maximum number of CPUs depends on the GIC version, or on how
1954 * many redistributors we can fit into the memory map.
1955 */
1956 if (vms->gic_version == VIRT_GIC_VERSION_3) {
1957 virt_max_cpus =
1958 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
1959 virt_max_cpus +=
1960 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
1961 } else {
1962 virt_max_cpus = GIC_NCPU;
1963 }
1964
1965 if (max_cpus > virt_max_cpus) {
1966 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1967 "supported by machine 'mach-virt' (%d)",
1968 max_cpus, virt_max_cpus);
1969 exit(1);
1970 }
1971
1972 if (vms->virt && kvm_enabled()) {
1973 error_report("mach-virt: KVM does not support providing "
1974 "Virtualization extensions to the guest CPU");
1975 exit(1);
1976 }
1977
1978 if (vms->mte && kvm_enabled()) {
1979 error_report("mach-virt: KVM does not support providing "
1980 "MTE to the guest CPU");
1981 exit(1);
1982 }
1983
1984 create_fdt(vms);
1985
1986 possible_cpus = mc->possible_cpu_arch_ids(machine);
1987 assert(possible_cpus->len == max_cpus);
1988 for (n = 0; n < possible_cpus->len; n++) {
1989 Object *cpuobj;
1990 CPUState *cs;
1991
1992 if (n >= smp_cpus) {
1993 break;
1994 }
1995
1996 cpuobj = object_new(possible_cpus->cpus[n].type);
1997 object_property_set_int(cpuobj, "mp-affinity",
1998 possible_cpus->cpus[n].arch_id, NULL);
1999
2000 cs = CPU(cpuobj);
2001 cs->cpu_index = n;
2002
2003 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
2004 &error_fatal);
2005
2006 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL);
2007
2008 if (!vms->secure) {
2009 object_property_set_bool(cpuobj, "has_el3", false, NULL);
2010 }
2011
2012 if (!vms->virt && object_property_find(cpuobj, "has_el2")) {
2013 object_property_set_bool(cpuobj, "has_el2", false, NULL);
2014 }
2015
2016 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
2017 object_property_set_int(cpuobj, "psci-conduit", vms->psci_conduit,
2018 NULL);
2019
2020 /* Secondary CPUs start in PSCI powered-down state */
2021 if (n > 0) {
2022 object_property_set_bool(cpuobj, "start-powered-off", true,
2023 NULL);
2024 }
2025 }
2026
2027 if (vmc->kvm_no_adjvtime &&
2028 object_property_find(cpuobj, "kvm-no-adjvtime")) {
2029 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL);
2030 }
2031
2032 if (vmc->no_kvm_steal_time &&
2033 object_property_find(cpuobj, "kvm-steal-time")) {
2034 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL);
2035 }
2036
2037 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) {
2038 object_property_set_bool(cpuobj, "pmu", false, NULL);
2039 }
2040
2041 if (object_property_find(cpuobj, "reset-cbar")) {
2042 object_property_set_int(cpuobj, "reset-cbar",
2043 vms->memmap[VIRT_CPUPERIPHS].base,
2044 &error_abort);
2045 }
2046
2047 object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
2048 &error_abort);
2049 if (vms->secure) {
2050 object_property_set_link(cpuobj, "secure-memory",
2051 OBJECT(secure_sysmem), &error_abort);
2052 }
2053
2054 if (vms->mte) {
2055 /* Create the memory region only once, but link to all cpus. */
2056 if (!tag_sysmem) {
2057 /*
2058 * The property exists only if MemTag is supported.
2059 * If it is, we must allocate the ram to back that up.
2060 */
2061 if (!object_property_find(cpuobj, "tag-memory")) {
2062 error_report("MTE requested, but not supported "
2063 "by the guest CPU");
2064 exit(1);
2065 }
2066
2067 tag_sysmem = g_new(MemoryRegion, 1);
2068 memory_region_init(tag_sysmem, OBJECT(machine),
2069 "tag-memory", UINT64_MAX / 32);
2070
2071 if (vms->secure) {
2072 secure_tag_sysmem = g_new(MemoryRegion, 1);
2073 memory_region_init(secure_tag_sysmem, OBJECT(machine),
2074 "secure-tag-memory", UINT64_MAX / 32);
2075
2076 /* As with ram, secure-tag takes precedence over tag. */
2077 memory_region_add_subregion_overlap(secure_tag_sysmem, 0,
2078 tag_sysmem, -1);
2079 }
2080 }
2081
2082 object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem),
2083 &error_abort);
2084 if (vms->secure) {
2085 object_property_set_link(cpuobj, "secure-tag-memory",
2086 OBJECT(secure_tag_sysmem),
2087 &error_abort);
2088 }
2089 }
2090
2091 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
2092 object_unref(cpuobj);
2093 }
2094 fdt_add_timer_nodes(vms);
2095 fdt_add_cpu_nodes(vms);
2096
2097 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base,
2098 machine->ram);
2099 if (machine->device_memory) {
2100 memory_region_add_subregion(sysmem, machine->device_memory->base,
2101 &machine->device_memory->mr);
2102 }
2103
2104 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
2105
2106 create_gic(vms, sysmem);
2107
2108 virt_cpu_post_init(vms, sysmem);
2109
2110 fdt_add_pmu_nodes(vms);
2111
2112 create_uart(vms, VIRT_UART, sysmem, serial_hd(0));
2113
2114 if (vms->secure) {
2115 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem);
2116 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1));
2117 }
2118
2119 if (tag_sysmem) {
2120 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base,
2121 machine->ram_size, "mach-virt.tag");
2122 }
2123
2124 vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64);
2125
2126 create_rtc(vms);
2127
2128 create_pcie(vms);
2129
2130 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) {
2131 vms->acpi_dev = create_acpi_ged(vms);
2132 } else {
2133 create_gpio_devices(vms, VIRT_GPIO, sysmem);
2134 }
2135
2136 if (vms->secure && !vmc->no_secure_gpio) {
2137 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem);
2138 }
2139
2140 /* connect powerdown request */
2141 vms->powerdown_notifier.notify = virt_powerdown_req;
2142 qemu_register_powerdown_notifier(&vms->powerdown_notifier);
2143
2144 /* Create mmio transports, so the user can create virtio backends
2145 * (which will be automatically plugged in to the transports). If
2146 * no backend is created the transport will just sit harmlessly idle.
2147 */
2148 create_virtio_devices(vms);
2149
2150 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
2151 rom_set_fw(vms->fw_cfg);
2152
2153 create_platform_bus(vms);
2154
2155 if (machine->nvdimms_state->is_enabled) {
2156 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = {
2157 .space_id = AML_AS_SYSTEM_MEMORY,
2158 .address = vms->memmap[VIRT_NVDIMM_ACPI].base,
2159 .bit_width = NVDIMM_ACPI_IO_LEN << 3
2160 };
2161
2162 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem,
2163 arm_virt_nvdimm_acpi_dsmio,
2164 vms->fw_cfg, OBJECT(vms));
2165 }
2166
2167 vms->bootinfo.ram_size = machine->ram_size;
2168 vms->bootinfo.nb_cpus = smp_cpus;
2169 vms->bootinfo.board_id = -1;
2170 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
2171 vms->bootinfo.get_dtb = machvirt_dtb;
2172 vms->bootinfo.skip_dtb_autoload = true;
2173 vms->bootinfo.firmware_loaded = firmware_loaded;
2174 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo);
2175
2176 vms->machine_done.notify = virt_machine_done;
2177 qemu_add_machine_init_done_notifier(&vms->machine_done);
2178 }
2179
2180 static bool virt_get_secure(Object *obj, Error **errp)
2181 {
2182 VirtMachineState *vms = VIRT_MACHINE(obj);
2183
2184 return vms->secure;
2185 }
2186
2187 static void virt_set_secure(Object *obj, bool value, Error **errp)
2188 {
2189 VirtMachineState *vms = VIRT_MACHINE(obj);
2190
2191 vms->secure = value;
2192 }
2193
2194 static bool virt_get_virt(Object *obj, Error **errp)
2195 {
2196 VirtMachineState *vms = VIRT_MACHINE(obj);
2197
2198 return vms->virt;
2199 }
2200
2201 static void virt_set_virt(Object *obj, bool value, Error **errp)
2202 {
2203 VirtMachineState *vms = VIRT_MACHINE(obj);
2204
2205 vms->virt = value;
2206 }
2207
2208 static bool virt_get_highmem(Object *obj, Error **errp)
2209 {
2210 VirtMachineState *vms = VIRT_MACHINE(obj);
2211
2212 return vms->highmem;
2213 }
2214
2215 static void virt_set_highmem(Object *obj, bool value, Error **errp)
2216 {
2217 VirtMachineState *vms = VIRT_MACHINE(obj);
2218
2219 vms->highmem = value;
2220 }
2221
2222 static bool virt_get_its(Object *obj, Error **errp)
2223 {
2224 VirtMachineState *vms = VIRT_MACHINE(obj);
2225
2226 return vms->its;
2227 }
2228
2229 static void virt_set_its(Object *obj, bool value, Error **errp)
2230 {
2231 VirtMachineState *vms = VIRT_MACHINE(obj);
2232
2233 vms->its = value;
2234 }
2235
2236 static char *virt_get_oem_id(Object *obj, Error **errp)
2237 {
2238 VirtMachineState *vms = VIRT_MACHINE(obj);
2239
2240 return g_strdup(vms->oem_id);
2241 }
2242
2243 static void virt_set_oem_id(Object *obj, const char *value, Error **errp)
2244 {
2245 VirtMachineState *vms = VIRT_MACHINE(obj);
2246 size_t len = strlen(value);
2247
2248 if (len > 6) {
2249 error_setg(errp,
2250 "User specified oem-id value is bigger than 6 bytes in size");
2251 return;
2252 }
2253
2254 strncpy(vms->oem_id, value, 6);
2255 }
2256
2257 static char *virt_get_oem_table_id(Object *obj, Error **errp)
2258 {
2259 VirtMachineState *vms = VIRT_MACHINE(obj);
2260
2261 return g_strdup(vms->oem_table_id);
2262 }
2263
2264 static void virt_set_oem_table_id(Object *obj, const char *value,
2265 Error **errp)
2266 {
2267 VirtMachineState *vms = VIRT_MACHINE(obj);
2268 size_t len = strlen(value);
2269
2270 if (len > 8) {
2271 error_setg(errp,
2272 "User specified oem-table-id value is bigger than 8 bytes in size");
2273 return;
2274 }
2275 strncpy(vms->oem_table_id, value, 8);
2276 }
2277
2278
2279 bool virt_is_acpi_enabled(VirtMachineState *vms)
2280 {
2281 if (vms->acpi == ON_OFF_AUTO_OFF) {
2282 return false;
2283 }
2284 return true;
2285 }
2286
2287 static void virt_get_acpi(Object *obj, Visitor *v, const char *name,
2288 void *opaque, Error **errp)
2289 {
2290 VirtMachineState *vms = VIRT_MACHINE(obj);
2291 OnOffAuto acpi = vms->acpi;
2292
2293 visit_type_OnOffAuto(v, name, &acpi, errp);
2294 }
2295
2296 static void virt_set_acpi(Object *obj, Visitor *v, const char *name,
2297 void *opaque, Error **errp)
2298 {
2299 VirtMachineState *vms = VIRT_MACHINE(obj);
2300
2301 visit_type_OnOffAuto(v, name, &vms->acpi, errp);
2302 }
2303
2304 static bool virt_get_ras(Object *obj, Error **errp)
2305 {
2306 VirtMachineState *vms = VIRT_MACHINE(obj);
2307
2308 return vms->ras;
2309 }
2310
2311 static void virt_set_ras(Object *obj, bool value, Error **errp)
2312 {
2313 VirtMachineState *vms = VIRT_MACHINE(obj);
2314
2315 vms->ras = value;
2316 }
2317
2318 static bool virt_get_mte(Object *obj, Error **errp)
2319 {
2320 VirtMachineState *vms = VIRT_MACHINE(obj);
2321
2322 return vms->mte;
2323 }
2324
2325 static void virt_set_mte(Object *obj, bool value, Error **errp)
2326 {
2327 VirtMachineState *vms = VIRT_MACHINE(obj);
2328
2329 vms->mte = value;
2330 }
2331
2332 static char *virt_get_gic_version(Object *obj, Error **errp)
2333 {
2334 VirtMachineState *vms = VIRT_MACHINE(obj);
2335 const char *val = vms->gic_version == VIRT_GIC_VERSION_3 ? "3" : "2";
2336
2337 return g_strdup(val);
2338 }
2339
2340 static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
2341 {
2342 VirtMachineState *vms = VIRT_MACHINE(obj);
2343
2344 if (!strcmp(value, "3")) {
2345 vms->gic_version = VIRT_GIC_VERSION_3;
2346 } else if (!strcmp(value, "2")) {
2347 vms->gic_version = VIRT_GIC_VERSION_2;
2348 } else if (!strcmp(value, "host")) {
2349 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */
2350 } else if (!strcmp(value, "max")) {
2351 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */
2352 } else {
2353 error_setg(errp, "Invalid gic-version value");
2354 error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
2355 }
2356 }
2357
2358 static char *virt_get_iommu(Object *obj, Error **errp)
2359 {
2360 VirtMachineState *vms = VIRT_MACHINE(obj);
2361
2362 switch (vms->iommu) {
2363 case VIRT_IOMMU_NONE:
2364 return g_strdup("none");
2365 case VIRT_IOMMU_SMMUV3:
2366 return g_strdup("smmuv3");
2367 default:
2368 g_assert_not_reached();
2369 }
2370 }
2371
2372 static void virt_set_iommu(Object *obj, const char *value, Error **errp)
2373 {
2374 VirtMachineState *vms = VIRT_MACHINE(obj);
2375
2376 if (!strcmp(value, "smmuv3")) {
2377 vms->iommu = VIRT_IOMMU_SMMUV3;
2378 } else if (!strcmp(value, "none")) {
2379 vms->iommu = VIRT_IOMMU_NONE;
2380 } else {
2381 error_setg(errp, "Invalid iommu value");
2382 error_append_hint(errp, "Valid values are none, smmuv3.\n");
2383 }
2384 }
2385
2386 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp)
2387 {
2388 VirtMachineState *vms = VIRT_MACHINE(obj);
2389
2390 return vms->default_bus_bypass_iommu;
2391 }
2392
2393 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value,
2394 Error **errp)
2395 {
2396 VirtMachineState *vms = VIRT_MACHINE(obj);
2397
2398 vms->default_bus_bypass_iommu = value;
2399 }
2400
2401 static CpuInstanceProperties
2402 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
2403 {
2404 MachineClass *mc = MACHINE_GET_CLASS(ms);
2405 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2406
2407 assert(cpu_index < possible_cpus->len);
2408 return possible_cpus->cpus[cpu_index].props;
2409 }
2410
2411 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
2412 {
2413 return idx % ms->numa_state->num_nodes;
2414 }
2415
2416 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
2417 {
2418 int n;
2419 unsigned int max_cpus = ms->smp.max_cpus;
2420 VirtMachineState *vms = VIRT_MACHINE(ms);
2421
2422 if (ms->possible_cpus) {
2423 assert(ms->possible_cpus->len == max_cpus);
2424 return ms->possible_cpus;
2425 }
2426
2427 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2428 sizeof(CPUArchId) * max_cpus);
2429 ms->possible_cpus->len = max_cpus;
2430 for (n = 0; n < ms->possible_cpus->len; n++) {
2431 ms->possible_cpus->cpus[n].type = ms->cpu_type;
2432 ms->possible_cpus->cpus[n].arch_id =
2433 virt_cpu_mp_affinity(vms, n);
2434 ms->possible_cpus->cpus[n].props.has_thread_id = true;
2435 ms->possible_cpus->cpus[n].props.thread_id = n;
2436 }
2437 return ms->possible_cpus;
2438 }
2439
2440 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2441 Error **errp)
2442 {
2443 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2444 const MachineState *ms = MACHINE(hotplug_dev);
2445 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2446
2447 if (!vms->acpi_dev) {
2448 error_setg(errp,
2449 "memory hotplug is not enabled: missing acpi-ged device");
2450 return;
2451 }
2452
2453 if (vms->mte) {
2454 error_setg(errp, "memory hotplug is not enabled: MTE is enabled");
2455 return;
2456 }
2457
2458 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
2459 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2460 return;
2461 }
2462
2463 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp);
2464 }
2465
2466 static void virt_memory_plug(HotplugHandler *hotplug_dev,
2467 DeviceState *dev, Error **errp)
2468 {
2469 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2470 MachineState *ms = MACHINE(hotplug_dev);
2471 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2472
2473 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms));
2474
2475 if (is_nvdimm) {
2476 nvdimm_plug(ms->nvdimms_state);
2477 }
2478
2479 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev),
2480 dev, &error_abort);
2481 }
2482
2483 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2484 DeviceState *dev, Error **errp)
2485 {
2486 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2487
2488 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2489 virt_memory_pre_plug(hotplug_dev, dev, errp);
2490 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2491 hwaddr db_start = 0, db_end = 0;
2492 char *resv_prop_str;
2493
2494 switch (vms->msi_controller) {
2495 case VIRT_MSI_CTRL_NONE:
2496 return;
2497 case VIRT_MSI_CTRL_ITS:
2498 /* GITS_TRANSLATER page */
2499 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000;
2500 db_end = base_memmap[VIRT_GIC_ITS].base +
2501 base_memmap[VIRT_GIC_ITS].size - 1;
2502 break;
2503 case VIRT_MSI_CTRL_GICV2M:
2504 /* MSI_SETSPI_NS page */
2505 db_start = base_memmap[VIRT_GIC_V2M].base;
2506 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1;
2507 break;
2508 }
2509 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u",
2510 db_start, db_end,
2511 VIRTIO_IOMMU_RESV_MEM_T_MSI);
2512
2513 qdev_prop_set_uint32(dev, "len-reserved-regions", 1);
2514 qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str);
2515 g_free(resv_prop_str);
2516 }
2517 }
2518
2519 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2520 DeviceState *dev, Error **errp)
2521 {
2522 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2523
2524 if (vms->platform_bus_dev) {
2525 MachineClass *mc = MACHINE_GET_CLASS(vms);
2526
2527 if (device_is_dynamic_sysbus(mc, dev)) {
2528 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
2529 SYS_BUS_DEVICE(dev));
2530 }
2531 }
2532 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2533 virt_memory_plug(hotplug_dev, dev, errp);
2534 }
2535 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2536 PCIDevice *pdev = PCI_DEVICE(dev);
2537
2538 vms->iommu = VIRT_IOMMU_VIRTIO;
2539 vms->virtio_iommu_bdf = pci_get_bdf(pdev);
2540 create_virtio_iommu_dt_bindings(vms);
2541 }
2542 }
2543
2544 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev,
2545 DeviceState *dev, Error **errp)
2546 {
2547 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2548 Error *local_err = NULL;
2549
2550 if (!vms->acpi_dev) {
2551 error_setg(&local_err,
2552 "memory hotplug is not enabled: missing acpi-ged device");
2553 goto out;
2554 }
2555
2556 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
2557 error_setg(&local_err,
2558 "nvdimm device hot unplug is not supported yet.");
2559 goto out;
2560 }
2561
2562 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev,
2563 &local_err);
2564 out:
2565 error_propagate(errp, local_err);
2566 }
2567
2568 static void virt_dimm_unplug(HotplugHandler *hotplug_dev,
2569 DeviceState *dev, Error **errp)
2570 {
2571 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2572 Error *local_err = NULL;
2573
2574 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err);
2575 if (local_err) {
2576 goto out;
2577 }
2578
2579 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms));
2580 qdev_unrealize(dev);
2581
2582 out:
2583 error_propagate(errp, local_err);
2584 }
2585
2586 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2587 DeviceState *dev, Error **errp)
2588 {
2589 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2590 virt_dimm_unplug_request(hotplug_dev, dev, errp);
2591 } else {
2592 error_setg(errp, "device unplug request for unsupported device"
2593 " type: %s", object_get_typename(OBJECT(dev)));
2594 }
2595 }
2596
2597 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2598 DeviceState *dev, Error **errp)
2599 {
2600 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2601 virt_dimm_unplug(hotplug_dev, dev, errp);
2602 } else {
2603 error_setg(errp, "virt: device unplug for unsupported device"
2604 " type: %s", object_get_typename(OBJECT(dev)));
2605 }
2606 }
2607
2608 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
2609 DeviceState *dev)
2610 {
2611 MachineClass *mc = MACHINE_GET_CLASS(machine);
2612
2613 if (device_is_dynamic_sysbus(mc, dev) ||
2614 (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))) {
2615 return HOTPLUG_HANDLER(machine);
2616 }
2617 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2618 VirtMachineState *vms = VIRT_MACHINE(machine);
2619
2620 if (!vms->bootinfo.firmware_loaded || !virt_is_acpi_enabled(vms)) {
2621 return HOTPLUG_HANDLER(machine);
2622 }
2623 }
2624 return NULL;
2625 }
2626
2627 /*
2628 * for arm64 kvm_type [7-0] encodes the requested number of bits
2629 * in the IPA address space
2630 */
2631 static int virt_kvm_type(MachineState *ms, const char *type_str)
2632 {
2633 VirtMachineState *vms = VIRT_MACHINE(ms);
2634 int max_vm_pa_size, requested_pa_size;
2635 bool fixed_ipa;
2636
2637 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa);
2638
2639 /* we freeze the memory map to compute the highest gpa */
2640 virt_set_memmap(vms);
2641
2642 requested_pa_size = 64 - clz64(vms->highest_gpa);
2643
2644 /*
2645 * KVM requires the IPA size to be at least 32 bits.
2646 */
2647 if (requested_pa_size < 32) {
2648 requested_pa_size = 32;
2649 }
2650
2651 if (requested_pa_size > max_vm_pa_size) {
2652 error_report("-m and ,maxmem option values "
2653 "require an IPA range (%d bits) larger than "
2654 "the one supported by the host (%d bits)",
2655 requested_pa_size, max_vm_pa_size);
2656 exit(1);
2657 }
2658 /*
2659 * We return the requested PA log size, unless KVM only supports
2660 * the implicit legacy 40b IPA setting, in which case the kvm_type
2661 * must be 0.
2662 */
2663 return fixed_ipa ? 0 : requested_pa_size;
2664 }
2665
2666 static void virt_machine_class_init(ObjectClass *oc, void *data)
2667 {
2668 MachineClass *mc = MACHINE_CLASS(oc);
2669 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2670
2671 mc->init = machvirt_init;
2672 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
2673 * The value may be reduced later when we have more information about the
2674 * configuration of the particular instance.
2675 */
2676 mc->max_cpus = 512;
2677 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC);
2678 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE);
2679 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
2680 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM);
2681 #ifdef CONFIG_TPM
2682 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
2683 #endif
2684 mc->block_default_type = IF_VIRTIO;
2685 mc->no_cdrom = 1;
2686 mc->pci_allow_0_address = true;
2687 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
2688 mc->minimum_page_bits = 12;
2689 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
2690 mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
2691 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
2692 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
2693 mc->kvm_type = virt_kvm_type;
2694 assert(!mc->get_hotplug_handler);
2695 mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
2696 hc->pre_plug = virt_machine_device_pre_plug_cb;
2697 hc->plug = virt_machine_device_plug_cb;
2698 hc->unplug_request = virt_machine_device_unplug_request_cb;
2699 hc->unplug = virt_machine_device_unplug_cb;
2700 mc->nvdimm_supported = true;
2701 mc->auto_enable_numa_with_memhp = true;
2702 mc->auto_enable_numa_with_memdev = true;
2703 mc->default_ram_id = "mach-virt.ram";
2704
2705 object_class_property_add(oc, "acpi", "OnOffAuto",
2706 virt_get_acpi, virt_set_acpi,
2707 NULL, NULL);
2708 object_class_property_set_description(oc, "acpi",
2709 "Enable ACPI");
2710 object_class_property_add_bool(oc, "secure", virt_get_secure,
2711 virt_set_secure);
2712 object_class_property_set_description(oc, "secure",
2713 "Set on/off to enable/disable the ARM "
2714 "Security Extensions (TrustZone)");
2715
2716 object_class_property_add_bool(oc, "virtualization", virt_get_virt,
2717 virt_set_virt);
2718 object_class_property_set_description(oc, "virtualization",
2719 "Set on/off to enable/disable emulating a "
2720 "guest CPU which implements the ARM "
2721 "Virtualization Extensions");
2722
2723 object_class_property_add_bool(oc, "highmem", virt_get_highmem,
2724 virt_set_highmem);
2725 object_class_property_set_description(oc, "highmem",
2726 "Set on/off to enable/disable using "
2727 "physical address space above 32 bits");
2728
2729 object_class_property_add_str(oc, "gic-version", virt_get_gic_version,
2730 virt_set_gic_version);
2731 object_class_property_set_description(oc, "gic-version",
2732 "Set GIC version. "
2733 "Valid values are 2, 3, host and max");
2734
2735 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu);
2736 object_class_property_set_description(oc, "iommu",
2737 "Set the IOMMU type. "
2738 "Valid values are none and smmuv3");
2739
2740 object_class_property_add_bool(oc, "default_bus_bypass_iommu",
2741 virt_get_default_bus_bypass_iommu,
2742 virt_set_default_bus_bypass_iommu);
2743 object_class_property_set_description(oc, "default_bus_bypass_iommu",
2744 "Set on/off to enable/disable "
2745 "bypass_iommu for default root bus");
2746
2747 object_class_property_add_bool(oc, "ras", virt_get_ras,
2748 virt_set_ras);
2749 object_class_property_set_description(oc, "ras",
2750 "Set on/off to enable/disable reporting host memory errors "
2751 "to a KVM guest using ACPI and guest external abort exceptions");
2752
2753 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte);
2754 object_class_property_set_description(oc, "mte",
2755 "Set on/off to enable/disable emulating a "
2756 "guest CPU which implements the ARM "
2757 "Memory Tagging Extension");
2758
2759 object_class_property_add_bool(oc, "its", virt_get_its,
2760 virt_set_its);
2761 object_class_property_set_description(oc, "its",
2762 "Set on/off to enable/disable "
2763 "ITS instantiation");
2764
2765 object_class_property_add_str(oc, "x-oem-id",
2766 virt_get_oem_id,
2767 virt_set_oem_id);
2768 object_class_property_set_description(oc, "x-oem-id",
2769 "Override the default value of field OEMID "
2770 "in ACPI table header."
2771 "The string may be up to 6 bytes in size");
2772
2773
2774 object_class_property_add_str(oc, "x-oem-table-id",
2775 virt_get_oem_table_id,
2776 virt_set_oem_table_id);
2777 object_class_property_set_description(oc, "x-oem-table-id",
2778 "Override the default value of field OEM Table ID "
2779 "in ACPI table header."
2780 "The string may be up to 8 bytes in size");
2781
2782 }
2783
2784 static void virt_instance_init(Object *obj)
2785 {
2786 VirtMachineState *vms = VIRT_MACHINE(obj);
2787 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
2788
2789 /* EL3 is disabled by default on virt: this makes us consistent
2790 * between KVM and TCG for this board, and it also allows us to
2791 * boot UEFI blobs which assume no TrustZone support.
2792 */
2793 vms->secure = false;
2794
2795 /* EL2 is also disabled by default, for similar reasons */
2796 vms->virt = false;
2797
2798 /* High memory is enabled by default */
2799 vms->highmem = true;
2800 vms->gic_version = VIRT_GIC_VERSION_NOSEL;
2801
2802 vms->highmem_ecam = !vmc->no_highmem_ecam;
2803
2804 if (vmc->no_its) {
2805 vms->its = false;
2806 } else {
2807 /* Default allows ITS instantiation */
2808 vms->its = true;
2809
2810 if (vmc->no_tcg_its) {
2811 vms->tcg_its = false;
2812 } else {
2813 vms->tcg_its = true;
2814 }
2815 }
2816
2817 /* Default disallows iommu instantiation */
2818 vms->iommu = VIRT_IOMMU_NONE;
2819
2820 /* The default root bus is attached to iommu by default */
2821 vms->default_bus_bypass_iommu = false;
2822
2823 /* Default disallows RAS instantiation */
2824 vms->ras = false;
2825
2826 /* MTE is disabled by default. */
2827 vms->mte = false;
2828
2829 vms->irqmap = a15irqmap;
2830
2831 virt_flash_create(vms);
2832
2833 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
2834 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
2835 }
2836
2837 static const TypeInfo virt_machine_info = {
2838 .name = TYPE_VIRT_MACHINE,
2839 .parent = TYPE_MACHINE,
2840 .abstract = true,
2841 .instance_size = sizeof(VirtMachineState),
2842 .class_size = sizeof(VirtMachineClass),
2843 .class_init = virt_machine_class_init,
2844 .instance_init = virt_instance_init,
2845 .interfaces = (InterfaceInfo[]) {
2846 { TYPE_HOTPLUG_HANDLER },
2847 { }
2848 },
2849 };
2850
2851 static void machvirt_machine_init(void)
2852 {
2853 type_register_static(&virt_machine_info);
2854 }
2855 type_init(machvirt_machine_init);
2856
2857 static void virt_machine_6_2_options(MachineClass *mc)
2858 {
2859 }
2860 DEFINE_VIRT_MACHINE_AS_LATEST(6, 2)
2861
2862 static void virt_machine_6_1_options(MachineClass *mc)
2863 {
2864 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2865
2866 virt_machine_6_2_options(mc);
2867 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len);
2868 mc->smp_props.prefer_sockets = true;
2869 vmc->no_cpu_topology = true;
2870
2871 /* qemu ITS was introduced with 6.2 */
2872 vmc->no_tcg_its = true;
2873 }
2874 DEFINE_VIRT_MACHINE(6, 1)
2875
2876 static void virt_machine_6_0_options(MachineClass *mc)
2877 {
2878 virt_machine_6_1_options(mc);
2879 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len);
2880 }
2881 DEFINE_VIRT_MACHINE(6, 0)
2882
2883 static void virt_machine_5_2_options(MachineClass *mc)
2884 {
2885 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2886
2887 virt_machine_6_0_options(mc);
2888 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len);
2889 vmc->no_secure_gpio = true;
2890 }
2891 DEFINE_VIRT_MACHINE(5, 2)
2892
2893 static void virt_machine_5_1_options(MachineClass *mc)
2894 {
2895 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2896
2897 virt_machine_5_2_options(mc);
2898 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len);
2899 vmc->no_kvm_steal_time = true;
2900 }
2901 DEFINE_VIRT_MACHINE(5, 1)
2902
2903 static void virt_machine_5_0_options(MachineClass *mc)
2904 {
2905 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2906
2907 virt_machine_5_1_options(mc);
2908 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
2909 mc->numa_mem_supported = true;
2910 vmc->acpi_expose_flash = true;
2911 mc->auto_enable_numa_with_memdev = false;
2912 }
2913 DEFINE_VIRT_MACHINE(5, 0)
2914
2915 static void virt_machine_4_2_options(MachineClass *mc)
2916 {
2917 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2918
2919 virt_machine_5_0_options(mc);
2920 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len);
2921 vmc->kvm_no_adjvtime = true;
2922 }
2923 DEFINE_VIRT_MACHINE(4, 2)
2924
2925 static void virt_machine_4_1_options(MachineClass *mc)
2926 {
2927 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2928
2929 virt_machine_4_2_options(mc);
2930 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len);
2931 vmc->no_ged = true;
2932 mc->auto_enable_numa_with_memhp = false;
2933 }
2934 DEFINE_VIRT_MACHINE(4, 1)
2935
2936 static void virt_machine_4_0_options(MachineClass *mc)
2937 {
2938 virt_machine_4_1_options(mc);
2939 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len);
2940 }
2941 DEFINE_VIRT_MACHINE(4, 0)
2942
2943 static void virt_machine_3_1_options(MachineClass *mc)
2944 {
2945 virt_machine_4_0_options(mc);
2946 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
2947 }
2948 DEFINE_VIRT_MACHINE(3, 1)
2949
2950 static void virt_machine_3_0_options(MachineClass *mc)
2951 {
2952 virt_machine_3_1_options(mc);
2953 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
2954 }
2955 DEFINE_VIRT_MACHINE(3, 0)
2956
2957 static void virt_machine_2_12_options(MachineClass *mc)
2958 {
2959 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2960
2961 virt_machine_3_0_options(mc);
2962 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
2963 vmc->no_highmem_ecam = true;
2964 mc->max_cpus = 255;
2965 }
2966 DEFINE_VIRT_MACHINE(2, 12)
2967
2968 static void virt_machine_2_11_options(MachineClass *mc)
2969 {
2970 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2971
2972 virt_machine_2_12_options(mc);
2973 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
2974 vmc->smbios_old_sys_ver = true;
2975 }
2976 DEFINE_VIRT_MACHINE(2, 11)
2977
2978 static void virt_machine_2_10_options(MachineClass *mc)
2979 {
2980 virt_machine_2_11_options(mc);
2981 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
2982 /* before 2.11 we never faulted accesses to bad addresses */
2983 mc->ignore_memory_transaction_failures = true;
2984 }
2985 DEFINE_VIRT_MACHINE(2, 10)
2986
2987 static void virt_machine_2_9_options(MachineClass *mc)
2988 {
2989 virt_machine_2_10_options(mc);
2990 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
2991 }
2992 DEFINE_VIRT_MACHINE(2, 9)
2993
2994 static void virt_machine_2_8_options(MachineClass *mc)
2995 {
2996 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2997
2998 virt_machine_2_9_options(mc);
2999 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
3000 /* For 2.8 and earlier we falsely claimed in the DT that
3001 * our timers were edge-triggered, not level-triggered.
3002 */
3003 vmc->claim_edge_triggered_timers = true;
3004 }
3005 DEFINE_VIRT_MACHINE(2, 8)
3006
3007 static void virt_machine_2_7_options(MachineClass *mc)
3008 {
3009 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3010
3011 virt_machine_2_8_options(mc);
3012 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
3013 /* ITS was introduced with 2.8 */
3014 vmc->no_its = true;
3015 /* Stick with 1K pages for migration compatibility */
3016 mc->minimum_page_bits = 0;
3017 }
3018 DEFINE_VIRT_MACHINE(2, 7)
3019
3020 static void virt_machine_2_6_options(MachineClass *mc)
3021 {
3022 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3023
3024 virt_machine_2_7_options(mc);
3025 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
3026 vmc->disallow_affinity_adjustment = true;
3027 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
3028 vmc->no_pmu = true;
3029 }
3030 DEFINE_VIRT_MACHINE(2, 6)