Merge tag 'linux-user-for-7.1-pull-request' of https://gitlab.com/laurent_vivier...
[qemu.git] / hw / arm / virt.c
1 /*
2 * ARM mach-virt emulation
3 *
4 * Copyright (c) 2013 Linaro Limited
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
29 */
30
31 #include "qemu/osdep.h"
32 #include "qemu/datadir.h"
33 #include "qemu/units.h"
34 #include "qemu/option.h"
35 #include "monitor/qdev.h"
36 #include "qapi/error.h"
37 #include "hw/sysbus.h"
38 #include "hw/arm/boot.h"
39 #include "hw/arm/primecell.h"
40 #include "hw/arm/virt.h"
41 #include "hw/block/flash.h"
42 #include "hw/vfio/vfio-calxeda-xgmac.h"
43 #include "hw/vfio/vfio-amd-xgbe.h"
44 #include "hw/display/ramfb.h"
45 #include "net/net.h"
46 #include "sysemu/device_tree.h"
47 #include "sysemu/numa.h"
48 #include "sysemu/runstate.h"
49 #include "sysemu/tpm.h"
50 #include "sysemu/kvm.h"
51 #include "sysemu/hvf.h"
52 #include "hw/loader.h"
53 #include "qapi/error.h"
54 #include "qemu/bitops.h"
55 #include "qemu/error-report.h"
56 #include "qemu/module.h"
57 #include "hw/pci-host/gpex.h"
58 #include "hw/virtio/virtio-pci.h"
59 #include "hw/core/sysbus-fdt.h"
60 #include "hw/platform-bus.h"
61 #include "hw/qdev-properties.h"
62 #include "hw/arm/fdt.h"
63 #include "hw/intc/arm_gic.h"
64 #include "hw/intc/arm_gicv3_common.h"
65 #include "hw/irq.h"
66 #include "kvm_arm.h"
67 #include "hw/firmware/smbios.h"
68 #include "qapi/visitor.h"
69 #include "qapi/qapi-visit-common.h"
70 #include "standard-headers/linux/input.h"
71 #include "hw/arm/smmuv3.h"
72 #include "hw/acpi/acpi.h"
73 #include "target/arm/internals.h"
74 #include "hw/mem/memory-device.h"
75 #include "hw/mem/pc-dimm.h"
76 #include "hw/mem/nvdimm.h"
77 #include "hw/acpi/generic_event_device.h"
78 #include "hw/virtio/virtio-mem-pci.h"
79 #include "hw/virtio/virtio-iommu.h"
80 #include "hw/char/pl011.h"
81 #include "qemu/guest-random.h"
82
83 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
84 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
85 void *data) \
86 { \
87 MachineClass *mc = MACHINE_CLASS(oc); \
88 virt_machine_##major##_##minor##_options(mc); \
89 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
90 if (latest) { \
91 mc->alias = "virt"; \
92 } \
93 } \
94 static const TypeInfo machvirt_##major##_##minor##_info = { \
95 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
96 .parent = TYPE_VIRT_MACHINE, \
97 .class_init = virt_##major##_##minor##_class_init, \
98 }; \
99 static void machvirt_machine_##major##_##minor##_init(void) \
100 { \
101 type_register_static(&machvirt_##major##_##minor##_info); \
102 } \
103 type_init(machvirt_machine_##major##_##minor##_init);
104
105 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
106 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
107 #define DEFINE_VIRT_MACHINE(major, minor) \
108 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
109
110
111 /* Number of external interrupt lines to configure the GIC with */
112 #define NUM_IRQS 256
113
114 #define PLATFORM_BUS_NUM_IRQS 64
115
116 /* Legacy RAM limit in GB (< version 4.0) */
117 #define LEGACY_RAMLIMIT_GB 255
118 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
119
120 /* Addresses and sizes of our components.
121 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
122 * 128MB..256MB is used for miscellaneous device I/O.
123 * 256MB..1GB is reserved for possible future PCI support (ie where the
124 * PCI memory window will go if we add a PCI host controller).
125 * 1GB and up is RAM (which may happily spill over into the
126 * high memory region beyond 4GB).
127 * This represents a compromise between how much RAM can be given to
128 * a 32 bit VM and leaving space for expansion and in particular for PCI.
129 * Note that devices should generally be placed at multiples of 0x10000,
130 * to accommodate guests using 64K pages.
131 */
132 static const MemMapEntry base_memmap[] = {
133 /* Space up to 0x8000000 is reserved for a boot ROM */
134 [VIRT_FLASH] = { 0, 0x08000000 },
135 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 },
136 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
137 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 },
138 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 },
139 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 },
140 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 },
141 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 },
142 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
143 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 },
144 /* This redistributor space allows up to 2*64kB*123 CPUs */
145 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },
146 [VIRT_UART] = { 0x09000000, 0x00001000 },
147 [VIRT_RTC] = { 0x09010000, 0x00001000 },
148 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
149 [VIRT_GPIO] = { 0x09030000, 0x00001000 },
150 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 },
151 [VIRT_SMMU] = { 0x09050000, 0x00020000 },
152 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN },
153 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN },
154 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN},
155 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 },
156 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 },
157 [VIRT_MMIO] = { 0x0a000000, 0x00000200 },
158 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
159 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
160 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 },
161 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
162 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
163 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
164 /* Actual RAM size depends on initial RAM and device memory settings */
165 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES },
166 };
167
168 /*
169 * Highmem IO Regions: This memory map is floating, located after the RAM.
170 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
171 * top of the RAM, so that its base get the same alignment as the size,
172 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
173 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
174 * Note the extended_memmap is sized so that it eventually also includes the
175 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
176 * index of base_memmap).
177 */
178 static MemMapEntry extended_memmap[] = {
179 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
180 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB },
181 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB },
182 /* Second PCIe window */
183 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB },
184 };
185
186 static const int a15irqmap[] = {
187 [VIRT_UART] = 1,
188 [VIRT_RTC] = 2,
189 [VIRT_PCIE] = 3, /* ... to 6 */
190 [VIRT_GPIO] = 7,
191 [VIRT_SECURE_UART] = 8,
192 [VIRT_ACPI_GED] = 9,
193 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
194 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
195 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
196 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
197 };
198
199 static const char *valid_cpus[] = {
200 ARM_CPU_TYPE_NAME("cortex-a7"),
201 ARM_CPU_TYPE_NAME("cortex-a15"),
202 ARM_CPU_TYPE_NAME("cortex-a53"),
203 ARM_CPU_TYPE_NAME("cortex-a57"),
204 ARM_CPU_TYPE_NAME("cortex-a72"),
205 ARM_CPU_TYPE_NAME("cortex-a76"),
206 ARM_CPU_TYPE_NAME("a64fx"),
207 ARM_CPU_TYPE_NAME("neoverse-n1"),
208 ARM_CPU_TYPE_NAME("host"),
209 ARM_CPU_TYPE_NAME("max"),
210 };
211
212 static bool cpu_type_valid(const char *cpu)
213 {
214 int i;
215
216 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
217 if (strcmp(cpu, valid_cpus[i]) == 0) {
218 return true;
219 }
220 }
221 return false;
222 }
223
224 static void create_randomness(MachineState *ms, const char *node)
225 {
226 struct {
227 uint64_t kaslr;
228 uint8_t rng[32];
229 } seed;
230
231 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) {
232 return;
233 }
234 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr);
235 qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng));
236 }
237
238 static void create_fdt(VirtMachineState *vms)
239 {
240 MachineState *ms = MACHINE(vms);
241 int nb_numa_nodes = ms->numa_state->num_nodes;
242 void *fdt = create_device_tree(&vms->fdt_size);
243
244 if (!fdt) {
245 error_report("create_device_tree() failed");
246 exit(1);
247 }
248
249 ms->fdt = fdt;
250
251 /* Header */
252 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
253 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
254 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
255
256 /* /chosen must exist for load_dtb to fill in necessary properties later */
257 qemu_fdt_add_subnode(fdt, "/chosen");
258 if (vms->dtb_randomness) {
259 create_randomness(ms, "/chosen");
260 }
261
262 if (vms->secure) {
263 qemu_fdt_add_subnode(fdt, "/secure-chosen");
264 if (vms->dtb_randomness) {
265 create_randomness(ms, "/secure-chosen");
266 }
267 }
268
269 /* Clock node, for the benefit of the UART. The kernel device tree
270 * binding documentation claims the PL011 node clock properties are
271 * optional but in practice if you omit them the kernel refuses to
272 * probe for the device.
273 */
274 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
275 qemu_fdt_add_subnode(fdt, "/apb-pclk");
276 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
277 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
278 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
279 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
280 "clk24mhz");
281 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
282
283 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) {
284 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
285 uint32_t *matrix = g_malloc0(size);
286 int idx, i, j;
287
288 for (i = 0; i < nb_numa_nodes; i++) {
289 for (j = 0; j < nb_numa_nodes; j++) {
290 idx = (i * nb_numa_nodes + j) * 3;
291 matrix[idx + 0] = cpu_to_be32(i);
292 matrix[idx + 1] = cpu_to_be32(j);
293 matrix[idx + 2] =
294 cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
295 }
296 }
297
298 qemu_fdt_add_subnode(fdt, "/distance-map");
299 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
300 "numa-distance-map-v1");
301 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
302 matrix, size);
303 g_free(matrix);
304 }
305 }
306
307 static void fdt_add_timer_nodes(const VirtMachineState *vms)
308 {
309 /* On real hardware these interrupts are level-triggered.
310 * On KVM they were edge-triggered before host kernel version 4.4,
311 * and level-triggered afterwards.
312 * On emulated QEMU they are level-triggered.
313 *
314 * Getting the DTB info about them wrong is awkward for some
315 * guest kernels:
316 * pre-4.8 ignore the DT and leave the interrupt configured
317 * with whatever the GIC reset value (or the bootloader) left it at
318 * 4.8 before rc6 honour the incorrect data by programming it back
319 * into the GIC, causing problems
320 * 4.8rc6 and later ignore the DT and always write "level triggered"
321 * into the GIC
322 *
323 * For backwards-compatibility, virt-2.8 and earlier will continue
324 * to say these are edge-triggered, but later machines will report
325 * the correct information.
326 */
327 ARMCPU *armcpu;
328 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
329 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
330 MachineState *ms = MACHINE(vms);
331
332 if (vmc->claim_edge_triggered_timers) {
333 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
334 }
335
336 if (vms->gic_version == VIRT_GIC_VERSION_2) {
337 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
338 GIC_FDT_IRQ_PPI_CPU_WIDTH,
339 (1 << MACHINE(vms)->smp.cpus) - 1);
340 }
341
342 qemu_fdt_add_subnode(ms->fdt, "/timer");
343
344 armcpu = ARM_CPU(qemu_get_cpu(0));
345 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
346 const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
347 qemu_fdt_setprop(ms->fdt, "/timer", "compatible",
348 compat, sizeof(compat));
349 } else {
350 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible",
351 "arm,armv7-timer");
352 }
353 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
354 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
355 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
356 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
357 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
358 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
359 }
360
361 static void fdt_add_cpu_nodes(const VirtMachineState *vms)
362 {
363 int cpu;
364 int addr_cells = 1;
365 const MachineState *ms = MACHINE(vms);
366 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
367 int smp_cpus = ms->smp.cpus;
368
369 /*
370 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml
371 * On ARM v8 64-bit systems value should be set to 2,
372 * that corresponds to the MPIDR_EL1 register size.
373 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
374 * in the system, #address-cells can be set to 1, since
375 * MPIDR_EL1[63:32] bits are not used for CPUs
376 * identification.
377 *
378 * Here we actually don't know whether our system is 32- or 64-bit one.
379 * The simplest way to go is to examine affinity IDs of all our CPUs. If
380 * at least one of them has Aff3 populated, we set #address-cells to 2.
381 */
382 for (cpu = 0; cpu < smp_cpus; cpu++) {
383 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
384
385 if (armcpu->mp_affinity & ARM_AFF3_MASK) {
386 addr_cells = 2;
387 break;
388 }
389 }
390
391 qemu_fdt_add_subnode(ms->fdt, "/cpus");
392 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells);
393 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
394
395 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
396 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
397 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
398 CPUState *cs = CPU(armcpu);
399
400 qemu_fdt_add_subnode(ms->fdt, nodename);
401 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
402 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
403 armcpu->dtb_compatible);
404
405 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) {
406 qemu_fdt_setprop_string(ms->fdt, nodename,
407 "enable-method", "psci");
408 }
409
410 if (addr_cells == 2) {
411 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg",
412 armcpu->mp_affinity);
413 } else {
414 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg",
415 armcpu->mp_affinity);
416 }
417
418 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
419 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",
420 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
421 }
422
423 if (!vmc->no_cpu_topology) {
424 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle",
425 qemu_fdt_alloc_phandle(ms->fdt));
426 }
427
428 g_free(nodename);
429 }
430
431 if (!vmc->no_cpu_topology) {
432 /*
433 * Add vCPU topology description through fdt node cpu-map.
434 *
435 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt
436 * In a SMP system, the hierarchy of CPUs can be defined through
437 * four entities that are used to describe the layout of CPUs in
438 * the system: socket/cluster/core/thread.
439 *
440 * A socket node represents the boundary of system physical package
441 * and its child nodes must be one or more cluster nodes. A system
442 * can contain several layers of clustering within a single physical
443 * package and cluster nodes can be contained in parent cluster nodes.
444 *
445 * Note: currently we only support one layer of clustering within
446 * each physical package.
447 */
448 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
449
450 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
451 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu);
452 char *map_path;
453
454 if (ms->smp.threads > 1) {
455 map_path = g_strdup_printf(
456 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d",
457 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads),
458 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters,
459 (cpu / ms->smp.threads) % ms->smp.cores,
460 cpu % ms->smp.threads);
461 } else {
462 map_path = g_strdup_printf(
463 "/cpus/cpu-map/socket%d/cluster%d/core%d",
464 cpu / (ms->smp.clusters * ms->smp.cores),
465 (cpu / ms->smp.cores) % ms->smp.clusters,
466 cpu % ms->smp.cores);
467 }
468 qemu_fdt_add_path(ms->fdt, map_path);
469 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path);
470
471 g_free(map_path);
472 g_free(cpu_path);
473 }
474 }
475 }
476
477 static void fdt_add_its_gic_node(VirtMachineState *vms)
478 {
479 char *nodename;
480 MachineState *ms = MACHINE(vms);
481
482 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
483 nodename = g_strdup_printf("/intc/its@%" PRIx64,
484 vms->memmap[VIRT_GIC_ITS].base);
485 qemu_fdt_add_subnode(ms->fdt, nodename);
486 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
487 "arm,gic-v3-its");
488 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
489 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
490 2, vms->memmap[VIRT_GIC_ITS].base,
491 2, vms->memmap[VIRT_GIC_ITS].size);
492 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
493 g_free(nodename);
494 }
495
496 static void fdt_add_v2m_gic_node(VirtMachineState *vms)
497 {
498 MachineState *ms = MACHINE(vms);
499 char *nodename;
500
501 nodename = g_strdup_printf("/intc/v2m@%" PRIx64,
502 vms->memmap[VIRT_GIC_V2M].base);
503 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
504 qemu_fdt_add_subnode(ms->fdt, nodename);
505 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
506 "arm,gic-v2m-frame");
507 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
508 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
509 2, vms->memmap[VIRT_GIC_V2M].base,
510 2, vms->memmap[VIRT_GIC_V2M].size);
511 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
512 g_free(nodename);
513 }
514
515 static void fdt_add_gic_node(VirtMachineState *vms)
516 {
517 MachineState *ms = MACHINE(vms);
518 char *nodename;
519
520 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt);
521 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle);
522
523 nodename = g_strdup_printf("/intc@%" PRIx64,
524 vms->memmap[VIRT_GIC_DIST].base);
525 qemu_fdt_add_subnode(ms->fdt, nodename);
526 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3);
527 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
528 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2);
529 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2);
530 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0);
531 if (vms->gic_version != VIRT_GIC_VERSION_2) {
532 int nb_redist_regions = virt_gicv3_redist_region_count(vms);
533
534 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
535 "arm,gic-v3");
536
537 qemu_fdt_setprop_cell(ms->fdt, nodename,
538 "#redistributor-regions", nb_redist_regions);
539
540 if (nb_redist_regions == 1) {
541 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
542 2, vms->memmap[VIRT_GIC_DIST].base,
543 2, vms->memmap[VIRT_GIC_DIST].size,
544 2, vms->memmap[VIRT_GIC_REDIST].base,
545 2, vms->memmap[VIRT_GIC_REDIST].size);
546 } else {
547 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
548 2, vms->memmap[VIRT_GIC_DIST].base,
549 2, vms->memmap[VIRT_GIC_DIST].size,
550 2, vms->memmap[VIRT_GIC_REDIST].base,
551 2, vms->memmap[VIRT_GIC_REDIST].size,
552 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base,
553 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size);
554 }
555
556 if (vms->virt) {
557 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
558 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
559 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
560 }
561 } else {
562 /* 'cortex-a15-gic' means 'GIC v2' */
563 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
564 "arm,cortex-a15-gic");
565 if (!vms->virt) {
566 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
567 2, vms->memmap[VIRT_GIC_DIST].base,
568 2, vms->memmap[VIRT_GIC_DIST].size,
569 2, vms->memmap[VIRT_GIC_CPU].base,
570 2, vms->memmap[VIRT_GIC_CPU].size);
571 } else {
572 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
573 2, vms->memmap[VIRT_GIC_DIST].base,
574 2, vms->memmap[VIRT_GIC_DIST].size,
575 2, vms->memmap[VIRT_GIC_CPU].base,
576 2, vms->memmap[VIRT_GIC_CPU].size,
577 2, vms->memmap[VIRT_GIC_HYP].base,
578 2, vms->memmap[VIRT_GIC_HYP].size,
579 2, vms->memmap[VIRT_GIC_VCPU].base,
580 2, vms->memmap[VIRT_GIC_VCPU].size);
581 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
582 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
583 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
584 }
585 }
586
587 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle);
588 g_free(nodename);
589 }
590
591 static void fdt_add_pmu_nodes(const VirtMachineState *vms)
592 {
593 ARMCPU *armcpu = ARM_CPU(first_cpu);
594 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
595 MachineState *ms = MACHINE(vms);
596
597 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
598 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL));
599 return;
600 }
601
602 if (vms->gic_version == VIRT_GIC_VERSION_2) {
603 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
604 GIC_FDT_IRQ_PPI_CPU_WIDTH,
605 (1 << MACHINE(vms)->smp.cpus) - 1);
606 }
607
608 qemu_fdt_add_subnode(ms->fdt, "/pmu");
609 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
610 const char compat[] = "arm,armv8-pmuv3";
611 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible",
612 compat, sizeof(compat));
613 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts",
614 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags);
615 }
616 }
617
618 static inline DeviceState *create_acpi_ged(VirtMachineState *vms)
619 {
620 DeviceState *dev;
621 MachineState *ms = MACHINE(vms);
622 int irq = vms->irqmap[VIRT_ACPI_GED];
623 uint32_t event = ACPI_GED_PWR_DOWN_EVT;
624
625 if (ms->ram_slots) {
626 event |= ACPI_GED_MEM_HOTPLUG_EVT;
627 }
628
629 if (ms->nvdimms_state->is_enabled) {
630 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT;
631 }
632
633 dev = qdev_new(TYPE_ACPI_GED);
634 qdev_prop_set_uint32(dev, "ged-event", event);
635
636 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base);
637 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base);
638 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq));
639
640 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
641
642 return dev;
643 }
644
645 static void create_its(VirtMachineState *vms)
646 {
647 const char *itsclass = its_class_name();
648 DeviceState *dev;
649
650 if (!strcmp(itsclass, "arm-gicv3-its")) {
651 if (!vms->tcg_its) {
652 itsclass = NULL;
653 }
654 }
655
656 if (!itsclass) {
657 /* Do nothing if not supported */
658 return;
659 }
660
661 dev = qdev_new(itsclass);
662
663 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic),
664 &error_abort);
665 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
666 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
667
668 fdt_add_its_gic_node(vms);
669 vms->msi_controller = VIRT_MSI_CTRL_ITS;
670 }
671
672 static void create_v2m(VirtMachineState *vms)
673 {
674 int i;
675 int irq = vms->irqmap[VIRT_GIC_V2M];
676 DeviceState *dev;
677
678 dev = qdev_new("arm-gicv2m");
679 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
680 qdev_prop_set_uint32(dev, "base-spi", irq);
681 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
682 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
683
684 for (i = 0; i < NUM_GICV2M_SPIS; i++) {
685 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
686 qdev_get_gpio_in(vms->gic, irq + i));
687 }
688
689 fdt_add_v2m_gic_node(vms);
690 vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
691 }
692
693 static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
694 {
695 MachineState *ms = MACHINE(vms);
696 /* We create a standalone GIC */
697 SysBusDevice *gicbusdev;
698 const char *gictype;
699 int i;
700 unsigned int smp_cpus = ms->smp.cpus;
701 uint32_t nb_redist_regions = 0;
702 int revision;
703
704 if (vms->gic_version == VIRT_GIC_VERSION_2) {
705 gictype = gic_class_name();
706 } else {
707 gictype = gicv3_class_name();
708 }
709
710 switch (vms->gic_version) {
711 case VIRT_GIC_VERSION_2:
712 revision = 2;
713 break;
714 case VIRT_GIC_VERSION_3:
715 revision = 3;
716 break;
717 case VIRT_GIC_VERSION_4:
718 revision = 4;
719 break;
720 default:
721 g_assert_not_reached();
722 }
723 vms->gic = qdev_new(gictype);
724 qdev_prop_set_uint32(vms->gic, "revision", revision);
725 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus);
726 /* Note that the num-irq property counts both internal and external
727 * interrupts; there are always 32 of the former (mandated by GIC spec).
728 */
729 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32);
730 if (!kvm_irqchip_in_kernel()) {
731 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure);
732 }
733
734 if (vms->gic_version != VIRT_GIC_VERSION_2) {
735 uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST);
736 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
737
738 nb_redist_regions = virt_gicv3_redist_region_count(vms);
739
740 qdev_prop_set_uint32(vms->gic, "len-redist-region-count",
741 nb_redist_regions);
742 qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count);
743
744 if (!kvm_irqchip_in_kernel()) {
745 if (vms->tcg_its) {
746 object_property_set_link(OBJECT(vms->gic), "sysmem",
747 OBJECT(mem), &error_fatal);
748 qdev_prop_set_bit(vms->gic, "has-lpi", true);
749 }
750 }
751
752 if (nb_redist_regions == 2) {
753 uint32_t redist1_capacity =
754 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
755
756 qdev_prop_set_uint32(vms->gic, "redist-region-count[1]",
757 MIN(smp_cpus - redist0_count, redist1_capacity));
758 }
759 } else {
760 if (!kvm_irqchip_in_kernel()) {
761 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions",
762 vms->virt);
763 }
764 }
765 gicbusdev = SYS_BUS_DEVICE(vms->gic);
766 sysbus_realize_and_unref(gicbusdev, &error_fatal);
767 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
768 if (vms->gic_version != VIRT_GIC_VERSION_2) {
769 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
770 if (nb_redist_regions == 2) {
771 sysbus_mmio_map(gicbusdev, 2,
772 vms->memmap[VIRT_HIGH_GIC_REDIST2].base);
773 }
774 } else {
775 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
776 if (vms->virt) {
777 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);
778 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);
779 }
780 }
781
782 /* Wire the outputs from each CPU's generic timer and the GICv3
783 * maintenance interrupt signal to the appropriate GIC PPI inputs,
784 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
785 */
786 for (i = 0; i < smp_cpus; i++) {
787 DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
788 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
789 int irq;
790 /* Mapping from the output timer irq lines from the CPU to the
791 * GIC PPI inputs we use for the virt board.
792 */
793 const int timer_irq[] = {
794 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
795 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
796 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
797 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
798 };
799
800 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
801 qdev_connect_gpio_out(cpudev, irq,
802 qdev_get_gpio_in(vms->gic,
803 ppibase + timer_irq[irq]));
804 }
805
806 if (vms->gic_version != VIRT_GIC_VERSION_2) {
807 qemu_irq irq = qdev_get_gpio_in(vms->gic,
808 ppibase + ARCH_GIC_MAINT_IRQ);
809 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
810 0, irq);
811 } else if (vms->virt) {
812 qemu_irq irq = qdev_get_gpio_in(vms->gic,
813 ppibase + ARCH_GIC_MAINT_IRQ);
814 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
815 }
816
817 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
818 qdev_get_gpio_in(vms->gic, ppibase
819 + VIRTUAL_PMU_IRQ));
820
821 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
822 sysbus_connect_irq(gicbusdev, i + smp_cpus,
823 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
824 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
825 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
826 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
827 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
828 }
829
830 fdt_add_gic_node(vms);
831
832 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) {
833 create_its(vms);
834 } else if (vms->gic_version == VIRT_GIC_VERSION_2) {
835 create_v2m(vms);
836 }
837 }
838
839 static void create_uart(const VirtMachineState *vms, int uart,
840 MemoryRegion *mem, Chardev *chr)
841 {
842 char *nodename;
843 hwaddr base = vms->memmap[uart].base;
844 hwaddr size = vms->memmap[uart].size;
845 int irq = vms->irqmap[uart];
846 const char compat[] = "arm,pl011\0arm,primecell";
847 const char clocknames[] = "uartclk\0apb_pclk";
848 DeviceState *dev = qdev_new(TYPE_PL011);
849 SysBusDevice *s = SYS_BUS_DEVICE(dev);
850 MachineState *ms = MACHINE(vms);
851
852 qdev_prop_set_chr(dev, "chardev", chr);
853 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
854 memory_region_add_subregion(mem, base,
855 sysbus_mmio_get_region(s, 0));
856 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
857
858 nodename = g_strdup_printf("/pl011@%" PRIx64, base);
859 qemu_fdt_add_subnode(ms->fdt, nodename);
860 /* Note that we can't use setprop_string because of the embedded NUL */
861 qemu_fdt_setprop(ms->fdt, nodename, "compatible",
862 compat, sizeof(compat));
863 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
864 2, base, 2, size);
865 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
866 GIC_FDT_IRQ_TYPE_SPI, irq,
867 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
868 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks",
869 vms->clock_phandle, vms->clock_phandle);
870 qemu_fdt_setprop(ms->fdt, nodename, "clock-names",
871 clocknames, sizeof(clocknames));
872
873 if (uart == VIRT_UART) {
874 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename);
875 } else {
876 /* Mark as not usable by the normal world */
877 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
878 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
879
880 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path",
881 nodename);
882 }
883
884 g_free(nodename);
885 }
886
887 static void create_rtc(const VirtMachineState *vms)
888 {
889 char *nodename;
890 hwaddr base = vms->memmap[VIRT_RTC].base;
891 hwaddr size = vms->memmap[VIRT_RTC].size;
892 int irq = vms->irqmap[VIRT_RTC];
893 const char compat[] = "arm,pl031\0arm,primecell";
894 MachineState *ms = MACHINE(vms);
895
896 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq));
897
898 nodename = g_strdup_printf("/pl031@%" PRIx64, base);
899 qemu_fdt_add_subnode(ms->fdt, nodename);
900 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
901 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
902 2, base, 2, size);
903 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
904 GIC_FDT_IRQ_TYPE_SPI, irq,
905 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
906 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
907 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
908 g_free(nodename);
909 }
910
911 static DeviceState *gpio_key_dev;
912 static void virt_powerdown_req(Notifier *n, void *opaque)
913 {
914 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier);
915
916 if (s->acpi_dev) {
917 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS);
918 } else {
919 /* use gpio Pin 3 for power button event */
920 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
921 }
922 }
923
924 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev,
925 uint32_t phandle)
926 {
927 gpio_key_dev = sysbus_create_simple("gpio-key", -1,
928 qdev_get_gpio_in(pl061_dev, 3));
929
930 qemu_fdt_add_subnode(fdt, "/gpio-keys");
931 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys");
932
933 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff");
934 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff",
935 "label", "GPIO Key Poweroff");
936 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code",
937 KEY_POWER);
938 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff",
939 "gpios", phandle, 3, 0);
940 }
941
942 #define SECURE_GPIO_POWEROFF 0
943 #define SECURE_GPIO_RESET 1
944
945 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev,
946 uint32_t phandle)
947 {
948 DeviceState *gpio_pwr_dev;
949
950 /* gpio-pwr */
951 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL);
952
953 /* connect secure pl061 to gpio-pwr */
954 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET,
955 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0));
956 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF,
957 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0));
958
959 qemu_fdt_add_subnode(fdt, "/gpio-poweroff");
960 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible",
961 "gpio-poweroff");
962 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff",
963 "gpios", phandle, SECURE_GPIO_POWEROFF, 0);
964 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled");
965 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status",
966 "okay");
967
968 qemu_fdt_add_subnode(fdt, "/gpio-restart");
969 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible",
970 "gpio-restart");
971 qemu_fdt_setprop_cells(fdt, "/gpio-restart",
972 "gpios", phandle, SECURE_GPIO_RESET, 0);
973 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled");
974 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status",
975 "okay");
976 }
977
978 static void create_gpio_devices(const VirtMachineState *vms, int gpio,
979 MemoryRegion *mem)
980 {
981 char *nodename;
982 DeviceState *pl061_dev;
983 hwaddr base = vms->memmap[gpio].base;
984 hwaddr size = vms->memmap[gpio].size;
985 int irq = vms->irqmap[gpio];
986 const char compat[] = "arm,pl061\0arm,primecell";
987 SysBusDevice *s;
988 MachineState *ms = MACHINE(vms);
989
990 pl061_dev = qdev_new("pl061");
991 /* Pull lines down to 0 if not driven by the PL061 */
992 qdev_prop_set_uint32(pl061_dev, "pullups", 0);
993 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff);
994 s = SYS_BUS_DEVICE(pl061_dev);
995 sysbus_realize_and_unref(s, &error_fatal);
996 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0));
997 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
998
999 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt);
1000 nodename = g_strdup_printf("/pl061@%" PRIx64, base);
1001 qemu_fdt_add_subnode(ms->fdt, nodename);
1002 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1003 2, base, 2, size);
1004 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
1005 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2);
1006 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0);
1007 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1008 GIC_FDT_IRQ_TYPE_SPI, irq,
1009 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
1010 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
1011 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
1012 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle);
1013
1014 if (gpio != VIRT_GPIO) {
1015 /* Mark as not usable by the normal world */
1016 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1017 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1018 }
1019 g_free(nodename);
1020
1021 /* Child gpio devices */
1022 if (gpio == VIRT_GPIO) {
1023 create_gpio_keys(ms->fdt, pl061_dev, phandle);
1024 } else {
1025 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle);
1026 }
1027 }
1028
1029 static void create_virtio_devices(const VirtMachineState *vms)
1030 {
1031 int i;
1032 hwaddr size = vms->memmap[VIRT_MMIO].size;
1033 MachineState *ms = MACHINE(vms);
1034
1035 /* We create the transports in forwards order. Since qbus_realize()
1036 * prepends (not appends) new child buses, the incrementing loop below will
1037 * create a list of virtio-mmio buses with decreasing base addresses.
1038 *
1039 * When a -device option is processed from the command line,
1040 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
1041 * order. The upshot is that -device options in increasing command line
1042 * order are mapped to virtio-mmio buses with decreasing base addresses.
1043 *
1044 * When this code was originally written, that arrangement ensured that the
1045 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
1046 * the first -device on the command line. (The end-to-end order is a
1047 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
1048 * guest kernel's name-to-address assignment strategy.)
1049 *
1050 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
1051 * the message, if not necessarily the code, of commit 70161ff336.
1052 * Therefore the loop now establishes the inverse of the original intent.
1053 *
1054 * Unfortunately, we can't counteract the kernel change by reversing the
1055 * loop; it would break existing command lines.
1056 *
1057 * In any case, the kernel makes no guarantee about the stability of
1058 * enumeration order of virtio devices (as demonstrated by it changing
1059 * between kernel versions). For reliable and stable identification
1060 * of disks users must use UUIDs or similar mechanisms.
1061 */
1062 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
1063 int irq = vms->irqmap[VIRT_MMIO] + i;
1064 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1065
1066 sysbus_create_simple("virtio-mmio", base,
1067 qdev_get_gpio_in(vms->gic, irq));
1068 }
1069
1070 /* We add dtb nodes in reverse order so that they appear in the finished
1071 * device tree lowest address first.
1072 *
1073 * Note that this mapping is independent of the loop above. The previous
1074 * loop influences virtio device to virtio transport assignment, whereas
1075 * this loop controls how virtio transports are laid out in the dtb.
1076 */
1077 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
1078 char *nodename;
1079 int irq = vms->irqmap[VIRT_MMIO] + i;
1080 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1081
1082 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
1083 qemu_fdt_add_subnode(ms->fdt, nodename);
1084 qemu_fdt_setprop_string(ms->fdt, nodename,
1085 "compatible", "virtio,mmio");
1086 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1087 2, base, 2, size);
1088 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1089 GIC_FDT_IRQ_TYPE_SPI, irq,
1090 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1091 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1092 g_free(nodename);
1093 }
1094 }
1095
1096 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
1097
1098 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms,
1099 const char *name,
1100 const char *alias_prop_name)
1101 {
1102 /*
1103 * Create a single flash device. We use the same parameters as
1104 * the flash devices on the Versatile Express board.
1105 */
1106 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
1107
1108 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
1109 qdev_prop_set_uint8(dev, "width", 4);
1110 qdev_prop_set_uint8(dev, "device-width", 2);
1111 qdev_prop_set_bit(dev, "big-endian", false);
1112 qdev_prop_set_uint16(dev, "id0", 0x89);
1113 qdev_prop_set_uint16(dev, "id1", 0x18);
1114 qdev_prop_set_uint16(dev, "id2", 0x00);
1115 qdev_prop_set_uint16(dev, "id3", 0x00);
1116 qdev_prop_set_string(dev, "name", name);
1117 object_property_add_child(OBJECT(vms), name, OBJECT(dev));
1118 object_property_add_alias(OBJECT(vms), alias_prop_name,
1119 OBJECT(dev), "drive");
1120 return PFLASH_CFI01(dev);
1121 }
1122
1123 static void virt_flash_create(VirtMachineState *vms)
1124 {
1125 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0");
1126 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1");
1127 }
1128
1129 static void virt_flash_map1(PFlashCFI01 *flash,
1130 hwaddr base, hwaddr size,
1131 MemoryRegion *sysmem)
1132 {
1133 DeviceState *dev = DEVICE(flash);
1134
1135 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
1136 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
1137 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
1138 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1139
1140 memory_region_add_subregion(sysmem, base,
1141 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
1142 0));
1143 }
1144
1145 static void virt_flash_map(VirtMachineState *vms,
1146 MemoryRegion *sysmem,
1147 MemoryRegion *secure_sysmem)
1148 {
1149 /*
1150 * Map two flash devices to fill the VIRT_FLASH space in the memmap.
1151 * sysmem is the system memory space. secure_sysmem is the secure view
1152 * of the system, and the first flash device should be made visible only
1153 * there. The second flash device is visible to both secure and nonsecure.
1154 * If sysmem == secure_sysmem this means there is no separate Secure
1155 * address space and both flash devices are generally visible.
1156 */
1157 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1158 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1159
1160 virt_flash_map1(vms->flash[0], flashbase, flashsize,
1161 secure_sysmem);
1162 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize,
1163 sysmem);
1164 }
1165
1166 static void virt_flash_fdt(VirtMachineState *vms,
1167 MemoryRegion *sysmem,
1168 MemoryRegion *secure_sysmem)
1169 {
1170 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1171 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1172 MachineState *ms = MACHINE(vms);
1173 char *nodename;
1174
1175 if (sysmem == secure_sysmem) {
1176 /* Report both flash devices as a single node in the DT */
1177 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
1178 qemu_fdt_add_subnode(ms->fdt, nodename);
1179 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1180 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1181 2, flashbase, 2, flashsize,
1182 2, flashbase + flashsize, 2, flashsize);
1183 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1184 g_free(nodename);
1185 } else {
1186 /*
1187 * Report the devices as separate nodes so we can mark one as
1188 * only visible to the secure world.
1189 */
1190 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
1191 qemu_fdt_add_subnode(ms->fdt, nodename);
1192 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1193 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1194 2, flashbase, 2, flashsize);
1195 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1196 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1197 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1198 g_free(nodename);
1199
1200 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize);
1201 qemu_fdt_add_subnode(ms->fdt, nodename);
1202 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1203 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1204 2, flashbase + flashsize, 2, flashsize);
1205 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1206 g_free(nodename);
1207 }
1208 }
1209
1210 static bool virt_firmware_init(VirtMachineState *vms,
1211 MemoryRegion *sysmem,
1212 MemoryRegion *secure_sysmem)
1213 {
1214 int i;
1215 const char *bios_name;
1216 BlockBackend *pflash_blk0;
1217
1218 /* Map legacy -drive if=pflash to machine properties */
1219 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) {
1220 pflash_cfi01_legacy_drive(vms->flash[i],
1221 drive_get(IF_PFLASH, 0, i));
1222 }
1223
1224 virt_flash_map(vms, sysmem, secure_sysmem);
1225
1226 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]);
1227
1228 bios_name = MACHINE(vms)->firmware;
1229 if (bios_name) {
1230 char *fname;
1231 MemoryRegion *mr;
1232 int image_size;
1233
1234 if (pflash_blk0) {
1235 error_report("The contents of the first flash device may be "
1236 "specified with -bios or with -drive if=pflash... "
1237 "but you cannot use both options at once");
1238 exit(1);
1239 }
1240
1241 /* Fall back to -bios */
1242
1243 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1244 if (!fname) {
1245 error_report("Could not find ROM image '%s'", bios_name);
1246 exit(1);
1247 }
1248 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0);
1249 image_size = load_image_mr(fname, mr);
1250 g_free(fname);
1251 if (image_size < 0) {
1252 error_report("Could not load ROM image '%s'", bios_name);
1253 exit(1);
1254 }
1255 }
1256
1257 return pflash_blk0 || bios_name;
1258 }
1259
1260 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
1261 {
1262 MachineState *ms = MACHINE(vms);
1263 hwaddr base = vms->memmap[VIRT_FW_CFG].base;
1264 hwaddr size = vms->memmap[VIRT_FW_CFG].size;
1265 FWCfgState *fw_cfg;
1266 char *nodename;
1267
1268 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
1269 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
1270
1271 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
1272 qemu_fdt_add_subnode(ms->fdt, nodename);
1273 qemu_fdt_setprop_string(ms->fdt, nodename,
1274 "compatible", "qemu,fw-cfg-mmio");
1275 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1276 2, base, 2, size);
1277 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1278 g_free(nodename);
1279 return fw_cfg;
1280 }
1281
1282 static void create_pcie_irq_map(const MachineState *ms,
1283 uint32_t gic_phandle,
1284 int first_irq, const char *nodename)
1285 {
1286 int devfn, pin;
1287 uint32_t full_irq_map[4 * 4 * 10] = { 0 };
1288 uint32_t *irq_map = full_irq_map;
1289
1290 for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
1291 for (pin = 0; pin < 4; pin++) {
1292 int irq_type = GIC_FDT_IRQ_TYPE_SPI;
1293 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
1294 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
1295 int i;
1296
1297 uint32_t map[] = {
1298 devfn << 8, 0, 0, /* devfn */
1299 pin + 1, /* PCI pin */
1300 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */
1301
1302 /* Convert map to big endian */
1303 for (i = 0; i < 10; i++) {
1304 irq_map[i] = cpu_to_be32(map[i]);
1305 }
1306 irq_map += 10;
1307 }
1308 }
1309
1310 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map",
1311 full_irq_map, sizeof(full_irq_map));
1312
1313 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask",
1314 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */
1315 0, 0,
1316 0x7 /* PCI irq */);
1317 }
1318
1319 static void create_smmu(const VirtMachineState *vms,
1320 PCIBus *bus)
1321 {
1322 char *node;
1323 const char compat[] = "arm,smmu-v3";
1324 int irq = vms->irqmap[VIRT_SMMU];
1325 int i;
1326 hwaddr base = vms->memmap[VIRT_SMMU].base;
1327 hwaddr size = vms->memmap[VIRT_SMMU].size;
1328 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
1329 DeviceState *dev;
1330 MachineState *ms = MACHINE(vms);
1331
1332 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
1333 return;
1334 }
1335
1336 dev = qdev_new("arm-smmuv3");
1337
1338 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
1339 &error_abort);
1340 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1341 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1342 for (i = 0; i < NUM_SMMU_IRQS; i++) {
1343 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1344 qdev_get_gpio_in(vms->gic, irq + i));
1345 }
1346
1347 node = g_strdup_printf("/smmuv3@%" PRIx64, base);
1348 qemu_fdt_add_subnode(ms->fdt, node);
1349 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1350 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size);
1351
1352 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts",
1353 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1354 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1355 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1356 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1357
1358 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,
1359 sizeof(irq_names));
1360
1361 qemu_fdt_setprop_cell(ms->fdt, node, "clocks", vms->clock_phandle);
1362 qemu_fdt_setprop_string(ms->fdt, node, "clock-names", "apb_pclk");
1363 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);
1364
1365 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1366
1367 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1368 g_free(node);
1369 }
1370
1371 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms)
1372 {
1373 const char compat[] = "virtio,pci-iommu";
1374 uint16_t bdf = vms->virtio_iommu_bdf;
1375 MachineState *ms = MACHINE(vms);
1376 char *node;
1377
1378 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1379
1380 node = g_strdup_printf("%s/virtio_iommu@%d", vms->pciehb_nodename, bdf);
1381 qemu_fdt_add_subnode(ms->fdt, node);
1382 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1383 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg",
1384 1, bdf << 8, 1, 0, 1, 0,
1385 1, 0, 1, 0);
1386
1387 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1388 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1389 g_free(node);
1390
1391 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map",
1392 0x0, vms->iommu_phandle, 0x0, bdf,
1393 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf);
1394 }
1395
1396 static void create_pcie(VirtMachineState *vms)
1397 {
1398 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
1399 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
1400 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base;
1401 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size;
1402 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
1403 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
1404 hwaddr base_ecam, size_ecam;
1405 hwaddr base = base_mmio;
1406 int nr_pcie_buses;
1407 int irq = vms->irqmap[VIRT_PCIE];
1408 MemoryRegion *mmio_alias;
1409 MemoryRegion *mmio_reg;
1410 MemoryRegion *ecam_alias;
1411 MemoryRegion *ecam_reg;
1412 DeviceState *dev;
1413 char *nodename;
1414 int i, ecam_id;
1415 PCIHostState *pci;
1416 MachineState *ms = MACHINE(vms);
1417
1418 dev = qdev_new(TYPE_GPEX_HOST);
1419 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1420
1421 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
1422 base_ecam = vms->memmap[ecam_id].base;
1423 size_ecam = vms->memmap[ecam_id].size;
1424 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
1425 /* Map only the first size_ecam bytes of ECAM space */
1426 ecam_alias = g_new0(MemoryRegion, 1);
1427 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1428 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1429 ecam_reg, 0, size_ecam);
1430 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
1431
1432 /* Map the MMIO window into system address space so as to expose
1433 * the section of PCI MMIO space which starts at the same base address
1434 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1435 * the window).
1436 */
1437 mmio_alias = g_new0(MemoryRegion, 1);
1438 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1439 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1440 mmio_reg, base_mmio, size_mmio);
1441 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
1442
1443 if (vms->highmem_mmio) {
1444 /* Map high MMIO space */
1445 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
1446
1447 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1448 mmio_reg, base_mmio_high, size_mmio_high);
1449 memory_region_add_subregion(get_system_memory(), base_mmio_high,
1450 high_mmio_alias);
1451 }
1452
1453 /* Map IO port space */
1454 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
1455
1456 for (i = 0; i < GPEX_NUM_IRQS; i++) {
1457 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1458 qdev_get_gpio_in(vms->gic, irq + i));
1459 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
1460 }
1461
1462 pci = PCI_HOST_BRIDGE(dev);
1463 pci->bypass_iommu = vms->default_bus_bypass_iommu;
1464 vms->bus = pci->bus;
1465 if (vms->bus) {
1466 for (i = 0; i < nb_nics; i++) {
1467 NICInfo *nd = &nd_table[i];
1468
1469 if (!nd->model) {
1470 nd->model = g_strdup("virtio");
1471 }
1472
1473 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
1474 }
1475 }
1476
1477 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base);
1478 qemu_fdt_add_subnode(ms->fdt, nodename);
1479 qemu_fdt_setprop_string(ms->fdt, nodename,
1480 "compatible", "pci-host-ecam-generic");
1481 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci");
1482 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3);
1483 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2);
1484 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0);
1485 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0,
1486 nr_pcie_buses - 1);
1487 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1488
1489 if (vms->msi_phandle) {
1490 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-parent",
1491 vms->msi_phandle);
1492 }
1493
1494 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1495 2, base_ecam, 2, size_ecam);
1496
1497 if (vms->highmem_mmio) {
1498 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1499 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1500 2, base_pio, 2, size_pio,
1501 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1502 2, base_mmio, 2, size_mmio,
1503 1, FDT_PCI_RANGE_MMIO_64BIT,
1504 2, base_mmio_high,
1505 2, base_mmio_high, 2, size_mmio_high);
1506 } else {
1507 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1508 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1509 2, base_pio, 2, size_pio,
1510 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1511 2, base_mmio, 2, size_mmio);
1512 }
1513
1514 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
1515 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename);
1516
1517 if (vms->iommu) {
1518 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1519
1520 switch (vms->iommu) {
1521 case VIRT_IOMMU_SMMUV3:
1522 create_smmu(vms, vms->bus);
1523 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map",
1524 0x0, vms->iommu_phandle, 0x0, 0x10000);
1525 break;
1526 default:
1527 g_assert_not_reached();
1528 }
1529 }
1530 }
1531
1532 static void create_platform_bus(VirtMachineState *vms)
1533 {
1534 DeviceState *dev;
1535 SysBusDevice *s;
1536 int i;
1537 MemoryRegion *sysmem = get_system_memory();
1538
1539 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
1540 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
1541 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
1542 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
1543 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1544 vms->platform_bus_dev = dev;
1545
1546 s = SYS_BUS_DEVICE(dev);
1547 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) {
1548 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i;
1549 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq));
1550 }
1551
1552 memory_region_add_subregion(sysmem,
1553 vms->memmap[VIRT_PLATFORM_BUS].base,
1554 sysbus_mmio_get_region(s, 0));
1555 }
1556
1557 static void create_tag_ram(MemoryRegion *tag_sysmem,
1558 hwaddr base, hwaddr size,
1559 const char *name)
1560 {
1561 MemoryRegion *tagram = g_new(MemoryRegion, 1);
1562
1563 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal);
1564 memory_region_add_subregion(tag_sysmem, base / 32, tagram);
1565 }
1566
1567 static void create_secure_ram(VirtMachineState *vms,
1568 MemoryRegion *secure_sysmem,
1569 MemoryRegion *secure_tag_sysmem)
1570 {
1571 MemoryRegion *secram = g_new(MemoryRegion, 1);
1572 char *nodename;
1573 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
1574 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
1575 MachineState *ms = MACHINE(vms);
1576
1577 memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
1578 &error_fatal);
1579 memory_region_add_subregion(secure_sysmem, base, secram);
1580
1581 nodename = g_strdup_printf("/secram@%" PRIx64, base);
1582 qemu_fdt_add_subnode(ms->fdt, nodename);
1583 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");
1584 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
1585 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1586 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1587
1588 if (secure_tag_sysmem) {
1589 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag");
1590 }
1591
1592 g_free(nodename);
1593 }
1594
1595 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
1596 {
1597 const VirtMachineState *board = container_of(binfo, VirtMachineState,
1598 bootinfo);
1599 MachineState *ms = MACHINE(board);
1600
1601
1602 *fdt_size = board->fdt_size;
1603 return ms->fdt;
1604 }
1605
1606 static void virt_build_smbios(VirtMachineState *vms)
1607 {
1608 MachineClass *mc = MACHINE_GET_CLASS(vms);
1609 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1610 uint8_t *smbios_tables, *smbios_anchor;
1611 size_t smbios_tables_len, smbios_anchor_len;
1612 const char *product = "QEMU Virtual Machine";
1613
1614 if (kvm_enabled()) {
1615 product = "KVM Virtual Machine";
1616 }
1617
1618 smbios_set_defaults("QEMU", product,
1619 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false,
1620 true, SMBIOS_ENTRY_POINT_TYPE_64);
1621
1622 smbios_get_tables(MACHINE(vms), NULL, 0,
1623 &smbios_tables, &smbios_tables_len,
1624 &smbios_anchor, &smbios_anchor_len,
1625 &error_fatal);
1626
1627 if (smbios_anchor) {
1628 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
1629 smbios_tables, smbios_tables_len);
1630 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
1631 smbios_anchor, smbios_anchor_len);
1632 }
1633 }
1634
1635 static
1636 void virt_machine_done(Notifier *notifier, void *data)
1637 {
1638 VirtMachineState *vms = container_of(notifier, VirtMachineState,
1639 machine_done);
1640 MachineState *ms = MACHINE(vms);
1641 ARMCPU *cpu = ARM_CPU(first_cpu);
1642 struct arm_boot_info *info = &vms->bootinfo;
1643 AddressSpace *as = arm_boot_address_space(cpu, info);
1644
1645 /*
1646 * If the user provided a dtb, we assume the dynamic sysbus nodes
1647 * already are integrated there. This corresponds to a use case where
1648 * the dynamic sysbus nodes are complex and their generation is not yet
1649 * supported. In that case the user can take charge of the guest dt
1650 * while qemu takes charge of the qom stuff.
1651 */
1652 if (info->dtb_filename == NULL) {
1653 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc",
1654 vms->memmap[VIRT_PLATFORM_BUS].base,
1655 vms->memmap[VIRT_PLATFORM_BUS].size,
1656 vms->irqmap[VIRT_PLATFORM_BUS]);
1657 }
1658 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) {
1659 exit(1);
1660 }
1661
1662 fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg);
1663
1664 virt_acpi_setup(vms);
1665 virt_build_smbios(vms);
1666 }
1667
1668 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
1669 {
1670 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
1671 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1672
1673 if (!vmc->disallow_affinity_adjustment) {
1674 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1675 * GIC's target-list limitations. 32-bit KVM hosts currently
1676 * always create clusters of 4 CPUs, but that is expected to
1677 * change when they gain support for gicv3. When KVM is enabled
1678 * it will override the changes we make here, therefore our
1679 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1680 * and to improve SGI efficiency.
1681 */
1682 if (vms->gic_version == VIRT_GIC_VERSION_2) {
1683 clustersz = GIC_TARGETLIST_BITS;
1684 } else {
1685 clustersz = GICV3_TARGETLIST_BITS;
1686 }
1687 }
1688 return arm_cpu_mp_affinity(idx, clustersz);
1689 }
1690
1691 static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
1692 {
1693 MachineState *ms = MACHINE(vms);
1694 hwaddr base, device_memory_base, device_memory_size, memtop;
1695 int i;
1696
1697 vms->memmap = extended_memmap;
1698
1699 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) {
1700 vms->memmap[i] = base_memmap[i];
1701 }
1702
1703 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) {
1704 error_report("unsupported number of memory slots: %"PRIu64,
1705 ms->ram_slots);
1706 exit(EXIT_FAILURE);
1707 }
1708
1709 /*
1710 * !highmem is exactly the same as limiting the PA space to 32bit,
1711 * irrespective of the underlying capabilities of the HW.
1712 */
1713 if (!vms->highmem) {
1714 pa_bits = 32;
1715 }
1716
1717 /*
1718 * We compute the base of the high IO region depending on the
1719 * amount of initial and device memory. The device memory start/size
1720 * is aligned on 1GiB. We never put the high IO region below 256GiB
1721 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1722 * The device region size assumes 1GiB page max alignment per slot.
1723 */
1724 device_memory_base =
1725 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);
1726 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;
1727
1728 /* Base address of the high IO region */
1729 memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB);
1730 if (memtop > BIT_ULL(pa_bits)) {
1731 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n",
1732 pa_bits, memtop - BIT_ULL(pa_bits));
1733 exit(EXIT_FAILURE);
1734 }
1735 if (base < device_memory_base) {
1736 error_report("maxmem/slots too huge");
1737 exit(EXIT_FAILURE);
1738 }
1739 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
1740 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
1741 }
1742
1743 /* We know for sure that at least the memory fits in the PA space */
1744 vms->highest_gpa = memtop - 1;
1745
1746 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
1747 hwaddr size = extended_memmap[i].size;
1748 bool fits;
1749
1750 base = ROUND_UP(base, size);
1751 vms->memmap[i].base = base;
1752 vms->memmap[i].size = size;
1753
1754 /*
1755 * Check each device to see if they fit in the PA space,
1756 * moving highest_gpa as we go.
1757 *
1758 * For each device that doesn't fit, disable it.
1759 */
1760 fits = (base + size) <= BIT_ULL(pa_bits);
1761 if (fits) {
1762 vms->highest_gpa = base + size - 1;
1763 }
1764
1765 switch (i) {
1766 case VIRT_HIGH_GIC_REDIST2:
1767 vms->highmem_redists &= fits;
1768 break;
1769 case VIRT_HIGH_PCIE_ECAM:
1770 vms->highmem_ecam &= fits;
1771 break;
1772 case VIRT_HIGH_PCIE_MMIO:
1773 vms->highmem_mmio &= fits;
1774 break;
1775 }
1776
1777 base += size;
1778 }
1779
1780 if (device_memory_size > 0) {
1781 ms->device_memory = g_malloc0(sizeof(*ms->device_memory));
1782 ms->device_memory->base = device_memory_base;
1783 memory_region_init(&ms->device_memory->mr, OBJECT(vms),
1784 "device-memory", device_memory_size);
1785 }
1786 }
1787
1788 /*
1789 * finalize_gic_version - Determines the final gic_version
1790 * according to the gic-version property
1791 *
1792 * Default GIC type is v2
1793 */
1794 static void finalize_gic_version(VirtMachineState *vms)
1795 {
1796 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
1797
1798 if (kvm_enabled()) {
1799 int probe_bitmap;
1800
1801 if (!kvm_irqchip_in_kernel()) {
1802 switch (vms->gic_version) {
1803 case VIRT_GIC_VERSION_HOST:
1804 warn_report(
1805 "gic-version=host not relevant with kernel-irqchip=off "
1806 "as only userspace GICv2 is supported. Using v2 ...");
1807 return;
1808 case VIRT_GIC_VERSION_MAX:
1809 case VIRT_GIC_VERSION_NOSEL:
1810 vms->gic_version = VIRT_GIC_VERSION_2;
1811 return;
1812 case VIRT_GIC_VERSION_2:
1813 return;
1814 case VIRT_GIC_VERSION_3:
1815 error_report(
1816 "gic-version=3 is not supported with kernel-irqchip=off");
1817 exit(1);
1818 case VIRT_GIC_VERSION_4:
1819 error_report(
1820 "gic-version=4 is not supported with kernel-irqchip=off");
1821 exit(1);
1822 }
1823 }
1824
1825 probe_bitmap = kvm_arm_vgic_probe();
1826 if (!probe_bitmap) {
1827 error_report("Unable to determine GIC version supported by host");
1828 exit(1);
1829 }
1830
1831 switch (vms->gic_version) {
1832 case VIRT_GIC_VERSION_HOST:
1833 case VIRT_GIC_VERSION_MAX:
1834 if (probe_bitmap & KVM_ARM_VGIC_V3) {
1835 vms->gic_version = VIRT_GIC_VERSION_3;
1836 } else {
1837 vms->gic_version = VIRT_GIC_VERSION_2;
1838 }
1839 return;
1840 case VIRT_GIC_VERSION_NOSEL:
1841 if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) {
1842 vms->gic_version = VIRT_GIC_VERSION_2;
1843 } else if (probe_bitmap & KVM_ARM_VGIC_V3) {
1844 /*
1845 * in case the host does not support v2 in-kernel emulation or
1846 * the end-user requested more than 8 VCPUs we now default
1847 * to v3. In any case defaulting to v2 would be broken.
1848 */
1849 vms->gic_version = VIRT_GIC_VERSION_3;
1850 } else if (max_cpus > GIC_NCPU) {
1851 error_report("host only supports in-kernel GICv2 emulation "
1852 "but more than 8 vcpus are requested");
1853 exit(1);
1854 }
1855 break;
1856 case VIRT_GIC_VERSION_2:
1857 case VIRT_GIC_VERSION_3:
1858 break;
1859 case VIRT_GIC_VERSION_4:
1860 error_report("gic-version=4 is not supported with KVM");
1861 exit(1);
1862 }
1863
1864 /* Check chosen version is effectively supported by the host */
1865 if (vms->gic_version == VIRT_GIC_VERSION_2 &&
1866 !(probe_bitmap & KVM_ARM_VGIC_V2)) {
1867 error_report("host does not support in-kernel GICv2 emulation");
1868 exit(1);
1869 } else if (vms->gic_version == VIRT_GIC_VERSION_3 &&
1870 !(probe_bitmap & KVM_ARM_VGIC_V3)) {
1871 error_report("host does not support in-kernel GICv3 emulation");
1872 exit(1);
1873 }
1874 return;
1875 }
1876
1877 /* TCG mode */
1878 switch (vms->gic_version) {
1879 case VIRT_GIC_VERSION_NOSEL:
1880 vms->gic_version = VIRT_GIC_VERSION_2;
1881 break;
1882 case VIRT_GIC_VERSION_MAX:
1883 if (module_object_class_by_name("arm-gicv3")) {
1884 /* CONFIG_ARM_GICV3_TCG was set */
1885 if (vms->virt) {
1886 /* GICv4 only makes sense if CPU has EL2 */
1887 vms->gic_version = VIRT_GIC_VERSION_4;
1888 } else {
1889 vms->gic_version = VIRT_GIC_VERSION_3;
1890 }
1891 } else {
1892 vms->gic_version = VIRT_GIC_VERSION_2;
1893 }
1894 break;
1895 case VIRT_GIC_VERSION_HOST:
1896 error_report("gic-version=host requires KVM");
1897 exit(1);
1898 case VIRT_GIC_VERSION_4:
1899 if (!vms->virt) {
1900 error_report("gic-version=4 requires virtualization enabled");
1901 exit(1);
1902 }
1903 break;
1904 case VIRT_GIC_VERSION_2:
1905 case VIRT_GIC_VERSION_3:
1906 break;
1907 }
1908 }
1909
1910 /*
1911 * virt_cpu_post_init() must be called after the CPUs have
1912 * been realized and the GIC has been created.
1913 */
1914 static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem)
1915 {
1916 int max_cpus = MACHINE(vms)->smp.max_cpus;
1917 bool aarch64, pmu, steal_time;
1918 CPUState *cpu;
1919
1920 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
1921 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
1922 steal_time = object_property_get_bool(OBJECT(first_cpu),
1923 "kvm-steal-time", NULL);
1924
1925 if (kvm_enabled()) {
1926 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base;
1927 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size;
1928
1929 if (steal_time) {
1930 MemoryRegion *pvtime = g_new(MemoryRegion, 1);
1931 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU;
1932
1933 /* The memory region size must be a multiple of host page size. */
1934 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size);
1935
1936 if (pvtime_size > pvtime_reg_size) {
1937 error_report("pvtime requires a %" HWADDR_PRId
1938 " byte memory region for %d CPUs,"
1939 " but only %" HWADDR_PRId " has been reserved",
1940 pvtime_size, max_cpus, pvtime_reg_size);
1941 exit(1);
1942 }
1943
1944 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL);
1945 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime);
1946 }
1947
1948 CPU_FOREACH(cpu) {
1949 if (pmu) {
1950 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
1951 if (kvm_irqchip_in_kernel()) {
1952 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
1953 }
1954 kvm_arm_pmu_init(cpu);
1955 }
1956 if (steal_time) {
1957 kvm_arm_pvtime_init(cpu, pvtime_reg_base +
1958 cpu->cpu_index * PVTIME_SIZE_PER_CPU);
1959 }
1960 }
1961 } else {
1962 if (aarch64 && vms->highmem) {
1963 int requested_pa_size = 64 - clz64(vms->highest_gpa);
1964 int pamax = arm_pamax(ARM_CPU(first_cpu));
1965
1966 if (pamax < requested_pa_size) {
1967 error_report("VCPU supports less PA bits (%d) than "
1968 "requested by the memory map (%d)",
1969 pamax, requested_pa_size);
1970 exit(1);
1971 }
1972 }
1973 }
1974 }
1975
1976 static void machvirt_init(MachineState *machine)
1977 {
1978 VirtMachineState *vms = VIRT_MACHINE(machine);
1979 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
1980 MachineClass *mc = MACHINE_GET_CLASS(machine);
1981 const CPUArchIdList *possible_cpus;
1982 MemoryRegion *sysmem = get_system_memory();
1983 MemoryRegion *secure_sysmem = NULL;
1984 MemoryRegion *tag_sysmem = NULL;
1985 MemoryRegion *secure_tag_sysmem = NULL;
1986 int n, virt_max_cpus;
1987 bool firmware_loaded;
1988 bool aarch64 = true;
1989 bool has_ged = !vmc->no_ged;
1990 unsigned int smp_cpus = machine->smp.cpus;
1991 unsigned int max_cpus = machine->smp.max_cpus;
1992
1993 if (!cpu_type_valid(machine->cpu_type)) {
1994 error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
1995 exit(1);
1996 }
1997
1998 possible_cpus = mc->possible_cpu_arch_ids(machine);
1999
2000 /*
2001 * In accelerated mode, the memory map is computed earlier in kvm_type()
2002 * to create a VM with the right number of IPA bits.
2003 */
2004 if (!vms->memmap) {
2005 Object *cpuobj;
2006 ARMCPU *armcpu;
2007 int pa_bits;
2008
2009 /*
2010 * Instanciate a temporary CPU object to find out about what
2011 * we are about to deal with. Once this is done, get rid of
2012 * the object.
2013 */
2014 cpuobj = object_new(possible_cpus->cpus[0].type);
2015 armcpu = ARM_CPU(cpuobj);
2016
2017 pa_bits = arm_pamax(armcpu);
2018
2019 object_unref(cpuobj);
2020
2021 virt_set_memmap(vms, pa_bits);
2022 }
2023
2024 /* We can probe only here because during property set
2025 * KVM is not available yet
2026 */
2027 finalize_gic_version(vms);
2028
2029 if (vms->secure) {
2030 /*
2031 * The Secure view of the world is the same as the NonSecure,
2032 * but with a few extra devices. Create it as a container region
2033 * containing the system memory at low priority; any secure-only
2034 * devices go in at higher priority and take precedence.
2035 */
2036 secure_sysmem = g_new(MemoryRegion, 1);
2037 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
2038 UINT64_MAX);
2039 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
2040 }
2041
2042 firmware_loaded = virt_firmware_init(vms, sysmem,
2043 secure_sysmem ?: sysmem);
2044
2045 /* If we have an EL3 boot ROM then the assumption is that it will
2046 * implement PSCI itself, so disable QEMU's internal implementation
2047 * so it doesn't get in the way. Instead of starting secondary
2048 * CPUs in PSCI powerdown state we will start them all running and
2049 * let the boot ROM sort them out.
2050 * The usual case is that we do use QEMU's PSCI implementation;
2051 * if the guest has EL2 then we will use SMC as the conduit,
2052 * and otherwise we will use HVC (for backwards compatibility and
2053 * because if we're using KVM then we must use HVC).
2054 */
2055 if (vms->secure && firmware_loaded) {
2056 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
2057 } else if (vms->virt) {
2058 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
2059 } else {
2060 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
2061 }
2062
2063 /*
2064 * The maximum number of CPUs depends on the GIC version, or on how
2065 * many redistributors we can fit into the memory map (which in turn
2066 * depends on whether this is a GICv3 or v4).
2067 */
2068 if (vms->gic_version == VIRT_GIC_VERSION_2) {
2069 virt_max_cpus = GIC_NCPU;
2070 } else {
2071 virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST) +
2072 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
2073 }
2074
2075 if (max_cpus > virt_max_cpus) {
2076 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
2077 "supported by machine 'mach-virt' (%d)",
2078 max_cpus, virt_max_cpus);
2079 exit(1);
2080 }
2081
2082 if (vms->secure && (kvm_enabled() || hvf_enabled())) {
2083 error_report("mach-virt: %s does not support providing "
2084 "Security extensions (TrustZone) to the guest CPU",
2085 kvm_enabled() ? "KVM" : "HVF");
2086 exit(1);
2087 }
2088
2089 if (vms->virt && (kvm_enabled() || hvf_enabled())) {
2090 error_report("mach-virt: %s does not support providing "
2091 "Virtualization extensions to the guest CPU",
2092 kvm_enabled() ? "KVM" : "HVF");
2093 exit(1);
2094 }
2095
2096 if (vms->mte && (kvm_enabled() || hvf_enabled())) {
2097 error_report("mach-virt: %s does not support providing "
2098 "MTE to the guest CPU",
2099 kvm_enabled() ? "KVM" : "HVF");
2100 exit(1);
2101 }
2102
2103 create_fdt(vms);
2104
2105 assert(possible_cpus->len == max_cpus);
2106 for (n = 0; n < possible_cpus->len; n++) {
2107 Object *cpuobj;
2108 CPUState *cs;
2109
2110 if (n >= smp_cpus) {
2111 break;
2112 }
2113
2114 cpuobj = object_new(possible_cpus->cpus[n].type);
2115 object_property_set_int(cpuobj, "mp-affinity",
2116 possible_cpus->cpus[n].arch_id, NULL);
2117
2118 cs = CPU(cpuobj);
2119 cs->cpu_index = n;
2120
2121 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
2122 &error_fatal);
2123
2124 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL);
2125
2126 if (!vms->secure) {
2127 object_property_set_bool(cpuobj, "has_el3", false, NULL);
2128 }
2129
2130 if (!vms->virt && object_property_find(cpuobj, "has_el2")) {
2131 object_property_set_bool(cpuobj, "has_el2", false, NULL);
2132 }
2133
2134 if (vmc->kvm_no_adjvtime &&
2135 object_property_find(cpuobj, "kvm-no-adjvtime")) {
2136 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL);
2137 }
2138
2139 if (vmc->no_kvm_steal_time &&
2140 object_property_find(cpuobj, "kvm-steal-time")) {
2141 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL);
2142 }
2143
2144 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) {
2145 object_property_set_bool(cpuobj, "pmu", false, NULL);
2146 }
2147
2148 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) {
2149 object_property_set_bool(cpuobj, "lpa2", false, NULL);
2150 }
2151
2152 if (object_property_find(cpuobj, "reset-cbar")) {
2153 object_property_set_int(cpuobj, "reset-cbar",
2154 vms->memmap[VIRT_CPUPERIPHS].base,
2155 &error_abort);
2156 }
2157
2158 object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
2159 &error_abort);
2160 if (vms->secure) {
2161 object_property_set_link(cpuobj, "secure-memory",
2162 OBJECT(secure_sysmem), &error_abort);
2163 }
2164
2165 if (vms->mte) {
2166 /* Create the memory region only once, but link to all cpus. */
2167 if (!tag_sysmem) {
2168 /*
2169 * The property exists only if MemTag is supported.
2170 * If it is, we must allocate the ram to back that up.
2171 */
2172 if (!object_property_find(cpuobj, "tag-memory")) {
2173 error_report("MTE requested, but not supported "
2174 "by the guest CPU");
2175 exit(1);
2176 }
2177
2178 tag_sysmem = g_new(MemoryRegion, 1);
2179 memory_region_init(tag_sysmem, OBJECT(machine),
2180 "tag-memory", UINT64_MAX / 32);
2181
2182 if (vms->secure) {
2183 secure_tag_sysmem = g_new(MemoryRegion, 1);
2184 memory_region_init(secure_tag_sysmem, OBJECT(machine),
2185 "secure-tag-memory", UINT64_MAX / 32);
2186
2187 /* As with ram, secure-tag takes precedence over tag. */
2188 memory_region_add_subregion_overlap(secure_tag_sysmem, 0,
2189 tag_sysmem, -1);
2190 }
2191 }
2192
2193 object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem),
2194 &error_abort);
2195 if (vms->secure) {
2196 object_property_set_link(cpuobj, "secure-tag-memory",
2197 OBJECT(secure_tag_sysmem),
2198 &error_abort);
2199 }
2200 }
2201
2202 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
2203 object_unref(cpuobj);
2204 }
2205 fdt_add_timer_nodes(vms);
2206 fdt_add_cpu_nodes(vms);
2207
2208 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base,
2209 machine->ram);
2210 if (machine->device_memory) {
2211 memory_region_add_subregion(sysmem, machine->device_memory->base,
2212 &machine->device_memory->mr);
2213 }
2214
2215 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
2216
2217 create_gic(vms, sysmem);
2218
2219 virt_cpu_post_init(vms, sysmem);
2220
2221 fdt_add_pmu_nodes(vms);
2222
2223 create_uart(vms, VIRT_UART, sysmem, serial_hd(0));
2224
2225 if (vms->secure) {
2226 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem);
2227 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1));
2228 }
2229
2230 if (tag_sysmem) {
2231 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base,
2232 machine->ram_size, "mach-virt.tag");
2233 }
2234
2235 vms->highmem_ecam &= (!firmware_loaded || aarch64);
2236
2237 create_rtc(vms);
2238
2239 create_pcie(vms);
2240
2241 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) {
2242 vms->acpi_dev = create_acpi_ged(vms);
2243 } else {
2244 create_gpio_devices(vms, VIRT_GPIO, sysmem);
2245 }
2246
2247 if (vms->secure && !vmc->no_secure_gpio) {
2248 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem);
2249 }
2250
2251 /* connect powerdown request */
2252 vms->powerdown_notifier.notify = virt_powerdown_req;
2253 qemu_register_powerdown_notifier(&vms->powerdown_notifier);
2254
2255 /* Create mmio transports, so the user can create virtio backends
2256 * (which will be automatically plugged in to the transports). If
2257 * no backend is created the transport will just sit harmlessly idle.
2258 */
2259 create_virtio_devices(vms);
2260
2261 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
2262 rom_set_fw(vms->fw_cfg);
2263
2264 create_platform_bus(vms);
2265
2266 if (machine->nvdimms_state->is_enabled) {
2267 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = {
2268 .space_id = AML_AS_SYSTEM_MEMORY,
2269 .address = vms->memmap[VIRT_NVDIMM_ACPI].base,
2270 .bit_width = NVDIMM_ACPI_IO_LEN << 3
2271 };
2272
2273 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem,
2274 arm_virt_nvdimm_acpi_dsmio,
2275 vms->fw_cfg, OBJECT(vms));
2276 }
2277
2278 vms->bootinfo.ram_size = machine->ram_size;
2279 vms->bootinfo.board_id = -1;
2280 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
2281 vms->bootinfo.get_dtb = machvirt_dtb;
2282 vms->bootinfo.skip_dtb_autoload = true;
2283 vms->bootinfo.firmware_loaded = firmware_loaded;
2284 vms->bootinfo.psci_conduit = vms->psci_conduit;
2285 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo);
2286
2287 vms->machine_done.notify = virt_machine_done;
2288 qemu_add_machine_init_done_notifier(&vms->machine_done);
2289 }
2290
2291 static bool virt_get_secure(Object *obj, Error **errp)
2292 {
2293 VirtMachineState *vms = VIRT_MACHINE(obj);
2294
2295 return vms->secure;
2296 }
2297
2298 static void virt_set_secure(Object *obj, bool value, Error **errp)
2299 {
2300 VirtMachineState *vms = VIRT_MACHINE(obj);
2301
2302 vms->secure = value;
2303 }
2304
2305 static bool virt_get_virt(Object *obj, Error **errp)
2306 {
2307 VirtMachineState *vms = VIRT_MACHINE(obj);
2308
2309 return vms->virt;
2310 }
2311
2312 static void virt_set_virt(Object *obj, bool value, Error **errp)
2313 {
2314 VirtMachineState *vms = VIRT_MACHINE(obj);
2315
2316 vms->virt = value;
2317 }
2318
2319 static bool virt_get_highmem(Object *obj, Error **errp)
2320 {
2321 VirtMachineState *vms = VIRT_MACHINE(obj);
2322
2323 return vms->highmem;
2324 }
2325
2326 static void virt_set_highmem(Object *obj, bool value, Error **errp)
2327 {
2328 VirtMachineState *vms = VIRT_MACHINE(obj);
2329
2330 vms->highmem = value;
2331 }
2332
2333 static bool virt_get_its(Object *obj, Error **errp)
2334 {
2335 VirtMachineState *vms = VIRT_MACHINE(obj);
2336
2337 return vms->its;
2338 }
2339
2340 static void virt_set_its(Object *obj, bool value, Error **errp)
2341 {
2342 VirtMachineState *vms = VIRT_MACHINE(obj);
2343
2344 vms->its = value;
2345 }
2346
2347 static bool virt_get_dtb_randomness(Object *obj, Error **errp)
2348 {
2349 VirtMachineState *vms = VIRT_MACHINE(obj);
2350
2351 return vms->dtb_randomness;
2352 }
2353
2354 static void virt_set_dtb_randomness(Object *obj, bool value, Error **errp)
2355 {
2356 VirtMachineState *vms = VIRT_MACHINE(obj);
2357
2358 vms->dtb_randomness = value;
2359 }
2360
2361 static char *virt_get_oem_id(Object *obj, Error **errp)
2362 {
2363 VirtMachineState *vms = VIRT_MACHINE(obj);
2364
2365 return g_strdup(vms->oem_id);
2366 }
2367
2368 static void virt_set_oem_id(Object *obj, const char *value, Error **errp)
2369 {
2370 VirtMachineState *vms = VIRT_MACHINE(obj);
2371 size_t len = strlen(value);
2372
2373 if (len > 6) {
2374 error_setg(errp,
2375 "User specified oem-id value is bigger than 6 bytes in size");
2376 return;
2377 }
2378
2379 strncpy(vms->oem_id, value, 6);
2380 }
2381
2382 static char *virt_get_oem_table_id(Object *obj, Error **errp)
2383 {
2384 VirtMachineState *vms = VIRT_MACHINE(obj);
2385
2386 return g_strdup(vms->oem_table_id);
2387 }
2388
2389 static void virt_set_oem_table_id(Object *obj, const char *value,
2390 Error **errp)
2391 {
2392 VirtMachineState *vms = VIRT_MACHINE(obj);
2393 size_t len = strlen(value);
2394
2395 if (len > 8) {
2396 error_setg(errp,
2397 "User specified oem-table-id value is bigger than 8 bytes in size");
2398 return;
2399 }
2400 strncpy(vms->oem_table_id, value, 8);
2401 }
2402
2403
2404 bool virt_is_acpi_enabled(VirtMachineState *vms)
2405 {
2406 if (vms->acpi == ON_OFF_AUTO_OFF) {
2407 return false;
2408 }
2409 return true;
2410 }
2411
2412 static void virt_get_acpi(Object *obj, Visitor *v, const char *name,
2413 void *opaque, Error **errp)
2414 {
2415 VirtMachineState *vms = VIRT_MACHINE(obj);
2416 OnOffAuto acpi = vms->acpi;
2417
2418 visit_type_OnOffAuto(v, name, &acpi, errp);
2419 }
2420
2421 static void virt_set_acpi(Object *obj, Visitor *v, const char *name,
2422 void *opaque, Error **errp)
2423 {
2424 VirtMachineState *vms = VIRT_MACHINE(obj);
2425
2426 visit_type_OnOffAuto(v, name, &vms->acpi, errp);
2427 }
2428
2429 static bool virt_get_ras(Object *obj, Error **errp)
2430 {
2431 VirtMachineState *vms = VIRT_MACHINE(obj);
2432
2433 return vms->ras;
2434 }
2435
2436 static void virt_set_ras(Object *obj, bool value, Error **errp)
2437 {
2438 VirtMachineState *vms = VIRT_MACHINE(obj);
2439
2440 vms->ras = value;
2441 }
2442
2443 static bool virt_get_mte(Object *obj, Error **errp)
2444 {
2445 VirtMachineState *vms = VIRT_MACHINE(obj);
2446
2447 return vms->mte;
2448 }
2449
2450 static void virt_set_mte(Object *obj, bool value, Error **errp)
2451 {
2452 VirtMachineState *vms = VIRT_MACHINE(obj);
2453
2454 vms->mte = value;
2455 }
2456
2457 static char *virt_get_gic_version(Object *obj, Error **errp)
2458 {
2459 VirtMachineState *vms = VIRT_MACHINE(obj);
2460 const char *val;
2461
2462 switch (vms->gic_version) {
2463 case VIRT_GIC_VERSION_4:
2464 val = "4";
2465 break;
2466 case VIRT_GIC_VERSION_3:
2467 val = "3";
2468 break;
2469 default:
2470 val = "2";
2471 break;
2472 }
2473 return g_strdup(val);
2474 }
2475
2476 static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
2477 {
2478 VirtMachineState *vms = VIRT_MACHINE(obj);
2479
2480 if (!strcmp(value, "4")) {
2481 vms->gic_version = VIRT_GIC_VERSION_4;
2482 } else if (!strcmp(value, "3")) {
2483 vms->gic_version = VIRT_GIC_VERSION_3;
2484 } else if (!strcmp(value, "2")) {
2485 vms->gic_version = VIRT_GIC_VERSION_2;
2486 } else if (!strcmp(value, "host")) {
2487 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */
2488 } else if (!strcmp(value, "max")) {
2489 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */
2490 } else {
2491 error_setg(errp, "Invalid gic-version value");
2492 error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
2493 }
2494 }
2495
2496 static char *virt_get_iommu(Object *obj, Error **errp)
2497 {
2498 VirtMachineState *vms = VIRT_MACHINE(obj);
2499
2500 switch (vms->iommu) {
2501 case VIRT_IOMMU_NONE:
2502 return g_strdup("none");
2503 case VIRT_IOMMU_SMMUV3:
2504 return g_strdup("smmuv3");
2505 default:
2506 g_assert_not_reached();
2507 }
2508 }
2509
2510 static void virt_set_iommu(Object *obj, const char *value, Error **errp)
2511 {
2512 VirtMachineState *vms = VIRT_MACHINE(obj);
2513
2514 if (!strcmp(value, "smmuv3")) {
2515 vms->iommu = VIRT_IOMMU_SMMUV3;
2516 } else if (!strcmp(value, "none")) {
2517 vms->iommu = VIRT_IOMMU_NONE;
2518 } else {
2519 error_setg(errp, "Invalid iommu value");
2520 error_append_hint(errp, "Valid values are none, smmuv3.\n");
2521 }
2522 }
2523
2524 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp)
2525 {
2526 VirtMachineState *vms = VIRT_MACHINE(obj);
2527
2528 return vms->default_bus_bypass_iommu;
2529 }
2530
2531 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value,
2532 Error **errp)
2533 {
2534 VirtMachineState *vms = VIRT_MACHINE(obj);
2535
2536 vms->default_bus_bypass_iommu = value;
2537 }
2538
2539 static CpuInstanceProperties
2540 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
2541 {
2542 MachineClass *mc = MACHINE_GET_CLASS(ms);
2543 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2544
2545 assert(cpu_index < possible_cpus->len);
2546 return possible_cpus->cpus[cpu_index].props;
2547 }
2548
2549 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
2550 {
2551 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
2552
2553 return socket_id % ms->numa_state->num_nodes;
2554 }
2555
2556 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
2557 {
2558 int n;
2559 unsigned int max_cpus = ms->smp.max_cpus;
2560 VirtMachineState *vms = VIRT_MACHINE(ms);
2561 MachineClass *mc = MACHINE_GET_CLASS(vms);
2562
2563 if (ms->possible_cpus) {
2564 assert(ms->possible_cpus->len == max_cpus);
2565 return ms->possible_cpus;
2566 }
2567
2568 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2569 sizeof(CPUArchId) * max_cpus);
2570 ms->possible_cpus->len = max_cpus;
2571 for (n = 0; n < ms->possible_cpus->len; n++) {
2572 ms->possible_cpus->cpus[n].type = ms->cpu_type;
2573 ms->possible_cpus->cpus[n].arch_id =
2574 virt_cpu_mp_affinity(vms, n);
2575
2576 assert(!mc->smp_props.dies_supported);
2577 ms->possible_cpus->cpus[n].props.has_socket_id = true;
2578 ms->possible_cpus->cpus[n].props.socket_id =
2579 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads);
2580 ms->possible_cpus->cpus[n].props.has_cluster_id = true;
2581 ms->possible_cpus->cpus[n].props.cluster_id =
2582 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters;
2583 ms->possible_cpus->cpus[n].props.has_core_id = true;
2584 ms->possible_cpus->cpus[n].props.core_id =
2585 (n / ms->smp.threads) % ms->smp.cores;
2586 ms->possible_cpus->cpus[n].props.has_thread_id = true;
2587 ms->possible_cpus->cpus[n].props.thread_id =
2588 n % ms->smp.threads;
2589 }
2590 return ms->possible_cpus;
2591 }
2592
2593 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2594 Error **errp)
2595 {
2596 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2597 const MachineState *ms = MACHINE(hotplug_dev);
2598 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2599
2600 if (!vms->acpi_dev) {
2601 error_setg(errp,
2602 "memory hotplug is not enabled: missing acpi-ged device");
2603 return;
2604 }
2605
2606 if (vms->mte) {
2607 error_setg(errp, "memory hotplug is not enabled: MTE is enabled");
2608 return;
2609 }
2610
2611 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
2612 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2613 return;
2614 }
2615
2616 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp);
2617 }
2618
2619 static void virt_memory_plug(HotplugHandler *hotplug_dev,
2620 DeviceState *dev, Error **errp)
2621 {
2622 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2623 MachineState *ms = MACHINE(hotplug_dev);
2624 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2625
2626 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms));
2627
2628 if (is_nvdimm) {
2629 nvdimm_plug(ms->nvdimms_state);
2630 }
2631
2632 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev),
2633 dev, &error_abort);
2634 }
2635
2636 static void virt_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev,
2637 DeviceState *dev, Error **errp)
2638 {
2639 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
2640 Error *local_err = NULL;
2641
2642 if (!hotplug_dev2 && dev->hotplugged) {
2643 /*
2644 * Without a bus hotplug handler, we cannot control the plug/unplug
2645 * order. We should never reach this point when hotplugging on ARM.
2646 * However, it's nice to add a safety net, similar to what we have
2647 * on x86.
2648 */
2649 error_setg(errp, "hotplug of virtio based memory devices not supported"
2650 " on this bus.");
2651 return;
2652 }
2653 /*
2654 * First, see if we can plug this memory device at all. If that
2655 * succeeds, branch of to the actual hotplug handler.
2656 */
2657 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
2658 &local_err);
2659 if (!local_err && hotplug_dev2) {
2660 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
2661 }
2662 error_propagate(errp, local_err);
2663 }
2664
2665 static void virt_virtio_md_pci_plug(HotplugHandler *hotplug_dev,
2666 DeviceState *dev, Error **errp)
2667 {
2668 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
2669 Error *local_err = NULL;
2670
2671 /*
2672 * Plug the memory device first and then branch off to the actual
2673 * hotplug handler. If that one fails, we can easily undo the memory
2674 * device bits.
2675 */
2676 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
2677 if (hotplug_dev2) {
2678 hotplug_handler_plug(hotplug_dev2, dev, &local_err);
2679 if (local_err) {
2680 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
2681 }
2682 }
2683 error_propagate(errp, local_err);
2684 }
2685
2686 static void virt_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev,
2687 DeviceState *dev, Error **errp)
2688 {
2689 /* We don't support hot unplug of virtio based memory devices */
2690 error_setg(errp, "virtio based memory devices cannot be unplugged.");
2691 }
2692
2693
2694 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2695 DeviceState *dev, Error **errp)
2696 {
2697 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2698
2699 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2700 virt_memory_pre_plug(hotplug_dev, dev, errp);
2701 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
2702 virt_virtio_md_pci_pre_plug(hotplug_dev, dev, errp);
2703 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2704 hwaddr db_start = 0, db_end = 0;
2705 char *resv_prop_str;
2706
2707 if (vms->iommu != VIRT_IOMMU_NONE) {
2708 error_setg(errp, "virt machine does not support multiple IOMMUs");
2709 return;
2710 }
2711
2712 switch (vms->msi_controller) {
2713 case VIRT_MSI_CTRL_NONE:
2714 return;
2715 case VIRT_MSI_CTRL_ITS:
2716 /* GITS_TRANSLATER page */
2717 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000;
2718 db_end = base_memmap[VIRT_GIC_ITS].base +
2719 base_memmap[VIRT_GIC_ITS].size - 1;
2720 break;
2721 case VIRT_MSI_CTRL_GICV2M:
2722 /* MSI_SETSPI_NS page */
2723 db_start = base_memmap[VIRT_GIC_V2M].base;
2724 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1;
2725 break;
2726 }
2727 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u",
2728 db_start, db_end,
2729 VIRTIO_IOMMU_RESV_MEM_T_MSI);
2730
2731 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp);
2732 object_property_set_str(OBJECT(dev), "reserved-regions[0]",
2733 resv_prop_str, errp);
2734 g_free(resv_prop_str);
2735 }
2736 }
2737
2738 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2739 DeviceState *dev, Error **errp)
2740 {
2741 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2742
2743 if (vms->platform_bus_dev) {
2744 MachineClass *mc = MACHINE_GET_CLASS(vms);
2745
2746 if (device_is_dynamic_sysbus(mc, dev)) {
2747 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
2748 SYS_BUS_DEVICE(dev));
2749 }
2750 }
2751 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2752 virt_memory_plug(hotplug_dev, dev, errp);
2753 }
2754
2755 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
2756 virt_virtio_md_pci_plug(hotplug_dev, dev, errp);
2757 }
2758
2759 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2760 PCIDevice *pdev = PCI_DEVICE(dev);
2761
2762 vms->iommu = VIRT_IOMMU_VIRTIO;
2763 vms->virtio_iommu_bdf = pci_get_bdf(pdev);
2764 create_virtio_iommu_dt_bindings(vms);
2765 }
2766 }
2767
2768 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev,
2769 DeviceState *dev, Error **errp)
2770 {
2771 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2772 Error *local_err = NULL;
2773
2774 if (!vms->acpi_dev) {
2775 error_setg(&local_err,
2776 "memory hotplug is not enabled: missing acpi-ged device");
2777 goto out;
2778 }
2779
2780 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
2781 error_setg(&local_err,
2782 "nvdimm device hot unplug is not supported yet.");
2783 goto out;
2784 }
2785
2786 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev,
2787 &local_err);
2788 out:
2789 error_propagate(errp, local_err);
2790 }
2791
2792 static void virt_dimm_unplug(HotplugHandler *hotplug_dev,
2793 DeviceState *dev, Error **errp)
2794 {
2795 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2796 Error *local_err = NULL;
2797
2798 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err);
2799 if (local_err) {
2800 goto out;
2801 }
2802
2803 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms));
2804 qdev_unrealize(dev);
2805
2806 out:
2807 error_propagate(errp, local_err);
2808 }
2809
2810 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2811 DeviceState *dev, Error **errp)
2812 {
2813 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2814 virt_dimm_unplug_request(hotplug_dev, dev, errp);
2815 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
2816 virt_virtio_md_pci_unplug_request(hotplug_dev, dev, errp);
2817 } else {
2818 error_setg(errp, "device unplug request for unsupported device"
2819 " type: %s", object_get_typename(OBJECT(dev)));
2820 }
2821 }
2822
2823 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2824 DeviceState *dev, Error **errp)
2825 {
2826 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2827 virt_dimm_unplug(hotplug_dev, dev, errp);
2828 } else {
2829 error_setg(errp, "virt: device unplug for unsupported device"
2830 " type: %s", object_get_typename(OBJECT(dev)));
2831 }
2832 }
2833
2834 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
2835 DeviceState *dev)
2836 {
2837 MachineClass *mc = MACHINE_GET_CLASS(machine);
2838
2839 if (device_is_dynamic_sysbus(mc, dev) ||
2840 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2841 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) ||
2842 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2843 return HOTPLUG_HANDLER(machine);
2844 }
2845 return NULL;
2846 }
2847
2848 /*
2849 * for arm64 kvm_type [7-0] encodes the requested number of bits
2850 * in the IPA address space
2851 */
2852 static int virt_kvm_type(MachineState *ms, const char *type_str)
2853 {
2854 VirtMachineState *vms = VIRT_MACHINE(ms);
2855 int max_vm_pa_size, requested_pa_size;
2856 bool fixed_ipa;
2857
2858 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa);
2859
2860 /* we freeze the memory map to compute the highest gpa */
2861 virt_set_memmap(vms, max_vm_pa_size);
2862
2863 requested_pa_size = 64 - clz64(vms->highest_gpa);
2864
2865 /*
2866 * KVM requires the IPA size to be at least 32 bits.
2867 */
2868 if (requested_pa_size < 32) {
2869 requested_pa_size = 32;
2870 }
2871
2872 if (requested_pa_size > max_vm_pa_size) {
2873 error_report("-m and ,maxmem option values "
2874 "require an IPA range (%d bits) larger than "
2875 "the one supported by the host (%d bits)",
2876 requested_pa_size, max_vm_pa_size);
2877 exit(1);
2878 }
2879 /*
2880 * We return the requested PA log size, unless KVM only supports
2881 * the implicit legacy 40b IPA setting, in which case the kvm_type
2882 * must be 0.
2883 */
2884 return fixed_ipa ? 0 : requested_pa_size;
2885 }
2886
2887 static void virt_machine_class_init(ObjectClass *oc, void *data)
2888 {
2889 MachineClass *mc = MACHINE_CLASS(oc);
2890 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2891
2892 mc->init = machvirt_init;
2893 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
2894 * The value may be reduced later when we have more information about the
2895 * configuration of the particular instance.
2896 */
2897 mc->max_cpus = 512;
2898 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC);
2899 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE);
2900 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
2901 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM);
2902 #ifdef CONFIG_TPM
2903 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
2904 #endif
2905 mc->block_default_type = IF_VIRTIO;
2906 mc->no_cdrom = 1;
2907 mc->pci_allow_0_address = true;
2908 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
2909 mc->minimum_page_bits = 12;
2910 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
2911 mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
2912 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
2913 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
2914 mc->kvm_type = virt_kvm_type;
2915 assert(!mc->get_hotplug_handler);
2916 mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
2917 hc->pre_plug = virt_machine_device_pre_plug_cb;
2918 hc->plug = virt_machine_device_plug_cb;
2919 hc->unplug_request = virt_machine_device_unplug_request_cb;
2920 hc->unplug = virt_machine_device_unplug_cb;
2921 mc->nvdimm_supported = true;
2922 mc->smp_props.clusters_supported = true;
2923 mc->auto_enable_numa_with_memhp = true;
2924 mc->auto_enable_numa_with_memdev = true;
2925 mc->default_ram_id = "mach-virt.ram";
2926
2927 object_class_property_add(oc, "acpi", "OnOffAuto",
2928 virt_get_acpi, virt_set_acpi,
2929 NULL, NULL);
2930 object_class_property_set_description(oc, "acpi",
2931 "Enable ACPI");
2932 object_class_property_add_bool(oc, "secure", virt_get_secure,
2933 virt_set_secure);
2934 object_class_property_set_description(oc, "secure",
2935 "Set on/off to enable/disable the ARM "
2936 "Security Extensions (TrustZone)");
2937
2938 object_class_property_add_bool(oc, "virtualization", virt_get_virt,
2939 virt_set_virt);
2940 object_class_property_set_description(oc, "virtualization",
2941 "Set on/off to enable/disable emulating a "
2942 "guest CPU which implements the ARM "
2943 "Virtualization Extensions");
2944
2945 object_class_property_add_bool(oc, "highmem", virt_get_highmem,
2946 virt_set_highmem);
2947 object_class_property_set_description(oc, "highmem",
2948 "Set on/off to enable/disable using "
2949 "physical address space above 32 bits");
2950
2951 object_class_property_add_str(oc, "gic-version", virt_get_gic_version,
2952 virt_set_gic_version);
2953 object_class_property_set_description(oc, "gic-version",
2954 "Set GIC version. "
2955 "Valid values are 2, 3, 4, host and max");
2956
2957 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu);
2958 object_class_property_set_description(oc, "iommu",
2959 "Set the IOMMU type. "
2960 "Valid values are none and smmuv3");
2961
2962 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
2963 virt_get_default_bus_bypass_iommu,
2964 virt_set_default_bus_bypass_iommu);
2965 object_class_property_set_description(oc, "default-bus-bypass-iommu",
2966 "Set on/off to enable/disable "
2967 "bypass_iommu for default root bus");
2968
2969 object_class_property_add_bool(oc, "ras", virt_get_ras,
2970 virt_set_ras);
2971 object_class_property_set_description(oc, "ras",
2972 "Set on/off to enable/disable reporting host memory errors "
2973 "to a KVM guest using ACPI and guest external abort exceptions");
2974
2975 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte);
2976 object_class_property_set_description(oc, "mte",
2977 "Set on/off to enable/disable emulating a "
2978 "guest CPU which implements the ARM "
2979 "Memory Tagging Extension");
2980
2981 object_class_property_add_bool(oc, "its", virt_get_its,
2982 virt_set_its);
2983 object_class_property_set_description(oc, "its",
2984 "Set on/off to enable/disable "
2985 "ITS instantiation");
2986
2987 object_class_property_add_bool(oc, "dtb-randomness",
2988 virt_get_dtb_randomness,
2989 virt_set_dtb_randomness);
2990 object_class_property_set_description(oc, "dtb-randomness",
2991 "Set off to disable passing random or "
2992 "non-deterministic dtb nodes to guest");
2993
2994 object_class_property_add_bool(oc, "dtb-kaslr-seed",
2995 virt_get_dtb_randomness,
2996 virt_set_dtb_randomness);
2997 object_class_property_set_description(oc, "dtb-kaslr-seed",
2998 "Deprecated synonym of dtb-randomness");
2999
3000 object_class_property_add_str(oc, "x-oem-id",
3001 virt_get_oem_id,
3002 virt_set_oem_id);
3003 object_class_property_set_description(oc, "x-oem-id",
3004 "Override the default value of field OEMID "
3005 "in ACPI table header."
3006 "The string may be up to 6 bytes in size");
3007
3008
3009 object_class_property_add_str(oc, "x-oem-table-id",
3010 virt_get_oem_table_id,
3011 virt_set_oem_table_id);
3012 object_class_property_set_description(oc, "x-oem-table-id",
3013 "Override the default value of field OEM Table ID "
3014 "in ACPI table header."
3015 "The string may be up to 8 bytes in size");
3016
3017 }
3018
3019 static void virt_instance_init(Object *obj)
3020 {
3021 VirtMachineState *vms = VIRT_MACHINE(obj);
3022 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
3023
3024 /* EL3 is disabled by default on virt: this makes us consistent
3025 * between KVM and TCG for this board, and it also allows us to
3026 * boot UEFI blobs which assume no TrustZone support.
3027 */
3028 vms->secure = false;
3029
3030 /* EL2 is also disabled by default, for similar reasons */
3031 vms->virt = false;
3032
3033 /* High memory is enabled by default */
3034 vms->highmem = true;
3035 vms->gic_version = VIRT_GIC_VERSION_NOSEL;
3036
3037 vms->highmem_ecam = !vmc->no_highmem_ecam;
3038 vms->highmem_mmio = true;
3039 vms->highmem_redists = true;
3040
3041 if (vmc->no_its) {
3042 vms->its = false;
3043 } else {
3044 /* Default allows ITS instantiation */
3045 vms->its = true;
3046
3047 if (vmc->no_tcg_its) {
3048 vms->tcg_its = false;
3049 } else {
3050 vms->tcg_its = true;
3051 }
3052 }
3053
3054 /* Default disallows iommu instantiation */
3055 vms->iommu = VIRT_IOMMU_NONE;
3056
3057 /* The default root bus is attached to iommu by default */
3058 vms->default_bus_bypass_iommu = false;
3059
3060 /* Default disallows RAS instantiation */
3061 vms->ras = false;
3062
3063 /* MTE is disabled by default. */
3064 vms->mte = false;
3065
3066 /* Supply kaslr-seed and rng-seed by default */
3067 vms->dtb_randomness = true;
3068
3069 vms->irqmap = a15irqmap;
3070
3071 virt_flash_create(vms);
3072
3073 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
3074 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
3075 }
3076
3077 static const TypeInfo virt_machine_info = {
3078 .name = TYPE_VIRT_MACHINE,
3079 .parent = TYPE_MACHINE,
3080 .abstract = true,
3081 .instance_size = sizeof(VirtMachineState),
3082 .class_size = sizeof(VirtMachineClass),
3083 .class_init = virt_machine_class_init,
3084 .instance_init = virt_instance_init,
3085 .interfaces = (InterfaceInfo[]) {
3086 { TYPE_HOTPLUG_HANDLER },
3087 { }
3088 },
3089 };
3090
3091 static void machvirt_machine_init(void)
3092 {
3093 type_register_static(&virt_machine_info);
3094 }
3095 type_init(machvirt_machine_init);
3096
3097 static void virt_machine_7_1_options(MachineClass *mc)
3098 {
3099 }
3100 DEFINE_VIRT_MACHINE_AS_LATEST(7, 1)
3101
3102 static void virt_machine_7_0_options(MachineClass *mc)
3103 {
3104 virt_machine_7_1_options(mc);
3105 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len);
3106 }
3107 DEFINE_VIRT_MACHINE(7, 0)
3108
3109 static void virt_machine_6_2_options(MachineClass *mc)
3110 {
3111 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3112
3113 virt_machine_7_0_options(mc);
3114 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len);
3115 vmc->no_tcg_lpa2 = true;
3116 }
3117 DEFINE_VIRT_MACHINE(6, 2)
3118
3119 static void virt_machine_6_1_options(MachineClass *mc)
3120 {
3121 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3122
3123 virt_machine_6_2_options(mc);
3124 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len);
3125 mc->smp_props.prefer_sockets = true;
3126 vmc->no_cpu_topology = true;
3127
3128 /* qemu ITS was introduced with 6.2 */
3129 vmc->no_tcg_its = true;
3130 }
3131 DEFINE_VIRT_MACHINE(6, 1)
3132
3133 static void virt_machine_6_0_options(MachineClass *mc)
3134 {
3135 virt_machine_6_1_options(mc);
3136 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len);
3137 }
3138 DEFINE_VIRT_MACHINE(6, 0)
3139
3140 static void virt_machine_5_2_options(MachineClass *mc)
3141 {
3142 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3143
3144 virt_machine_6_0_options(mc);
3145 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len);
3146 vmc->no_secure_gpio = true;
3147 }
3148 DEFINE_VIRT_MACHINE(5, 2)
3149
3150 static void virt_machine_5_1_options(MachineClass *mc)
3151 {
3152 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3153
3154 virt_machine_5_2_options(mc);
3155 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len);
3156 vmc->no_kvm_steal_time = true;
3157 }
3158 DEFINE_VIRT_MACHINE(5, 1)
3159
3160 static void virt_machine_5_0_options(MachineClass *mc)
3161 {
3162 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3163
3164 virt_machine_5_1_options(mc);
3165 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
3166 mc->numa_mem_supported = true;
3167 vmc->acpi_expose_flash = true;
3168 mc->auto_enable_numa_with_memdev = false;
3169 }
3170 DEFINE_VIRT_MACHINE(5, 0)
3171
3172 static void virt_machine_4_2_options(MachineClass *mc)
3173 {
3174 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3175
3176 virt_machine_5_0_options(mc);
3177 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len);
3178 vmc->kvm_no_adjvtime = true;
3179 }
3180 DEFINE_VIRT_MACHINE(4, 2)
3181
3182 static void virt_machine_4_1_options(MachineClass *mc)
3183 {
3184 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3185
3186 virt_machine_4_2_options(mc);
3187 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len);
3188 vmc->no_ged = true;
3189 mc->auto_enable_numa_with_memhp = false;
3190 }
3191 DEFINE_VIRT_MACHINE(4, 1)
3192
3193 static void virt_machine_4_0_options(MachineClass *mc)
3194 {
3195 virt_machine_4_1_options(mc);
3196 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len);
3197 }
3198 DEFINE_VIRT_MACHINE(4, 0)
3199
3200 static void virt_machine_3_1_options(MachineClass *mc)
3201 {
3202 virt_machine_4_0_options(mc);
3203 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
3204 }
3205 DEFINE_VIRT_MACHINE(3, 1)
3206
3207 static void virt_machine_3_0_options(MachineClass *mc)
3208 {
3209 virt_machine_3_1_options(mc);
3210 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
3211 }
3212 DEFINE_VIRT_MACHINE(3, 0)
3213
3214 static void virt_machine_2_12_options(MachineClass *mc)
3215 {
3216 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3217
3218 virt_machine_3_0_options(mc);
3219 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
3220 vmc->no_highmem_ecam = true;
3221 mc->max_cpus = 255;
3222 }
3223 DEFINE_VIRT_MACHINE(2, 12)
3224
3225 static void virt_machine_2_11_options(MachineClass *mc)
3226 {
3227 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3228
3229 virt_machine_2_12_options(mc);
3230 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
3231 vmc->smbios_old_sys_ver = true;
3232 }
3233 DEFINE_VIRT_MACHINE(2, 11)
3234
3235 static void virt_machine_2_10_options(MachineClass *mc)
3236 {
3237 virt_machine_2_11_options(mc);
3238 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
3239 /* before 2.11 we never faulted accesses to bad addresses */
3240 mc->ignore_memory_transaction_failures = true;
3241 }
3242 DEFINE_VIRT_MACHINE(2, 10)
3243
3244 static void virt_machine_2_9_options(MachineClass *mc)
3245 {
3246 virt_machine_2_10_options(mc);
3247 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
3248 }
3249 DEFINE_VIRT_MACHINE(2, 9)
3250
3251 static void virt_machine_2_8_options(MachineClass *mc)
3252 {
3253 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3254
3255 virt_machine_2_9_options(mc);
3256 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
3257 /* For 2.8 and earlier we falsely claimed in the DT that
3258 * our timers were edge-triggered, not level-triggered.
3259 */
3260 vmc->claim_edge_triggered_timers = true;
3261 }
3262 DEFINE_VIRT_MACHINE(2, 8)
3263
3264 static void virt_machine_2_7_options(MachineClass *mc)
3265 {
3266 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3267
3268 virt_machine_2_8_options(mc);
3269 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
3270 /* ITS was introduced with 2.8 */
3271 vmc->no_its = true;
3272 /* Stick with 1K pages for migration compatibility */
3273 mc->minimum_page_bits = 0;
3274 }
3275 DEFINE_VIRT_MACHINE(2, 7)
3276
3277 static void virt_machine_2_6_options(MachineClass *mc)
3278 {
3279 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3280
3281 virt_machine_2_7_options(mc);
3282 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
3283 vmc->disallow_affinity_adjustment = true;
3284 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
3285 vmc->no_pmu = true;
3286 }
3287 DEFINE_VIRT_MACHINE(2, 6)