Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging
[qemu.git] / hw / arm / xlnx-zynqmp.c
1 /*
2 * Xilinx Zynq MPSoC emulation
3 *
4 * Copyright (C) 2015 Xilinx Inc
5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 */
17
18 #include "qemu/osdep.h"
19 #include "qapi/error.h"
20 #include "qemu/module.h"
21 #include "hw/arm/xlnx-zynqmp.h"
22 #include "hw/intc/arm_gic_common.h"
23 #include "hw/misc/unimp.h"
24 #include "hw/boards.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/sysemu.h"
27 #include "kvm_arm.h"
28
29 #define GIC_NUM_SPI_INTR 160
30
31 #define ARM_PHYS_TIMER_PPI 30
32 #define ARM_VIRT_TIMER_PPI 27
33 #define ARM_HYP_TIMER_PPI 26
34 #define ARM_SEC_TIMER_PPI 29
35 #define GIC_MAINTENANCE_PPI 25
36
37 #define GEM_REVISION 0x40070106
38
39 #define GIC_BASE_ADDR 0xf9000000
40 #define GIC_DIST_ADDR 0xf9010000
41 #define GIC_CPU_ADDR 0xf9020000
42 #define GIC_VIFACE_ADDR 0xf9040000
43 #define GIC_VCPU_ADDR 0xf9060000
44
45 #define SATA_INTR 133
46 #define SATA_ADDR 0xFD0C0000
47 #define SATA_NUM_PORTS 2
48
49 #define QSPI_ADDR 0xff0f0000
50 #define LQSPI_ADDR 0xc0000000
51 #define QSPI_IRQ 15
52 #define QSPI_DMA_ADDR 0xff0f0800
53
54 #define DP_ADDR 0xfd4a0000
55 #define DP_IRQ 113
56
57 #define DPDMA_ADDR 0xfd4c0000
58 #define DPDMA_IRQ 116
59
60 #define APU_ADDR 0xfd5c0000
61 #define APU_SIZE 0x100
62
63 #define IPI_ADDR 0xFF300000
64 #define IPI_IRQ 64
65
66 #define RTC_ADDR 0xffa60000
67 #define RTC_IRQ 26
68
69 #define BBRAM_ADDR 0xffcd0000
70 #define BBRAM_IRQ 11
71
72 #define EFUSE_ADDR 0xffcc0000
73 #define EFUSE_IRQ 87
74
75 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
76
77 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
78 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
79 };
80
81 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
82 57, 59, 61, 63,
83 };
84
85 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
86 0xFF000000, 0xFF010000,
87 };
88
89 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
90 21, 22,
91 };
92
93 static const uint64_t can_addr[XLNX_ZYNQMP_NUM_CAN] = {
94 0xFF060000, 0xFF070000,
95 };
96
97 static const int can_intr[XLNX_ZYNQMP_NUM_CAN] = {
98 23, 24,
99 };
100
101 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
102 0xFF160000, 0xFF170000,
103 };
104
105 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
106 48, 49,
107 };
108
109 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
110 0xFF040000, 0xFF050000,
111 };
112
113 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
114 19, 20,
115 };
116
117 static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
118 0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000,
119 0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000
120 };
121
122 static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
123 124, 125, 126, 127, 128, 129, 130, 131
124 };
125
126 static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
127 0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000,
128 0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000
129 };
130
131 static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
132 77, 78, 79, 80, 81, 82, 83, 84
133 };
134
135 typedef struct XlnxZynqMPGICRegion {
136 int region_index;
137 uint32_t address;
138 uint32_t offset;
139 bool virt;
140 } XlnxZynqMPGICRegion;
141
142 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
143 /* Distributor */
144 {
145 .region_index = 0,
146 .address = GIC_DIST_ADDR,
147 .offset = 0,
148 .virt = false
149 },
150
151 /* CPU interface */
152 {
153 .region_index = 1,
154 .address = GIC_CPU_ADDR,
155 .offset = 0,
156 .virt = false
157 },
158 {
159 .region_index = 1,
160 .address = GIC_CPU_ADDR + 0x10000,
161 .offset = 0x1000,
162 .virt = false
163 },
164
165 /* Virtual interface */
166 {
167 .region_index = 2,
168 .address = GIC_VIFACE_ADDR,
169 .offset = 0,
170 .virt = true
171 },
172
173 /* Virtual CPU interface */
174 {
175 .region_index = 3,
176 .address = GIC_VCPU_ADDR,
177 .offset = 0,
178 .virt = true
179 },
180 {
181 .region_index = 3,
182 .address = GIC_VCPU_ADDR + 0x10000,
183 .offset = 0x1000,
184 .virt = true
185 },
186 };
187
188 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
189 {
190 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
191 }
192
193 static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
194 const char *boot_cpu, Error **errp)
195 {
196 int i;
197 int num_rpus = MIN(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS,
198 XLNX_ZYNQMP_NUM_RPU_CPUS);
199
200 if (num_rpus <= 0) {
201 /* Don't create rpu-cluster object if there's nothing to put in it */
202 return;
203 }
204
205 object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster,
206 TYPE_CPU_CLUSTER);
207 qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1);
208
209 for (i = 0; i < num_rpus; i++) {
210 const char *name;
211
212 object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]",
213 &s->rpu_cpu[i],
214 ARM_CPU_TYPE_NAME("cortex-r5f"));
215
216 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
217 if (strcmp(name, boot_cpu)) {
218 /* Secondary CPUs start in PSCI powered-down state */
219 object_property_set_bool(OBJECT(&s->rpu_cpu[i]),
220 "start-powered-off", true, &error_abort);
221 } else {
222 s->boot_cpu_ptr = &s->rpu_cpu[i];
223 }
224
225 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), "reset-hivecs", true,
226 &error_abort);
227 if (!qdev_realize(DEVICE(&s->rpu_cpu[i]), NULL, errp)) {
228 return;
229 }
230 }
231
232 qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal);
233 }
234
235 static void xlnx_zynqmp_create_bbram(XlnxZynqMPState *s, qemu_irq *gic)
236 {
237 SysBusDevice *sbd;
238
239 object_initialize_child_with_props(OBJECT(s), "bbram", &s->bbram,
240 sizeof(s->bbram), TYPE_XLNX_BBRAM,
241 &error_fatal,
242 "crc-zpads", "1",
243 NULL);
244 sbd = SYS_BUS_DEVICE(&s->bbram);
245
246 sysbus_realize(sbd, &error_fatal);
247 sysbus_mmio_map(sbd, 0, BBRAM_ADDR);
248 sysbus_connect_irq(sbd, 0, gic[BBRAM_IRQ]);
249 }
250
251 static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic)
252 {
253 Object *bits = OBJECT(&s->efuse);
254 Object *ctrl = OBJECT(&s->efuse_ctrl);
255 SysBusDevice *sbd;
256
257 object_initialize_child(OBJECT(s), "efuse-ctrl", &s->efuse_ctrl,
258 TYPE_XLNX_ZYNQMP_EFUSE);
259
260 object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits,
261 sizeof(s->efuse),
262 TYPE_XLNX_EFUSE, &error_abort,
263 "efuse-nr", "3",
264 "efuse-size", "2048",
265 NULL);
266
267 qdev_realize(DEVICE(bits), NULL, &error_abort);
268 object_property_set_link(ctrl, "efuse", bits, &error_abort);
269
270 sbd = SYS_BUS_DEVICE(ctrl);
271 sysbus_realize(sbd, &error_abort);
272 sysbus_mmio_map(sbd, 0, EFUSE_ADDR);
273 sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]);
274 }
275
276 static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
277 {
278 static const struct UnimpInfo {
279 const char *name;
280 hwaddr base;
281 hwaddr size;
282 } unimp_areas[ARRAY_SIZE(s->mr_unimp)] = {
283 { .name = "apu", APU_ADDR, APU_SIZE },
284 };
285 unsigned int nr;
286
287 for (nr = 0; nr < ARRAY_SIZE(unimp_areas); nr++) {
288 const struct UnimpInfo *info = &unimp_areas[nr];
289 DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
290 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
291
292 assert(info->name && info->base && info->size > 0);
293 qdev_prop_set_string(dev, "name", info->name);
294 qdev_prop_set_uint64(dev, "size", info->size);
295 object_property_add_child(OBJECT(s), info->name, OBJECT(dev));
296
297 sysbus_realize_and_unref(sbd, &error_fatal);
298 sysbus_mmio_map(sbd, 0, info->base);
299 }
300 }
301
302 static void xlnx_zynqmp_init(Object *obj)
303 {
304 MachineState *ms = MACHINE(qdev_get_machine());
305 XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
306 int i;
307 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
308
309 object_initialize_child(obj, "apu-cluster", &s->apu_cluster,
310 TYPE_CPU_CLUSTER);
311 qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0);
312
313 for (i = 0; i < num_apus; i++) {
314 object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]",
315 &s->apu_cpu[i],
316 ARM_CPU_TYPE_NAME("cortex-a53"));
317 }
318
319 object_initialize_child(obj, "gic", &s->gic, gic_class_name());
320
321 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
322 object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GEM);
323 }
324
325 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
326 object_initialize_child(obj, "uart[*]", &s->uart[i],
327 TYPE_CADENCE_UART);
328 }
329
330 for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
331 object_initialize_child(obj, "can[*]", &s->can[i],
332 TYPE_XLNX_ZYNQMP_CAN);
333 }
334
335 object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI);
336
337 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
338 object_initialize_child(obj, "sdhci[*]", &s->sdhci[i],
339 TYPE_SYSBUS_SDHCI);
340 }
341
342 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
343 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_XILINX_SPIPS);
344 }
345
346 object_initialize_child(obj, "qspi", &s->qspi, TYPE_XLNX_ZYNQMP_QSPIPS);
347
348 object_initialize_child(obj, "xxxdp", &s->dp, TYPE_XLNX_DP);
349
350 object_initialize_child(obj, "dp-dma", &s->dpdma, TYPE_XLNX_DPDMA);
351
352 object_initialize_child(obj, "ipi", &s->ipi, TYPE_XLNX_ZYNQMP_IPI);
353
354 object_initialize_child(obj, "rtc", &s->rtc, TYPE_XLNX_ZYNQMP_RTC);
355
356 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
357 object_initialize_child(obj, "gdma[*]", &s->gdma[i], TYPE_XLNX_ZDMA);
358 }
359
360 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
361 object_initialize_child(obj, "adma[*]", &s->adma[i], TYPE_XLNX_ZDMA);
362 }
363
364 object_initialize_child(obj, "qspi-dma", &s->qspi_dma, TYPE_XLNX_CSU_DMA);
365 }
366
367 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
368 {
369 MachineState *ms = MACHINE(qdev_get_machine());
370 XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
371 MemoryRegion *system_memory = get_system_memory();
372 uint8_t i;
373 uint64_t ram_size;
374 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
375 const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
376 ram_addr_t ddr_low_size, ddr_high_size;
377 qemu_irq gic_spi[GIC_NUM_SPI_INTR];
378 Error *err = NULL;
379
380 ram_size = memory_region_size(s->ddr_ram);
381
382 /*
383 * Create the DDR Memory Regions. User friendly checks should happen at
384 * the board level
385 */
386 if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
387 /*
388 * The RAM size is above the maximum available for the low DDR.
389 * Create the high DDR memory region as well.
390 */
391 assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
392 ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
393 ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
394
395 memory_region_init_alias(&s->ddr_ram_high, OBJECT(dev),
396 "ddr-ram-high", s->ddr_ram, ddr_low_size,
397 ddr_high_size);
398 memory_region_add_subregion(get_system_memory(),
399 XLNX_ZYNQMP_HIGH_RAM_START,
400 &s->ddr_ram_high);
401 } else {
402 /* RAM must be non-zero */
403 assert(ram_size);
404 ddr_low_size = ram_size;
405 }
406
407 memory_region_init_alias(&s->ddr_ram_low, OBJECT(dev), "ddr-ram-low",
408 s->ddr_ram, 0, ddr_low_size);
409 memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);
410
411 /* Create the four OCM banks */
412 for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
413 char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
414
415 memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
416 XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
417 memory_region_add_subregion(get_system_memory(),
418 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
419 i * XLNX_ZYNQMP_OCM_RAM_SIZE,
420 &s->ocm_ram[i]);
421
422 g_free(ocm_name);
423 }
424
425 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
426 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
427 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus);
428 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure);
429 qdev_prop_set_bit(DEVICE(&s->gic),
430 "has-virtualization-extensions", s->virt);
431
432 qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal);
433
434 /* Realize APUs before realizing the GIC. KVM requires this. */
435 for (i = 0; i < num_apus; i++) {
436 const char *name;
437
438 object_property_set_int(OBJECT(&s->apu_cpu[i]), "psci-conduit",
439 QEMU_PSCI_CONDUIT_SMC, &error_abort);
440
441 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
442 if (strcmp(name, boot_cpu)) {
443 /* Secondary CPUs start in PSCI powered-down state */
444 object_property_set_bool(OBJECT(&s->apu_cpu[i]),
445 "start-powered-off", true, &error_abort);
446 } else {
447 s->boot_cpu_ptr = &s->apu_cpu[i];
448 }
449
450 object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el3", s->secure,
451 NULL);
452 object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el2", s->virt,
453 NULL);
454 object_property_set_int(OBJECT(&s->apu_cpu[i]), "reset-cbar",
455 GIC_BASE_ADDR, &error_abort);
456 object_property_set_int(OBJECT(&s->apu_cpu[i]), "core-count",
457 num_apus, &error_abort);
458 if (!qdev_realize(DEVICE(&s->apu_cpu[i]), NULL, errp)) {
459 return;
460 }
461 }
462
463 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) {
464 return;
465 }
466
467 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
468 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
469 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
470 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
471 MemoryRegion *mr;
472 uint32_t addr = r->address;
473 int j;
474
475 if (r->virt && !s->virt) {
476 continue;
477 }
478
479 mr = sysbus_mmio_get_region(gic, r->region_index);
480 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
481 MemoryRegion *alias = &s->gic_mr[i][j];
482
483 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
484 r->offset, XLNX_ZYNQMP_GIC_REGION_SIZE);
485 memory_region_add_subregion(system_memory, addr, alias);
486
487 addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
488 }
489 }
490
491 for (i = 0; i < num_apus; i++) {
492 qemu_irq irq;
493
494 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
495 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
496 ARM_CPU_IRQ));
497 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus,
498 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
499 ARM_CPU_FIQ));
500 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2,
501 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
502 ARM_CPU_VIRQ));
503 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3,
504 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
505 ARM_CPU_VFIQ));
506 irq = qdev_get_gpio_in(DEVICE(&s->gic),
507 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
508 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq);
509 irq = qdev_get_gpio_in(DEVICE(&s->gic),
510 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
511 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq);
512 irq = qdev_get_gpio_in(DEVICE(&s->gic),
513 arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI));
514 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq);
515 irq = qdev_get_gpio_in(DEVICE(&s->gic),
516 arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI));
517 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq);
518
519 if (s->virt) {
520 irq = qdev_get_gpio_in(DEVICE(&s->gic),
521 arm_gic_ppi_index(i, GIC_MAINTENANCE_PPI));
522 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, irq);
523 }
524 }
525
526 xlnx_zynqmp_create_rpu(ms, s, boot_cpu, &err);
527 if (err) {
528 error_propagate(errp, err);
529 return;
530 }
531
532 if (!s->boot_cpu_ptr) {
533 error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
534 return;
535 }
536
537 for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
538 gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
539 }
540
541 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
542 NICInfo *nd = &nd_table[i];
543
544 /* FIXME use qdev NIC properties instead of nd_table[] */
545 if (nd->used) {
546 qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
547 qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
548 }
549 object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISION,
550 &error_abort);
551 object_property_set_int(OBJECT(&s->gem[i]), "phy-addr", 23,
552 &error_abort);
553 object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2,
554 &error_abort);
555 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) {
556 return;
557 }
558 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
559 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
560 gic_spi[gem_intr[i]]);
561 }
562
563 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
564 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
565 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) {
566 return;
567 }
568 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
569 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
570 gic_spi[uart_intr[i]]);
571 }
572
573 for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
574 object_property_set_int(OBJECT(&s->can[i]), "ext_clk_freq",
575 XLNX_ZYNQMP_CAN_REF_CLK, &error_abort);
576
577 object_property_set_link(OBJECT(&s->can[i]), "canbus",
578 OBJECT(s->canbus[i]), &error_fatal);
579
580 sysbus_realize(SYS_BUS_DEVICE(&s->can[i]), &err);
581 if (err) {
582 error_propagate(errp, err);
583 return;
584 }
585 sysbus_mmio_map(SYS_BUS_DEVICE(&s->can[i]), 0, can_addr[i]);
586 sysbus_connect_irq(SYS_BUS_DEVICE(&s->can[i]), 0,
587 gic_spi[can_intr[i]]);
588 }
589
590 object_property_set_int(OBJECT(&s->sata), "num-ports", SATA_NUM_PORTS,
591 &error_abort);
592 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) {
593 return;
594 }
595
596 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
597 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
598
599 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
600 char *bus_name;
601 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]);
602 Object *sdhci = OBJECT(&s->sdhci[i]);
603
604 /*
605 * Compatible with:
606 * - SD Host Controller Specification Version 3.00
607 * - SDIO Specification Version 3.0
608 * - eMMC Specification Version 4.51
609 */
610 if (!object_property_set_uint(sdhci, "sd-spec-version", 3, errp)) {
611 return;
612 }
613 if (!object_property_set_uint(sdhci, "capareg", SDHCI_CAPABILITIES,
614 errp)) {
615 return;
616 }
617 if (!object_property_set_uint(sdhci, "uhs", UHS_I, errp)) {
618 return;
619 }
620 if (!sysbus_realize(SYS_BUS_DEVICE(sdhci), errp)) {
621 return;
622 }
623 sysbus_mmio_map(sbd, 0, sdhci_addr[i]);
624 sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]);
625
626 /* Alias controller SD bus to the SoC itself */
627 bus_name = g_strdup_printf("sd-bus%d", i);
628 object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus");
629 g_free(bus_name);
630 }
631
632 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
633 gchar *bus_name;
634
635 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
636 return;
637 }
638
639 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
640 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
641 gic_spi[spi_intr[i]]);
642
643 /* Alias controller SPI bus to the SoC itself */
644 bus_name = g_strdup_printf("spi%d", i);
645 object_property_add_alias(OBJECT(s), bus_name,
646 OBJECT(&s->spi[i]), "spi0");
647 g_free(bus_name);
648 }
649
650 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dp), errp)) {
651 return;
652 }
653 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
654 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
655
656 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dpdma), errp)) {
657 return;
658 }
659 object_property_set_link(OBJECT(&s->dp), "dpdma", OBJECT(&s->dpdma),
660 &error_abort);
661 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
662 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
663
664 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ipi), errp)) {
665 return;
666 }
667 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR);
668 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]);
669
670 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
671 return;
672 }
673 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR);
674 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
675
676 xlnx_zynqmp_create_bbram(s, gic_spi);
677 xlnx_zynqmp_create_efuse(s, gic_spi);
678 xlnx_zynqmp_create_unimp_mmio(s);
679
680 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
681 if (!object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128,
682 errp)) {
683 return;
684 }
685 if (!object_property_set_link(OBJECT(&s->gdma[i]), "dma",
686 OBJECT(system_memory), errp)) {
687 return;
688 }
689 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gdma[i]), errp)) {
690 return;
691 }
692
693 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]);
694 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0,
695 gic_spi[gdma_ch_intr[i]]);
696 }
697
698 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
699 if (!object_property_set_link(OBJECT(&s->adma[i]), "dma",
700 OBJECT(system_memory), errp)) {
701 return;
702 }
703 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adma[i]), errp)) {
704 return;
705 }
706
707 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]);
708 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0,
709 gic_spi[adma_ch_intr[i]]);
710 }
711
712 if (!object_property_set_link(OBJECT(&s->qspi_dma), "dma",
713 OBJECT(system_memory), errp)) {
714 return;
715 }
716 if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi_dma), errp)) {
717 return;
718 }
719
720 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi_dma), 0, QSPI_DMA_ADDR);
721 sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi_dma), 0, gic_spi[QSPI_IRQ]);
722
723 if (!object_property_set_link(OBJECT(&s->qspi), "stream-connected-dma",
724 OBJECT(&s->qspi_dma), errp)) {
725 return;
726 }
727 if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi), errp)) {
728 return;
729 }
730 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR);
731 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR);
732 sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]);
733
734 for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) {
735 g_autofree gchar *bus_name = g_strdup_printf("qspi%d", i);
736 g_autofree gchar *target_bus = g_strdup_printf("spi%d", i);
737
738 /* Alias controller SPI bus to the SoC itself */
739 object_property_add_alias(OBJECT(s), bus_name,
740 OBJECT(&s->qspi), target_bus);
741 }
742 }
743
744 static Property xlnx_zynqmp_props[] = {
745 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
746 DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
747 DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false),
748 DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
749 MemoryRegion *),
750 DEFINE_PROP_LINK("canbus0", XlnxZynqMPState, canbus[0], TYPE_CAN_BUS,
751 CanBusState *),
752 DEFINE_PROP_LINK("canbus1", XlnxZynqMPState, canbus[1], TYPE_CAN_BUS,
753 CanBusState *),
754 DEFINE_PROP_END_OF_LIST()
755 };
756
757 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
758 {
759 DeviceClass *dc = DEVICE_CLASS(oc);
760
761 device_class_set_props(dc, xlnx_zynqmp_props);
762 dc->realize = xlnx_zynqmp_realize;
763 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
764 dc->user_creatable = false;
765 }
766
767 static const TypeInfo xlnx_zynqmp_type_info = {
768 .name = TYPE_XLNX_ZYNQMP,
769 .parent = TYPE_DEVICE,
770 .instance_size = sizeof(XlnxZynqMPState),
771 .instance_init = xlnx_zynqmp_init,
772 .class_init = xlnx_zynqmp_class_init,
773 };
774
775 static void xlnx_zynqmp_register_types(void)
776 {
777 type_register_static(&xlnx_zynqmp_type_info);
778 }
779
780 type_init(xlnx_zynqmp_register_types)