PPC: e500mc: add missing IVORs to bitmap
[qemu.git] / hw / arm_mptimer.c
1 /*
2 * Private peripheral timer/watchdog blocks for ARM 11MPCore and A9MP
3 *
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Copyright (c) 2011 Linaro Limited
6 * Written by Paul Brook, Peter Maydell
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include "sysbus.h"
23 #include "qemu-timer.h"
24
25 /* This device implements the per-cpu private timer and watchdog block
26 * which is used in both the ARM11MPCore and Cortex-A9MP.
27 */
28
29 #define MAX_CPUS 4
30
31 /* State of a single timer or watchdog block */
32 typedef struct {
33 uint32_t count;
34 uint32_t load;
35 uint32_t control;
36 uint32_t status;
37 int64_t tick;
38 QEMUTimer *timer;
39 qemu_irq irq;
40 MemoryRegion iomem;
41 } timerblock;
42
43 typedef struct {
44 SysBusDevice busdev;
45 uint32_t num_cpu;
46 timerblock timerblock[MAX_CPUS * 2];
47 MemoryRegion iomem[2];
48 } arm_mptimer_state;
49
50 static inline int get_current_cpu(arm_mptimer_state *s)
51 {
52 if (cpu_single_env->cpu_index >= s->num_cpu) {
53 hw_error("arm_mptimer: num-cpu %d but this cpu is %d!\n",
54 s->num_cpu, cpu_single_env->cpu_index);
55 }
56 return cpu_single_env->cpu_index;
57 }
58
59 static inline void timerblock_update_irq(timerblock *tb)
60 {
61 qemu_set_irq(tb->irq, tb->status);
62 }
63
64 /* Return conversion factor from mpcore timer ticks to qemu timer ticks. */
65 static inline uint32_t timerblock_scale(timerblock *tb)
66 {
67 return (((tb->control >> 8) & 0xff) + 1) * 10;
68 }
69
70 static void timerblock_reload(timerblock *tb, int restart)
71 {
72 if (tb->count == 0) {
73 return;
74 }
75 if (restart) {
76 tb->tick = qemu_get_clock_ns(vm_clock);
77 }
78 tb->tick += (int64_t)tb->count * timerblock_scale(tb);
79 qemu_mod_timer(tb->timer, tb->tick);
80 }
81
82 static void timerblock_tick(void *opaque)
83 {
84 timerblock *tb = (timerblock *)opaque;
85 tb->status = 1;
86 if (tb->control & 2) {
87 tb->count = tb->load;
88 timerblock_reload(tb, 0);
89 } else {
90 tb->count = 0;
91 }
92 timerblock_update_irq(tb);
93 }
94
95 static uint64_t timerblock_read(void *opaque, target_phys_addr_t addr,
96 unsigned size)
97 {
98 timerblock *tb = (timerblock *)opaque;
99 int64_t val;
100 addr &= 0x1f;
101 switch (addr) {
102 case 0: /* Load */
103 return tb->load;
104 case 4: /* Counter. */
105 if (((tb->control & 1) == 0) || (tb->count == 0)) {
106 return 0;
107 }
108 /* Slow and ugly, but hopefully won't happen too often. */
109 val = tb->tick - qemu_get_clock_ns(vm_clock);
110 val /= timerblock_scale(tb);
111 if (val < 0) {
112 val = 0;
113 }
114 return val;
115 case 8: /* Control. */
116 return tb->control;
117 case 12: /* Interrupt status. */
118 return tb->status;
119 default:
120 return 0;
121 }
122 }
123
124 static void timerblock_write(void *opaque, target_phys_addr_t addr,
125 uint64_t value, unsigned size)
126 {
127 timerblock *tb = (timerblock *)opaque;
128 int64_t old;
129 addr &= 0x1f;
130 switch (addr) {
131 case 0: /* Load */
132 tb->load = value;
133 /* Fall through. */
134 case 4: /* Counter. */
135 if ((tb->control & 1) && tb->count) {
136 /* Cancel the previous timer. */
137 qemu_del_timer(tb->timer);
138 }
139 tb->count = value;
140 if (tb->control & 1) {
141 timerblock_reload(tb, 1);
142 }
143 break;
144 case 8: /* Control. */
145 old = tb->control;
146 tb->control = value;
147 if (((old & 1) == 0) && (value & 1)) {
148 if (tb->count == 0 && (tb->control & 2)) {
149 tb->count = tb->load;
150 }
151 timerblock_reload(tb, 1);
152 }
153 break;
154 case 12: /* Interrupt status. */
155 tb->status &= ~value;
156 timerblock_update_irq(tb);
157 break;
158 }
159 }
160
161 /* Wrapper functions to implement the "read timer/watchdog for
162 * the current CPU" memory regions.
163 */
164 static uint64_t arm_thistimer_read(void *opaque, target_phys_addr_t addr,
165 unsigned size)
166 {
167 arm_mptimer_state *s = (arm_mptimer_state *)opaque;
168 int id = get_current_cpu(s);
169 return timerblock_read(&s->timerblock[id * 2], addr, size);
170 }
171
172 static void arm_thistimer_write(void *opaque, target_phys_addr_t addr,
173 uint64_t value, unsigned size)
174 {
175 arm_mptimer_state *s = (arm_mptimer_state *)opaque;
176 int id = get_current_cpu(s);
177 timerblock_write(&s->timerblock[id * 2], addr, value, size);
178 }
179
180 static uint64_t arm_thiswdog_read(void *opaque, target_phys_addr_t addr,
181 unsigned size)
182 {
183 arm_mptimer_state *s = (arm_mptimer_state *)opaque;
184 int id = get_current_cpu(s);
185 return timerblock_read(&s->timerblock[id * 2 + 1], addr, size);
186 }
187
188 static void arm_thiswdog_write(void *opaque, target_phys_addr_t addr,
189 uint64_t value, unsigned size)
190 {
191 arm_mptimer_state *s = (arm_mptimer_state *)opaque;
192 int id = get_current_cpu(s);
193 timerblock_write(&s->timerblock[id * 2 + 1], addr, value, size);
194 }
195
196 static const MemoryRegionOps arm_thistimer_ops = {
197 .read = arm_thistimer_read,
198 .write = arm_thistimer_write,
199 .valid = {
200 .min_access_size = 4,
201 .max_access_size = 4,
202 },
203 .endianness = DEVICE_NATIVE_ENDIAN,
204 };
205
206 static const MemoryRegionOps arm_thiswdog_ops = {
207 .read = arm_thiswdog_read,
208 .write = arm_thiswdog_write,
209 .valid = {
210 .min_access_size = 4,
211 .max_access_size = 4,
212 },
213 .endianness = DEVICE_NATIVE_ENDIAN,
214 };
215
216 static const MemoryRegionOps timerblock_ops = {
217 .read = timerblock_read,
218 .write = timerblock_write,
219 .valid = {
220 .min_access_size = 4,
221 .max_access_size = 4,
222 },
223 .endianness = DEVICE_NATIVE_ENDIAN,
224 };
225
226 static void timerblock_reset(timerblock *tb)
227 {
228 tb->count = 0;
229 tb->load = 0;
230 tb->control = 0;
231 tb->status = 0;
232 tb->tick = 0;
233 }
234
235 static void arm_mptimer_reset(DeviceState *dev)
236 {
237 arm_mptimer_state *s =
238 FROM_SYSBUS(arm_mptimer_state, sysbus_from_qdev(dev));
239 int i;
240 /* We reset every timer in the array, not just the ones we're using,
241 * because vmsave will look at every array element.
242 */
243 for (i = 0; i < ARRAY_SIZE(s->timerblock); i++) {
244 timerblock_reset(&s->timerblock[i]);
245 }
246 }
247
248 static int arm_mptimer_init(SysBusDevice *dev)
249 {
250 arm_mptimer_state *s = FROM_SYSBUS(arm_mptimer_state, dev);
251 int i;
252 if (s->num_cpu < 1 || s->num_cpu > MAX_CPUS) {
253 hw_error("%s: num-cpu must be between 1 and %d\n", __func__, MAX_CPUS);
254 }
255 /* We implement one timer and one watchdog block per CPU, and
256 * expose multiple MMIO regions:
257 * * region 0 is "timer for this core"
258 * * region 1 is "watchdog for this core"
259 * * region 2 is "timer for core 0"
260 * * region 3 is "watchdog for core 0"
261 * * region 4 is "timer for core 1"
262 * * region 5 is "watchdog for core 1"
263 * and so on.
264 * The outgoing interrupt lines are
265 * * timer for core 0
266 * * watchdog for core 0
267 * * timer for core 1
268 * * watchdog for core 1
269 * and so on.
270 */
271 memory_region_init_io(&s->iomem[0], &arm_thistimer_ops, s,
272 "arm_mptimer_timer", 0x20);
273 sysbus_init_mmio(dev, &s->iomem[0]);
274 memory_region_init_io(&s->iomem[1], &arm_thiswdog_ops, s,
275 "arm_mptimer_wdog", 0x20);
276 sysbus_init_mmio(dev, &s->iomem[1]);
277 for (i = 0; i < (s->num_cpu * 2); i++) {
278 timerblock *tb = &s->timerblock[i];
279 tb->timer = qemu_new_timer_ns(vm_clock, timerblock_tick, tb);
280 sysbus_init_irq(dev, &tb->irq);
281 memory_region_init_io(&tb->iomem, &timerblock_ops, tb,
282 "arm_mptimer_timerblock", 0x20);
283 sysbus_init_mmio(dev, &tb->iomem);
284 }
285
286 return 0;
287 }
288
289 static const VMStateDescription vmstate_timerblock = {
290 .name = "arm_mptimer_timerblock",
291 .version_id = 1,
292 .minimum_version_id = 1,
293 .fields = (VMStateField[]) {
294 VMSTATE_UINT32(count, timerblock),
295 VMSTATE_UINT32(load, timerblock),
296 VMSTATE_UINT32(control, timerblock),
297 VMSTATE_UINT32(status, timerblock),
298 VMSTATE_INT64(tick, timerblock),
299 VMSTATE_END_OF_LIST()
300 }
301 };
302
303 static const VMStateDescription vmstate_arm_mptimer = {
304 .name = "arm_mptimer",
305 .version_id = 1,
306 .minimum_version_id = 1,
307 .fields = (VMStateField[]) {
308 VMSTATE_STRUCT_ARRAY(timerblock, arm_mptimer_state, (MAX_CPUS * 2),
309 1, vmstate_timerblock, timerblock),
310 VMSTATE_END_OF_LIST()
311 }
312 };
313
314 static void arm_mptimer_class_init(ObjectClass *klass, void *data)
315 {
316 SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
317
318 sbc->init = arm_mptimer_init;
319 }
320
321 static DeviceInfo arm_mptimer_info = {
322 .name = "arm_mptimer",
323 .size = sizeof(arm_mptimer_state),
324 .vmsd = &vmstate_arm_mptimer,
325 .reset = arm_mptimer_reset,
326 .no_user = 1,
327 .class_init = arm_mptimer_class_init,
328 .props = (Property[]) {
329 DEFINE_PROP_UINT32("num-cpu", arm_mptimer_state, num_cpu, 0),
330 DEFINE_PROP_END_OF_LIST()
331 }
332 };
333
334 static void arm_mptimer_register_devices(void)
335 {
336 sysbus_register_withprop(&arm_mptimer_info);
337 }
338
339 device_init(arm_mptimer_register_devices)