hw/block/nvme: additional tracing
[qemu.git] / hw / block / nvme.c
1 /*
2 * QEMU NVM Express Controller
3 *
4 * Copyright (c) 2012, Intel Corporation
5 *
6 * Written by Keith Busch <keith.busch@intel.com>
7 *
8 * This code is licensed under the GNU GPL v2 or later.
9 */
10
11 /**
12 * Reference Specs: http://www.nvmexpress.org, 1.2, 1.1, 1.0e
13 *
14 * https://nvmexpress.org/developers/nvme-specification/
15 */
16
17 /**
18 * Usage: add options:
19 * -drive file=<file>,if=none,id=<drive_id>
20 * -device nvme,drive=<drive_id>,serial=<serial>,id=<id[optional]>, \
21 * cmb_size_mb=<cmb_size_mb[optional]>, \
22 * [pmrdev=<mem_backend_file_id>,] \
23 * max_ioqpairs=<N[optional]>
24 *
25 * Note cmb_size_mb denotes size of CMB in MB. CMB is assumed to be at
26 * offset 0 in BAR2 and supports only WDS, RDS and SQS for now.
27 *
28 * cmb_size_mb= and pmrdev= options are mutually exclusive due to limitation
29 * in available BAR's. cmb_size_mb= will take precedence over pmrdev= when
30 * both provided.
31 * Enabling pmr emulation can be achieved by pointing to memory-backend-file.
32 * For example:
33 * -object memory-backend-file,id=<mem_id>,share=on,mem-path=<file_path>, \
34 * size=<size> .... -device nvme,...,pmrdev=<mem_id>
35 */
36
37 #include "qemu/osdep.h"
38 #include "qemu/units.h"
39 #include "qemu/error-report.h"
40 #include "hw/block/block.h"
41 #include "hw/pci/msix.h"
42 #include "hw/pci/pci.h"
43 #include "hw/qdev-properties.h"
44 #include "migration/vmstate.h"
45 #include "sysemu/sysemu.h"
46 #include "qapi/error.h"
47 #include "qapi/visitor.h"
48 #include "sysemu/hostmem.h"
49 #include "sysemu/block-backend.h"
50 #include "exec/memory.h"
51 #include "qemu/log.h"
52 #include "qemu/module.h"
53 #include "qemu/cutils.h"
54 #include "trace.h"
55 #include "nvme.h"
56
57 #define NVME_MAX_IOQPAIRS 0xffff
58 #define NVME_DB_SIZE 4
59 #define NVME_CMB_BIR 2
60 #define NVME_PMR_BIR 2
61
62 #define NVME_GUEST_ERR(trace, fmt, ...) \
63 do { \
64 (trace_##trace)(__VA_ARGS__); \
65 qemu_log_mask(LOG_GUEST_ERROR, #trace \
66 " in %s: " fmt "\n", __func__, ## __VA_ARGS__); \
67 } while (0)
68
69 static void nvme_process_sq(void *opaque);
70
71 static uint16_t nvme_cid(NvmeRequest *req)
72 {
73 if (!req) {
74 return 0xffff;
75 }
76
77 return le16_to_cpu(req->cqe.cid);
78 }
79
80 static uint16_t nvme_sqid(NvmeRequest *req)
81 {
82 return le16_to_cpu(req->sq->sqid);
83 }
84
85 static bool nvme_addr_is_cmb(NvmeCtrl *n, hwaddr addr)
86 {
87 hwaddr low = n->ctrl_mem.addr;
88 hwaddr hi = n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size);
89
90 return addr >= low && addr < hi;
91 }
92
93 static void nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size)
94 {
95 if (n->bar.cmbsz && nvme_addr_is_cmb(n, addr)) {
96 memcpy(buf, (void *)&n->cmbuf[addr - n->ctrl_mem.addr], size);
97 return;
98 }
99
100 pci_dma_read(&n->parent_obj, addr, buf, size);
101 }
102
103 static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid)
104 {
105 return sqid < n->params.max_ioqpairs + 1 && n->sq[sqid] != NULL ? 0 : -1;
106 }
107
108 static int nvme_check_cqid(NvmeCtrl *n, uint16_t cqid)
109 {
110 return cqid < n->params.max_ioqpairs + 1 && n->cq[cqid] != NULL ? 0 : -1;
111 }
112
113 static void nvme_inc_cq_tail(NvmeCQueue *cq)
114 {
115 cq->tail++;
116 if (cq->tail >= cq->size) {
117 cq->tail = 0;
118 cq->phase = !cq->phase;
119 }
120 }
121
122 static void nvme_inc_sq_head(NvmeSQueue *sq)
123 {
124 sq->head = (sq->head + 1) % sq->size;
125 }
126
127 static uint8_t nvme_cq_full(NvmeCQueue *cq)
128 {
129 return (cq->tail + 1) % cq->size == cq->head;
130 }
131
132 static uint8_t nvme_sq_empty(NvmeSQueue *sq)
133 {
134 return sq->head == sq->tail;
135 }
136
137 static void nvme_irq_check(NvmeCtrl *n)
138 {
139 if (msix_enabled(&(n->parent_obj))) {
140 return;
141 }
142 if (~n->bar.intms & n->irq_status) {
143 pci_irq_assert(&n->parent_obj);
144 } else {
145 pci_irq_deassert(&n->parent_obj);
146 }
147 }
148
149 static void nvme_irq_assert(NvmeCtrl *n, NvmeCQueue *cq)
150 {
151 if (cq->irq_enabled) {
152 if (msix_enabled(&(n->parent_obj))) {
153 trace_pci_nvme_irq_msix(cq->vector);
154 msix_notify(&(n->parent_obj), cq->vector);
155 } else {
156 trace_pci_nvme_irq_pin();
157 assert(cq->vector < 32);
158 n->irq_status |= 1 << cq->vector;
159 nvme_irq_check(n);
160 }
161 } else {
162 trace_pci_nvme_irq_masked();
163 }
164 }
165
166 static void nvme_irq_deassert(NvmeCtrl *n, NvmeCQueue *cq)
167 {
168 if (cq->irq_enabled) {
169 if (msix_enabled(&(n->parent_obj))) {
170 return;
171 } else {
172 assert(cq->vector < 32);
173 n->irq_status &= ~(1 << cq->vector);
174 nvme_irq_check(n);
175 }
176 }
177 }
178
179 static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVector *iov, uint64_t prp1,
180 uint64_t prp2, uint32_t len, NvmeCtrl *n)
181 {
182 hwaddr trans_len = n->page_size - (prp1 % n->page_size);
183 trans_len = MIN(len, trans_len);
184 int num_prps = (len >> n->page_bits) + 1;
185
186 if (unlikely(!prp1)) {
187 trace_pci_nvme_err_invalid_prp();
188 return NVME_INVALID_FIELD | NVME_DNR;
189 } else if (n->bar.cmbsz && prp1 >= n->ctrl_mem.addr &&
190 prp1 < n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size)) {
191 qsg->nsg = 0;
192 qemu_iovec_init(iov, num_prps);
193 qemu_iovec_add(iov, (void *)&n->cmbuf[prp1 - n->ctrl_mem.addr], trans_len);
194 } else {
195 pci_dma_sglist_init(qsg, &n->parent_obj, num_prps);
196 qemu_sglist_add(qsg, prp1, trans_len);
197 }
198 len -= trans_len;
199 if (len) {
200 if (unlikely(!prp2)) {
201 trace_pci_nvme_err_invalid_prp2_missing();
202 goto unmap;
203 }
204 if (len > n->page_size) {
205 uint64_t prp_list[n->max_prp_ents];
206 uint32_t nents, prp_trans;
207 int i = 0;
208
209 nents = (len + n->page_size - 1) >> n->page_bits;
210 prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
211 nvme_addr_read(n, prp2, (void *)prp_list, prp_trans);
212 while (len != 0) {
213 uint64_t prp_ent = le64_to_cpu(prp_list[i]);
214
215 if (i == n->max_prp_ents - 1 && len > n->page_size) {
216 if (unlikely(!prp_ent || prp_ent & (n->page_size - 1))) {
217 trace_pci_nvme_err_invalid_prplist_ent(prp_ent);
218 goto unmap;
219 }
220
221 i = 0;
222 nents = (len + n->page_size - 1) >> n->page_bits;
223 prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
224 nvme_addr_read(n, prp_ent, (void *)prp_list,
225 prp_trans);
226 prp_ent = le64_to_cpu(prp_list[i]);
227 }
228
229 if (unlikely(!prp_ent || prp_ent & (n->page_size - 1))) {
230 trace_pci_nvme_err_invalid_prplist_ent(prp_ent);
231 goto unmap;
232 }
233
234 trans_len = MIN(len, n->page_size);
235 if (qsg->nsg){
236 qemu_sglist_add(qsg, prp_ent, trans_len);
237 } else {
238 qemu_iovec_add(iov, (void *)&n->cmbuf[prp_ent - n->ctrl_mem.addr], trans_len);
239 }
240 len -= trans_len;
241 i++;
242 }
243 } else {
244 if (unlikely(prp2 & (n->page_size - 1))) {
245 trace_pci_nvme_err_invalid_prp2_align(prp2);
246 goto unmap;
247 }
248 if (qsg->nsg) {
249 qemu_sglist_add(qsg, prp2, len);
250 } else {
251 qemu_iovec_add(iov, (void *)&n->cmbuf[prp2 - n->ctrl_mem.addr], trans_len);
252 }
253 }
254 }
255 return NVME_SUCCESS;
256
257 unmap:
258 qemu_sglist_destroy(qsg);
259 return NVME_INVALID_FIELD | NVME_DNR;
260 }
261
262 static uint16_t nvme_dma_write_prp(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
263 uint64_t prp1, uint64_t prp2)
264 {
265 QEMUSGList qsg;
266 QEMUIOVector iov;
267 uint16_t status = NVME_SUCCESS;
268
269 if (nvme_map_prp(&qsg, &iov, prp1, prp2, len, n)) {
270 return NVME_INVALID_FIELD | NVME_DNR;
271 }
272 if (qsg.nsg > 0) {
273 if (dma_buf_write(ptr, len, &qsg)) {
274 status = NVME_INVALID_FIELD | NVME_DNR;
275 }
276 qemu_sglist_destroy(&qsg);
277 } else {
278 if (qemu_iovec_to_buf(&iov, 0, ptr, len) != len) {
279 status = NVME_INVALID_FIELD | NVME_DNR;
280 }
281 qemu_iovec_destroy(&iov);
282 }
283 return status;
284 }
285
286 static uint16_t nvme_dma_read_prp(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
287 uint64_t prp1, uint64_t prp2)
288 {
289 QEMUSGList qsg;
290 QEMUIOVector iov;
291 uint16_t status = NVME_SUCCESS;
292
293 trace_pci_nvme_dma_read(prp1, prp2);
294
295 if (nvme_map_prp(&qsg, &iov, prp1, prp2, len, n)) {
296 return NVME_INVALID_FIELD | NVME_DNR;
297 }
298 if (qsg.nsg > 0) {
299 if (unlikely(dma_buf_read(ptr, len, &qsg))) {
300 trace_pci_nvme_err_invalid_dma();
301 status = NVME_INVALID_FIELD | NVME_DNR;
302 }
303 qemu_sglist_destroy(&qsg);
304 } else {
305 if (unlikely(qemu_iovec_from_buf(&iov, 0, ptr, len) != len)) {
306 trace_pci_nvme_err_invalid_dma();
307 status = NVME_INVALID_FIELD | NVME_DNR;
308 }
309 qemu_iovec_destroy(&iov);
310 }
311 return status;
312 }
313
314 static void nvme_post_cqes(void *opaque)
315 {
316 NvmeCQueue *cq = opaque;
317 NvmeCtrl *n = cq->ctrl;
318 NvmeRequest *req, *next;
319
320 QTAILQ_FOREACH_SAFE(req, &cq->req_list, entry, next) {
321 NvmeSQueue *sq;
322 hwaddr addr;
323
324 if (nvme_cq_full(cq)) {
325 break;
326 }
327
328 QTAILQ_REMOVE(&cq->req_list, req, entry);
329 sq = req->sq;
330 req->cqe.status = cpu_to_le16((req->status << 1) | cq->phase);
331 req->cqe.sq_id = cpu_to_le16(sq->sqid);
332 req->cqe.sq_head = cpu_to_le16(sq->head);
333 addr = cq->dma_addr + cq->tail * n->cqe_size;
334 nvme_inc_cq_tail(cq);
335 pci_dma_write(&n->parent_obj, addr, (void *)&req->cqe,
336 sizeof(req->cqe));
337 QTAILQ_INSERT_TAIL(&sq->req_list, req, entry);
338 }
339 if (cq->tail != cq->head) {
340 nvme_irq_assert(n, cq);
341 }
342 }
343
344 static void nvme_enqueue_req_completion(NvmeCQueue *cq, NvmeRequest *req)
345 {
346 assert(cq->cqid == req->sq->cqid);
347 trace_pci_nvme_enqueue_req_completion(nvme_cid(req), cq->cqid,
348 req->status);
349 QTAILQ_REMOVE(&req->sq->out_req_list, req, entry);
350 QTAILQ_INSERT_TAIL(&cq->req_list, req, entry);
351 timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
352 }
353
354 static void nvme_rw_cb(void *opaque, int ret)
355 {
356 NvmeRequest *req = opaque;
357 NvmeSQueue *sq = req->sq;
358 NvmeCtrl *n = sq->ctrl;
359 NvmeCQueue *cq = n->cq[sq->cqid];
360
361 trace_pci_nvme_rw_cb(nvme_cid(req));
362
363 if (!ret) {
364 block_acct_done(blk_get_stats(n->conf.blk), &req->acct);
365 req->status = NVME_SUCCESS;
366 } else {
367 block_acct_failed(blk_get_stats(n->conf.blk), &req->acct);
368 req->status = NVME_INTERNAL_DEV_ERROR;
369 }
370 if (req->has_sg) {
371 qemu_sglist_destroy(&req->qsg);
372 }
373 nvme_enqueue_req_completion(cq, req);
374 }
375
376 static uint16_t nvme_flush(NvmeCtrl *n, NvmeNamespace *ns, NvmeCmd *cmd,
377 NvmeRequest *req)
378 {
379 req->has_sg = false;
380 block_acct_start(blk_get_stats(n->conf.blk), &req->acct, 0,
381 BLOCK_ACCT_FLUSH);
382 req->aiocb = blk_aio_flush(n->conf.blk, nvme_rw_cb, req);
383
384 return NVME_NO_COMPLETE;
385 }
386
387 static uint16_t nvme_write_zeros(NvmeCtrl *n, NvmeNamespace *ns, NvmeCmd *cmd,
388 NvmeRequest *req)
389 {
390 NvmeRwCmd *rw = (NvmeRwCmd *)cmd;
391 const uint8_t lba_index = NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas);
392 const uint8_t data_shift = ns->id_ns.lbaf[lba_index].ds;
393 uint64_t slba = le64_to_cpu(rw->slba);
394 uint32_t nlb = le16_to_cpu(rw->nlb) + 1;
395 uint64_t offset = slba << data_shift;
396 uint32_t count = nlb << data_shift;
397
398 trace_pci_nvme_write_zeroes(nvme_cid(req), slba, nlb);
399
400 if (unlikely(slba + nlb > ns->id_ns.nsze)) {
401 trace_pci_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze);
402 return NVME_LBA_RANGE | NVME_DNR;
403 }
404
405 req->has_sg = false;
406 block_acct_start(blk_get_stats(n->conf.blk), &req->acct, 0,
407 BLOCK_ACCT_WRITE);
408 req->aiocb = blk_aio_pwrite_zeroes(n->conf.blk, offset, count,
409 BDRV_REQ_MAY_UNMAP, nvme_rw_cb, req);
410 return NVME_NO_COMPLETE;
411 }
412
413 static uint16_t nvme_rw(NvmeCtrl *n, NvmeNamespace *ns, NvmeCmd *cmd,
414 NvmeRequest *req)
415 {
416 NvmeRwCmd *rw = (NvmeRwCmd *)cmd;
417 uint32_t nlb = le32_to_cpu(rw->nlb) + 1;
418 uint64_t slba = le64_to_cpu(rw->slba);
419 uint64_t prp1 = le64_to_cpu(rw->dptr.prp1);
420 uint64_t prp2 = le64_to_cpu(rw->dptr.prp2);
421
422 uint8_t lba_index = NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas);
423 uint8_t data_shift = ns->id_ns.lbaf[lba_index].ds;
424 uint64_t data_size = (uint64_t)nlb << data_shift;
425 uint64_t data_offset = slba << data_shift;
426 int is_write = rw->opcode == NVME_CMD_WRITE ? 1 : 0;
427 enum BlockAcctType acct = is_write ? BLOCK_ACCT_WRITE : BLOCK_ACCT_READ;
428
429 trace_pci_nvme_rw(is_write ? "write" : "read", nlb, data_size, slba);
430
431 if (unlikely((slba + nlb) > ns->id_ns.nsze)) {
432 block_acct_invalid(blk_get_stats(n->conf.blk), acct);
433 trace_pci_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze);
434 return NVME_LBA_RANGE | NVME_DNR;
435 }
436
437 if (nvme_map_prp(&req->qsg, &req->iov, prp1, prp2, data_size, n)) {
438 block_acct_invalid(blk_get_stats(n->conf.blk), acct);
439 return NVME_INVALID_FIELD | NVME_DNR;
440 }
441
442 dma_acct_start(n->conf.blk, &req->acct, &req->qsg, acct);
443 if (req->qsg.nsg > 0) {
444 req->has_sg = true;
445 req->aiocb = is_write ?
446 dma_blk_write(n->conf.blk, &req->qsg, data_offset, BDRV_SECTOR_SIZE,
447 nvme_rw_cb, req) :
448 dma_blk_read(n->conf.blk, &req->qsg, data_offset, BDRV_SECTOR_SIZE,
449 nvme_rw_cb, req);
450 } else {
451 req->has_sg = false;
452 req->aiocb = is_write ?
453 blk_aio_pwritev(n->conf.blk, data_offset, &req->iov, 0, nvme_rw_cb,
454 req) :
455 blk_aio_preadv(n->conf.blk, data_offset, &req->iov, 0, nvme_rw_cb,
456 req);
457 }
458
459 return NVME_NO_COMPLETE;
460 }
461
462 static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
463 {
464 NvmeNamespace *ns;
465 uint32_t nsid = le32_to_cpu(cmd->nsid);
466
467 trace_pci_nvme_io_cmd(nvme_cid(req), nsid, nvme_sqid(req), cmd->opcode);
468
469 if (unlikely(nsid == 0 || nsid > n->num_namespaces)) {
470 trace_pci_nvme_err_invalid_ns(nsid, n->num_namespaces);
471 return NVME_INVALID_NSID | NVME_DNR;
472 }
473
474 ns = &n->namespaces[nsid - 1];
475 switch (cmd->opcode) {
476 case NVME_CMD_FLUSH:
477 return nvme_flush(n, ns, cmd, req);
478 case NVME_CMD_WRITE_ZEROS:
479 return nvme_write_zeros(n, ns, cmd, req);
480 case NVME_CMD_WRITE:
481 case NVME_CMD_READ:
482 return nvme_rw(n, ns, cmd, req);
483 default:
484 trace_pci_nvme_err_invalid_opc(cmd->opcode);
485 return NVME_INVALID_OPCODE | NVME_DNR;
486 }
487 }
488
489 static void nvme_free_sq(NvmeSQueue *sq, NvmeCtrl *n)
490 {
491 n->sq[sq->sqid] = NULL;
492 timer_del(sq->timer);
493 timer_free(sq->timer);
494 g_free(sq->io_req);
495 if (sq->sqid) {
496 g_free(sq);
497 }
498 }
499
500 static uint16_t nvme_del_sq(NvmeCtrl *n, NvmeCmd *cmd)
501 {
502 NvmeDeleteQ *c = (NvmeDeleteQ *)cmd;
503 NvmeRequest *req, *next;
504 NvmeSQueue *sq;
505 NvmeCQueue *cq;
506 uint16_t qid = le16_to_cpu(c->qid);
507
508 if (unlikely(!qid || nvme_check_sqid(n, qid))) {
509 trace_pci_nvme_err_invalid_del_sq(qid);
510 return NVME_INVALID_QID | NVME_DNR;
511 }
512
513 trace_pci_nvme_del_sq(qid);
514
515 sq = n->sq[qid];
516 while (!QTAILQ_EMPTY(&sq->out_req_list)) {
517 req = QTAILQ_FIRST(&sq->out_req_list);
518 assert(req->aiocb);
519 blk_aio_cancel(req->aiocb);
520 }
521 if (!nvme_check_cqid(n, sq->cqid)) {
522 cq = n->cq[sq->cqid];
523 QTAILQ_REMOVE(&cq->sq_list, sq, entry);
524
525 nvme_post_cqes(cq);
526 QTAILQ_FOREACH_SAFE(req, &cq->req_list, entry, next) {
527 if (req->sq == sq) {
528 QTAILQ_REMOVE(&cq->req_list, req, entry);
529 QTAILQ_INSERT_TAIL(&sq->req_list, req, entry);
530 }
531 }
532 }
533
534 nvme_free_sq(sq, n);
535 return NVME_SUCCESS;
536 }
537
538 static void nvme_init_sq(NvmeSQueue *sq, NvmeCtrl *n, uint64_t dma_addr,
539 uint16_t sqid, uint16_t cqid, uint16_t size)
540 {
541 int i;
542 NvmeCQueue *cq;
543
544 sq->ctrl = n;
545 sq->dma_addr = dma_addr;
546 sq->sqid = sqid;
547 sq->size = size;
548 sq->cqid = cqid;
549 sq->head = sq->tail = 0;
550 sq->io_req = g_new(NvmeRequest, sq->size);
551
552 QTAILQ_INIT(&sq->req_list);
553 QTAILQ_INIT(&sq->out_req_list);
554 for (i = 0; i < sq->size; i++) {
555 sq->io_req[i].sq = sq;
556 QTAILQ_INSERT_TAIL(&(sq->req_list), &sq->io_req[i], entry);
557 }
558 sq->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, nvme_process_sq, sq);
559
560 assert(n->cq[cqid]);
561 cq = n->cq[cqid];
562 QTAILQ_INSERT_TAIL(&(cq->sq_list), sq, entry);
563 n->sq[sqid] = sq;
564 }
565
566 static uint16_t nvme_create_sq(NvmeCtrl *n, NvmeCmd *cmd)
567 {
568 NvmeSQueue *sq;
569 NvmeCreateSq *c = (NvmeCreateSq *)cmd;
570
571 uint16_t cqid = le16_to_cpu(c->cqid);
572 uint16_t sqid = le16_to_cpu(c->sqid);
573 uint16_t qsize = le16_to_cpu(c->qsize);
574 uint16_t qflags = le16_to_cpu(c->sq_flags);
575 uint64_t prp1 = le64_to_cpu(c->prp1);
576
577 trace_pci_nvme_create_sq(prp1, sqid, cqid, qsize, qflags);
578
579 if (unlikely(!cqid || nvme_check_cqid(n, cqid))) {
580 trace_pci_nvme_err_invalid_create_sq_cqid(cqid);
581 return NVME_INVALID_CQID | NVME_DNR;
582 }
583 if (unlikely(!sqid || !nvme_check_sqid(n, sqid))) {
584 trace_pci_nvme_err_invalid_create_sq_sqid(sqid);
585 return NVME_INVALID_QID | NVME_DNR;
586 }
587 if (unlikely(!qsize || qsize > NVME_CAP_MQES(n->bar.cap))) {
588 trace_pci_nvme_err_invalid_create_sq_size(qsize);
589 return NVME_MAX_QSIZE_EXCEEDED | NVME_DNR;
590 }
591 if (unlikely(!prp1 || prp1 & (n->page_size - 1))) {
592 trace_pci_nvme_err_invalid_create_sq_addr(prp1);
593 return NVME_INVALID_FIELD | NVME_DNR;
594 }
595 if (unlikely(!(NVME_SQ_FLAGS_PC(qflags)))) {
596 trace_pci_nvme_err_invalid_create_sq_qflags(NVME_SQ_FLAGS_PC(qflags));
597 return NVME_INVALID_FIELD | NVME_DNR;
598 }
599 sq = g_malloc0(sizeof(*sq));
600 nvme_init_sq(sq, n, prp1, sqid, cqid, qsize + 1);
601 return NVME_SUCCESS;
602 }
603
604 static void nvme_free_cq(NvmeCQueue *cq, NvmeCtrl *n)
605 {
606 n->cq[cq->cqid] = NULL;
607 timer_del(cq->timer);
608 timer_free(cq->timer);
609 msix_vector_unuse(&n->parent_obj, cq->vector);
610 if (cq->cqid) {
611 g_free(cq);
612 }
613 }
614
615 static uint16_t nvme_del_cq(NvmeCtrl *n, NvmeCmd *cmd)
616 {
617 NvmeDeleteQ *c = (NvmeDeleteQ *)cmd;
618 NvmeCQueue *cq;
619 uint16_t qid = le16_to_cpu(c->qid);
620
621 if (unlikely(!qid || nvme_check_cqid(n, qid))) {
622 trace_pci_nvme_err_invalid_del_cq_cqid(qid);
623 return NVME_INVALID_CQID | NVME_DNR;
624 }
625
626 cq = n->cq[qid];
627 if (unlikely(!QTAILQ_EMPTY(&cq->sq_list))) {
628 trace_pci_nvme_err_invalid_del_cq_notempty(qid);
629 return NVME_INVALID_QUEUE_DEL;
630 }
631 nvme_irq_deassert(n, cq);
632 trace_pci_nvme_del_cq(qid);
633 nvme_free_cq(cq, n);
634 return NVME_SUCCESS;
635 }
636
637 static void nvme_init_cq(NvmeCQueue *cq, NvmeCtrl *n, uint64_t dma_addr,
638 uint16_t cqid, uint16_t vector, uint16_t size, uint16_t irq_enabled)
639 {
640 int ret;
641
642 ret = msix_vector_use(&n->parent_obj, vector);
643 assert(ret == 0);
644 cq->ctrl = n;
645 cq->cqid = cqid;
646 cq->size = size;
647 cq->dma_addr = dma_addr;
648 cq->phase = 1;
649 cq->irq_enabled = irq_enabled;
650 cq->vector = vector;
651 cq->head = cq->tail = 0;
652 QTAILQ_INIT(&cq->req_list);
653 QTAILQ_INIT(&cq->sq_list);
654 n->cq[cqid] = cq;
655 cq->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, nvme_post_cqes, cq);
656 }
657
658 static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeCmd *cmd)
659 {
660 NvmeCQueue *cq;
661 NvmeCreateCq *c = (NvmeCreateCq *)cmd;
662 uint16_t cqid = le16_to_cpu(c->cqid);
663 uint16_t vector = le16_to_cpu(c->irq_vector);
664 uint16_t qsize = le16_to_cpu(c->qsize);
665 uint16_t qflags = le16_to_cpu(c->cq_flags);
666 uint64_t prp1 = le64_to_cpu(c->prp1);
667
668 trace_pci_nvme_create_cq(prp1, cqid, vector, qsize, qflags,
669 NVME_CQ_FLAGS_IEN(qflags) != 0);
670
671 if (unlikely(!cqid || !nvme_check_cqid(n, cqid))) {
672 trace_pci_nvme_err_invalid_create_cq_cqid(cqid);
673 return NVME_INVALID_CQID | NVME_DNR;
674 }
675 if (unlikely(!qsize || qsize > NVME_CAP_MQES(n->bar.cap))) {
676 trace_pci_nvme_err_invalid_create_cq_size(qsize);
677 return NVME_MAX_QSIZE_EXCEEDED | NVME_DNR;
678 }
679 if (unlikely(!prp1)) {
680 trace_pci_nvme_err_invalid_create_cq_addr(prp1);
681 return NVME_INVALID_FIELD | NVME_DNR;
682 }
683 if (unlikely(!msix_enabled(&n->parent_obj) && vector)) {
684 trace_pci_nvme_err_invalid_create_cq_vector(vector);
685 return NVME_INVALID_IRQ_VECTOR | NVME_DNR;
686 }
687 if (unlikely(vector >= n->params.msix_qsize)) {
688 trace_pci_nvme_err_invalid_create_cq_vector(vector);
689 return NVME_INVALID_IRQ_VECTOR | NVME_DNR;
690 }
691 if (unlikely(!(NVME_CQ_FLAGS_PC(qflags)))) {
692 trace_pci_nvme_err_invalid_create_cq_qflags(NVME_CQ_FLAGS_PC(qflags));
693 return NVME_INVALID_FIELD | NVME_DNR;
694 }
695
696 cq = g_malloc0(sizeof(*cq));
697 nvme_init_cq(cq, n, prp1, cqid, vector, qsize + 1,
698 NVME_CQ_FLAGS_IEN(qflags));
699 return NVME_SUCCESS;
700 }
701
702 static uint16_t nvme_identify_ctrl(NvmeCtrl *n, NvmeIdentify *c)
703 {
704 uint64_t prp1 = le64_to_cpu(c->prp1);
705 uint64_t prp2 = le64_to_cpu(c->prp2);
706
707 trace_pci_nvme_identify_ctrl();
708
709 return nvme_dma_read_prp(n, (uint8_t *)&n->id_ctrl, sizeof(n->id_ctrl),
710 prp1, prp2);
711 }
712
713 static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeIdentify *c)
714 {
715 NvmeNamespace *ns;
716 uint32_t nsid = le32_to_cpu(c->nsid);
717 uint64_t prp1 = le64_to_cpu(c->prp1);
718 uint64_t prp2 = le64_to_cpu(c->prp2);
719
720 trace_pci_nvme_identify_ns(nsid);
721
722 if (unlikely(nsid == 0 || nsid > n->num_namespaces)) {
723 trace_pci_nvme_err_invalid_ns(nsid, n->num_namespaces);
724 return NVME_INVALID_NSID | NVME_DNR;
725 }
726
727 ns = &n->namespaces[nsid - 1];
728
729 return nvme_dma_read_prp(n, (uint8_t *)&ns->id_ns, sizeof(ns->id_ns),
730 prp1, prp2);
731 }
732
733 static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeIdentify *c)
734 {
735 static const int data_len = NVME_IDENTIFY_DATA_SIZE;
736 uint32_t min_nsid = le32_to_cpu(c->nsid);
737 uint64_t prp1 = le64_to_cpu(c->prp1);
738 uint64_t prp2 = le64_to_cpu(c->prp2);
739 uint32_t *list;
740 uint16_t ret;
741 int i, j = 0;
742
743 trace_pci_nvme_identify_nslist(min_nsid);
744
745 list = g_malloc0(data_len);
746 for (i = 0; i < n->num_namespaces; i++) {
747 if (i < min_nsid) {
748 continue;
749 }
750 list[j++] = cpu_to_le32(i + 1);
751 if (j == data_len / sizeof(uint32_t)) {
752 break;
753 }
754 }
755 ret = nvme_dma_read_prp(n, (uint8_t *)list, data_len, prp1, prp2);
756 g_free(list);
757 return ret;
758 }
759
760 static uint16_t nvme_identify(NvmeCtrl *n, NvmeCmd *cmd)
761 {
762 NvmeIdentify *c = (NvmeIdentify *)cmd;
763
764 switch (le32_to_cpu(c->cns)) {
765 case NVME_ID_CNS_NS:
766 return nvme_identify_ns(n, c);
767 case NVME_ID_CNS_CTRL:
768 return nvme_identify_ctrl(n, c);
769 case NVME_ID_CNS_NS_ACTIVE_LIST:
770 return nvme_identify_nslist(n, c);
771 default:
772 trace_pci_nvme_err_invalid_identify_cns(le32_to_cpu(c->cns));
773 return NVME_INVALID_FIELD | NVME_DNR;
774 }
775 }
776
777 static inline void nvme_set_timestamp(NvmeCtrl *n, uint64_t ts)
778 {
779 trace_pci_nvme_setfeat_timestamp(ts);
780
781 n->host_timestamp = le64_to_cpu(ts);
782 n->timestamp_set_qemu_clock_ms = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
783 }
784
785 static inline uint64_t nvme_get_timestamp(const NvmeCtrl *n)
786 {
787 uint64_t current_time = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
788 uint64_t elapsed_time = current_time - n->timestamp_set_qemu_clock_ms;
789
790 union nvme_timestamp {
791 struct {
792 uint64_t timestamp:48;
793 uint64_t sync:1;
794 uint64_t origin:3;
795 uint64_t rsvd1:12;
796 };
797 uint64_t all;
798 };
799
800 union nvme_timestamp ts;
801 ts.all = 0;
802
803 /*
804 * If the sum of the Timestamp value set by the host and the elapsed
805 * time exceeds 2^48, the value returned should be reduced modulo 2^48.
806 */
807 ts.timestamp = (n->host_timestamp + elapsed_time) & 0xffffffffffff;
808
809 /* If the host timestamp is non-zero, set the timestamp origin */
810 ts.origin = n->host_timestamp ? 0x01 : 0x00;
811
812 trace_pci_nvme_getfeat_timestamp(ts.all);
813
814 return cpu_to_le64(ts.all);
815 }
816
817 static uint16_t nvme_get_feature_timestamp(NvmeCtrl *n, NvmeCmd *cmd)
818 {
819 uint64_t prp1 = le64_to_cpu(cmd->dptr.prp1);
820 uint64_t prp2 = le64_to_cpu(cmd->dptr.prp2);
821
822 uint64_t timestamp = nvme_get_timestamp(n);
823
824 return nvme_dma_read_prp(n, (uint8_t *)&timestamp,
825 sizeof(timestamp), prp1, prp2);
826 }
827
828 static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
829 {
830 uint32_t dw10 = le32_to_cpu(cmd->cdw10);
831 uint32_t result;
832
833 switch (dw10) {
834 case NVME_VOLATILE_WRITE_CACHE:
835 result = blk_enable_write_cache(n->conf.blk);
836 trace_pci_nvme_getfeat_vwcache(result ? "enabled" : "disabled");
837 break;
838 case NVME_NUMBER_OF_QUEUES:
839 result = (n->params.max_ioqpairs - 1) |
840 ((n->params.max_ioqpairs - 1) << 16);
841 trace_pci_nvme_getfeat_numq(result);
842 break;
843 case NVME_TIMESTAMP:
844 return nvme_get_feature_timestamp(n, cmd);
845 default:
846 trace_pci_nvme_err_invalid_getfeat(dw10);
847 return NVME_INVALID_FIELD | NVME_DNR;
848 }
849
850 req->cqe.result = cpu_to_le32(result);
851 return NVME_SUCCESS;
852 }
853
854 static uint16_t nvme_set_feature_timestamp(NvmeCtrl *n, NvmeCmd *cmd)
855 {
856 uint16_t ret;
857 uint64_t timestamp;
858 uint64_t prp1 = le64_to_cpu(cmd->dptr.prp1);
859 uint64_t prp2 = le64_to_cpu(cmd->dptr.prp2);
860
861 ret = nvme_dma_write_prp(n, (uint8_t *)&timestamp,
862 sizeof(timestamp), prp1, prp2);
863 if (ret != NVME_SUCCESS) {
864 return ret;
865 }
866
867 nvme_set_timestamp(n, timestamp);
868
869 return NVME_SUCCESS;
870 }
871
872 static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
873 {
874 uint32_t dw10 = le32_to_cpu(cmd->cdw10);
875 uint32_t dw11 = le32_to_cpu(cmd->cdw11);
876
877 switch (dw10) {
878 case NVME_VOLATILE_WRITE_CACHE:
879 blk_set_enable_write_cache(n->conf.blk, dw11 & 1);
880 break;
881 case NVME_NUMBER_OF_QUEUES:
882 trace_pci_nvme_setfeat_numq((dw11 & 0xFFFF) + 1,
883 ((dw11 >> 16) & 0xFFFF) + 1,
884 n->params.max_ioqpairs,
885 n->params.max_ioqpairs);
886 req->cqe.result = cpu_to_le32((n->params.max_ioqpairs - 1) |
887 ((n->params.max_ioqpairs - 1) << 16));
888 break;
889 case NVME_TIMESTAMP:
890 return nvme_set_feature_timestamp(n, cmd);
891 default:
892 trace_pci_nvme_err_invalid_setfeat(dw10);
893 return NVME_INVALID_FIELD | NVME_DNR;
894 }
895 return NVME_SUCCESS;
896 }
897
898 static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
899 {
900 trace_pci_nvme_admin_cmd(nvme_cid(req), nvme_sqid(req), cmd->opcode);
901
902 switch (cmd->opcode) {
903 case NVME_ADM_CMD_DELETE_SQ:
904 return nvme_del_sq(n, cmd);
905 case NVME_ADM_CMD_CREATE_SQ:
906 return nvme_create_sq(n, cmd);
907 case NVME_ADM_CMD_DELETE_CQ:
908 return nvme_del_cq(n, cmd);
909 case NVME_ADM_CMD_CREATE_CQ:
910 return nvme_create_cq(n, cmd);
911 case NVME_ADM_CMD_IDENTIFY:
912 return nvme_identify(n, cmd);
913 case NVME_ADM_CMD_SET_FEATURES:
914 return nvme_set_feature(n, cmd, req);
915 case NVME_ADM_CMD_GET_FEATURES:
916 return nvme_get_feature(n, cmd, req);
917 default:
918 trace_pci_nvme_err_invalid_admin_opc(cmd->opcode);
919 return NVME_INVALID_OPCODE | NVME_DNR;
920 }
921 }
922
923 static void nvme_process_sq(void *opaque)
924 {
925 NvmeSQueue *sq = opaque;
926 NvmeCtrl *n = sq->ctrl;
927 NvmeCQueue *cq = n->cq[sq->cqid];
928
929 uint16_t status;
930 hwaddr addr;
931 NvmeCmd cmd;
932 NvmeRequest *req;
933
934 while (!(nvme_sq_empty(sq) || QTAILQ_EMPTY(&sq->req_list))) {
935 addr = sq->dma_addr + sq->head * n->sqe_size;
936 nvme_addr_read(n, addr, (void *)&cmd, sizeof(cmd));
937 nvme_inc_sq_head(sq);
938
939 req = QTAILQ_FIRST(&sq->req_list);
940 QTAILQ_REMOVE(&sq->req_list, req, entry);
941 QTAILQ_INSERT_TAIL(&sq->out_req_list, req, entry);
942 memset(&req->cqe, 0, sizeof(req->cqe));
943 req->cqe.cid = cmd.cid;
944
945 status = sq->sqid ? nvme_io_cmd(n, &cmd, req) :
946 nvme_admin_cmd(n, &cmd, req);
947 if (status != NVME_NO_COMPLETE) {
948 req->status = status;
949 nvme_enqueue_req_completion(cq, req);
950 }
951 }
952 }
953
954 static void nvme_clear_ctrl(NvmeCtrl *n)
955 {
956 int i;
957
958 blk_drain(n->conf.blk);
959
960 for (i = 0; i < n->params.max_ioqpairs + 1; i++) {
961 if (n->sq[i] != NULL) {
962 nvme_free_sq(n->sq[i], n);
963 }
964 }
965 for (i = 0; i < n->params.max_ioqpairs + 1; i++) {
966 if (n->cq[i] != NULL) {
967 nvme_free_cq(n->cq[i], n);
968 }
969 }
970
971 blk_flush(n->conf.blk);
972 n->bar.cc = 0;
973 }
974
975 static int nvme_start_ctrl(NvmeCtrl *n)
976 {
977 uint32_t page_bits = NVME_CC_MPS(n->bar.cc) + 12;
978 uint32_t page_size = 1 << page_bits;
979
980 if (unlikely(n->cq[0])) {
981 trace_pci_nvme_err_startfail_cq();
982 return -1;
983 }
984 if (unlikely(n->sq[0])) {
985 trace_pci_nvme_err_startfail_sq();
986 return -1;
987 }
988 if (unlikely(!n->bar.asq)) {
989 trace_pci_nvme_err_startfail_nbarasq();
990 return -1;
991 }
992 if (unlikely(!n->bar.acq)) {
993 trace_pci_nvme_err_startfail_nbaracq();
994 return -1;
995 }
996 if (unlikely(n->bar.asq & (page_size - 1))) {
997 trace_pci_nvme_err_startfail_asq_misaligned(n->bar.asq);
998 return -1;
999 }
1000 if (unlikely(n->bar.acq & (page_size - 1))) {
1001 trace_pci_nvme_err_startfail_acq_misaligned(n->bar.acq);
1002 return -1;
1003 }
1004 if (unlikely(NVME_CC_MPS(n->bar.cc) <
1005 NVME_CAP_MPSMIN(n->bar.cap))) {
1006 trace_pci_nvme_err_startfail_page_too_small(
1007 NVME_CC_MPS(n->bar.cc),
1008 NVME_CAP_MPSMIN(n->bar.cap));
1009 return -1;
1010 }
1011 if (unlikely(NVME_CC_MPS(n->bar.cc) >
1012 NVME_CAP_MPSMAX(n->bar.cap))) {
1013 trace_pci_nvme_err_startfail_page_too_large(
1014 NVME_CC_MPS(n->bar.cc),
1015 NVME_CAP_MPSMAX(n->bar.cap));
1016 return -1;
1017 }
1018 if (unlikely(NVME_CC_IOCQES(n->bar.cc) <
1019 NVME_CTRL_CQES_MIN(n->id_ctrl.cqes))) {
1020 trace_pci_nvme_err_startfail_cqent_too_small(
1021 NVME_CC_IOCQES(n->bar.cc),
1022 NVME_CTRL_CQES_MIN(n->bar.cap));
1023 return -1;
1024 }
1025 if (unlikely(NVME_CC_IOCQES(n->bar.cc) >
1026 NVME_CTRL_CQES_MAX(n->id_ctrl.cqes))) {
1027 trace_pci_nvme_err_startfail_cqent_too_large(
1028 NVME_CC_IOCQES(n->bar.cc),
1029 NVME_CTRL_CQES_MAX(n->bar.cap));
1030 return -1;
1031 }
1032 if (unlikely(NVME_CC_IOSQES(n->bar.cc) <
1033 NVME_CTRL_SQES_MIN(n->id_ctrl.sqes))) {
1034 trace_pci_nvme_err_startfail_sqent_too_small(
1035 NVME_CC_IOSQES(n->bar.cc),
1036 NVME_CTRL_SQES_MIN(n->bar.cap));
1037 return -1;
1038 }
1039 if (unlikely(NVME_CC_IOSQES(n->bar.cc) >
1040 NVME_CTRL_SQES_MAX(n->id_ctrl.sqes))) {
1041 trace_pci_nvme_err_startfail_sqent_too_large(
1042 NVME_CC_IOSQES(n->bar.cc),
1043 NVME_CTRL_SQES_MAX(n->bar.cap));
1044 return -1;
1045 }
1046 if (unlikely(!NVME_AQA_ASQS(n->bar.aqa))) {
1047 trace_pci_nvme_err_startfail_asqent_sz_zero();
1048 return -1;
1049 }
1050 if (unlikely(!NVME_AQA_ACQS(n->bar.aqa))) {
1051 trace_pci_nvme_err_startfail_acqent_sz_zero();
1052 return -1;
1053 }
1054
1055 n->page_bits = page_bits;
1056 n->page_size = page_size;
1057 n->max_prp_ents = n->page_size / sizeof(uint64_t);
1058 n->cqe_size = 1 << NVME_CC_IOCQES(n->bar.cc);
1059 n->sqe_size = 1 << NVME_CC_IOSQES(n->bar.cc);
1060 nvme_init_cq(&n->admin_cq, n, n->bar.acq, 0, 0,
1061 NVME_AQA_ACQS(n->bar.aqa) + 1, 1);
1062 nvme_init_sq(&n->admin_sq, n, n->bar.asq, 0, 0,
1063 NVME_AQA_ASQS(n->bar.aqa) + 1);
1064
1065 nvme_set_timestamp(n, 0ULL);
1066
1067 return 0;
1068 }
1069
1070 static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
1071 unsigned size)
1072 {
1073 if (unlikely(offset & (sizeof(uint32_t) - 1))) {
1074 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_misaligned32,
1075 "MMIO write not 32-bit aligned,"
1076 " offset=0x%"PRIx64"", offset);
1077 /* should be ignored, fall through for now */
1078 }
1079
1080 if (unlikely(size < sizeof(uint32_t))) {
1081 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_toosmall,
1082 "MMIO write smaller than 32-bits,"
1083 " offset=0x%"PRIx64", size=%u",
1084 offset, size);
1085 /* should be ignored, fall through for now */
1086 }
1087
1088 switch (offset) {
1089 case 0xc: /* INTMS */
1090 if (unlikely(msix_enabled(&(n->parent_obj)))) {
1091 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_intmask_with_msix,
1092 "undefined access to interrupt mask set"
1093 " when MSI-X is enabled");
1094 /* should be ignored, fall through for now */
1095 }
1096 n->bar.intms |= data & 0xffffffff;
1097 n->bar.intmc = n->bar.intms;
1098 trace_pci_nvme_mmio_intm_set(data & 0xffffffff, n->bar.intmc);
1099 nvme_irq_check(n);
1100 break;
1101 case 0x10: /* INTMC */
1102 if (unlikely(msix_enabled(&(n->parent_obj)))) {
1103 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_intmask_with_msix,
1104 "undefined access to interrupt mask clr"
1105 " when MSI-X is enabled");
1106 /* should be ignored, fall through for now */
1107 }
1108 n->bar.intms &= ~(data & 0xffffffff);
1109 n->bar.intmc = n->bar.intms;
1110 trace_pci_nvme_mmio_intm_clr(data & 0xffffffff, n->bar.intmc);
1111 nvme_irq_check(n);
1112 break;
1113 case 0x14: /* CC */
1114 trace_pci_nvme_mmio_cfg(data & 0xffffffff);
1115 /* Windows first sends data, then sends enable bit */
1116 if (!NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc) &&
1117 !NVME_CC_SHN(data) && !NVME_CC_SHN(n->bar.cc))
1118 {
1119 n->bar.cc = data;
1120 }
1121
1122 if (NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc)) {
1123 n->bar.cc = data;
1124 if (unlikely(nvme_start_ctrl(n))) {
1125 trace_pci_nvme_err_startfail();
1126 n->bar.csts = NVME_CSTS_FAILED;
1127 } else {
1128 trace_pci_nvme_mmio_start_success();
1129 n->bar.csts = NVME_CSTS_READY;
1130 }
1131 } else if (!NVME_CC_EN(data) && NVME_CC_EN(n->bar.cc)) {
1132 trace_pci_nvme_mmio_stopped();
1133 nvme_clear_ctrl(n);
1134 n->bar.csts &= ~NVME_CSTS_READY;
1135 }
1136 if (NVME_CC_SHN(data) && !(NVME_CC_SHN(n->bar.cc))) {
1137 trace_pci_nvme_mmio_shutdown_set();
1138 nvme_clear_ctrl(n);
1139 n->bar.cc = data;
1140 n->bar.csts |= NVME_CSTS_SHST_COMPLETE;
1141 } else if (!NVME_CC_SHN(data) && NVME_CC_SHN(n->bar.cc)) {
1142 trace_pci_nvme_mmio_shutdown_cleared();
1143 n->bar.csts &= ~NVME_CSTS_SHST_COMPLETE;
1144 n->bar.cc = data;
1145 }
1146 break;
1147 case 0x1C: /* CSTS */
1148 if (data & (1 << 4)) {
1149 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_ssreset_w1c_unsupported,
1150 "attempted to W1C CSTS.NSSRO"
1151 " but CAP.NSSRS is zero (not supported)");
1152 } else if (data != 0) {
1153 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_ro_csts,
1154 "attempted to set a read only bit"
1155 " of controller status");
1156 }
1157 break;
1158 case 0x20: /* NSSR */
1159 if (data == 0x4E564D65) {
1160 trace_pci_nvme_ub_mmiowr_ssreset_unsupported();
1161 } else {
1162 /* The spec says that writes of other values have no effect */
1163 return;
1164 }
1165 break;
1166 case 0x24: /* AQA */
1167 n->bar.aqa = data & 0xffffffff;
1168 trace_pci_nvme_mmio_aqattr(data & 0xffffffff);
1169 break;
1170 case 0x28: /* ASQ */
1171 n->bar.asq = data;
1172 trace_pci_nvme_mmio_asqaddr(data);
1173 break;
1174 case 0x2c: /* ASQ hi */
1175 n->bar.asq |= data << 32;
1176 trace_pci_nvme_mmio_asqaddr_hi(data, n->bar.asq);
1177 break;
1178 case 0x30: /* ACQ */
1179 trace_pci_nvme_mmio_acqaddr(data);
1180 n->bar.acq = data;
1181 break;
1182 case 0x34: /* ACQ hi */
1183 n->bar.acq |= data << 32;
1184 trace_pci_nvme_mmio_acqaddr_hi(data, n->bar.acq);
1185 break;
1186 case 0x38: /* CMBLOC */
1187 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_cmbloc_reserved,
1188 "invalid write to reserved CMBLOC"
1189 " when CMBSZ is zero, ignored");
1190 return;
1191 case 0x3C: /* CMBSZ */
1192 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_cmbsz_readonly,
1193 "invalid write to read only CMBSZ, ignored");
1194 return;
1195 case 0xE00: /* PMRCAP */
1196 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrcap_readonly,
1197 "invalid write to PMRCAP register, ignored");
1198 return;
1199 case 0xE04: /* TODO PMRCTL */
1200 break;
1201 case 0xE08: /* PMRSTS */
1202 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrsts_readonly,
1203 "invalid write to PMRSTS register, ignored");
1204 return;
1205 case 0xE0C: /* PMREBS */
1206 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrebs_readonly,
1207 "invalid write to PMREBS register, ignored");
1208 return;
1209 case 0xE10: /* PMRSWTP */
1210 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrswtp_readonly,
1211 "invalid write to PMRSWTP register, ignored");
1212 return;
1213 case 0xE14: /* TODO PMRMSC */
1214 break;
1215 default:
1216 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_invalid,
1217 "invalid MMIO write,"
1218 " offset=0x%"PRIx64", data=%"PRIx64"",
1219 offset, data);
1220 break;
1221 }
1222 }
1223
1224 static uint64_t nvme_mmio_read(void *opaque, hwaddr addr, unsigned size)
1225 {
1226 NvmeCtrl *n = (NvmeCtrl *)opaque;
1227 uint8_t *ptr = (uint8_t *)&n->bar;
1228 uint64_t val = 0;
1229
1230 trace_pci_nvme_mmio_read(addr);
1231
1232 if (unlikely(addr & (sizeof(uint32_t) - 1))) {
1233 NVME_GUEST_ERR(pci_nvme_ub_mmiord_misaligned32,
1234 "MMIO read not 32-bit aligned,"
1235 " offset=0x%"PRIx64"", addr);
1236 /* should RAZ, fall through for now */
1237 } else if (unlikely(size < sizeof(uint32_t))) {
1238 NVME_GUEST_ERR(pci_nvme_ub_mmiord_toosmall,
1239 "MMIO read smaller than 32-bits,"
1240 " offset=0x%"PRIx64"", addr);
1241 /* should RAZ, fall through for now */
1242 }
1243
1244 if (addr < sizeof(n->bar)) {
1245 /*
1246 * When PMRWBM bit 1 is set then read from
1247 * from PMRSTS should ensure prior writes
1248 * made it to persistent media
1249 */
1250 if (addr == 0xE08 &&
1251 (NVME_PMRCAP_PMRWBM(n->bar.pmrcap) & 0x02)) {
1252 memory_region_msync(&n->pmrdev->mr, 0, n->pmrdev->size);
1253 }
1254 memcpy(&val, ptr + addr, size);
1255 } else {
1256 NVME_GUEST_ERR(pci_nvme_ub_mmiord_invalid_ofs,
1257 "MMIO read beyond last register,"
1258 " offset=0x%"PRIx64", returning 0", addr);
1259 }
1260
1261 return val;
1262 }
1263
1264 static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val)
1265 {
1266 uint32_t qid;
1267
1268 if (unlikely(addr & ((1 << 2) - 1))) {
1269 NVME_GUEST_ERR(pci_nvme_ub_db_wr_misaligned,
1270 "doorbell write not 32-bit aligned,"
1271 " offset=0x%"PRIx64", ignoring", addr);
1272 return;
1273 }
1274
1275 if (((addr - 0x1000) >> 2) & 1) {
1276 /* Completion queue doorbell write */
1277
1278 uint16_t new_head = val & 0xffff;
1279 int start_sqs;
1280 NvmeCQueue *cq;
1281
1282 qid = (addr - (0x1000 + (1 << 2))) >> 3;
1283 if (unlikely(nvme_check_cqid(n, qid))) {
1284 NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_cq,
1285 "completion queue doorbell write"
1286 " for nonexistent queue,"
1287 " sqid=%"PRIu32", ignoring", qid);
1288 return;
1289 }
1290
1291 cq = n->cq[qid];
1292 if (unlikely(new_head >= cq->size)) {
1293 NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_cqhead,
1294 "completion queue doorbell write value"
1295 " beyond queue size, sqid=%"PRIu32","
1296 " new_head=%"PRIu16", ignoring",
1297 qid, new_head);
1298 return;
1299 }
1300
1301 trace_pci_nvme_mmio_doorbell_cq(cq->cqid, new_head);
1302
1303 start_sqs = nvme_cq_full(cq) ? 1 : 0;
1304 cq->head = new_head;
1305 if (start_sqs) {
1306 NvmeSQueue *sq;
1307 QTAILQ_FOREACH(sq, &cq->sq_list, entry) {
1308 timer_mod(sq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
1309 }
1310 timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
1311 }
1312
1313 if (cq->tail == cq->head) {
1314 nvme_irq_deassert(n, cq);
1315 }
1316 } else {
1317 /* Submission queue doorbell write */
1318
1319 uint16_t new_tail = val & 0xffff;
1320 NvmeSQueue *sq;
1321
1322 qid = (addr - 0x1000) >> 3;
1323 if (unlikely(nvme_check_sqid(n, qid))) {
1324 NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_sq,
1325 "submission queue doorbell write"
1326 " for nonexistent queue,"
1327 " sqid=%"PRIu32", ignoring", qid);
1328 return;
1329 }
1330
1331 sq = n->sq[qid];
1332 if (unlikely(new_tail >= sq->size)) {
1333 NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_sqtail,
1334 "submission queue doorbell write value"
1335 " beyond queue size, sqid=%"PRIu32","
1336 " new_tail=%"PRIu16", ignoring",
1337 qid, new_tail);
1338 return;
1339 }
1340
1341 trace_pci_nvme_mmio_doorbell_sq(sq->sqid, new_tail);
1342
1343 sq->tail = new_tail;
1344 timer_mod(sq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
1345 }
1346 }
1347
1348 static void nvme_mmio_write(void *opaque, hwaddr addr, uint64_t data,
1349 unsigned size)
1350 {
1351 NvmeCtrl *n = (NvmeCtrl *)opaque;
1352
1353 trace_pci_nvme_mmio_write(addr, data);
1354
1355 if (addr < sizeof(n->bar)) {
1356 nvme_write_bar(n, addr, data, size);
1357 } else {
1358 nvme_process_db(n, addr, data);
1359 }
1360 }
1361
1362 static const MemoryRegionOps nvme_mmio_ops = {
1363 .read = nvme_mmio_read,
1364 .write = nvme_mmio_write,
1365 .endianness = DEVICE_LITTLE_ENDIAN,
1366 .impl = {
1367 .min_access_size = 2,
1368 .max_access_size = 8,
1369 },
1370 };
1371
1372 static void nvme_cmb_write(void *opaque, hwaddr addr, uint64_t data,
1373 unsigned size)
1374 {
1375 NvmeCtrl *n = (NvmeCtrl *)opaque;
1376 stn_le_p(&n->cmbuf[addr], size, data);
1377 }
1378
1379 static uint64_t nvme_cmb_read(void *opaque, hwaddr addr, unsigned size)
1380 {
1381 NvmeCtrl *n = (NvmeCtrl *)opaque;
1382 return ldn_le_p(&n->cmbuf[addr], size);
1383 }
1384
1385 static const MemoryRegionOps nvme_cmb_ops = {
1386 .read = nvme_cmb_read,
1387 .write = nvme_cmb_write,
1388 .endianness = DEVICE_LITTLE_ENDIAN,
1389 .impl = {
1390 .min_access_size = 1,
1391 .max_access_size = 8,
1392 },
1393 };
1394
1395 static void nvme_check_constraints(NvmeCtrl *n, Error **errp)
1396 {
1397 NvmeParams *params = &n->params;
1398
1399 if (params->num_queues) {
1400 warn_report("num_queues is deprecated; please use max_ioqpairs "
1401 "instead");
1402
1403 params->max_ioqpairs = params->num_queues - 1;
1404 }
1405
1406 if (params->max_ioqpairs < 1 ||
1407 params->max_ioqpairs > NVME_MAX_IOQPAIRS) {
1408 error_setg(errp, "max_ioqpairs must be between 1 and %d",
1409 NVME_MAX_IOQPAIRS);
1410 return;
1411 }
1412
1413 if (params->msix_qsize < 1 ||
1414 params->msix_qsize > PCI_MSIX_FLAGS_QSIZE + 1) {
1415 error_setg(errp, "msix_qsize must be between 1 and %d",
1416 PCI_MSIX_FLAGS_QSIZE + 1);
1417 return;
1418 }
1419
1420 if (!n->conf.blk) {
1421 error_setg(errp, "drive property not set");
1422 return;
1423 }
1424
1425 if (!params->serial) {
1426 error_setg(errp, "serial property not set");
1427 return;
1428 }
1429
1430 if (!n->params.cmb_size_mb && n->pmrdev) {
1431 if (host_memory_backend_is_mapped(n->pmrdev)) {
1432 error_setg(errp, "can't use already busy memdev: %s",
1433 object_get_canonical_path_component(OBJECT(n->pmrdev)));
1434 return;
1435 }
1436
1437 if (!is_power_of_2(n->pmrdev->size)) {
1438 error_setg(errp, "pmr backend size needs to be power of 2 in size");
1439 return;
1440 }
1441
1442 host_memory_backend_set_mapped(n->pmrdev, true);
1443 }
1444 }
1445
1446 static void nvme_init_state(NvmeCtrl *n)
1447 {
1448 n->num_namespaces = 1;
1449 /* add one to max_ioqpairs to account for the admin queue pair */
1450 n->reg_size = pow2ceil(sizeof(NvmeBar) +
1451 2 * (n->params.max_ioqpairs + 1) * NVME_DB_SIZE);
1452 n->namespaces = g_new0(NvmeNamespace, n->num_namespaces);
1453 n->sq = g_new0(NvmeSQueue *, n->params.max_ioqpairs + 1);
1454 n->cq = g_new0(NvmeCQueue *, n->params.max_ioqpairs + 1);
1455 }
1456
1457 static void nvme_init_blk(NvmeCtrl *n, Error **errp)
1458 {
1459 if (!blkconf_blocksizes(&n->conf, errp)) {
1460 return;
1461 }
1462 blkconf_apply_backend_options(&n->conf, blk_is_read_only(n->conf.blk),
1463 false, errp);
1464 }
1465
1466 static void nvme_init_namespace(NvmeCtrl *n, NvmeNamespace *ns, Error **errp)
1467 {
1468 int64_t bs_size;
1469 NvmeIdNs *id_ns = &ns->id_ns;
1470
1471 bs_size = blk_getlength(n->conf.blk);
1472 if (bs_size < 0) {
1473 error_setg_errno(errp, -bs_size, "could not get backing file size");
1474 return;
1475 }
1476
1477 n->ns_size = bs_size;
1478
1479 id_ns->lbaf[0].ds = BDRV_SECTOR_BITS;
1480 id_ns->nsze = cpu_to_le64(nvme_ns_nlbas(n, ns));
1481
1482 /* no thin provisioning */
1483 id_ns->ncap = id_ns->nsze;
1484 id_ns->nuse = id_ns->ncap;
1485 }
1486
1487 static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev)
1488 {
1489 NVME_CMBLOC_SET_BIR(n->bar.cmbloc, NVME_CMB_BIR);
1490 NVME_CMBLOC_SET_OFST(n->bar.cmbloc, 0);
1491
1492 NVME_CMBSZ_SET_SQS(n->bar.cmbsz, 1);
1493 NVME_CMBSZ_SET_CQS(n->bar.cmbsz, 0);
1494 NVME_CMBSZ_SET_LISTS(n->bar.cmbsz, 0);
1495 NVME_CMBSZ_SET_RDS(n->bar.cmbsz, 1);
1496 NVME_CMBSZ_SET_WDS(n->bar.cmbsz, 1);
1497 NVME_CMBSZ_SET_SZU(n->bar.cmbsz, 2); /* MBs */
1498 NVME_CMBSZ_SET_SZ(n->bar.cmbsz, n->params.cmb_size_mb);
1499
1500 n->cmbuf = g_malloc0(NVME_CMBSZ_GETSIZE(n->bar.cmbsz));
1501 memory_region_init_io(&n->ctrl_mem, OBJECT(n), &nvme_cmb_ops, n,
1502 "nvme-cmb", NVME_CMBSZ_GETSIZE(n->bar.cmbsz));
1503 pci_register_bar(pci_dev, NVME_CMBLOC_BIR(n->bar.cmbloc),
1504 PCI_BASE_ADDRESS_SPACE_MEMORY |
1505 PCI_BASE_ADDRESS_MEM_TYPE_64 |
1506 PCI_BASE_ADDRESS_MEM_PREFETCH, &n->ctrl_mem);
1507 }
1508
1509 static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev)
1510 {
1511 /* Controller Capabilities register */
1512 NVME_CAP_SET_PMRS(n->bar.cap, 1);
1513
1514 /* PMR Capabities register */
1515 n->bar.pmrcap = 0;
1516 NVME_PMRCAP_SET_RDS(n->bar.pmrcap, 0);
1517 NVME_PMRCAP_SET_WDS(n->bar.pmrcap, 0);
1518 NVME_PMRCAP_SET_BIR(n->bar.pmrcap, NVME_PMR_BIR);
1519 NVME_PMRCAP_SET_PMRTU(n->bar.pmrcap, 0);
1520 /* Turn on bit 1 support */
1521 NVME_PMRCAP_SET_PMRWBM(n->bar.pmrcap, 0x02);
1522 NVME_PMRCAP_SET_PMRTO(n->bar.pmrcap, 0);
1523 NVME_PMRCAP_SET_CMSS(n->bar.pmrcap, 0);
1524
1525 /* PMR Control register */
1526 n->bar.pmrctl = 0;
1527 NVME_PMRCTL_SET_EN(n->bar.pmrctl, 0);
1528
1529 /* PMR Status register */
1530 n->bar.pmrsts = 0;
1531 NVME_PMRSTS_SET_ERR(n->bar.pmrsts, 0);
1532 NVME_PMRSTS_SET_NRDY(n->bar.pmrsts, 0);
1533 NVME_PMRSTS_SET_HSTS(n->bar.pmrsts, 0);
1534 NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 0);
1535
1536 /* PMR Elasticity Buffer Size register */
1537 n->bar.pmrebs = 0;
1538 NVME_PMREBS_SET_PMRSZU(n->bar.pmrebs, 0);
1539 NVME_PMREBS_SET_RBB(n->bar.pmrebs, 0);
1540 NVME_PMREBS_SET_PMRWBZ(n->bar.pmrebs, 0);
1541
1542 /* PMR Sustained Write Throughput register */
1543 n->bar.pmrswtp = 0;
1544 NVME_PMRSWTP_SET_PMRSWTU(n->bar.pmrswtp, 0);
1545 NVME_PMRSWTP_SET_PMRSWTV(n->bar.pmrswtp, 0);
1546
1547 /* PMR Memory Space Control register */
1548 n->bar.pmrmsc = 0;
1549 NVME_PMRMSC_SET_CMSE(n->bar.pmrmsc, 0);
1550 NVME_PMRMSC_SET_CBA(n->bar.pmrmsc, 0);
1551
1552 pci_register_bar(pci_dev, NVME_PMRCAP_BIR(n->bar.pmrcap),
1553 PCI_BASE_ADDRESS_SPACE_MEMORY |
1554 PCI_BASE_ADDRESS_MEM_TYPE_64 |
1555 PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmrdev->mr);
1556 }
1557
1558 static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
1559 {
1560 uint8_t *pci_conf = pci_dev->config;
1561
1562 pci_conf[PCI_INTERRUPT_PIN] = 1;
1563 pci_config_set_prog_interface(pci_conf, 0x2);
1564 pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_EXPRESS);
1565 pcie_endpoint_cap_init(pci_dev, 0x80);
1566
1567 memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme",
1568 n->reg_size);
1569 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY |
1570 PCI_BASE_ADDRESS_MEM_TYPE_64, &n->iomem);
1571 if (msix_init_exclusive_bar(pci_dev, n->params.msix_qsize, 4, errp)) {
1572 return;
1573 }
1574
1575 if (n->params.cmb_size_mb) {
1576 nvme_init_cmb(n, pci_dev);
1577 } else if (n->pmrdev) {
1578 nvme_init_pmr(n, pci_dev);
1579 }
1580 }
1581
1582 static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
1583 {
1584 NvmeIdCtrl *id = &n->id_ctrl;
1585 uint8_t *pci_conf = pci_dev->config;
1586
1587 id->vid = cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID));
1588 id->ssvid = cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID));
1589 strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' ');
1590 strpadcpy((char *)id->fr, sizeof(id->fr), "1.0", ' ');
1591 strpadcpy((char *)id->sn, sizeof(id->sn), n->params.serial, ' ');
1592 id->rab = 6;
1593 id->ieee[0] = 0x00;
1594 id->ieee[1] = 0x02;
1595 id->ieee[2] = 0xb3;
1596 id->oacs = cpu_to_le16(0);
1597 id->frmw = 7 << 1;
1598 id->lpa = 1 << 0;
1599 id->sqes = (0x6 << 4) | 0x6;
1600 id->cqes = (0x4 << 4) | 0x4;
1601 id->nn = cpu_to_le32(n->num_namespaces);
1602 id->oncs = cpu_to_le16(NVME_ONCS_WRITE_ZEROS | NVME_ONCS_TIMESTAMP);
1603 id->psd[0].mp = cpu_to_le16(0x9c4);
1604 id->psd[0].enlat = cpu_to_le32(0x10);
1605 id->psd[0].exlat = cpu_to_le32(0x4);
1606 if (blk_enable_write_cache(n->conf.blk)) {
1607 id->vwc = 1;
1608 }
1609
1610 n->bar.cap = 0;
1611 NVME_CAP_SET_MQES(n->bar.cap, 0x7ff);
1612 NVME_CAP_SET_CQR(n->bar.cap, 1);
1613 NVME_CAP_SET_TO(n->bar.cap, 0xf);
1614 NVME_CAP_SET_CSS(n->bar.cap, 1);
1615 NVME_CAP_SET_MPSMAX(n->bar.cap, 4);
1616
1617 n->bar.vs = 0x00010200;
1618 n->bar.intmc = n->bar.intms = 0;
1619 }
1620
1621 static void nvme_realize(PCIDevice *pci_dev, Error **errp)
1622 {
1623 NvmeCtrl *n = NVME(pci_dev);
1624 Error *local_err = NULL;
1625
1626 int i;
1627
1628 nvme_check_constraints(n, &local_err);
1629 if (local_err) {
1630 error_propagate(errp, local_err);
1631 return;
1632 }
1633
1634 nvme_init_state(n);
1635 nvme_init_blk(n, &local_err);
1636 if (local_err) {
1637 error_propagate(errp, local_err);
1638 return;
1639 }
1640
1641 nvme_init_pci(n, pci_dev, &local_err);
1642 if (local_err) {
1643 error_propagate(errp, local_err);
1644 return;
1645 }
1646
1647 nvme_init_ctrl(n, pci_dev);
1648
1649 for (i = 0; i < n->num_namespaces; i++) {
1650 nvme_init_namespace(n, &n->namespaces[i], &local_err);
1651 if (local_err) {
1652 error_propagate(errp, local_err);
1653 return;
1654 }
1655 }
1656 }
1657
1658 static void nvme_exit(PCIDevice *pci_dev)
1659 {
1660 NvmeCtrl *n = NVME(pci_dev);
1661
1662 nvme_clear_ctrl(n);
1663 g_free(n->namespaces);
1664 g_free(n->cq);
1665 g_free(n->sq);
1666
1667 if (n->params.cmb_size_mb) {
1668 g_free(n->cmbuf);
1669 }
1670
1671 if (n->pmrdev) {
1672 host_memory_backend_set_mapped(n->pmrdev, false);
1673 }
1674 msix_uninit_exclusive_bar(pci_dev);
1675 }
1676
1677 static Property nvme_props[] = {
1678 DEFINE_BLOCK_PROPERTIES(NvmeCtrl, conf),
1679 DEFINE_PROP_LINK("pmrdev", NvmeCtrl, pmrdev, TYPE_MEMORY_BACKEND,
1680 HostMemoryBackend *),
1681 DEFINE_PROP_STRING("serial", NvmeCtrl, params.serial),
1682 DEFINE_PROP_UINT32("cmb_size_mb", NvmeCtrl, params.cmb_size_mb, 0),
1683 DEFINE_PROP_UINT32("num_queues", NvmeCtrl, params.num_queues, 0),
1684 DEFINE_PROP_UINT32("max_ioqpairs", NvmeCtrl, params.max_ioqpairs, 64),
1685 DEFINE_PROP_UINT16("msix_qsize", NvmeCtrl, params.msix_qsize, 65),
1686 DEFINE_PROP_END_OF_LIST(),
1687 };
1688
1689 static const VMStateDescription nvme_vmstate = {
1690 .name = "nvme",
1691 .unmigratable = 1,
1692 };
1693
1694 static void nvme_class_init(ObjectClass *oc, void *data)
1695 {
1696 DeviceClass *dc = DEVICE_CLASS(oc);
1697 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
1698
1699 pc->realize = nvme_realize;
1700 pc->exit = nvme_exit;
1701 pc->class_id = PCI_CLASS_STORAGE_EXPRESS;
1702 pc->vendor_id = PCI_VENDOR_ID_INTEL;
1703 pc->device_id = 0x5845;
1704 pc->revision = 2;
1705
1706 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1707 dc->desc = "Non-Volatile Memory Express";
1708 device_class_set_props(dc, nvme_props);
1709 dc->vmsd = &nvme_vmstate;
1710 }
1711
1712 static void nvme_instance_init(Object *obj)
1713 {
1714 NvmeCtrl *s = NVME(obj);
1715
1716 device_add_bootindex_property(obj, &s->conf.bootindex,
1717 "bootindex", "/namespace@1,0",
1718 DEVICE(obj));
1719 }
1720
1721 static const TypeInfo nvme_info = {
1722 .name = TYPE_NVME,
1723 .parent = TYPE_PCI_DEVICE,
1724 .instance_size = sizeof(NvmeCtrl),
1725 .class_init = nvme_class_init,
1726 .instance_init = nvme_instance_init,
1727 .interfaces = (InterfaceInfo[]) {
1728 { INTERFACE_PCIE_DEVICE },
1729 { }
1730 },
1731 };
1732
1733 static void nvme_register_types(void)
1734 {
1735 type_register_static(&nvme_info);
1736 }
1737
1738 type_init(nvme_register_types)