hw/block/nvme: Align I/O BAR to 4 KiB
[qemu.git] / hw / block / nvme.c
1 /*
2 * QEMU NVM Express Controller
3 *
4 * Copyright (c) 2012, Intel Corporation
5 *
6 * Written by Keith Busch <keith.busch@intel.com>
7 *
8 * This code is licensed under the GNU GPL v2 or later.
9 */
10
11 /**
12 * Reference Specs: http://www.nvmexpress.org, 1.2, 1.1, 1.0e
13 *
14 * https://nvmexpress.org/developers/nvme-specification/
15 */
16
17 /**
18 * Usage: add options:
19 * -drive file=<file>,if=none,id=<drive_id>
20 * -device nvme,drive=<drive_id>,serial=<serial>,id=<id[optional]>, \
21 * cmb_size_mb=<cmb_size_mb[optional]>, \
22 * [pmrdev=<mem_backend_file_id>,] \
23 * max_ioqpairs=<N[optional]>
24 *
25 * Note cmb_size_mb denotes size of CMB in MB. CMB is assumed to be at
26 * offset 0 in BAR2 and supports only WDS, RDS and SQS for now.
27 *
28 * cmb_size_mb= and pmrdev= options are mutually exclusive due to limitation
29 * in available BAR's. cmb_size_mb= will take precedence over pmrdev= when
30 * both provided.
31 * Enabling pmr emulation can be achieved by pointing to memory-backend-file.
32 * For example:
33 * -object memory-backend-file,id=<mem_id>,share=on,mem-path=<file_path>, \
34 * size=<size> .... -device nvme,...,pmrdev=<mem_id>
35 */
36
37 #include "qemu/osdep.h"
38 #include "qemu/units.h"
39 #include "qemu/error-report.h"
40 #include "hw/block/block.h"
41 #include "hw/pci/msix.h"
42 #include "hw/pci/pci.h"
43 #include "hw/qdev-properties.h"
44 #include "migration/vmstate.h"
45 #include "sysemu/sysemu.h"
46 #include "qapi/error.h"
47 #include "qapi/visitor.h"
48 #include "sysemu/hostmem.h"
49 #include "sysemu/block-backend.h"
50 #include "exec/memory.h"
51 #include "qemu/log.h"
52 #include "qemu/module.h"
53 #include "qemu/cutils.h"
54 #include "trace.h"
55 #include "nvme.h"
56
57 #define NVME_MAX_IOQPAIRS 0xffff
58 #define NVME_DB_SIZE 4
59 #define NVME_CMB_BIR 2
60 #define NVME_PMR_BIR 2
61
62 #define NVME_GUEST_ERR(trace, fmt, ...) \
63 do { \
64 (trace_##trace)(__VA_ARGS__); \
65 qemu_log_mask(LOG_GUEST_ERROR, #trace \
66 " in %s: " fmt "\n", __func__, ## __VA_ARGS__); \
67 } while (0)
68
69 static void nvme_process_sq(void *opaque);
70
71 static bool nvme_addr_is_cmb(NvmeCtrl *n, hwaddr addr)
72 {
73 hwaddr low = n->ctrl_mem.addr;
74 hwaddr hi = n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size);
75
76 return addr >= low && addr < hi;
77 }
78
79 static void nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size)
80 {
81 if (n->bar.cmbsz && nvme_addr_is_cmb(n, addr)) {
82 memcpy(buf, (void *)&n->cmbuf[addr - n->ctrl_mem.addr], size);
83 return;
84 }
85
86 pci_dma_read(&n->parent_obj, addr, buf, size);
87 }
88
89 static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid)
90 {
91 return sqid < n->params.max_ioqpairs + 1 && n->sq[sqid] != NULL ? 0 : -1;
92 }
93
94 static int nvme_check_cqid(NvmeCtrl *n, uint16_t cqid)
95 {
96 return cqid < n->params.max_ioqpairs + 1 && n->cq[cqid] != NULL ? 0 : -1;
97 }
98
99 static void nvme_inc_cq_tail(NvmeCQueue *cq)
100 {
101 cq->tail++;
102 if (cq->tail >= cq->size) {
103 cq->tail = 0;
104 cq->phase = !cq->phase;
105 }
106 }
107
108 static void nvme_inc_sq_head(NvmeSQueue *sq)
109 {
110 sq->head = (sq->head + 1) % sq->size;
111 }
112
113 static uint8_t nvme_cq_full(NvmeCQueue *cq)
114 {
115 return (cq->tail + 1) % cq->size == cq->head;
116 }
117
118 static uint8_t nvme_sq_empty(NvmeSQueue *sq)
119 {
120 return sq->head == sq->tail;
121 }
122
123 static void nvme_irq_check(NvmeCtrl *n)
124 {
125 if (msix_enabled(&(n->parent_obj))) {
126 return;
127 }
128 if (~n->bar.intms & n->irq_status) {
129 pci_irq_assert(&n->parent_obj);
130 } else {
131 pci_irq_deassert(&n->parent_obj);
132 }
133 }
134
135 static void nvme_irq_assert(NvmeCtrl *n, NvmeCQueue *cq)
136 {
137 if (cq->irq_enabled) {
138 if (msix_enabled(&(n->parent_obj))) {
139 trace_pci_nvme_irq_msix(cq->vector);
140 msix_notify(&(n->parent_obj), cq->vector);
141 } else {
142 trace_pci_nvme_irq_pin();
143 assert(cq->vector < 32);
144 n->irq_status |= 1 << cq->vector;
145 nvme_irq_check(n);
146 }
147 } else {
148 trace_pci_nvme_irq_masked();
149 }
150 }
151
152 static void nvme_irq_deassert(NvmeCtrl *n, NvmeCQueue *cq)
153 {
154 if (cq->irq_enabled) {
155 if (msix_enabled(&(n->parent_obj))) {
156 return;
157 } else {
158 assert(cq->vector < 32);
159 n->irq_status &= ~(1 << cq->vector);
160 nvme_irq_check(n);
161 }
162 }
163 }
164
165 static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVector *iov, uint64_t prp1,
166 uint64_t prp2, uint32_t len, NvmeCtrl *n)
167 {
168 hwaddr trans_len = n->page_size - (prp1 % n->page_size);
169 trans_len = MIN(len, trans_len);
170 int num_prps = (len >> n->page_bits) + 1;
171
172 if (unlikely(!prp1)) {
173 trace_pci_nvme_err_invalid_prp();
174 return NVME_INVALID_FIELD | NVME_DNR;
175 } else if (n->bar.cmbsz && prp1 >= n->ctrl_mem.addr &&
176 prp1 < n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size)) {
177 qsg->nsg = 0;
178 qemu_iovec_init(iov, num_prps);
179 qemu_iovec_add(iov, (void *)&n->cmbuf[prp1 - n->ctrl_mem.addr], trans_len);
180 } else {
181 pci_dma_sglist_init(qsg, &n->parent_obj, num_prps);
182 qemu_sglist_add(qsg, prp1, trans_len);
183 }
184 len -= trans_len;
185 if (len) {
186 if (unlikely(!prp2)) {
187 trace_pci_nvme_err_invalid_prp2_missing();
188 goto unmap;
189 }
190 if (len > n->page_size) {
191 uint64_t prp_list[n->max_prp_ents];
192 uint32_t nents, prp_trans;
193 int i = 0;
194
195 nents = (len + n->page_size - 1) >> n->page_bits;
196 prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
197 nvme_addr_read(n, prp2, (void *)prp_list, prp_trans);
198 while (len != 0) {
199 uint64_t prp_ent = le64_to_cpu(prp_list[i]);
200
201 if (i == n->max_prp_ents - 1 && len > n->page_size) {
202 if (unlikely(!prp_ent || prp_ent & (n->page_size - 1))) {
203 trace_pci_nvme_err_invalid_prplist_ent(prp_ent);
204 goto unmap;
205 }
206
207 i = 0;
208 nents = (len + n->page_size - 1) >> n->page_bits;
209 prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
210 nvme_addr_read(n, prp_ent, (void *)prp_list,
211 prp_trans);
212 prp_ent = le64_to_cpu(prp_list[i]);
213 }
214
215 if (unlikely(!prp_ent || prp_ent & (n->page_size - 1))) {
216 trace_pci_nvme_err_invalid_prplist_ent(prp_ent);
217 goto unmap;
218 }
219
220 trans_len = MIN(len, n->page_size);
221 if (qsg->nsg){
222 qemu_sglist_add(qsg, prp_ent, trans_len);
223 } else {
224 qemu_iovec_add(iov, (void *)&n->cmbuf[prp_ent - n->ctrl_mem.addr], trans_len);
225 }
226 len -= trans_len;
227 i++;
228 }
229 } else {
230 if (unlikely(prp2 & (n->page_size - 1))) {
231 trace_pci_nvme_err_invalid_prp2_align(prp2);
232 goto unmap;
233 }
234 if (qsg->nsg) {
235 qemu_sglist_add(qsg, prp2, len);
236 } else {
237 qemu_iovec_add(iov, (void *)&n->cmbuf[prp2 - n->ctrl_mem.addr], trans_len);
238 }
239 }
240 }
241 return NVME_SUCCESS;
242
243 unmap:
244 qemu_sglist_destroy(qsg);
245 return NVME_INVALID_FIELD | NVME_DNR;
246 }
247
248 static uint16_t nvme_dma_write_prp(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
249 uint64_t prp1, uint64_t prp2)
250 {
251 QEMUSGList qsg;
252 QEMUIOVector iov;
253 uint16_t status = NVME_SUCCESS;
254
255 if (nvme_map_prp(&qsg, &iov, prp1, prp2, len, n)) {
256 return NVME_INVALID_FIELD | NVME_DNR;
257 }
258 if (qsg.nsg > 0) {
259 if (dma_buf_write(ptr, len, &qsg)) {
260 status = NVME_INVALID_FIELD | NVME_DNR;
261 }
262 qemu_sglist_destroy(&qsg);
263 } else {
264 if (qemu_iovec_to_buf(&iov, 0, ptr, len) != len) {
265 status = NVME_INVALID_FIELD | NVME_DNR;
266 }
267 qemu_iovec_destroy(&iov);
268 }
269 return status;
270 }
271
272 static uint16_t nvme_dma_read_prp(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
273 uint64_t prp1, uint64_t prp2)
274 {
275 QEMUSGList qsg;
276 QEMUIOVector iov;
277 uint16_t status = NVME_SUCCESS;
278
279 trace_pci_nvme_dma_read(prp1, prp2);
280
281 if (nvme_map_prp(&qsg, &iov, prp1, prp2, len, n)) {
282 return NVME_INVALID_FIELD | NVME_DNR;
283 }
284 if (qsg.nsg > 0) {
285 if (unlikely(dma_buf_read(ptr, len, &qsg))) {
286 trace_pci_nvme_err_invalid_dma();
287 status = NVME_INVALID_FIELD | NVME_DNR;
288 }
289 qemu_sglist_destroy(&qsg);
290 } else {
291 if (unlikely(qemu_iovec_from_buf(&iov, 0, ptr, len) != len)) {
292 trace_pci_nvme_err_invalid_dma();
293 status = NVME_INVALID_FIELD | NVME_DNR;
294 }
295 qemu_iovec_destroy(&iov);
296 }
297 return status;
298 }
299
300 static void nvme_post_cqes(void *opaque)
301 {
302 NvmeCQueue *cq = opaque;
303 NvmeCtrl *n = cq->ctrl;
304 NvmeRequest *req, *next;
305
306 QTAILQ_FOREACH_SAFE(req, &cq->req_list, entry, next) {
307 NvmeSQueue *sq;
308 hwaddr addr;
309
310 if (nvme_cq_full(cq)) {
311 break;
312 }
313
314 QTAILQ_REMOVE(&cq->req_list, req, entry);
315 sq = req->sq;
316 req->cqe.status = cpu_to_le16((req->status << 1) | cq->phase);
317 req->cqe.sq_id = cpu_to_le16(sq->sqid);
318 req->cqe.sq_head = cpu_to_le16(sq->head);
319 addr = cq->dma_addr + cq->tail * n->cqe_size;
320 nvme_inc_cq_tail(cq);
321 pci_dma_write(&n->parent_obj, addr, (void *)&req->cqe,
322 sizeof(req->cqe));
323 QTAILQ_INSERT_TAIL(&sq->req_list, req, entry);
324 }
325 if (cq->tail != cq->head) {
326 nvme_irq_assert(n, cq);
327 }
328 }
329
330 static void nvme_enqueue_req_completion(NvmeCQueue *cq, NvmeRequest *req)
331 {
332 assert(cq->cqid == req->sq->cqid);
333 QTAILQ_REMOVE(&req->sq->out_req_list, req, entry);
334 QTAILQ_INSERT_TAIL(&cq->req_list, req, entry);
335 timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
336 }
337
338 static void nvme_rw_cb(void *opaque, int ret)
339 {
340 NvmeRequest *req = opaque;
341 NvmeSQueue *sq = req->sq;
342 NvmeCtrl *n = sq->ctrl;
343 NvmeCQueue *cq = n->cq[sq->cqid];
344
345 if (!ret) {
346 block_acct_done(blk_get_stats(n->conf.blk), &req->acct);
347 req->status = NVME_SUCCESS;
348 } else {
349 block_acct_failed(blk_get_stats(n->conf.blk), &req->acct);
350 req->status = NVME_INTERNAL_DEV_ERROR;
351 }
352 if (req->has_sg) {
353 qemu_sglist_destroy(&req->qsg);
354 }
355 nvme_enqueue_req_completion(cq, req);
356 }
357
358 static uint16_t nvme_flush(NvmeCtrl *n, NvmeNamespace *ns, NvmeCmd *cmd,
359 NvmeRequest *req)
360 {
361 req->has_sg = false;
362 block_acct_start(blk_get_stats(n->conf.blk), &req->acct, 0,
363 BLOCK_ACCT_FLUSH);
364 req->aiocb = blk_aio_flush(n->conf.blk, nvme_rw_cb, req);
365
366 return NVME_NO_COMPLETE;
367 }
368
369 static uint16_t nvme_write_zeros(NvmeCtrl *n, NvmeNamespace *ns, NvmeCmd *cmd,
370 NvmeRequest *req)
371 {
372 NvmeRwCmd *rw = (NvmeRwCmd *)cmd;
373 const uint8_t lba_index = NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas);
374 const uint8_t data_shift = ns->id_ns.lbaf[lba_index].ds;
375 uint64_t slba = le64_to_cpu(rw->slba);
376 uint32_t nlb = le16_to_cpu(rw->nlb) + 1;
377 uint64_t offset = slba << data_shift;
378 uint32_t count = nlb << data_shift;
379
380 if (unlikely(slba + nlb > ns->id_ns.nsze)) {
381 trace_pci_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze);
382 return NVME_LBA_RANGE | NVME_DNR;
383 }
384
385 req->has_sg = false;
386 block_acct_start(blk_get_stats(n->conf.blk), &req->acct, 0,
387 BLOCK_ACCT_WRITE);
388 req->aiocb = blk_aio_pwrite_zeroes(n->conf.blk, offset, count,
389 BDRV_REQ_MAY_UNMAP, nvme_rw_cb, req);
390 return NVME_NO_COMPLETE;
391 }
392
393 static uint16_t nvme_rw(NvmeCtrl *n, NvmeNamespace *ns, NvmeCmd *cmd,
394 NvmeRequest *req)
395 {
396 NvmeRwCmd *rw = (NvmeRwCmd *)cmd;
397 uint32_t nlb = le32_to_cpu(rw->nlb) + 1;
398 uint64_t slba = le64_to_cpu(rw->slba);
399 uint64_t prp1 = le64_to_cpu(rw->prp1);
400 uint64_t prp2 = le64_to_cpu(rw->prp2);
401
402 uint8_t lba_index = NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas);
403 uint8_t data_shift = ns->id_ns.lbaf[lba_index].ds;
404 uint64_t data_size = (uint64_t)nlb << data_shift;
405 uint64_t data_offset = slba << data_shift;
406 int is_write = rw->opcode == NVME_CMD_WRITE ? 1 : 0;
407 enum BlockAcctType acct = is_write ? BLOCK_ACCT_WRITE : BLOCK_ACCT_READ;
408
409 trace_pci_nvme_rw(is_write ? "write" : "read", nlb, data_size, slba);
410
411 if (unlikely((slba + nlb) > ns->id_ns.nsze)) {
412 block_acct_invalid(blk_get_stats(n->conf.blk), acct);
413 trace_pci_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze);
414 return NVME_LBA_RANGE | NVME_DNR;
415 }
416
417 if (nvme_map_prp(&req->qsg, &req->iov, prp1, prp2, data_size, n)) {
418 block_acct_invalid(blk_get_stats(n->conf.blk), acct);
419 return NVME_INVALID_FIELD | NVME_DNR;
420 }
421
422 dma_acct_start(n->conf.blk, &req->acct, &req->qsg, acct);
423 if (req->qsg.nsg > 0) {
424 req->has_sg = true;
425 req->aiocb = is_write ?
426 dma_blk_write(n->conf.blk, &req->qsg, data_offset, BDRV_SECTOR_SIZE,
427 nvme_rw_cb, req) :
428 dma_blk_read(n->conf.blk, &req->qsg, data_offset, BDRV_SECTOR_SIZE,
429 nvme_rw_cb, req);
430 } else {
431 req->has_sg = false;
432 req->aiocb = is_write ?
433 blk_aio_pwritev(n->conf.blk, data_offset, &req->iov, 0, nvme_rw_cb,
434 req) :
435 blk_aio_preadv(n->conf.blk, data_offset, &req->iov, 0, nvme_rw_cb,
436 req);
437 }
438
439 return NVME_NO_COMPLETE;
440 }
441
442 static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
443 {
444 NvmeNamespace *ns;
445 uint32_t nsid = le32_to_cpu(cmd->nsid);
446
447 if (unlikely(nsid == 0 || nsid > n->num_namespaces)) {
448 trace_pci_nvme_err_invalid_ns(nsid, n->num_namespaces);
449 return NVME_INVALID_NSID | NVME_DNR;
450 }
451
452 ns = &n->namespaces[nsid - 1];
453 switch (cmd->opcode) {
454 case NVME_CMD_FLUSH:
455 return nvme_flush(n, ns, cmd, req);
456 case NVME_CMD_WRITE_ZEROS:
457 return nvme_write_zeros(n, ns, cmd, req);
458 case NVME_CMD_WRITE:
459 case NVME_CMD_READ:
460 return nvme_rw(n, ns, cmd, req);
461 default:
462 trace_pci_nvme_err_invalid_opc(cmd->opcode);
463 return NVME_INVALID_OPCODE | NVME_DNR;
464 }
465 }
466
467 static void nvme_free_sq(NvmeSQueue *sq, NvmeCtrl *n)
468 {
469 n->sq[sq->sqid] = NULL;
470 timer_del(sq->timer);
471 timer_free(sq->timer);
472 g_free(sq->io_req);
473 if (sq->sqid) {
474 g_free(sq);
475 }
476 }
477
478 static uint16_t nvme_del_sq(NvmeCtrl *n, NvmeCmd *cmd)
479 {
480 NvmeDeleteQ *c = (NvmeDeleteQ *)cmd;
481 NvmeRequest *req, *next;
482 NvmeSQueue *sq;
483 NvmeCQueue *cq;
484 uint16_t qid = le16_to_cpu(c->qid);
485
486 if (unlikely(!qid || nvme_check_sqid(n, qid))) {
487 trace_pci_nvme_err_invalid_del_sq(qid);
488 return NVME_INVALID_QID | NVME_DNR;
489 }
490
491 trace_pci_nvme_del_sq(qid);
492
493 sq = n->sq[qid];
494 while (!QTAILQ_EMPTY(&sq->out_req_list)) {
495 req = QTAILQ_FIRST(&sq->out_req_list);
496 assert(req->aiocb);
497 blk_aio_cancel(req->aiocb);
498 }
499 if (!nvme_check_cqid(n, sq->cqid)) {
500 cq = n->cq[sq->cqid];
501 QTAILQ_REMOVE(&cq->sq_list, sq, entry);
502
503 nvme_post_cqes(cq);
504 QTAILQ_FOREACH_SAFE(req, &cq->req_list, entry, next) {
505 if (req->sq == sq) {
506 QTAILQ_REMOVE(&cq->req_list, req, entry);
507 QTAILQ_INSERT_TAIL(&sq->req_list, req, entry);
508 }
509 }
510 }
511
512 nvme_free_sq(sq, n);
513 return NVME_SUCCESS;
514 }
515
516 static void nvme_init_sq(NvmeSQueue *sq, NvmeCtrl *n, uint64_t dma_addr,
517 uint16_t sqid, uint16_t cqid, uint16_t size)
518 {
519 int i;
520 NvmeCQueue *cq;
521
522 sq->ctrl = n;
523 sq->dma_addr = dma_addr;
524 sq->sqid = sqid;
525 sq->size = size;
526 sq->cqid = cqid;
527 sq->head = sq->tail = 0;
528 sq->io_req = g_new(NvmeRequest, sq->size);
529
530 QTAILQ_INIT(&sq->req_list);
531 QTAILQ_INIT(&sq->out_req_list);
532 for (i = 0; i < sq->size; i++) {
533 sq->io_req[i].sq = sq;
534 QTAILQ_INSERT_TAIL(&(sq->req_list), &sq->io_req[i], entry);
535 }
536 sq->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, nvme_process_sq, sq);
537
538 assert(n->cq[cqid]);
539 cq = n->cq[cqid];
540 QTAILQ_INSERT_TAIL(&(cq->sq_list), sq, entry);
541 n->sq[sqid] = sq;
542 }
543
544 static uint16_t nvme_create_sq(NvmeCtrl *n, NvmeCmd *cmd)
545 {
546 NvmeSQueue *sq;
547 NvmeCreateSq *c = (NvmeCreateSq *)cmd;
548
549 uint16_t cqid = le16_to_cpu(c->cqid);
550 uint16_t sqid = le16_to_cpu(c->sqid);
551 uint16_t qsize = le16_to_cpu(c->qsize);
552 uint16_t qflags = le16_to_cpu(c->sq_flags);
553 uint64_t prp1 = le64_to_cpu(c->prp1);
554
555 trace_pci_nvme_create_sq(prp1, sqid, cqid, qsize, qflags);
556
557 if (unlikely(!cqid || nvme_check_cqid(n, cqid))) {
558 trace_pci_nvme_err_invalid_create_sq_cqid(cqid);
559 return NVME_INVALID_CQID | NVME_DNR;
560 }
561 if (unlikely(!sqid || !nvme_check_sqid(n, sqid))) {
562 trace_pci_nvme_err_invalid_create_sq_sqid(sqid);
563 return NVME_INVALID_QID | NVME_DNR;
564 }
565 if (unlikely(!qsize || qsize > NVME_CAP_MQES(n->bar.cap))) {
566 trace_pci_nvme_err_invalid_create_sq_size(qsize);
567 return NVME_MAX_QSIZE_EXCEEDED | NVME_DNR;
568 }
569 if (unlikely(!prp1 || prp1 & (n->page_size - 1))) {
570 trace_pci_nvme_err_invalid_create_sq_addr(prp1);
571 return NVME_INVALID_FIELD | NVME_DNR;
572 }
573 if (unlikely(!(NVME_SQ_FLAGS_PC(qflags)))) {
574 trace_pci_nvme_err_invalid_create_sq_qflags(NVME_SQ_FLAGS_PC(qflags));
575 return NVME_INVALID_FIELD | NVME_DNR;
576 }
577 sq = g_malloc0(sizeof(*sq));
578 nvme_init_sq(sq, n, prp1, sqid, cqid, qsize + 1);
579 return NVME_SUCCESS;
580 }
581
582 static void nvme_free_cq(NvmeCQueue *cq, NvmeCtrl *n)
583 {
584 n->cq[cq->cqid] = NULL;
585 timer_del(cq->timer);
586 timer_free(cq->timer);
587 msix_vector_unuse(&n->parent_obj, cq->vector);
588 if (cq->cqid) {
589 g_free(cq);
590 }
591 }
592
593 static uint16_t nvme_del_cq(NvmeCtrl *n, NvmeCmd *cmd)
594 {
595 NvmeDeleteQ *c = (NvmeDeleteQ *)cmd;
596 NvmeCQueue *cq;
597 uint16_t qid = le16_to_cpu(c->qid);
598
599 if (unlikely(!qid || nvme_check_cqid(n, qid))) {
600 trace_pci_nvme_err_invalid_del_cq_cqid(qid);
601 return NVME_INVALID_CQID | NVME_DNR;
602 }
603
604 cq = n->cq[qid];
605 if (unlikely(!QTAILQ_EMPTY(&cq->sq_list))) {
606 trace_pci_nvme_err_invalid_del_cq_notempty(qid);
607 return NVME_INVALID_QUEUE_DEL;
608 }
609 nvme_irq_deassert(n, cq);
610 trace_pci_nvme_del_cq(qid);
611 nvme_free_cq(cq, n);
612 return NVME_SUCCESS;
613 }
614
615 static void nvme_init_cq(NvmeCQueue *cq, NvmeCtrl *n, uint64_t dma_addr,
616 uint16_t cqid, uint16_t vector, uint16_t size, uint16_t irq_enabled)
617 {
618 int ret;
619
620 ret = msix_vector_use(&n->parent_obj, vector);
621 assert(ret == 0);
622 cq->ctrl = n;
623 cq->cqid = cqid;
624 cq->size = size;
625 cq->dma_addr = dma_addr;
626 cq->phase = 1;
627 cq->irq_enabled = irq_enabled;
628 cq->vector = vector;
629 cq->head = cq->tail = 0;
630 QTAILQ_INIT(&cq->req_list);
631 QTAILQ_INIT(&cq->sq_list);
632 n->cq[cqid] = cq;
633 cq->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, nvme_post_cqes, cq);
634 }
635
636 static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeCmd *cmd)
637 {
638 NvmeCQueue *cq;
639 NvmeCreateCq *c = (NvmeCreateCq *)cmd;
640 uint16_t cqid = le16_to_cpu(c->cqid);
641 uint16_t vector = le16_to_cpu(c->irq_vector);
642 uint16_t qsize = le16_to_cpu(c->qsize);
643 uint16_t qflags = le16_to_cpu(c->cq_flags);
644 uint64_t prp1 = le64_to_cpu(c->prp1);
645
646 trace_pci_nvme_create_cq(prp1, cqid, vector, qsize, qflags,
647 NVME_CQ_FLAGS_IEN(qflags) != 0);
648
649 if (unlikely(!cqid || !nvme_check_cqid(n, cqid))) {
650 trace_pci_nvme_err_invalid_create_cq_cqid(cqid);
651 return NVME_INVALID_CQID | NVME_DNR;
652 }
653 if (unlikely(!qsize || qsize > NVME_CAP_MQES(n->bar.cap))) {
654 trace_pci_nvme_err_invalid_create_cq_size(qsize);
655 return NVME_MAX_QSIZE_EXCEEDED | NVME_DNR;
656 }
657 if (unlikely(!prp1)) {
658 trace_pci_nvme_err_invalid_create_cq_addr(prp1);
659 return NVME_INVALID_FIELD | NVME_DNR;
660 }
661 if (unlikely(!msix_enabled(&n->parent_obj) && vector)) {
662 trace_pci_nvme_err_invalid_create_cq_vector(vector);
663 return NVME_INVALID_IRQ_VECTOR | NVME_DNR;
664 }
665 if (unlikely(vector >= n->params.msix_qsize)) {
666 trace_pci_nvme_err_invalid_create_cq_vector(vector);
667 return NVME_INVALID_IRQ_VECTOR | NVME_DNR;
668 }
669 if (unlikely(!(NVME_CQ_FLAGS_PC(qflags)))) {
670 trace_pci_nvme_err_invalid_create_cq_qflags(NVME_CQ_FLAGS_PC(qflags));
671 return NVME_INVALID_FIELD | NVME_DNR;
672 }
673
674 cq = g_malloc0(sizeof(*cq));
675 nvme_init_cq(cq, n, prp1, cqid, vector, qsize + 1,
676 NVME_CQ_FLAGS_IEN(qflags));
677 return NVME_SUCCESS;
678 }
679
680 static uint16_t nvme_identify_ctrl(NvmeCtrl *n, NvmeIdentify *c)
681 {
682 uint64_t prp1 = le64_to_cpu(c->prp1);
683 uint64_t prp2 = le64_to_cpu(c->prp2);
684
685 trace_pci_nvme_identify_ctrl();
686
687 return nvme_dma_read_prp(n, (uint8_t *)&n->id_ctrl, sizeof(n->id_ctrl),
688 prp1, prp2);
689 }
690
691 static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeIdentify *c)
692 {
693 NvmeNamespace *ns;
694 uint32_t nsid = le32_to_cpu(c->nsid);
695 uint64_t prp1 = le64_to_cpu(c->prp1);
696 uint64_t prp2 = le64_to_cpu(c->prp2);
697
698 trace_pci_nvme_identify_ns(nsid);
699
700 if (unlikely(nsid == 0 || nsid > n->num_namespaces)) {
701 trace_pci_nvme_err_invalid_ns(nsid, n->num_namespaces);
702 return NVME_INVALID_NSID | NVME_DNR;
703 }
704
705 ns = &n->namespaces[nsid - 1];
706
707 return nvme_dma_read_prp(n, (uint8_t *)&ns->id_ns, sizeof(ns->id_ns),
708 prp1, prp2);
709 }
710
711 static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeIdentify *c)
712 {
713 static const int data_len = NVME_IDENTIFY_DATA_SIZE;
714 uint32_t min_nsid = le32_to_cpu(c->nsid);
715 uint64_t prp1 = le64_to_cpu(c->prp1);
716 uint64_t prp2 = le64_to_cpu(c->prp2);
717 uint32_t *list;
718 uint16_t ret;
719 int i, j = 0;
720
721 trace_pci_nvme_identify_nslist(min_nsid);
722
723 list = g_malloc0(data_len);
724 for (i = 0; i < n->num_namespaces; i++) {
725 if (i < min_nsid) {
726 continue;
727 }
728 list[j++] = cpu_to_le32(i + 1);
729 if (j == data_len / sizeof(uint32_t)) {
730 break;
731 }
732 }
733 ret = nvme_dma_read_prp(n, (uint8_t *)list, data_len, prp1, prp2);
734 g_free(list);
735 return ret;
736 }
737
738 static uint16_t nvme_identify(NvmeCtrl *n, NvmeCmd *cmd)
739 {
740 NvmeIdentify *c = (NvmeIdentify *)cmd;
741
742 switch (le32_to_cpu(c->cns)) {
743 case NVME_ID_CNS_NS:
744 return nvme_identify_ns(n, c);
745 case NVME_ID_CNS_CTRL:
746 return nvme_identify_ctrl(n, c);
747 case NVME_ID_CNS_NS_ACTIVE_LIST:
748 return nvme_identify_nslist(n, c);
749 default:
750 trace_pci_nvme_err_invalid_identify_cns(le32_to_cpu(c->cns));
751 return NVME_INVALID_FIELD | NVME_DNR;
752 }
753 }
754
755 static inline void nvme_set_timestamp(NvmeCtrl *n, uint64_t ts)
756 {
757 trace_pci_nvme_setfeat_timestamp(ts);
758
759 n->host_timestamp = le64_to_cpu(ts);
760 n->timestamp_set_qemu_clock_ms = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
761 }
762
763 static inline uint64_t nvme_get_timestamp(const NvmeCtrl *n)
764 {
765 uint64_t current_time = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
766 uint64_t elapsed_time = current_time - n->timestamp_set_qemu_clock_ms;
767
768 union nvme_timestamp {
769 struct {
770 uint64_t timestamp:48;
771 uint64_t sync:1;
772 uint64_t origin:3;
773 uint64_t rsvd1:12;
774 };
775 uint64_t all;
776 };
777
778 union nvme_timestamp ts;
779 ts.all = 0;
780
781 /*
782 * If the sum of the Timestamp value set by the host and the elapsed
783 * time exceeds 2^48, the value returned should be reduced modulo 2^48.
784 */
785 ts.timestamp = (n->host_timestamp + elapsed_time) & 0xffffffffffff;
786
787 /* If the host timestamp is non-zero, set the timestamp origin */
788 ts.origin = n->host_timestamp ? 0x01 : 0x00;
789
790 trace_pci_nvme_getfeat_timestamp(ts.all);
791
792 return cpu_to_le64(ts.all);
793 }
794
795 static uint16_t nvme_get_feature_timestamp(NvmeCtrl *n, NvmeCmd *cmd)
796 {
797 uint64_t prp1 = le64_to_cpu(cmd->prp1);
798 uint64_t prp2 = le64_to_cpu(cmd->prp2);
799
800 uint64_t timestamp = nvme_get_timestamp(n);
801
802 return nvme_dma_read_prp(n, (uint8_t *)&timestamp,
803 sizeof(timestamp), prp1, prp2);
804 }
805
806 static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
807 {
808 uint32_t dw10 = le32_to_cpu(cmd->cdw10);
809 uint32_t result;
810
811 switch (dw10) {
812 case NVME_VOLATILE_WRITE_CACHE:
813 result = blk_enable_write_cache(n->conf.blk);
814 trace_pci_nvme_getfeat_vwcache(result ? "enabled" : "disabled");
815 break;
816 case NVME_NUMBER_OF_QUEUES:
817 result = cpu_to_le32((n->params.max_ioqpairs - 1) |
818 ((n->params.max_ioqpairs - 1) << 16));
819 trace_pci_nvme_getfeat_numq(result);
820 break;
821 case NVME_TIMESTAMP:
822 return nvme_get_feature_timestamp(n, cmd);
823 default:
824 trace_pci_nvme_err_invalid_getfeat(dw10);
825 return NVME_INVALID_FIELD | NVME_DNR;
826 }
827
828 req->cqe.result = result;
829 return NVME_SUCCESS;
830 }
831
832 static uint16_t nvme_set_feature_timestamp(NvmeCtrl *n, NvmeCmd *cmd)
833 {
834 uint16_t ret;
835 uint64_t timestamp;
836 uint64_t prp1 = le64_to_cpu(cmd->prp1);
837 uint64_t prp2 = le64_to_cpu(cmd->prp2);
838
839 ret = nvme_dma_write_prp(n, (uint8_t *)&timestamp,
840 sizeof(timestamp), prp1, prp2);
841 if (ret != NVME_SUCCESS) {
842 return ret;
843 }
844
845 nvme_set_timestamp(n, timestamp);
846
847 return NVME_SUCCESS;
848 }
849
850 static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
851 {
852 uint32_t dw10 = le32_to_cpu(cmd->cdw10);
853 uint32_t dw11 = le32_to_cpu(cmd->cdw11);
854
855 switch (dw10) {
856 case NVME_VOLATILE_WRITE_CACHE:
857 blk_set_enable_write_cache(n->conf.blk, dw11 & 1);
858 break;
859 case NVME_NUMBER_OF_QUEUES:
860 trace_pci_nvme_setfeat_numq((dw11 & 0xFFFF) + 1,
861 ((dw11 >> 16) & 0xFFFF) + 1,
862 n->params.max_ioqpairs,
863 n->params.max_ioqpairs);
864 req->cqe.result = cpu_to_le32((n->params.max_ioqpairs - 1) |
865 ((n->params.max_ioqpairs - 1) << 16));
866 break;
867 case NVME_TIMESTAMP:
868 return nvme_set_feature_timestamp(n, cmd);
869 default:
870 trace_pci_nvme_err_invalid_setfeat(dw10);
871 return NVME_INVALID_FIELD | NVME_DNR;
872 }
873 return NVME_SUCCESS;
874 }
875
876 static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
877 {
878 switch (cmd->opcode) {
879 case NVME_ADM_CMD_DELETE_SQ:
880 return nvme_del_sq(n, cmd);
881 case NVME_ADM_CMD_CREATE_SQ:
882 return nvme_create_sq(n, cmd);
883 case NVME_ADM_CMD_DELETE_CQ:
884 return nvme_del_cq(n, cmd);
885 case NVME_ADM_CMD_CREATE_CQ:
886 return nvme_create_cq(n, cmd);
887 case NVME_ADM_CMD_IDENTIFY:
888 return nvme_identify(n, cmd);
889 case NVME_ADM_CMD_SET_FEATURES:
890 return nvme_set_feature(n, cmd, req);
891 case NVME_ADM_CMD_GET_FEATURES:
892 return nvme_get_feature(n, cmd, req);
893 default:
894 trace_pci_nvme_err_invalid_admin_opc(cmd->opcode);
895 return NVME_INVALID_OPCODE | NVME_DNR;
896 }
897 }
898
899 static void nvme_process_sq(void *opaque)
900 {
901 NvmeSQueue *sq = opaque;
902 NvmeCtrl *n = sq->ctrl;
903 NvmeCQueue *cq = n->cq[sq->cqid];
904
905 uint16_t status;
906 hwaddr addr;
907 NvmeCmd cmd;
908 NvmeRequest *req;
909
910 while (!(nvme_sq_empty(sq) || QTAILQ_EMPTY(&sq->req_list))) {
911 addr = sq->dma_addr + sq->head * n->sqe_size;
912 nvme_addr_read(n, addr, (void *)&cmd, sizeof(cmd));
913 nvme_inc_sq_head(sq);
914
915 req = QTAILQ_FIRST(&sq->req_list);
916 QTAILQ_REMOVE(&sq->req_list, req, entry);
917 QTAILQ_INSERT_TAIL(&sq->out_req_list, req, entry);
918 memset(&req->cqe, 0, sizeof(req->cqe));
919 req->cqe.cid = cmd.cid;
920
921 status = sq->sqid ? nvme_io_cmd(n, &cmd, req) :
922 nvme_admin_cmd(n, &cmd, req);
923 if (status != NVME_NO_COMPLETE) {
924 req->status = status;
925 nvme_enqueue_req_completion(cq, req);
926 }
927 }
928 }
929
930 static void nvme_clear_ctrl(NvmeCtrl *n)
931 {
932 int i;
933
934 blk_drain(n->conf.blk);
935
936 for (i = 0; i < n->params.max_ioqpairs + 1; i++) {
937 if (n->sq[i] != NULL) {
938 nvme_free_sq(n->sq[i], n);
939 }
940 }
941 for (i = 0; i < n->params.max_ioqpairs + 1; i++) {
942 if (n->cq[i] != NULL) {
943 nvme_free_cq(n->cq[i], n);
944 }
945 }
946
947 blk_flush(n->conf.blk);
948 n->bar.cc = 0;
949 }
950
951 static int nvme_start_ctrl(NvmeCtrl *n)
952 {
953 uint32_t page_bits = NVME_CC_MPS(n->bar.cc) + 12;
954 uint32_t page_size = 1 << page_bits;
955
956 if (unlikely(n->cq[0])) {
957 trace_pci_nvme_err_startfail_cq();
958 return -1;
959 }
960 if (unlikely(n->sq[0])) {
961 trace_pci_nvme_err_startfail_sq();
962 return -1;
963 }
964 if (unlikely(!n->bar.asq)) {
965 trace_pci_nvme_err_startfail_nbarasq();
966 return -1;
967 }
968 if (unlikely(!n->bar.acq)) {
969 trace_pci_nvme_err_startfail_nbaracq();
970 return -1;
971 }
972 if (unlikely(n->bar.asq & (page_size - 1))) {
973 trace_pci_nvme_err_startfail_asq_misaligned(n->bar.asq);
974 return -1;
975 }
976 if (unlikely(n->bar.acq & (page_size - 1))) {
977 trace_pci_nvme_err_startfail_acq_misaligned(n->bar.acq);
978 return -1;
979 }
980 if (unlikely(NVME_CC_MPS(n->bar.cc) <
981 NVME_CAP_MPSMIN(n->bar.cap))) {
982 trace_pci_nvme_err_startfail_page_too_small(
983 NVME_CC_MPS(n->bar.cc),
984 NVME_CAP_MPSMIN(n->bar.cap));
985 return -1;
986 }
987 if (unlikely(NVME_CC_MPS(n->bar.cc) >
988 NVME_CAP_MPSMAX(n->bar.cap))) {
989 trace_pci_nvme_err_startfail_page_too_large(
990 NVME_CC_MPS(n->bar.cc),
991 NVME_CAP_MPSMAX(n->bar.cap));
992 return -1;
993 }
994 if (unlikely(NVME_CC_IOCQES(n->bar.cc) <
995 NVME_CTRL_CQES_MIN(n->id_ctrl.cqes))) {
996 trace_pci_nvme_err_startfail_cqent_too_small(
997 NVME_CC_IOCQES(n->bar.cc),
998 NVME_CTRL_CQES_MIN(n->bar.cap));
999 return -1;
1000 }
1001 if (unlikely(NVME_CC_IOCQES(n->bar.cc) >
1002 NVME_CTRL_CQES_MAX(n->id_ctrl.cqes))) {
1003 trace_pci_nvme_err_startfail_cqent_too_large(
1004 NVME_CC_IOCQES(n->bar.cc),
1005 NVME_CTRL_CQES_MAX(n->bar.cap));
1006 return -1;
1007 }
1008 if (unlikely(NVME_CC_IOSQES(n->bar.cc) <
1009 NVME_CTRL_SQES_MIN(n->id_ctrl.sqes))) {
1010 trace_pci_nvme_err_startfail_sqent_too_small(
1011 NVME_CC_IOSQES(n->bar.cc),
1012 NVME_CTRL_SQES_MIN(n->bar.cap));
1013 return -1;
1014 }
1015 if (unlikely(NVME_CC_IOSQES(n->bar.cc) >
1016 NVME_CTRL_SQES_MAX(n->id_ctrl.sqes))) {
1017 trace_pci_nvme_err_startfail_sqent_too_large(
1018 NVME_CC_IOSQES(n->bar.cc),
1019 NVME_CTRL_SQES_MAX(n->bar.cap));
1020 return -1;
1021 }
1022 if (unlikely(!NVME_AQA_ASQS(n->bar.aqa))) {
1023 trace_pci_nvme_err_startfail_asqent_sz_zero();
1024 return -1;
1025 }
1026 if (unlikely(!NVME_AQA_ACQS(n->bar.aqa))) {
1027 trace_pci_nvme_err_startfail_acqent_sz_zero();
1028 return -1;
1029 }
1030
1031 n->page_bits = page_bits;
1032 n->page_size = page_size;
1033 n->max_prp_ents = n->page_size / sizeof(uint64_t);
1034 n->cqe_size = 1 << NVME_CC_IOCQES(n->bar.cc);
1035 n->sqe_size = 1 << NVME_CC_IOSQES(n->bar.cc);
1036 nvme_init_cq(&n->admin_cq, n, n->bar.acq, 0, 0,
1037 NVME_AQA_ACQS(n->bar.aqa) + 1, 1);
1038 nvme_init_sq(&n->admin_sq, n, n->bar.asq, 0, 0,
1039 NVME_AQA_ASQS(n->bar.aqa) + 1);
1040
1041 nvme_set_timestamp(n, 0ULL);
1042
1043 return 0;
1044 }
1045
1046 static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
1047 unsigned size)
1048 {
1049 if (unlikely(offset & (sizeof(uint32_t) - 1))) {
1050 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_misaligned32,
1051 "MMIO write not 32-bit aligned,"
1052 " offset=0x%"PRIx64"", offset);
1053 /* should be ignored, fall through for now */
1054 }
1055
1056 if (unlikely(size < sizeof(uint32_t))) {
1057 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_toosmall,
1058 "MMIO write smaller than 32-bits,"
1059 " offset=0x%"PRIx64", size=%u",
1060 offset, size);
1061 /* should be ignored, fall through for now */
1062 }
1063
1064 switch (offset) {
1065 case 0xc: /* INTMS */
1066 if (unlikely(msix_enabled(&(n->parent_obj)))) {
1067 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_intmask_with_msix,
1068 "undefined access to interrupt mask set"
1069 " when MSI-X is enabled");
1070 /* should be ignored, fall through for now */
1071 }
1072 n->bar.intms |= data & 0xffffffff;
1073 n->bar.intmc = n->bar.intms;
1074 trace_pci_nvme_mmio_intm_set(data & 0xffffffff, n->bar.intmc);
1075 nvme_irq_check(n);
1076 break;
1077 case 0x10: /* INTMC */
1078 if (unlikely(msix_enabled(&(n->parent_obj)))) {
1079 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_intmask_with_msix,
1080 "undefined access to interrupt mask clr"
1081 " when MSI-X is enabled");
1082 /* should be ignored, fall through for now */
1083 }
1084 n->bar.intms &= ~(data & 0xffffffff);
1085 n->bar.intmc = n->bar.intms;
1086 trace_pci_nvme_mmio_intm_clr(data & 0xffffffff, n->bar.intmc);
1087 nvme_irq_check(n);
1088 break;
1089 case 0x14: /* CC */
1090 trace_pci_nvme_mmio_cfg(data & 0xffffffff);
1091 /* Windows first sends data, then sends enable bit */
1092 if (!NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc) &&
1093 !NVME_CC_SHN(data) && !NVME_CC_SHN(n->bar.cc))
1094 {
1095 n->bar.cc = data;
1096 }
1097
1098 if (NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc)) {
1099 n->bar.cc = data;
1100 if (unlikely(nvme_start_ctrl(n))) {
1101 trace_pci_nvme_err_startfail();
1102 n->bar.csts = NVME_CSTS_FAILED;
1103 } else {
1104 trace_pci_nvme_mmio_start_success();
1105 n->bar.csts = NVME_CSTS_READY;
1106 }
1107 } else if (!NVME_CC_EN(data) && NVME_CC_EN(n->bar.cc)) {
1108 trace_pci_nvme_mmio_stopped();
1109 nvme_clear_ctrl(n);
1110 n->bar.csts &= ~NVME_CSTS_READY;
1111 }
1112 if (NVME_CC_SHN(data) && !(NVME_CC_SHN(n->bar.cc))) {
1113 trace_pci_nvme_mmio_shutdown_set();
1114 nvme_clear_ctrl(n);
1115 n->bar.cc = data;
1116 n->bar.csts |= NVME_CSTS_SHST_COMPLETE;
1117 } else if (!NVME_CC_SHN(data) && NVME_CC_SHN(n->bar.cc)) {
1118 trace_pci_nvme_mmio_shutdown_cleared();
1119 n->bar.csts &= ~NVME_CSTS_SHST_COMPLETE;
1120 n->bar.cc = data;
1121 }
1122 break;
1123 case 0x1C: /* CSTS */
1124 if (data & (1 << 4)) {
1125 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_ssreset_w1c_unsupported,
1126 "attempted to W1C CSTS.NSSRO"
1127 " but CAP.NSSRS is zero (not supported)");
1128 } else if (data != 0) {
1129 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_ro_csts,
1130 "attempted to set a read only bit"
1131 " of controller status");
1132 }
1133 break;
1134 case 0x20: /* NSSR */
1135 if (data == 0x4E564D65) {
1136 trace_pci_nvme_ub_mmiowr_ssreset_unsupported();
1137 } else {
1138 /* The spec says that writes of other values have no effect */
1139 return;
1140 }
1141 break;
1142 case 0x24: /* AQA */
1143 n->bar.aqa = data & 0xffffffff;
1144 trace_pci_nvme_mmio_aqattr(data & 0xffffffff);
1145 break;
1146 case 0x28: /* ASQ */
1147 n->bar.asq = data;
1148 trace_pci_nvme_mmio_asqaddr(data);
1149 break;
1150 case 0x2c: /* ASQ hi */
1151 n->bar.asq |= data << 32;
1152 trace_pci_nvme_mmio_asqaddr_hi(data, n->bar.asq);
1153 break;
1154 case 0x30: /* ACQ */
1155 trace_pci_nvme_mmio_acqaddr(data);
1156 n->bar.acq = data;
1157 break;
1158 case 0x34: /* ACQ hi */
1159 n->bar.acq |= data << 32;
1160 trace_pci_nvme_mmio_acqaddr_hi(data, n->bar.acq);
1161 break;
1162 case 0x38: /* CMBLOC */
1163 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_cmbloc_reserved,
1164 "invalid write to reserved CMBLOC"
1165 " when CMBSZ is zero, ignored");
1166 return;
1167 case 0x3C: /* CMBSZ */
1168 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_cmbsz_readonly,
1169 "invalid write to read only CMBSZ, ignored");
1170 return;
1171 case 0xE00: /* PMRCAP */
1172 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrcap_readonly,
1173 "invalid write to PMRCAP register, ignored");
1174 return;
1175 case 0xE04: /* TODO PMRCTL */
1176 break;
1177 case 0xE08: /* PMRSTS */
1178 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrsts_readonly,
1179 "invalid write to PMRSTS register, ignored");
1180 return;
1181 case 0xE0C: /* PMREBS */
1182 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrebs_readonly,
1183 "invalid write to PMREBS register, ignored");
1184 return;
1185 case 0xE10: /* PMRSWTP */
1186 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrswtp_readonly,
1187 "invalid write to PMRSWTP register, ignored");
1188 return;
1189 case 0xE14: /* TODO PMRMSC */
1190 break;
1191 default:
1192 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_invalid,
1193 "invalid MMIO write,"
1194 " offset=0x%"PRIx64", data=%"PRIx64"",
1195 offset, data);
1196 break;
1197 }
1198 }
1199
1200 static uint64_t nvme_mmio_read(void *opaque, hwaddr addr, unsigned size)
1201 {
1202 NvmeCtrl *n = (NvmeCtrl *)opaque;
1203 uint8_t *ptr = (uint8_t *)&n->bar;
1204 uint64_t val = 0;
1205
1206 if (unlikely(addr & (sizeof(uint32_t) - 1))) {
1207 NVME_GUEST_ERR(pci_nvme_ub_mmiord_misaligned32,
1208 "MMIO read not 32-bit aligned,"
1209 " offset=0x%"PRIx64"", addr);
1210 /* should RAZ, fall through for now */
1211 } else if (unlikely(size < sizeof(uint32_t))) {
1212 NVME_GUEST_ERR(pci_nvme_ub_mmiord_toosmall,
1213 "MMIO read smaller than 32-bits,"
1214 " offset=0x%"PRIx64"", addr);
1215 /* should RAZ, fall through for now */
1216 }
1217
1218 if (addr < sizeof(n->bar)) {
1219 /*
1220 * When PMRWBM bit 1 is set then read from
1221 * from PMRSTS should ensure prior writes
1222 * made it to persistent media
1223 */
1224 if (addr == 0xE08 &&
1225 (NVME_PMRCAP_PMRWBM(n->bar.pmrcap) & 0x02)) {
1226 memory_region_msync(&n->pmrdev->mr, 0, n->pmrdev->size);
1227 }
1228 memcpy(&val, ptr + addr, size);
1229 } else {
1230 NVME_GUEST_ERR(pci_nvme_ub_mmiord_invalid_ofs,
1231 "MMIO read beyond last register,"
1232 " offset=0x%"PRIx64", returning 0", addr);
1233 }
1234
1235 return val;
1236 }
1237
1238 static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val)
1239 {
1240 uint32_t qid;
1241
1242 if (unlikely(addr & ((1 << 2) - 1))) {
1243 NVME_GUEST_ERR(pci_nvme_ub_db_wr_misaligned,
1244 "doorbell write not 32-bit aligned,"
1245 " offset=0x%"PRIx64", ignoring", addr);
1246 return;
1247 }
1248
1249 if (((addr - 0x1000) >> 2) & 1) {
1250 /* Completion queue doorbell write */
1251
1252 uint16_t new_head = val & 0xffff;
1253 int start_sqs;
1254 NvmeCQueue *cq;
1255
1256 qid = (addr - (0x1000 + (1 << 2))) >> 3;
1257 if (unlikely(nvme_check_cqid(n, qid))) {
1258 NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_cq,
1259 "completion queue doorbell write"
1260 " for nonexistent queue,"
1261 " sqid=%"PRIu32", ignoring", qid);
1262 return;
1263 }
1264
1265 cq = n->cq[qid];
1266 if (unlikely(new_head >= cq->size)) {
1267 NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_cqhead,
1268 "completion queue doorbell write value"
1269 " beyond queue size, sqid=%"PRIu32","
1270 " new_head=%"PRIu16", ignoring",
1271 qid, new_head);
1272 return;
1273 }
1274
1275 start_sqs = nvme_cq_full(cq) ? 1 : 0;
1276 cq->head = new_head;
1277 if (start_sqs) {
1278 NvmeSQueue *sq;
1279 QTAILQ_FOREACH(sq, &cq->sq_list, entry) {
1280 timer_mod(sq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
1281 }
1282 timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
1283 }
1284
1285 if (cq->tail == cq->head) {
1286 nvme_irq_deassert(n, cq);
1287 }
1288 } else {
1289 /* Submission queue doorbell write */
1290
1291 uint16_t new_tail = val & 0xffff;
1292 NvmeSQueue *sq;
1293
1294 qid = (addr - 0x1000) >> 3;
1295 if (unlikely(nvme_check_sqid(n, qid))) {
1296 NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_sq,
1297 "submission queue doorbell write"
1298 " for nonexistent queue,"
1299 " sqid=%"PRIu32", ignoring", qid);
1300 return;
1301 }
1302
1303 sq = n->sq[qid];
1304 if (unlikely(new_tail >= sq->size)) {
1305 NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_sqtail,
1306 "submission queue doorbell write value"
1307 " beyond queue size, sqid=%"PRIu32","
1308 " new_tail=%"PRIu16", ignoring",
1309 qid, new_tail);
1310 return;
1311 }
1312
1313 sq->tail = new_tail;
1314 timer_mod(sq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
1315 }
1316 }
1317
1318 static void nvme_mmio_write(void *opaque, hwaddr addr, uint64_t data,
1319 unsigned size)
1320 {
1321 NvmeCtrl *n = (NvmeCtrl *)opaque;
1322 if (addr < sizeof(n->bar)) {
1323 nvme_write_bar(n, addr, data, size);
1324 } else {
1325 nvme_process_db(n, addr, data);
1326 }
1327 }
1328
1329 static const MemoryRegionOps nvme_mmio_ops = {
1330 .read = nvme_mmio_read,
1331 .write = nvme_mmio_write,
1332 .endianness = DEVICE_LITTLE_ENDIAN,
1333 .impl = {
1334 .min_access_size = 2,
1335 .max_access_size = 8,
1336 },
1337 };
1338
1339 static void nvme_cmb_write(void *opaque, hwaddr addr, uint64_t data,
1340 unsigned size)
1341 {
1342 NvmeCtrl *n = (NvmeCtrl *)opaque;
1343 stn_le_p(&n->cmbuf[addr], size, data);
1344 }
1345
1346 static uint64_t nvme_cmb_read(void *opaque, hwaddr addr, unsigned size)
1347 {
1348 NvmeCtrl *n = (NvmeCtrl *)opaque;
1349 return ldn_le_p(&n->cmbuf[addr], size);
1350 }
1351
1352 static const MemoryRegionOps nvme_cmb_ops = {
1353 .read = nvme_cmb_read,
1354 .write = nvme_cmb_write,
1355 .endianness = DEVICE_LITTLE_ENDIAN,
1356 .impl = {
1357 .min_access_size = 1,
1358 .max_access_size = 8,
1359 },
1360 };
1361
1362 static void nvme_check_constraints(NvmeCtrl *n, Error **errp)
1363 {
1364 NvmeParams *params = &n->params;
1365
1366 if (params->num_queues) {
1367 warn_report("num_queues is deprecated; please use max_ioqpairs "
1368 "instead");
1369
1370 params->max_ioqpairs = params->num_queues - 1;
1371 }
1372
1373 if (params->max_ioqpairs < 1 ||
1374 params->max_ioqpairs > NVME_MAX_IOQPAIRS) {
1375 error_setg(errp, "max_ioqpairs must be between 1 and %d",
1376 NVME_MAX_IOQPAIRS);
1377 return;
1378 }
1379
1380 if (params->msix_qsize < 1 ||
1381 params->msix_qsize > PCI_MSIX_FLAGS_QSIZE + 1) {
1382 error_setg(errp, "msix_qsize must be between 1 and %d",
1383 PCI_MSIX_FLAGS_QSIZE + 1);
1384 return;
1385 }
1386
1387 if (!n->conf.blk) {
1388 error_setg(errp, "drive property not set");
1389 return;
1390 }
1391
1392 if (!params->serial) {
1393 error_setg(errp, "serial property not set");
1394 return;
1395 }
1396
1397 if (!n->params.cmb_size_mb && n->pmrdev) {
1398 if (host_memory_backend_is_mapped(n->pmrdev)) {
1399 error_setg(errp, "can't use already busy memdev: %s",
1400 object_get_canonical_path_component(OBJECT(n->pmrdev)));
1401 return;
1402 }
1403
1404 if (!is_power_of_2(n->pmrdev->size)) {
1405 error_setg(errp, "pmr backend size needs to be power of 2 in size");
1406 return;
1407 }
1408
1409 host_memory_backend_set_mapped(n->pmrdev, true);
1410 }
1411 }
1412
1413 static void nvme_init_state(NvmeCtrl *n)
1414 {
1415 n->num_namespaces = 1;
1416 /* add one to max_ioqpairs to account for the admin queue pair */
1417 n->reg_size = pow2ceil(sizeof(NvmeBar) +
1418 2 * (n->params.max_ioqpairs + 1) * NVME_DB_SIZE);
1419 n->namespaces = g_new0(NvmeNamespace, n->num_namespaces);
1420 n->sq = g_new0(NvmeSQueue *, n->params.max_ioqpairs + 1);
1421 n->cq = g_new0(NvmeCQueue *, n->params.max_ioqpairs + 1);
1422 }
1423
1424 static void nvme_init_blk(NvmeCtrl *n, Error **errp)
1425 {
1426 if (!blkconf_blocksizes(&n->conf, errp)) {
1427 return;
1428 }
1429 blkconf_apply_backend_options(&n->conf, blk_is_read_only(n->conf.blk),
1430 false, errp);
1431 }
1432
1433 static void nvme_init_namespace(NvmeCtrl *n, NvmeNamespace *ns, Error **errp)
1434 {
1435 int64_t bs_size;
1436 NvmeIdNs *id_ns = &ns->id_ns;
1437
1438 bs_size = blk_getlength(n->conf.blk);
1439 if (bs_size < 0) {
1440 error_setg_errno(errp, -bs_size, "could not get backing file size");
1441 return;
1442 }
1443
1444 n->ns_size = bs_size;
1445
1446 id_ns->lbaf[0].ds = BDRV_SECTOR_BITS;
1447 id_ns->nsze = cpu_to_le64(nvme_ns_nlbas(n, ns));
1448
1449 /* no thin provisioning */
1450 id_ns->ncap = id_ns->nsze;
1451 id_ns->nuse = id_ns->ncap;
1452 }
1453
1454 static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev)
1455 {
1456 NVME_CMBLOC_SET_BIR(n->bar.cmbloc, NVME_CMB_BIR);
1457 NVME_CMBLOC_SET_OFST(n->bar.cmbloc, 0);
1458
1459 NVME_CMBSZ_SET_SQS(n->bar.cmbsz, 1);
1460 NVME_CMBSZ_SET_CQS(n->bar.cmbsz, 0);
1461 NVME_CMBSZ_SET_LISTS(n->bar.cmbsz, 0);
1462 NVME_CMBSZ_SET_RDS(n->bar.cmbsz, 1);
1463 NVME_CMBSZ_SET_WDS(n->bar.cmbsz, 1);
1464 NVME_CMBSZ_SET_SZU(n->bar.cmbsz, 2); /* MBs */
1465 NVME_CMBSZ_SET_SZ(n->bar.cmbsz, n->params.cmb_size_mb);
1466
1467 n->cmbuf = g_malloc0(NVME_CMBSZ_GETSIZE(n->bar.cmbsz));
1468 memory_region_init_io(&n->ctrl_mem, OBJECT(n), &nvme_cmb_ops, n,
1469 "nvme-cmb", NVME_CMBSZ_GETSIZE(n->bar.cmbsz));
1470 pci_register_bar(pci_dev, NVME_CMBLOC_BIR(n->bar.cmbloc),
1471 PCI_BASE_ADDRESS_SPACE_MEMORY |
1472 PCI_BASE_ADDRESS_MEM_TYPE_64 |
1473 PCI_BASE_ADDRESS_MEM_PREFETCH, &n->ctrl_mem);
1474 }
1475
1476 static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev)
1477 {
1478 /* Controller Capabilities register */
1479 NVME_CAP_SET_PMRS(n->bar.cap, 1);
1480
1481 /* PMR Capabities register */
1482 n->bar.pmrcap = 0;
1483 NVME_PMRCAP_SET_RDS(n->bar.pmrcap, 0);
1484 NVME_PMRCAP_SET_WDS(n->bar.pmrcap, 0);
1485 NVME_PMRCAP_SET_BIR(n->bar.pmrcap, NVME_PMR_BIR);
1486 NVME_PMRCAP_SET_PMRTU(n->bar.pmrcap, 0);
1487 /* Turn on bit 1 support */
1488 NVME_PMRCAP_SET_PMRWBM(n->bar.pmrcap, 0x02);
1489 NVME_PMRCAP_SET_PMRTO(n->bar.pmrcap, 0);
1490 NVME_PMRCAP_SET_CMSS(n->bar.pmrcap, 0);
1491
1492 /* PMR Control register */
1493 n->bar.pmrctl = 0;
1494 NVME_PMRCTL_SET_EN(n->bar.pmrctl, 0);
1495
1496 /* PMR Status register */
1497 n->bar.pmrsts = 0;
1498 NVME_PMRSTS_SET_ERR(n->bar.pmrsts, 0);
1499 NVME_PMRSTS_SET_NRDY(n->bar.pmrsts, 0);
1500 NVME_PMRSTS_SET_HSTS(n->bar.pmrsts, 0);
1501 NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 0);
1502
1503 /* PMR Elasticity Buffer Size register */
1504 n->bar.pmrebs = 0;
1505 NVME_PMREBS_SET_PMRSZU(n->bar.pmrebs, 0);
1506 NVME_PMREBS_SET_RBB(n->bar.pmrebs, 0);
1507 NVME_PMREBS_SET_PMRWBZ(n->bar.pmrebs, 0);
1508
1509 /* PMR Sustained Write Throughput register */
1510 n->bar.pmrswtp = 0;
1511 NVME_PMRSWTP_SET_PMRSWTU(n->bar.pmrswtp, 0);
1512 NVME_PMRSWTP_SET_PMRSWTV(n->bar.pmrswtp, 0);
1513
1514 /* PMR Memory Space Control register */
1515 n->bar.pmrmsc = 0;
1516 NVME_PMRMSC_SET_CMSE(n->bar.pmrmsc, 0);
1517 NVME_PMRMSC_SET_CBA(n->bar.pmrmsc, 0);
1518
1519 pci_register_bar(pci_dev, NVME_PMRCAP_BIR(n->bar.pmrcap),
1520 PCI_BASE_ADDRESS_SPACE_MEMORY |
1521 PCI_BASE_ADDRESS_MEM_TYPE_64 |
1522 PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmrdev->mr);
1523 }
1524
1525 static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
1526 {
1527 uint8_t *pci_conf = pci_dev->config;
1528
1529 pci_conf[PCI_INTERRUPT_PIN] = 1;
1530 pci_config_set_prog_interface(pci_conf, 0x2);
1531 pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_EXPRESS);
1532 pcie_endpoint_cap_init(pci_dev, 0x80);
1533
1534 memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme",
1535 n->reg_size);
1536 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY |
1537 PCI_BASE_ADDRESS_MEM_TYPE_64, &n->iomem);
1538 if (msix_init_exclusive_bar(pci_dev, n->params.msix_qsize, 4, errp)) {
1539 return;
1540 }
1541
1542 if (n->params.cmb_size_mb) {
1543 nvme_init_cmb(n, pci_dev);
1544 } else if (n->pmrdev) {
1545 nvme_init_pmr(n, pci_dev);
1546 }
1547 }
1548
1549 static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
1550 {
1551 NvmeIdCtrl *id = &n->id_ctrl;
1552 uint8_t *pci_conf = pci_dev->config;
1553
1554 id->vid = cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID));
1555 id->ssvid = cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID));
1556 strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' ');
1557 strpadcpy((char *)id->fr, sizeof(id->fr), "1.0", ' ');
1558 strpadcpy((char *)id->sn, sizeof(id->sn), n->params.serial, ' ');
1559 id->rab = 6;
1560 id->ieee[0] = 0x00;
1561 id->ieee[1] = 0x02;
1562 id->ieee[2] = 0xb3;
1563 id->oacs = cpu_to_le16(0);
1564 id->frmw = 7 << 1;
1565 id->lpa = 1 << 0;
1566 id->sqes = (0x6 << 4) | 0x6;
1567 id->cqes = (0x4 << 4) | 0x4;
1568 id->nn = cpu_to_le32(n->num_namespaces);
1569 id->oncs = cpu_to_le16(NVME_ONCS_WRITE_ZEROS | NVME_ONCS_TIMESTAMP);
1570 id->psd[0].mp = cpu_to_le16(0x9c4);
1571 id->psd[0].enlat = cpu_to_le32(0x10);
1572 id->psd[0].exlat = cpu_to_le32(0x4);
1573 if (blk_enable_write_cache(n->conf.blk)) {
1574 id->vwc = 1;
1575 }
1576
1577 n->bar.cap = 0;
1578 NVME_CAP_SET_MQES(n->bar.cap, 0x7ff);
1579 NVME_CAP_SET_CQR(n->bar.cap, 1);
1580 NVME_CAP_SET_TO(n->bar.cap, 0xf);
1581 NVME_CAP_SET_CSS(n->bar.cap, 1);
1582 NVME_CAP_SET_MPSMAX(n->bar.cap, 4);
1583
1584 n->bar.vs = 0x00010200;
1585 n->bar.intmc = n->bar.intms = 0;
1586 }
1587
1588 static void nvme_realize(PCIDevice *pci_dev, Error **errp)
1589 {
1590 NvmeCtrl *n = NVME(pci_dev);
1591 Error *local_err = NULL;
1592
1593 int i;
1594
1595 nvme_check_constraints(n, &local_err);
1596 if (local_err) {
1597 error_propagate(errp, local_err);
1598 return;
1599 }
1600
1601 nvme_init_state(n);
1602 nvme_init_blk(n, &local_err);
1603 if (local_err) {
1604 error_propagate(errp, local_err);
1605 return;
1606 }
1607
1608 nvme_init_pci(n, pci_dev, &local_err);
1609 if (local_err) {
1610 error_propagate(errp, local_err);
1611 return;
1612 }
1613
1614 nvme_init_ctrl(n, pci_dev);
1615
1616 for (i = 0; i < n->num_namespaces; i++) {
1617 nvme_init_namespace(n, &n->namespaces[i], &local_err);
1618 if (local_err) {
1619 error_propagate(errp, local_err);
1620 return;
1621 }
1622 }
1623 }
1624
1625 static void nvme_exit(PCIDevice *pci_dev)
1626 {
1627 NvmeCtrl *n = NVME(pci_dev);
1628
1629 nvme_clear_ctrl(n);
1630 g_free(n->namespaces);
1631 g_free(n->cq);
1632 g_free(n->sq);
1633
1634 if (n->params.cmb_size_mb) {
1635 g_free(n->cmbuf);
1636 }
1637
1638 if (n->pmrdev) {
1639 host_memory_backend_set_mapped(n->pmrdev, false);
1640 }
1641 msix_uninit_exclusive_bar(pci_dev);
1642 }
1643
1644 static Property nvme_props[] = {
1645 DEFINE_BLOCK_PROPERTIES(NvmeCtrl, conf),
1646 DEFINE_PROP_LINK("pmrdev", NvmeCtrl, pmrdev, TYPE_MEMORY_BACKEND,
1647 HostMemoryBackend *),
1648 DEFINE_PROP_STRING("serial", NvmeCtrl, params.serial),
1649 DEFINE_PROP_UINT32("cmb_size_mb", NvmeCtrl, params.cmb_size_mb, 0),
1650 DEFINE_PROP_UINT32("num_queues", NvmeCtrl, params.num_queues, 0),
1651 DEFINE_PROP_UINT32("max_ioqpairs", NvmeCtrl, params.max_ioqpairs, 64),
1652 DEFINE_PROP_UINT16("msix_qsize", NvmeCtrl, params.msix_qsize, 65),
1653 DEFINE_PROP_END_OF_LIST(),
1654 };
1655
1656 static const VMStateDescription nvme_vmstate = {
1657 .name = "nvme",
1658 .unmigratable = 1,
1659 };
1660
1661 static void nvme_class_init(ObjectClass *oc, void *data)
1662 {
1663 DeviceClass *dc = DEVICE_CLASS(oc);
1664 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
1665
1666 pc->realize = nvme_realize;
1667 pc->exit = nvme_exit;
1668 pc->class_id = PCI_CLASS_STORAGE_EXPRESS;
1669 pc->vendor_id = PCI_VENDOR_ID_INTEL;
1670 pc->device_id = 0x5845;
1671 pc->revision = 2;
1672
1673 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1674 dc->desc = "Non-Volatile Memory Express";
1675 device_class_set_props(dc, nvme_props);
1676 dc->vmsd = &nvme_vmstate;
1677 }
1678
1679 static void nvme_instance_init(Object *obj)
1680 {
1681 NvmeCtrl *s = NVME(obj);
1682
1683 device_add_bootindex_property(obj, &s->conf.bootindex,
1684 "bootindex", "/namespace@1,0",
1685 DEVICE(obj));
1686 }
1687
1688 static const TypeInfo nvme_info = {
1689 .name = TYPE_NVME,
1690 .parent = TYPE_PCI_DEVICE,
1691 .instance_size = sizeof(NvmeCtrl),
1692 .class_init = nvme_class_init,
1693 .instance_init = nvme_instance_init,
1694 .interfaces = (InterfaceInfo[]) {
1695 { INTERFACE_PCIE_DEVICE },
1696 { }
1697 },
1698 };
1699
1700 static void nvme_register_types(void)
1701 {
1702 type_register_static(&nvme_info);
1703 }
1704
1705 type_init(nvme_register_types)