Merge remote-tracking branch 'remotes/philmd-gitlab/tags/renesas-20201027' into staging
[qemu.git] / hw / char / cadence_uart.c
1 /*
2 * Device model for Cadence UART
3 *
4 * Reference: Xilinx Zynq 7000 reference manual
5 * - http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
6 * - Chapter 19 UART Controller
7 * - Appendix B for Register details
8 *
9 * Copyright (c) 2010 Xilinx Inc.
10 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
11 * Copyright (c) 2012 PetaLogix Pty Ltd.
12 * Written by Haibing Ma
13 * M.Habib
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 */
23
24 #include "qemu/osdep.h"
25 #include "hw/sysbus.h"
26 #include "migration/vmstate.h"
27 #include "chardev/char-fe.h"
28 #include "chardev/char-serial.h"
29 #include "qemu/timer.h"
30 #include "qemu/log.h"
31 #include "qemu/module.h"
32 #include "hw/char/cadence_uart.h"
33 #include "hw/irq.h"
34 #include "hw/qdev-clock.h"
35 #include "trace.h"
36
37 #ifdef CADENCE_UART_ERR_DEBUG
38 #define DB_PRINT(...) do { \
39 fprintf(stderr, ": %s: ", __func__); \
40 fprintf(stderr, ## __VA_ARGS__); \
41 } while (0)
42 #else
43 #define DB_PRINT(...)
44 #endif
45
46 #define UART_SR_INTR_RTRIG 0x00000001
47 #define UART_SR_INTR_REMPTY 0x00000002
48 #define UART_SR_INTR_RFUL 0x00000004
49 #define UART_SR_INTR_TEMPTY 0x00000008
50 #define UART_SR_INTR_TFUL 0x00000010
51 /* somewhat awkwardly, TTRIG is misaligned between SR and ISR */
52 #define UART_SR_TTRIG 0x00002000
53 #define UART_INTR_TTRIG 0x00000400
54 /* bits fields in CSR that correlate to CISR. If any of these bits are set in
55 * SR, then the same bit in CISR is set high too */
56 #define UART_SR_TO_CISR_MASK 0x0000001F
57
58 #define UART_INTR_ROVR 0x00000020
59 #define UART_INTR_FRAME 0x00000040
60 #define UART_INTR_PARE 0x00000080
61 #define UART_INTR_TIMEOUT 0x00000100
62 #define UART_INTR_DMSI 0x00000200
63 #define UART_INTR_TOVR 0x00001000
64
65 #define UART_SR_RACTIVE 0x00000400
66 #define UART_SR_TACTIVE 0x00000800
67 #define UART_SR_FDELT 0x00001000
68
69 #define UART_CR_RXRST 0x00000001
70 #define UART_CR_TXRST 0x00000002
71 #define UART_CR_RX_EN 0x00000004
72 #define UART_CR_RX_DIS 0x00000008
73 #define UART_CR_TX_EN 0x00000010
74 #define UART_CR_TX_DIS 0x00000020
75 #define UART_CR_RST_TO 0x00000040
76 #define UART_CR_STARTBRK 0x00000080
77 #define UART_CR_STOPBRK 0x00000100
78
79 #define UART_MR_CLKS 0x00000001
80 #define UART_MR_CHRL 0x00000006
81 #define UART_MR_CHRL_SH 1
82 #define UART_MR_PAR 0x00000038
83 #define UART_MR_PAR_SH 3
84 #define UART_MR_NBSTOP 0x000000C0
85 #define UART_MR_NBSTOP_SH 6
86 #define UART_MR_CHMODE 0x00000300
87 #define UART_MR_CHMODE_SH 8
88 #define UART_MR_UCLKEN 0x00000400
89 #define UART_MR_IRMODE 0x00000800
90
91 #define UART_DATA_BITS_6 (0x3 << UART_MR_CHRL_SH)
92 #define UART_DATA_BITS_7 (0x2 << UART_MR_CHRL_SH)
93 #define UART_PARITY_ODD (0x1 << UART_MR_PAR_SH)
94 #define UART_PARITY_EVEN (0x0 << UART_MR_PAR_SH)
95 #define UART_STOP_BITS_1 (0x3 << UART_MR_NBSTOP_SH)
96 #define UART_STOP_BITS_2 (0x2 << UART_MR_NBSTOP_SH)
97 #define NORMAL_MODE (0x0 << UART_MR_CHMODE_SH)
98 #define ECHO_MODE (0x1 << UART_MR_CHMODE_SH)
99 #define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH)
100 #define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH)
101
102 #define UART_DEFAULT_REF_CLK (50 * 1000 * 1000)
103
104 #define R_CR (0x00/4)
105 #define R_MR (0x04/4)
106 #define R_IER (0x08/4)
107 #define R_IDR (0x0C/4)
108 #define R_IMR (0x10/4)
109 #define R_CISR (0x14/4)
110 #define R_BRGR (0x18/4)
111 #define R_RTOR (0x1C/4)
112 #define R_RTRIG (0x20/4)
113 #define R_MCR (0x24/4)
114 #define R_MSR (0x28/4)
115 #define R_SR (0x2C/4)
116 #define R_TX_RX (0x30/4)
117 #define R_BDIV (0x34/4)
118 #define R_FDEL (0x38/4)
119 #define R_PMIN (0x3C/4)
120 #define R_PWID (0x40/4)
121 #define R_TTRIG (0x44/4)
122
123
124 static void uart_update_status(CadenceUARTState *s)
125 {
126 s->r[R_SR] = 0;
127
128 s->r[R_SR] |= s->rx_count == CADENCE_UART_RX_FIFO_SIZE ? UART_SR_INTR_RFUL
129 : 0;
130 s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0;
131 s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0;
132
133 s->r[R_SR] |= s->tx_count == CADENCE_UART_TX_FIFO_SIZE ? UART_SR_INTR_TFUL
134 : 0;
135 s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0;
136 s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0;
137
138 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK;
139 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0;
140 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR]));
141 }
142
143 static void fifo_trigger_update(void *opaque)
144 {
145 CadenceUARTState *s = opaque;
146
147 if (s->r[R_RTOR]) {
148 s->r[R_CISR] |= UART_INTR_TIMEOUT;
149 uart_update_status(s);
150 }
151 }
152
153 static void uart_rx_reset(CadenceUARTState *s)
154 {
155 s->rx_wpos = 0;
156 s->rx_count = 0;
157 qemu_chr_fe_accept_input(&s->chr);
158 }
159
160 static void uart_tx_reset(CadenceUARTState *s)
161 {
162 s->tx_count = 0;
163 }
164
165 static void uart_send_breaks(CadenceUARTState *s)
166 {
167 int break_enabled = 1;
168
169 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
170 &break_enabled);
171 }
172
173 static void uart_parameters_setup(CadenceUARTState *s)
174 {
175 QEMUSerialSetParams ssp;
176 unsigned int baud_rate, packet_size, input_clk;
177 input_clk = clock_get_hz(s->refclk);
178
179 baud_rate = (s->r[R_MR] & UART_MR_CLKS) ? input_clk / 8 : input_clk;
180 baud_rate /= (s->r[R_BRGR] * (s->r[R_BDIV] + 1));
181 trace_cadence_uart_baudrate(baud_rate);
182
183 ssp.speed = baud_rate;
184
185 packet_size = 1;
186
187 switch (s->r[R_MR] & UART_MR_PAR) {
188 case UART_PARITY_EVEN:
189 ssp.parity = 'E';
190 packet_size++;
191 break;
192 case UART_PARITY_ODD:
193 ssp.parity = 'O';
194 packet_size++;
195 break;
196 default:
197 ssp.parity = 'N';
198 break;
199 }
200
201 switch (s->r[R_MR] & UART_MR_CHRL) {
202 case UART_DATA_BITS_6:
203 ssp.data_bits = 6;
204 break;
205 case UART_DATA_BITS_7:
206 ssp.data_bits = 7;
207 break;
208 default:
209 ssp.data_bits = 8;
210 break;
211 }
212
213 switch (s->r[R_MR] & UART_MR_NBSTOP) {
214 case UART_STOP_BITS_1:
215 ssp.stop_bits = 1;
216 break;
217 default:
218 ssp.stop_bits = 2;
219 break;
220 }
221
222 packet_size += ssp.data_bits + ssp.stop_bits;
223 if (ssp.speed == 0) {
224 /*
225 * Avoid division-by-zero below.
226 * TODO: find something better
227 */
228 ssp.speed = 1;
229 }
230 s->char_tx_time = (NANOSECONDS_PER_SECOND / ssp.speed) * packet_size;
231 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
232 }
233
234 static int uart_can_receive(void *opaque)
235 {
236 CadenceUARTState *s = opaque;
237 int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE);
238 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
239
240 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
241 ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count);
242 }
243 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
244 ret = MIN(ret, CADENCE_UART_TX_FIFO_SIZE - s->tx_count);
245 }
246 return ret;
247 }
248
249 static void uart_ctrl_update(CadenceUARTState *s)
250 {
251 if (s->r[R_CR] & UART_CR_TXRST) {
252 uart_tx_reset(s);
253 }
254
255 if (s->r[R_CR] & UART_CR_RXRST) {
256 uart_rx_reset(s);
257 }
258
259 s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST);
260
261 if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) {
262 uart_send_breaks(s);
263 }
264 }
265
266 static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size)
267 {
268 CadenceUARTState *s = opaque;
269 uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
270 int i;
271
272 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
273 return;
274 }
275
276 if (s->rx_count == CADENCE_UART_RX_FIFO_SIZE) {
277 s->r[R_CISR] |= UART_INTR_ROVR;
278 } else {
279 for (i = 0; i < size; i++) {
280 s->rx_fifo[s->rx_wpos] = buf[i];
281 s->rx_wpos = (s->rx_wpos + 1) % CADENCE_UART_RX_FIFO_SIZE;
282 s->rx_count++;
283 }
284 timer_mod(s->fifo_trigger_handle, new_rx_time +
285 (s->char_tx_time * 4));
286 }
287 uart_update_status(s);
288 }
289
290 static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond,
291 void *opaque)
292 {
293 CadenceUARTState *s = opaque;
294 int ret;
295
296 /* instant drain the fifo when there's no back-end */
297 if (!qemu_chr_fe_backend_connected(&s->chr)) {
298 s->tx_count = 0;
299 return FALSE;
300 }
301
302 if (!s->tx_count) {
303 return FALSE;
304 }
305
306 ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_count);
307
308 if (ret >= 0) {
309 s->tx_count -= ret;
310 memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_count);
311 }
312
313 if (s->tx_count) {
314 guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
315 cadence_uart_xmit, s);
316 if (!r) {
317 s->tx_count = 0;
318 return FALSE;
319 }
320 }
321
322 uart_update_status(s);
323 return FALSE;
324 }
325
326 static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf,
327 int size)
328 {
329 if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) {
330 return;
331 }
332
333 if (size > CADENCE_UART_TX_FIFO_SIZE - s->tx_count) {
334 size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count;
335 /*
336 * This can only be a guest error via a bad tx fifo register push,
337 * as can_receive() should stop remote loop and echo modes ever getting
338 * us to here.
339 */
340 qemu_log_mask(LOG_GUEST_ERROR, "cadence_uart: TxFIFO overflow");
341 s->r[R_CISR] |= UART_INTR_ROVR;
342 }
343
344 memcpy(s->tx_fifo + s->tx_count, buf, size);
345 s->tx_count += size;
346
347 cadence_uart_xmit(NULL, G_IO_OUT, s);
348 }
349
350 static void uart_receive(void *opaque, const uint8_t *buf, int size)
351 {
352 CadenceUARTState *s = opaque;
353 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
354
355 /* ignore characters when unclocked or in reset */
356 if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
357 return;
358 }
359
360 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
361 uart_write_rx_fifo(opaque, buf, size);
362 }
363 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
364 uart_write_tx_fifo(s, buf, size);
365 }
366 }
367
368 static void uart_event(void *opaque, QEMUChrEvent event)
369 {
370 CadenceUARTState *s = opaque;
371 uint8_t buf = '\0';
372
373 /* ignore characters when unclocked or in reset */
374 if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
375 return;
376 }
377
378 if (event == CHR_EVENT_BREAK) {
379 uart_write_rx_fifo(opaque, &buf, 1);
380 }
381
382 uart_update_status(s);
383 }
384
385 static void uart_read_rx_fifo(CadenceUARTState *s, uint32_t *c)
386 {
387 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
388 return;
389 }
390
391 if (s->rx_count) {
392 uint32_t rx_rpos = (CADENCE_UART_RX_FIFO_SIZE + s->rx_wpos -
393 s->rx_count) % CADENCE_UART_RX_FIFO_SIZE;
394 *c = s->rx_fifo[rx_rpos];
395 s->rx_count--;
396
397 qemu_chr_fe_accept_input(&s->chr);
398 } else {
399 *c = 0;
400 }
401
402 uart_update_status(s);
403 }
404
405 static void uart_write(void *opaque, hwaddr offset,
406 uint64_t value, unsigned size)
407 {
408 CadenceUARTState *s = opaque;
409
410 DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
411 offset >>= 2;
412 if (offset >= CADENCE_UART_R_MAX) {
413 return;
414 }
415 switch (offset) {
416 case R_IER: /* ier (wts imr) */
417 s->r[R_IMR] |= value;
418 break;
419 case R_IDR: /* idr (wtc imr) */
420 s->r[R_IMR] &= ~value;
421 break;
422 case R_IMR: /* imr (read only) */
423 break;
424 case R_CISR: /* cisr (wtc) */
425 s->r[R_CISR] &= ~value;
426 break;
427 case R_TX_RX: /* UARTDR */
428 switch (s->r[R_MR] & UART_MR_CHMODE) {
429 case NORMAL_MODE:
430 uart_write_tx_fifo(s, (uint8_t *) &value, 1);
431 break;
432 case LOCAL_LOOPBACK:
433 uart_write_rx_fifo(opaque, (uint8_t *) &value, 1);
434 break;
435 }
436 break;
437 case R_BRGR: /* Baud rate generator */
438 if (value >= 0x01) {
439 s->r[offset] = value & 0xFFFF;
440 }
441 break;
442 case R_BDIV: /* Baud rate divider */
443 if (value >= 0x04) {
444 s->r[offset] = value & 0xFF;
445 }
446 break;
447 default:
448 s->r[offset] = value;
449 }
450
451 switch (offset) {
452 case R_CR:
453 uart_ctrl_update(s);
454 break;
455 case R_MR:
456 uart_parameters_setup(s);
457 break;
458 }
459 uart_update_status(s);
460 }
461
462 static uint64_t uart_read(void *opaque, hwaddr offset,
463 unsigned size)
464 {
465 CadenceUARTState *s = opaque;
466 uint32_t c = 0;
467
468 offset >>= 2;
469 if (offset >= CADENCE_UART_R_MAX) {
470 c = 0;
471 } else if (offset == R_TX_RX) {
472 uart_read_rx_fifo(s, &c);
473 } else {
474 c = s->r[offset];
475 }
476
477 DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c);
478 return c;
479 }
480
481 static const MemoryRegionOps uart_ops = {
482 .read = uart_read,
483 .write = uart_write,
484 .endianness = DEVICE_NATIVE_ENDIAN,
485 };
486
487 static void cadence_uart_reset_init(Object *obj, ResetType type)
488 {
489 CadenceUARTState *s = CADENCE_UART(obj);
490
491 s->r[R_CR] = 0x00000128;
492 s->r[R_IMR] = 0;
493 s->r[R_CISR] = 0;
494 s->r[R_RTRIG] = 0x00000020;
495 s->r[R_BRGR] = 0x0000028B;
496 s->r[R_BDIV] = 0x0000000F;
497 s->r[R_TTRIG] = 0x00000020;
498 }
499
500 static void cadence_uart_reset_hold(Object *obj)
501 {
502 CadenceUARTState *s = CADENCE_UART(obj);
503
504 uart_rx_reset(s);
505 uart_tx_reset(s);
506
507 uart_update_status(s);
508 }
509
510 static void cadence_uart_realize(DeviceState *dev, Error **errp)
511 {
512 CadenceUARTState *s = CADENCE_UART(dev);
513
514 s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
515 fifo_trigger_update, s);
516
517 qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive,
518 uart_event, NULL, s, NULL, true);
519 }
520
521 static void cadence_uart_refclk_update(void *opaque)
522 {
523 CadenceUARTState *s = opaque;
524
525 /* recompute uart's speed on clock change */
526 uart_parameters_setup(s);
527 }
528
529 static void cadence_uart_init(Object *obj)
530 {
531 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
532 CadenceUARTState *s = CADENCE_UART(obj);
533
534 memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000);
535 sysbus_init_mmio(sbd, &s->iomem);
536 sysbus_init_irq(sbd, &s->irq);
537
538 s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk",
539 cadence_uart_refclk_update, s);
540 /* initialize the frequency in case the clock remains unconnected */
541 clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK);
542
543 s->char_tx_time = (NANOSECONDS_PER_SECOND / 9600) * 10;
544 }
545
546 static int cadence_uart_pre_load(void *opaque)
547 {
548 CadenceUARTState *s = opaque;
549
550 /* the frequency will be overriden if the refclk field is present */
551 clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK);
552 return 0;
553 }
554
555 static int cadence_uart_post_load(void *opaque, int version_id)
556 {
557 CadenceUARTState *s = opaque;
558
559 /* Ensure these two aren't invalid numbers */
560 if (s->r[R_BRGR] < 1 || s->r[R_BRGR] & ~0xFFFF ||
561 s->r[R_BDIV] <= 3 || s->r[R_BDIV] & ~0xFF) {
562 /* Value is invalid, abort */
563 return 1;
564 }
565
566 uart_parameters_setup(s);
567 uart_update_status(s);
568 return 0;
569 }
570
571 static const VMStateDescription vmstate_cadence_uart = {
572 .name = "cadence_uart",
573 .version_id = 3,
574 .minimum_version_id = 2,
575 .pre_load = cadence_uart_pre_load,
576 .post_load = cadence_uart_post_load,
577 .fields = (VMStateField[]) {
578 VMSTATE_UINT32_ARRAY(r, CadenceUARTState, CADENCE_UART_R_MAX),
579 VMSTATE_UINT8_ARRAY(rx_fifo, CadenceUARTState,
580 CADENCE_UART_RX_FIFO_SIZE),
581 VMSTATE_UINT8_ARRAY(tx_fifo, CadenceUARTState,
582 CADENCE_UART_TX_FIFO_SIZE),
583 VMSTATE_UINT32(rx_count, CadenceUARTState),
584 VMSTATE_UINT32(tx_count, CadenceUARTState),
585 VMSTATE_UINT32(rx_wpos, CadenceUARTState),
586 VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState),
587 VMSTATE_CLOCK_V(refclk, CadenceUARTState, 3),
588 VMSTATE_END_OF_LIST()
589 },
590 };
591
592 static Property cadence_uart_properties[] = {
593 DEFINE_PROP_CHR("chardev", CadenceUARTState, chr),
594 DEFINE_PROP_END_OF_LIST(),
595 };
596
597 static void cadence_uart_class_init(ObjectClass *klass, void *data)
598 {
599 DeviceClass *dc = DEVICE_CLASS(klass);
600 ResettableClass *rc = RESETTABLE_CLASS(klass);
601
602 dc->realize = cadence_uart_realize;
603 dc->vmsd = &vmstate_cadence_uart;
604 rc->phases.enter = cadence_uart_reset_init;
605 rc->phases.hold = cadence_uart_reset_hold;
606 device_class_set_props(dc, cadence_uart_properties);
607 }
608
609 static const TypeInfo cadence_uart_info = {
610 .name = TYPE_CADENCE_UART,
611 .parent = TYPE_SYS_BUS_DEVICE,
612 .instance_size = sizeof(CadenceUARTState),
613 .instance_init = cadence_uart_init,
614 .class_init = cadence_uart_class_init,
615 };
616
617 static void cadence_uart_register_types(void)
618 {
619 type_register_static(&cadence_uart_info);
620 }
621
622 type_init(cadence_uart_register_types)