pcie_aer: support configurable AER capa version
[qemu.git] / hw / char / etraxfs_ser.c
1 /*
2 * QEMU ETRAX System Emulator
3 *
4 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "hw/sysbus.h"
27 #include "sysemu/char.h"
28 #include "qemu/log.h"
29
30 #define D(x)
31
32 #define RW_TR_CTRL (0x00 / 4)
33 #define RW_TR_DMA_EN (0x04 / 4)
34 #define RW_REC_CTRL (0x08 / 4)
35 #define RW_DOUT (0x1c / 4)
36 #define RS_STAT_DIN (0x20 / 4)
37 #define R_STAT_DIN (0x24 / 4)
38 #define RW_INTR_MASK (0x2c / 4)
39 #define RW_ACK_INTR (0x30 / 4)
40 #define R_INTR (0x34 / 4)
41 #define R_MASKED_INTR (0x38 / 4)
42 #define R_MAX (0x3c / 4)
43
44 #define STAT_DAV 16
45 #define STAT_TR_IDLE 22
46 #define STAT_TR_RDY 24
47
48 #define TYPE_ETRAX_FS_SERIAL "etraxfs,serial"
49 #define ETRAX_SERIAL(obj) \
50 OBJECT_CHECK(ETRAXSerial, (obj), TYPE_ETRAX_FS_SERIAL)
51
52 typedef struct ETRAXSerial {
53 SysBusDevice parent_obj;
54
55 MemoryRegion mmio;
56 CharBackend chr;
57 qemu_irq irq;
58
59 int pending_tx;
60
61 uint8_t rx_fifo[16];
62 unsigned int rx_fifo_pos;
63 unsigned int rx_fifo_len;
64
65 /* Control registers. */
66 uint32_t regs[R_MAX];
67 } ETRAXSerial;
68
69 static void ser_update_irq(ETRAXSerial *s)
70 {
71
72 if (s->rx_fifo_len) {
73 s->regs[R_INTR] |= 8;
74 } else {
75 s->regs[R_INTR] &= ~8;
76 }
77
78 s->regs[R_MASKED_INTR] = s->regs[R_INTR] & s->regs[RW_INTR_MASK];
79 qemu_set_irq(s->irq, !!s->regs[R_MASKED_INTR]);
80 }
81
82 static uint64_t
83 ser_read(void *opaque, hwaddr addr, unsigned int size)
84 {
85 ETRAXSerial *s = opaque;
86 uint32_t r = 0;
87
88 addr >>= 2;
89 switch (addr)
90 {
91 case R_STAT_DIN:
92 r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15];
93 if (s->rx_fifo_len) {
94 r |= 1 << STAT_DAV;
95 }
96 r |= 1 << STAT_TR_RDY;
97 r |= 1 << STAT_TR_IDLE;
98 break;
99 case RS_STAT_DIN:
100 r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15];
101 if (s->rx_fifo_len) {
102 r |= 1 << STAT_DAV;
103 s->rx_fifo_len--;
104 }
105 r |= 1 << STAT_TR_RDY;
106 r |= 1 << STAT_TR_IDLE;
107 break;
108 default:
109 r = s->regs[addr];
110 D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, r));
111 break;
112 }
113 return r;
114 }
115
116 static void
117 ser_write(void *opaque, hwaddr addr,
118 uint64_t val64, unsigned int size)
119 {
120 ETRAXSerial *s = opaque;
121 uint32_t value = val64;
122 unsigned char ch = val64;
123
124 D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, value));
125 addr >>= 2;
126 switch (addr)
127 {
128 case RW_DOUT:
129 /* XXX this blocks entire thread. Rewrite to use
130 * qemu_chr_fe_write and background I/O callbacks */
131 qemu_chr_fe_write_all(&s->chr, &ch, 1);
132 s->regs[R_INTR] |= 3;
133 s->pending_tx = 1;
134 s->regs[addr] = value;
135 break;
136 case RW_ACK_INTR:
137 if (s->pending_tx) {
138 value &= ~1;
139 s->pending_tx = 0;
140 D(qemu_log("fixedup value=%x r_intr=%x\n",
141 value, s->regs[R_INTR]));
142 }
143 s->regs[addr] = value;
144 s->regs[R_INTR] &= ~value;
145 D(printf("r_intr=%x\n", s->regs[R_INTR]));
146 break;
147 default:
148 s->regs[addr] = value;
149 break;
150 }
151 ser_update_irq(s);
152 }
153
154 static const MemoryRegionOps ser_ops = {
155 .read = ser_read,
156 .write = ser_write,
157 .endianness = DEVICE_NATIVE_ENDIAN,
158 .valid = {
159 .min_access_size = 4,
160 .max_access_size = 4
161 }
162 };
163
164 static Property etraxfs_ser_properties[] = {
165 DEFINE_PROP_CHR("chardev", ETRAXSerial, chr),
166 DEFINE_PROP_END_OF_LIST(),
167 };
168
169 static void serial_receive(void *opaque, const uint8_t *buf, int size)
170 {
171 ETRAXSerial *s = opaque;
172 int i;
173
174 /* Got a byte. */
175 if (s->rx_fifo_len >= 16) {
176 D(qemu_log("WARNING: UART dropped char.\n"));
177 return;
178 }
179
180 for (i = 0; i < size; i++) {
181 s->rx_fifo[s->rx_fifo_pos] = buf[i];
182 s->rx_fifo_pos++;
183 s->rx_fifo_pos &= 15;
184 s->rx_fifo_len++;
185 }
186
187 ser_update_irq(s);
188 }
189
190 static int serial_can_receive(void *opaque)
191 {
192 ETRAXSerial *s = opaque;
193
194 /* Is the receiver enabled? */
195 if (!(s->regs[RW_REC_CTRL] & (1 << 3))) {
196 return 0;
197 }
198
199 return sizeof(s->rx_fifo) - s->rx_fifo_len;
200 }
201
202 static void serial_event(void *opaque, int event)
203 {
204
205 }
206
207 static void etraxfs_ser_reset(DeviceState *d)
208 {
209 ETRAXSerial *s = ETRAX_SERIAL(d);
210
211 /* transmitter begins ready and idle. */
212 s->regs[RS_STAT_DIN] |= (1 << STAT_TR_RDY);
213 s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE);
214
215 s->regs[RW_REC_CTRL] = 0x10000;
216
217 }
218
219 static void etraxfs_ser_init(Object *obj)
220 {
221 ETRAXSerial *s = ETRAX_SERIAL(obj);
222 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
223
224 sysbus_init_irq(dev, &s->irq);
225 memory_region_init_io(&s->mmio, obj, &ser_ops, s,
226 "etraxfs-serial", R_MAX * 4);
227 sysbus_init_mmio(dev, &s->mmio);
228 }
229
230 static void etraxfs_ser_realize(DeviceState *dev, Error **errp)
231 {
232 ETRAXSerial *s = ETRAX_SERIAL(dev);
233
234 qemu_chr_fe_set_handlers(&s->chr,
235 serial_can_receive, serial_receive,
236 serial_event, s, NULL, true);
237 }
238
239 static void etraxfs_ser_class_init(ObjectClass *klass, void *data)
240 {
241 DeviceClass *dc = DEVICE_CLASS(klass);
242
243 dc->reset = etraxfs_ser_reset;
244 dc->props = etraxfs_ser_properties;
245 dc->realize = etraxfs_ser_realize;
246 }
247
248 static const TypeInfo etraxfs_ser_info = {
249 .name = TYPE_ETRAX_FS_SERIAL,
250 .parent = TYPE_SYS_BUS_DEVICE,
251 .instance_size = sizeof(ETRAXSerial),
252 .instance_init = etraxfs_ser_init,
253 .class_init = etraxfs_ser_class_init,
254 };
255
256 static void etraxfs_serial_register_types(void)
257 {
258 type_register_static(&etraxfs_ser_info);
259 }
260
261 type_init(etraxfs_serial_register_types)