pcie_aer: support configurable AER capa version
[qemu.git] / hw / char / exynos4210_uart.c
1 /*
2 * Exynos4210 UART Emulation
3 *
4 * Copyright (C) 2011 Samsung Electronics Co Ltd.
5 * Maksim Kozlov, <m.kozlov@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 *
20 */
21
22 #include "qemu/osdep.h"
23 #include "hw/sysbus.h"
24 #include "qemu/error-report.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/char.h"
27
28 #include "hw/arm/exynos4210.h"
29
30 #undef DEBUG_UART
31 #undef DEBUG_UART_EXTEND
32 #undef DEBUG_IRQ
33 #undef DEBUG_Rx_DATA
34 #undef DEBUG_Tx_DATA
35
36 #define DEBUG_UART 0
37 #define DEBUG_UART_EXTEND 0
38 #define DEBUG_IRQ 0
39 #define DEBUG_Rx_DATA 0
40 #define DEBUG_Tx_DATA 0
41
42 #if DEBUG_UART
43 #define PRINT_DEBUG(fmt, args...) \
44 do { \
45 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
46 } while (0)
47
48 #if DEBUG_UART_EXTEND
49 #define PRINT_DEBUG_EXTEND(fmt, args...) \
50 do { \
51 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
52 } while (0)
53 #else
54 #define PRINT_DEBUG_EXTEND(fmt, args...) \
55 do {} while (0)
56 #endif /* EXTEND */
57
58 #else
59 #define PRINT_DEBUG(fmt, args...) \
60 do {} while (0)
61 #define PRINT_DEBUG_EXTEND(fmt, args...) \
62 do {} while (0)
63 #endif
64
65 #define PRINT_ERROR(fmt, args...) \
66 do { \
67 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
68 } while (0)
69
70 /*
71 * Offsets for UART registers relative to SFR base address
72 * for UARTn
73 *
74 */
75 #define ULCON 0x0000 /* Line Control */
76 #define UCON 0x0004 /* Control */
77 #define UFCON 0x0008 /* FIFO Control */
78 #define UMCON 0x000C /* Modem Control */
79 #define UTRSTAT 0x0010 /* Tx/Rx Status */
80 #define UERSTAT 0x0014 /* UART Error Status */
81 #define UFSTAT 0x0018 /* FIFO Status */
82 #define UMSTAT 0x001C /* Modem Status */
83 #define UTXH 0x0020 /* Transmit Buffer */
84 #define URXH 0x0024 /* Receive Buffer */
85 #define UBRDIV 0x0028 /* Baud Rate Divisor */
86 #define UFRACVAL 0x002C /* Divisor Fractional Value */
87 #define UINTP 0x0030 /* Interrupt Pending */
88 #define UINTSP 0x0034 /* Interrupt Source Pending */
89 #define UINTM 0x0038 /* Interrupt Mask */
90
91 /*
92 * for indexing register in the uint32_t array
93 *
94 * 'reg' - register offset (see offsets definitions above)
95 *
96 */
97 #define I_(reg) (reg / sizeof(uint32_t))
98
99 typedef struct Exynos4210UartReg {
100 const char *name; /* the only reason is the debug output */
101 hwaddr offset;
102 uint32_t reset_value;
103 } Exynos4210UartReg;
104
105 static Exynos4210UartReg exynos4210_uart_regs[] = {
106 {"ULCON", ULCON, 0x00000000},
107 {"UCON", UCON, 0x00003000},
108 {"UFCON", UFCON, 0x00000000},
109 {"UMCON", UMCON, 0x00000000},
110 {"UTRSTAT", UTRSTAT, 0x00000006}, /* RO */
111 {"UERSTAT", UERSTAT, 0x00000000}, /* RO */
112 {"UFSTAT", UFSTAT, 0x00000000}, /* RO */
113 {"UMSTAT", UMSTAT, 0x00000000}, /* RO */
114 {"UTXH", UTXH, 0x5c5c5c5c}, /* WO, undefined reset value*/
115 {"URXH", URXH, 0x00000000}, /* RO */
116 {"UBRDIV", UBRDIV, 0x00000000},
117 {"UFRACVAL", UFRACVAL, 0x00000000},
118 {"UINTP", UINTP, 0x00000000},
119 {"UINTSP", UINTSP, 0x00000000},
120 {"UINTM", UINTM, 0x00000000},
121 };
122
123 #define EXYNOS4210_UART_REGS_MEM_SIZE 0x3C
124
125 /* UART FIFO Control */
126 #define UFCON_FIFO_ENABLE 0x1
127 #define UFCON_Rx_FIFO_RESET 0x2
128 #define UFCON_Tx_FIFO_RESET 0x4
129 #define UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT 8
130 #define UFCON_Tx_FIFO_TRIGGER_LEVEL (7 << UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT)
131 #define UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT 4
132 #define UFCON_Rx_FIFO_TRIGGER_LEVEL (7 << UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT)
133
134 /* Uart FIFO Status */
135 #define UFSTAT_Rx_FIFO_COUNT 0xff
136 #define UFSTAT_Rx_FIFO_FULL 0x100
137 #define UFSTAT_Rx_FIFO_ERROR 0x200
138 #define UFSTAT_Tx_FIFO_COUNT_SHIFT 16
139 #define UFSTAT_Tx_FIFO_COUNT (0xff << UFSTAT_Tx_FIFO_COUNT_SHIFT)
140 #define UFSTAT_Tx_FIFO_FULL_SHIFT 24
141 #define UFSTAT_Tx_FIFO_FULL (1 << UFSTAT_Tx_FIFO_FULL_SHIFT)
142
143 /* UART Interrupt Source Pending */
144 #define UINTSP_RXD 0x1 /* Receive interrupt */
145 #define UINTSP_ERROR 0x2 /* Error interrupt */
146 #define UINTSP_TXD 0x4 /* Transmit interrupt */
147 #define UINTSP_MODEM 0x8 /* Modem interrupt */
148
149 /* UART Line Control */
150 #define ULCON_IR_MODE_SHIFT 6
151 #define ULCON_PARITY_SHIFT 3
152 #define ULCON_STOP_BIT_SHIFT 1
153
154 /* UART Tx/Rx Status */
155 #define UTRSTAT_TRANSMITTER_EMPTY 0x4
156 #define UTRSTAT_Tx_BUFFER_EMPTY 0x2
157 #define UTRSTAT_Rx_BUFFER_DATA_READY 0x1
158
159 /* UART Error Status */
160 #define UERSTAT_OVERRUN 0x1
161 #define UERSTAT_PARITY 0x2
162 #define UERSTAT_FRAME 0x4
163 #define UERSTAT_BREAK 0x8
164
165 typedef struct {
166 uint8_t *data;
167 uint32_t sp, rp; /* store and retrieve pointers */
168 uint32_t size;
169 } Exynos4210UartFIFO;
170
171 #define TYPE_EXYNOS4210_UART "exynos4210.uart"
172 #define EXYNOS4210_UART(obj) \
173 OBJECT_CHECK(Exynos4210UartState, (obj), TYPE_EXYNOS4210_UART)
174
175 typedef struct Exynos4210UartState {
176 SysBusDevice parent_obj;
177
178 MemoryRegion iomem;
179
180 uint32_t reg[EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)];
181 Exynos4210UartFIFO rx;
182 Exynos4210UartFIFO tx;
183
184 CharBackend chr;
185 qemu_irq irq;
186
187 uint32_t channel;
188
189 } Exynos4210UartState;
190
191
192 #if DEBUG_UART
193 /* Used only for debugging inside PRINT_DEBUG_... macros */
194 static const char *exynos4210_uart_regname(hwaddr offset)
195 {
196
197 int i;
198
199 for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) {
200 if (offset == exynos4210_uart_regs[i].offset) {
201 return exynos4210_uart_regs[i].name;
202 }
203 }
204
205 return NULL;
206 }
207 #endif
208
209
210 static void fifo_store(Exynos4210UartFIFO *q, uint8_t ch)
211 {
212 q->data[q->sp] = ch;
213 q->sp = (q->sp + 1) % q->size;
214 }
215
216 static uint8_t fifo_retrieve(Exynos4210UartFIFO *q)
217 {
218 uint8_t ret = q->data[q->rp];
219 q->rp = (q->rp + 1) % q->size;
220 return ret;
221 }
222
223 static int fifo_elements_number(Exynos4210UartFIFO *q)
224 {
225 if (q->sp < q->rp) {
226 return q->size - q->rp + q->sp;
227 }
228
229 return q->sp - q->rp;
230 }
231
232 static int fifo_empty_elements_number(Exynos4210UartFIFO *q)
233 {
234 return q->size - fifo_elements_number(q);
235 }
236
237 static void fifo_reset(Exynos4210UartFIFO *q)
238 {
239 g_free(q->data);
240 q->data = NULL;
241
242 q->data = (uint8_t *)g_malloc0(q->size);
243
244 q->sp = 0;
245 q->rp = 0;
246 }
247
248 static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(Exynos4210UartState *s)
249 {
250 uint32_t level = 0;
251 uint32_t reg;
252
253 reg = (s->reg[I_(UFCON)] & UFCON_Tx_FIFO_TRIGGER_LEVEL) >>
254 UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT;
255
256 switch (s->channel) {
257 case 0:
258 level = reg * 32;
259 break;
260 case 1:
261 case 4:
262 level = reg * 8;
263 break;
264 case 2:
265 case 3:
266 level = reg * 2;
267 break;
268 default:
269 level = 0;
270 PRINT_ERROR("Wrong UART channel number: %d\n", s->channel);
271 }
272
273 return level;
274 }
275
276 static void exynos4210_uart_update_irq(Exynos4210UartState *s)
277 {
278 /*
279 * The Tx interrupt is always requested if the number of data in the
280 * transmit FIFO is smaller than the trigger level.
281 */
282 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
283
284 uint32_t count = (s->reg[I_(UFSTAT)] & UFSTAT_Tx_FIFO_COUNT) >>
285 UFSTAT_Tx_FIFO_COUNT_SHIFT;
286
287 if (count <= exynos4210_uart_Tx_FIFO_trigger_level(s)) {
288 s->reg[I_(UINTSP)] |= UINTSP_TXD;
289 }
290 }
291
292 s->reg[I_(UINTP)] = s->reg[I_(UINTSP)] & ~s->reg[I_(UINTM)];
293
294 if (s->reg[I_(UINTP)]) {
295 qemu_irq_raise(s->irq);
296
297 #if DEBUG_IRQ
298 fprintf(stderr, "UART%d: IRQ has been raised: %08x\n",
299 s->channel, s->reg[I_(UINTP)]);
300 #endif
301
302 } else {
303 qemu_irq_lower(s->irq);
304 }
305 }
306
307 static void exynos4210_uart_update_parameters(Exynos4210UartState *s)
308 {
309 int speed, parity, data_bits, stop_bits, frame_size;
310 QEMUSerialSetParams ssp;
311 uint64_t uclk_rate;
312
313 if (s->reg[I_(UBRDIV)] == 0) {
314 return;
315 }
316
317 frame_size = 1; /* start bit */
318 if (s->reg[I_(ULCON)] & 0x20) {
319 frame_size++; /* parity bit */
320 if (s->reg[I_(ULCON)] & 0x28) {
321 parity = 'E';
322 } else {
323 parity = 'O';
324 }
325 } else {
326 parity = 'N';
327 }
328
329 if (s->reg[I_(ULCON)] & 0x4) {
330 stop_bits = 2;
331 } else {
332 stop_bits = 1;
333 }
334
335 data_bits = (s->reg[I_(ULCON)] & 0x3) + 5;
336
337 frame_size += data_bits + stop_bits;
338
339 uclk_rate = 24000000;
340
341 speed = uclk_rate / ((16 * (s->reg[I_(UBRDIV)]) & 0xffff) +
342 (s->reg[I_(UFRACVAL)] & 0x7) + 16);
343
344 ssp.speed = speed;
345 ssp.parity = parity;
346 ssp.data_bits = data_bits;
347 ssp.stop_bits = stop_bits;
348
349 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
350
351 PRINT_DEBUG("UART%d: speed: %d, parity: %c, data: %d, stop: %d\n",
352 s->channel, speed, parity, data_bits, stop_bits);
353 }
354
355 static void exynos4210_uart_write(void *opaque, hwaddr offset,
356 uint64_t val, unsigned size)
357 {
358 Exynos4210UartState *s = (Exynos4210UartState *)opaque;
359 uint8_t ch;
360
361 PRINT_DEBUG_EXTEND("UART%d: <0x%04x> %s <- 0x%08llx\n", s->channel,
362 offset, exynos4210_uart_regname(offset), (long long unsigned int)val);
363
364 switch (offset) {
365 case ULCON:
366 case UBRDIV:
367 case UFRACVAL:
368 s->reg[I_(offset)] = val;
369 exynos4210_uart_update_parameters(s);
370 break;
371 case UFCON:
372 s->reg[I_(UFCON)] = val;
373 if (val & UFCON_Rx_FIFO_RESET) {
374 fifo_reset(&s->rx);
375 s->reg[I_(UFCON)] &= ~UFCON_Rx_FIFO_RESET;
376 PRINT_DEBUG("UART%d: Rx FIFO Reset\n", s->channel);
377 }
378 if (val & UFCON_Tx_FIFO_RESET) {
379 fifo_reset(&s->tx);
380 s->reg[I_(UFCON)] &= ~UFCON_Tx_FIFO_RESET;
381 PRINT_DEBUG("UART%d: Tx FIFO Reset\n", s->channel);
382 }
383 break;
384
385 case UTXH:
386 if (qemu_chr_fe_get_driver(&s->chr)) {
387 s->reg[I_(UTRSTAT)] &= ~(UTRSTAT_TRANSMITTER_EMPTY |
388 UTRSTAT_Tx_BUFFER_EMPTY);
389 ch = (uint8_t)val;
390 /* XXX this blocks entire thread. Rewrite to use
391 * qemu_chr_fe_write and background I/O callbacks */
392 qemu_chr_fe_write_all(&s->chr, &ch, 1);
393 #if DEBUG_Tx_DATA
394 fprintf(stderr, "%c", ch);
395 #endif
396 s->reg[I_(UTRSTAT)] |= UTRSTAT_TRANSMITTER_EMPTY |
397 UTRSTAT_Tx_BUFFER_EMPTY;
398 s->reg[I_(UINTSP)] |= UINTSP_TXD;
399 exynos4210_uart_update_irq(s);
400 }
401 break;
402
403 case UINTP:
404 s->reg[I_(UINTP)] &= ~val;
405 s->reg[I_(UINTSP)] &= ~val;
406 PRINT_DEBUG("UART%d: UINTP [%04x] have been cleared: %08x\n",
407 s->channel, offset, s->reg[I_(UINTP)]);
408 exynos4210_uart_update_irq(s);
409 break;
410 case UTRSTAT:
411 case UERSTAT:
412 case UFSTAT:
413 case UMSTAT:
414 case URXH:
415 PRINT_DEBUG("UART%d: Trying to write into RO register: %s [%04x]\n",
416 s->channel, exynos4210_uart_regname(offset), offset);
417 break;
418 case UINTSP:
419 s->reg[I_(UINTSP)] &= ~val;
420 break;
421 case UINTM:
422 s->reg[I_(UINTM)] = val;
423 exynos4210_uart_update_irq(s);
424 break;
425 case UCON:
426 case UMCON:
427 default:
428 s->reg[I_(offset)] = val;
429 break;
430 }
431 }
432 static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset,
433 unsigned size)
434 {
435 Exynos4210UartState *s = (Exynos4210UartState *)opaque;
436 uint32_t res;
437
438 switch (offset) {
439 case UERSTAT: /* Read Only */
440 res = s->reg[I_(UERSTAT)];
441 s->reg[I_(UERSTAT)] = 0;
442 return res;
443 case UFSTAT: /* Read Only */
444 s->reg[I_(UFSTAT)] = fifo_elements_number(&s->rx) & 0xff;
445 if (fifo_empty_elements_number(&s->rx) == 0) {
446 s->reg[I_(UFSTAT)] |= UFSTAT_Rx_FIFO_FULL;
447 s->reg[I_(UFSTAT)] &= ~0xff;
448 }
449 return s->reg[I_(UFSTAT)];
450 case URXH:
451 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
452 if (fifo_elements_number(&s->rx)) {
453 res = fifo_retrieve(&s->rx);
454 #if DEBUG_Rx_DATA
455 fprintf(stderr, "%c", res);
456 #endif
457 if (!fifo_elements_number(&s->rx)) {
458 s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY;
459 } else {
460 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
461 }
462 } else {
463 s->reg[I_(UINTSP)] |= UINTSP_ERROR;
464 exynos4210_uart_update_irq(s);
465 res = 0;
466 }
467 } else {
468 s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY;
469 res = s->reg[I_(URXH)];
470 }
471 return res;
472 case UTXH:
473 PRINT_DEBUG("UART%d: Trying to read from WO register: %s [%04x]\n",
474 s->channel, exynos4210_uart_regname(offset), offset);
475 break;
476 default:
477 return s->reg[I_(offset)];
478 }
479
480 return 0;
481 }
482
483 static const MemoryRegionOps exynos4210_uart_ops = {
484 .read = exynos4210_uart_read,
485 .write = exynos4210_uart_write,
486 .endianness = DEVICE_NATIVE_ENDIAN,
487 .valid = {
488 .max_access_size = 4,
489 .unaligned = false
490 },
491 };
492
493 static int exynos4210_uart_can_receive(void *opaque)
494 {
495 Exynos4210UartState *s = (Exynos4210UartState *)opaque;
496
497 return fifo_empty_elements_number(&s->rx);
498 }
499
500
501 static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size)
502 {
503 Exynos4210UartState *s = (Exynos4210UartState *)opaque;
504 int i;
505
506 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
507 if (fifo_empty_elements_number(&s->rx) < size) {
508 for (i = 0; i < fifo_empty_elements_number(&s->rx); i++) {
509 fifo_store(&s->rx, buf[i]);
510 }
511 s->reg[I_(UINTSP)] |= UINTSP_ERROR;
512 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
513 } else {
514 for (i = 0; i < size; i++) {
515 fifo_store(&s->rx, buf[i]);
516 }
517 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
518 }
519 /* XXX: Around here we maybe should check Rx trigger level */
520 s->reg[I_(UINTSP)] |= UINTSP_RXD;
521 } else {
522 s->reg[I_(URXH)] = buf[0];
523 s->reg[I_(UINTSP)] |= UINTSP_RXD;
524 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
525 }
526
527 exynos4210_uart_update_irq(s);
528 }
529
530
531 static void exynos4210_uart_event(void *opaque, int event)
532 {
533 Exynos4210UartState *s = (Exynos4210UartState *)opaque;
534
535 if (event == CHR_EVENT_BREAK) {
536 /* When the RxDn is held in logic 0, then a null byte is pushed into the
537 * fifo */
538 fifo_store(&s->rx, '\0');
539 s->reg[I_(UERSTAT)] |= UERSTAT_BREAK;
540 exynos4210_uart_update_irq(s);
541 }
542 }
543
544
545 static void exynos4210_uart_reset(DeviceState *dev)
546 {
547 Exynos4210UartState *s = EXYNOS4210_UART(dev);
548 int i;
549
550 for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) {
551 s->reg[I_(exynos4210_uart_regs[i].offset)] =
552 exynos4210_uart_regs[i].reset_value;
553 }
554
555 fifo_reset(&s->rx);
556 fifo_reset(&s->tx);
557
558 PRINT_DEBUG("UART%d: Rx FIFO size: %d\n", s->channel, s->rx.size);
559 }
560
561 static const VMStateDescription vmstate_exynos4210_uart_fifo = {
562 .name = "exynos4210.uart.fifo",
563 .version_id = 1,
564 .minimum_version_id = 1,
565 .fields = (VMStateField[]) {
566 VMSTATE_UINT32(sp, Exynos4210UartFIFO),
567 VMSTATE_UINT32(rp, Exynos4210UartFIFO),
568 VMSTATE_VBUFFER_UINT32(data, Exynos4210UartFIFO, 1, NULL, 0, size),
569 VMSTATE_END_OF_LIST()
570 }
571 };
572
573 static const VMStateDescription vmstate_exynos4210_uart = {
574 .name = "exynos4210.uart",
575 .version_id = 1,
576 .minimum_version_id = 1,
577 .fields = (VMStateField[]) {
578 VMSTATE_STRUCT(rx, Exynos4210UartState, 1,
579 vmstate_exynos4210_uart_fifo, Exynos4210UartFIFO),
580 VMSTATE_UINT32_ARRAY(reg, Exynos4210UartState,
581 EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)),
582 VMSTATE_END_OF_LIST()
583 }
584 };
585
586 DeviceState *exynos4210_uart_create(hwaddr addr,
587 int fifo_size,
588 int channel,
589 CharDriverState *chr,
590 qemu_irq irq)
591 {
592 DeviceState *dev;
593 SysBusDevice *bus;
594
595 const char chr_name[] = "serial";
596 char label[ARRAY_SIZE(chr_name) + 1];
597
598 dev = qdev_create(NULL, TYPE_EXYNOS4210_UART);
599
600 if (!chr) {
601 if (channel >= MAX_SERIAL_PORTS) {
602 error_report("Only %d serial ports are supported by QEMU",
603 MAX_SERIAL_PORTS);
604 exit(1);
605 }
606 chr = serial_hds[channel];
607 if (!chr) {
608 snprintf(label, ARRAY_SIZE(label), "%s%d", chr_name, channel);
609 chr = qemu_chr_new(label, "null");
610 if (!(chr)) {
611 error_report("Can't assign serial port to UART%d", channel);
612 exit(1);
613 }
614 }
615 }
616
617 qdev_prop_set_chr(dev, "chardev", chr);
618 qdev_prop_set_uint32(dev, "channel", channel);
619 qdev_prop_set_uint32(dev, "rx-size", fifo_size);
620 qdev_prop_set_uint32(dev, "tx-size", fifo_size);
621
622 bus = SYS_BUS_DEVICE(dev);
623 qdev_init_nofail(dev);
624 if (addr != (hwaddr)-1) {
625 sysbus_mmio_map(bus, 0, addr);
626 }
627 sysbus_connect_irq(bus, 0, irq);
628
629 return dev;
630 }
631
632 static void exynos4210_uart_init(Object *obj)
633 {
634 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
635 Exynos4210UartState *s = EXYNOS4210_UART(dev);
636
637 /* memory mapping */
638 memory_region_init_io(&s->iomem, obj, &exynos4210_uart_ops, s,
639 "exynos4210.uart", EXYNOS4210_UART_REGS_MEM_SIZE);
640 sysbus_init_mmio(dev, &s->iomem);
641
642 sysbus_init_irq(dev, &s->irq);
643 }
644
645 static void exynos4210_uart_realize(DeviceState *dev, Error **errp)
646 {
647 Exynos4210UartState *s = EXYNOS4210_UART(dev);
648
649 qemu_chr_fe_set_handlers(&s->chr, exynos4210_uart_can_receive,
650 exynos4210_uart_receive, exynos4210_uart_event,
651 s, NULL, true);
652 }
653
654 static Property exynos4210_uart_properties[] = {
655 DEFINE_PROP_CHR("chardev", Exynos4210UartState, chr),
656 DEFINE_PROP_UINT32("channel", Exynos4210UartState, channel, 0),
657 DEFINE_PROP_UINT32("rx-size", Exynos4210UartState, rx.size, 16),
658 DEFINE_PROP_UINT32("tx-size", Exynos4210UartState, tx.size, 16),
659 DEFINE_PROP_END_OF_LIST(),
660 };
661
662 static void exynos4210_uart_class_init(ObjectClass *klass, void *data)
663 {
664 DeviceClass *dc = DEVICE_CLASS(klass);
665
666 dc->realize = exynos4210_uart_realize;
667 dc->reset = exynos4210_uart_reset;
668 dc->props = exynos4210_uart_properties;
669 dc->vmsd = &vmstate_exynos4210_uart;
670 }
671
672 static const TypeInfo exynos4210_uart_info = {
673 .name = TYPE_EXYNOS4210_UART,
674 .parent = TYPE_SYS_BUS_DEVICE,
675 .instance_size = sizeof(Exynos4210UartState),
676 .instance_init = exynos4210_uart_init,
677 .class_init = exynos4210_uart_class_init,
678 };
679
680 static void exynos4210_uart_register(void)
681 {
682 type_register_static(&exynos4210_uart_info);
683 }
684
685 type_init(exynos4210_uart_register)