pcie_aer: support configurable AER capa version
[qemu.git] / hw / char / ipoctal232.c
1 /*
2 * QEMU GE IP-Octal 232 IndustryPack emulation
3 *
4 * Copyright (C) 2012 Igalia, S.L.
5 * Author: Alberto Garcia <berto@igalia.com>
6 *
7 * This code is licensed under the GNU GPL v2 or (at your option) any
8 * later version.
9 */
10
11 #include "qemu/osdep.h"
12 #include "hw/ipack/ipack.h"
13 #include "qemu/bitops.h"
14 #include "sysemu/char.h"
15
16 /* #define DEBUG_IPOCTAL */
17
18 #ifdef DEBUG_IPOCTAL
19 #define DPRINTF2(fmt, ...) \
20 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
21 #else
22 #define DPRINTF2(fmt, ...) do { } while (0)
23 #endif
24
25 #define DPRINTF(fmt, ...) DPRINTF2("IP-Octal: " fmt, ## __VA_ARGS__)
26
27 #define RX_FIFO_SIZE 3
28
29 /* The IP-Octal has 8 channels (a-h)
30 divided into 4 blocks (A-D) */
31 #define N_CHANNELS 8
32 #define N_BLOCKS 4
33
34 #define REG_MRa 0x01
35 #define REG_MRb 0x11
36 #define REG_SRa 0x03
37 #define REG_SRb 0x13
38 #define REG_CSRa 0x03
39 #define REG_CSRb 0x13
40 #define REG_CRa 0x05
41 #define REG_CRb 0x15
42 #define REG_RHRa 0x07
43 #define REG_RHRb 0x17
44 #define REG_THRa 0x07
45 #define REG_THRb 0x17
46 #define REG_ACR 0x09
47 #define REG_ISR 0x0B
48 #define REG_IMR 0x0B
49 #define REG_OPCR 0x1B
50
51 #define CR_ENABLE_RX BIT(0)
52 #define CR_DISABLE_RX BIT(1)
53 #define CR_ENABLE_TX BIT(2)
54 #define CR_DISABLE_TX BIT(3)
55 #define CR_CMD(cr) ((cr) >> 4)
56 #define CR_NO_OP 0
57 #define CR_RESET_MR 1
58 #define CR_RESET_RX 2
59 #define CR_RESET_TX 3
60 #define CR_RESET_ERR 4
61 #define CR_RESET_BRKINT 5
62 #define CR_START_BRK 6
63 #define CR_STOP_BRK 7
64 #define CR_ASSERT_RTSN 8
65 #define CR_NEGATE_RTSN 9
66 #define CR_TIMEOUT_ON 10
67 #define CR_TIMEOUT_OFF 12
68
69 #define SR_RXRDY BIT(0)
70 #define SR_FFULL BIT(1)
71 #define SR_TXRDY BIT(2)
72 #define SR_TXEMT BIT(3)
73 #define SR_OVERRUN BIT(4)
74 #define SR_PARITY BIT(5)
75 #define SR_FRAMING BIT(6)
76 #define SR_BREAK BIT(7)
77
78 #define ISR_TXRDYA BIT(0)
79 #define ISR_RXRDYA BIT(1)
80 #define ISR_BREAKA BIT(2)
81 #define ISR_CNTRDY BIT(3)
82 #define ISR_TXRDYB BIT(4)
83 #define ISR_RXRDYB BIT(5)
84 #define ISR_BREAKB BIT(6)
85 #define ISR_MPICHG BIT(7)
86 #define ISR_TXRDY(CH) (((CH) & 1) ? BIT(4) : BIT(0))
87 #define ISR_RXRDY(CH) (((CH) & 1) ? BIT(5) : BIT(1))
88 #define ISR_BREAK(CH) (((CH) & 1) ? BIT(6) : BIT(2))
89
90 typedef struct IPOctalState IPOctalState;
91 typedef struct SCC2698Channel SCC2698Channel;
92 typedef struct SCC2698Block SCC2698Block;
93
94 struct SCC2698Channel {
95 IPOctalState *ipoctal;
96 CharBackend dev;
97 bool rx_enabled;
98 uint8_t mr[2];
99 uint8_t mr_idx;
100 uint8_t sr;
101 uint8_t rhr[RX_FIFO_SIZE];
102 uint8_t rhr_idx;
103 uint8_t rx_pending;
104 };
105
106 struct SCC2698Block {
107 uint8_t imr;
108 uint8_t isr;
109 };
110
111 struct IPOctalState {
112 IPackDevice parent_obj;
113
114 SCC2698Channel ch[N_CHANNELS];
115 SCC2698Block blk[N_BLOCKS];
116 uint8_t irq_vector;
117 };
118
119 #define TYPE_IPOCTAL "ipoctal232"
120
121 #define IPOCTAL(obj) \
122 OBJECT_CHECK(IPOctalState, (obj), TYPE_IPOCTAL)
123
124 static const VMStateDescription vmstate_scc2698_channel = {
125 .name = "scc2698_channel",
126 .version_id = 1,
127 .minimum_version_id = 1,
128 .fields = (VMStateField[]) {
129 VMSTATE_BOOL(rx_enabled, SCC2698Channel),
130 VMSTATE_UINT8_ARRAY(mr, SCC2698Channel, 2),
131 VMSTATE_UINT8(mr_idx, SCC2698Channel),
132 VMSTATE_UINT8(sr, SCC2698Channel),
133 VMSTATE_UINT8_ARRAY(rhr, SCC2698Channel, RX_FIFO_SIZE),
134 VMSTATE_UINT8(rhr_idx, SCC2698Channel),
135 VMSTATE_UINT8(rx_pending, SCC2698Channel),
136 VMSTATE_END_OF_LIST()
137 }
138 };
139
140 static const VMStateDescription vmstate_scc2698_block = {
141 .name = "scc2698_block",
142 .version_id = 1,
143 .minimum_version_id = 1,
144 .fields = (VMStateField[]) {
145 VMSTATE_UINT8(imr, SCC2698Block),
146 VMSTATE_UINT8(isr, SCC2698Block),
147 VMSTATE_END_OF_LIST()
148 }
149 };
150
151 static const VMStateDescription vmstate_ipoctal = {
152 .name = "ipoctal232",
153 .version_id = 1,
154 .minimum_version_id = 1,
155 .fields = (VMStateField[]) {
156 VMSTATE_IPACK_DEVICE(parent_obj, IPOctalState),
157 VMSTATE_STRUCT_ARRAY(ch, IPOctalState, N_CHANNELS, 1,
158 vmstate_scc2698_channel, SCC2698Channel),
159 VMSTATE_STRUCT_ARRAY(blk, IPOctalState, N_BLOCKS, 1,
160 vmstate_scc2698_block, SCC2698Block),
161 VMSTATE_UINT8(irq_vector, IPOctalState),
162 VMSTATE_END_OF_LIST()
163 }
164 };
165
166 /* data[10] is 0x0C, not 0x0B as the doc says */
167 static const uint8_t id_prom_data[] = {
168 0x49, 0x50, 0x41, 0x43, 0xF0, 0x22,
169 0xA1, 0x00, 0x00, 0x00, 0x0C, 0xCC
170 };
171
172 static void update_irq(IPOctalState *dev, unsigned block)
173 {
174 IPackDevice *idev = IPACK_DEVICE(dev);
175 /* Blocks A and B interrupt on INT0#, C and D on INT1#.
176 Thus, to get the status we have to check two blocks. */
177 SCC2698Block *blk0 = &dev->blk[block];
178 SCC2698Block *blk1 = &dev->blk[block^1];
179 unsigned intno = block / 2;
180
181 if ((blk0->isr & blk0->imr) || (blk1->isr & blk1->imr)) {
182 qemu_irq_raise(idev->irq[intno]);
183 } else {
184 qemu_irq_lower(idev->irq[intno]);
185 }
186 }
187
188 static void write_cr(IPOctalState *dev, unsigned channel, uint8_t val)
189 {
190 SCC2698Channel *ch = &dev->ch[channel];
191 SCC2698Block *blk = &dev->blk[channel / 2];
192
193 DPRINTF("Write CR%c %u: ", channel + 'a', val);
194
195 /* The lower 4 bits are used to enable and disable Tx and Rx */
196 if (val & CR_ENABLE_RX) {
197 DPRINTF2("Rx on, ");
198 ch->rx_enabled = true;
199 }
200 if (val & CR_DISABLE_RX) {
201 DPRINTF2("Rx off, ");
202 ch->rx_enabled = false;
203 }
204 if (val & CR_ENABLE_TX) {
205 DPRINTF2("Tx on, ");
206 ch->sr |= SR_TXRDY | SR_TXEMT;
207 blk->isr |= ISR_TXRDY(channel);
208 }
209 if (val & CR_DISABLE_TX) {
210 DPRINTF2("Tx off, ");
211 ch->sr &= ~(SR_TXRDY | SR_TXEMT);
212 blk->isr &= ~ISR_TXRDY(channel);
213 }
214
215 DPRINTF2("cmd: ");
216
217 /* The rest of the bits implement different commands */
218 switch (CR_CMD(val)) {
219 case CR_NO_OP:
220 DPRINTF2("none");
221 break;
222 case CR_RESET_MR:
223 DPRINTF2("reset MR");
224 ch->mr_idx = 0;
225 break;
226 case CR_RESET_RX:
227 DPRINTF2("reset Rx");
228 ch->rx_enabled = false;
229 ch->rx_pending = 0;
230 ch->sr &= ~SR_RXRDY;
231 blk->isr &= ~ISR_RXRDY(channel);
232 break;
233 case CR_RESET_TX:
234 DPRINTF2("reset Tx");
235 ch->sr &= ~(SR_TXRDY | SR_TXEMT);
236 blk->isr &= ~ISR_TXRDY(channel);
237 break;
238 case CR_RESET_ERR:
239 DPRINTF2("reset err");
240 ch->sr &= ~(SR_OVERRUN | SR_PARITY | SR_FRAMING | SR_BREAK);
241 break;
242 case CR_RESET_BRKINT:
243 DPRINTF2("reset brk ch int");
244 blk->isr &= ~(ISR_BREAKA | ISR_BREAKB);
245 break;
246 default:
247 DPRINTF2("unsupported 0x%x", CR_CMD(val));
248 }
249
250 DPRINTF2("\n");
251 }
252
253 static uint16_t io_read(IPackDevice *ip, uint8_t addr)
254 {
255 IPOctalState *dev = IPOCTAL(ip);
256 uint16_t ret = 0;
257 /* addr[7:6]: block (A-D)
258 addr[7:5]: channel (a-h)
259 addr[5:0]: register */
260 unsigned block = addr >> 5;
261 unsigned channel = addr >> 4;
262 /* Big endian, accessed using 8-bit bytes at odd locations */
263 unsigned offset = (addr & 0x1F) ^ 1;
264 SCC2698Channel *ch = &dev->ch[channel];
265 SCC2698Block *blk = &dev->blk[block];
266 uint8_t old_isr = blk->isr;
267
268 switch (offset) {
269
270 case REG_MRa:
271 case REG_MRb:
272 ret = ch->mr[ch->mr_idx];
273 DPRINTF("Read MR%u%c: 0x%x\n", ch->mr_idx + 1, channel + 'a', ret);
274 ch->mr_idx = 1;
275 break;
276
277 case REG_SRa:
278 case REG_SRb:
279 ret = ch->sr;
280 DPRINTF("Read SR%c: 0x%x\n", channel + 'a', ret);
281 break;
282
283 case REG_RHRa:
284 case REG_RHRb:
285 ret = ch->rhr[ch->rhr_idx];
286 if (ch->rx_pending > 0) {
287 ch->rx_pending--;
288 if (ch->rx_pending == 0) {
289 ch->sr &= ~SR_RXRDY;
290 blk->isr &= ~ISR_RXRDY(channel);
291 qemu_chr_fe_accept_input(&ch->dev);
292 } else {
293 ch->rhr_idx = (ch->rhr_idx + 1) % RX_FIFO_SIZE;
294 }
295 if (ch->sr & SR_BREAK) {
296 ch->sr &= ~SR_BREAK;
297 blk->isr |= ISR_BREAK(channel);
298 }
299 }
300 DPRINTF("Read RHR%c (0x%x)\n", channel + 'a', ret);
301 break;
302
303 case REG_ISR:
304 ret = blk->isr;
305 DPRINTF("Read ISR%c: 0x%x\n", block + 'A', ret);
306 break;
307
308 default:
309 DPRINTF("Read unknown/unsupported register 0x%02x\n", offset);
310 }
311
312 if (old_isr != blk->isr) {
313 update_irq(dev, block);
314 }
315
316 return ret;
317 }
318
319 static void io_write(IPackDevice *ip, uint8_t addr, uint16_t val)
320 {
321 IPOctalState *dev = IPOCTAL(ip);
322 unsigned reg = val & 0xFF;
323 /* addr[7:6]: block (A-D)
324 addr[7:5]: channel (a-h)
325 addr[5:0]: register */
326 unsigned block = addr >> 5;
327 unsigned channel = addr >> 4;
328 /* Big endian, accessed using 8-bit bytes at odd locations */
329 unsigned offset = (addr & 0x1F) ^ 1;
330 SCC2698Channel *ch = &dev->ch[channel];
331 SCC2698Block *blk = &dev->blk[block];
332 uint8_t old_isr = blk->isr;
333 uint8_t old_imr = blk->imr;
334
335 switch (offset) {
336
337 case REG_MRa:
338 case REG_MRb:
339 ch->mr[ch->mr_idx] = reg;
340 DPRINTF("Write MR%u%c 0x%x\n", ch->mr_idx + 1, channel + 'a', reg);
341 ch->mr_idx = 1;
342 break;
343
344 /* Not implemented */
345 case REG_CSRa:
346 case REG_CSRb:
347 DPRINTF("Write CSR%c: 0x%x\n", channel + 'a', reg);
348 break;
349
350 case REG_CRa:
351 case REG_CRb:
352 write_cr(dev, channel, reg);
353 break;
354
355 case REG_THRa:
356 case REG_THRb:
357 if (ch->sr & SR_TXRDY) {
358 uint8_t thr = reg;
359 DPRINTF("Write THR%c (0x%x)\n", channel + 'a', reg);
360 /* XXX this blocks entire thread. Rewrite to use
361 * qemu_chr_fe_write and background I/O callbacks */
362 qemu_chr_fe_write_all(&ch->dev, &thr, 1);
363 } else {
364 DPRINTF("Write THR%c (0x%x), Tx disabled\n", channel + 'a', reg);
365 }
366 break;
367
368 /* Not implemented */
369 case REG_ACR:
370 DPRINTF("Write ACR%c 0x%x\n", block + 'A', val);
371 break;
372
373 case REG_IMR:
374 DPRINTF("Write IMR%c 0x%x\n", block + 'A', val);
375 blk->imr = reg;
376 break;
377
378 /* Not implemented */
379 case REG_OPCR:
380 DPRINTF("Write OPCR%c 0x%x\n", block + 'A', val);
381 break;
382
383 default:
384 DPRINTF("Write unknown/unsupported register 0x%02x %u\n", offset, val);
385 }
386
387 if (old_isr != blk->isr || old_imr != blk->imr) {
388 update_irq(dev, block);
389 }
390 }
391
392 static uint16_t id_read(IPackDevice *ip, uint8_t addr)
393 {
394 uint16_t ret = 0;
395 unsigned pos = addr / 2; /* The ID PROM data is stored every other byte */
396
397 if (pos < ARRAY_SIZE(id_prom_data)) {
398 ret = id_prom_data[pos];
399 } else {
400 DPRINTF("Attempt to read unavailable PROM data at 0x%x\n", addr);
401 }
402
403 return ret;
404 }
405
406 static void id_write(IPackDevice *ip, uint8_t addr, uint16_t val)
407 {
408 IPOctalState *dev = IPOCTAL(ip);
409 if (addr == 1) {
410 DPRINTF("Write IRQ vector: %u\n", (unsigned) val);
411 dev->irq_vector = val; /* Undocumented, but the hw works like that */
412 } else {
413 DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
414 }
415 }
416
417 static uint16_t int_read(IPackDevice *ip, uint8_t addr)
418 {
419 IPOctalState *dev = IPOCTAL(ip);
420 /* Read address 0 to ACK INT0# and address 2 to ACK INT1# */
421 if (addr != 0 && addr != 2) {
422 DPRINTF("Attempt to read from 0x%x\n", addr);
423 return 0;
424 } else {
425 /* Update interrupts if necessary */
426 update_irq(dev, addr);
427 return dev->irq_vector;
428 }
429 }
430
431 static void int_write(IPackDevice *ip, uint8_t addr, uint16_t val)
432 {
433 DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
434 }
435
436 static uint16_t mem_read16(IPackDevice *ip, uint32_t addr)
437 {
438 DPRINTF("Attempt to read from 0x%x\n", addr);
439 return 0;
440 }
441
442 static void mem_write16(IPackDevice *ip, uint32_t addr, uint16_t val)
443 {
444 DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
445 }
446
447 static uint8_t mem_read8(IPackDevice *ip, uint32_t addr)
448 {
449 DPRINTF("Attempt to read from 0x%x\n", addr);
450 return 0;
451 }
452
453 static void mem_write8(IPackDevice *ip, uint32_t addr, uint8_t val)
454 {
455 IPOctalState *dev = IPOCTAL(ip);
456 if (addr == 1) {
457 DPRINTF("Write IRQ vector: %u\n", (unsigned) val);
458 dev->irq_vector = val;
459 } else {
460 DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
461 }
462 }
463
464 static int hostdev_can_receive(void *opaque)
465 {
466 SCC2698Channel *ch = opaque;
467 int available_bytes = RX_FIFO_SIZE - ch->rx_pending;
468 return ch->rx_enabled ? available_bytes : 0;
469 }
470
471 static void hostdev_receive(void *opaque, const uint8_t *buf, int size)
472 {
473 SCC2698Channel *ch = opaque;
474 IPOctalState *dev = ch->ipoctal;
475 unsigned pos = ch->rhr_idx + ch->rx_pending;
476 int i;
477
478 assert(size + ch->rx_pending <= RX_FIFO_SIZE);
479
480 /* Copy data to the RxFIFO */
481 for (i = 0; i < size; i++) {
482 pos %= RX_FIFO_SIZE;
483 ch->rhr[pos++] = buf[i];
484 }
485
486 ch->rx_pending += size;
487
488 /* If the RxFIFO was empty raise an interrupt */
489 if (!(ch->sr & SR_RXRDY)) {
490 unsigned block, channel = 0;
491 /* Find channel number to update the ISR register */
492 while (&dev->ch[channel] != ch) {
493 channel++;
494 }
495 block = channel / 2;
496 dev->blk[block].isr |= ISR_RXRDY(channel);
497 ch->sr |= SR_RXRDY;
498 update_irq(dev, block);
499 }
500 }
501
502 static void hostdev_event(void *opaque, int event)
503 {
504 SCC2698Channel *ch = opaque;
505 switch (event) {
506 case CHR_EVENT_OPENED:
507 DPRINTF("Device %s opened\n", ch->dev->label);
508 break;
509 case CHR_EVENT_BREAK: {
510 uint8_t zero = 0;
511 DPRINTF("Device %s received break\n", ch->dev->label);
512
513 if (!(ch->sr & SR_BREAK)) {
514 IPOctalState *dev = ch->ipoctal;
515 unsigned block, channel = 0;
516
517 while (&dev->ch[channel] != ch) {
518 channel++;
519 }
520 block = channel / 2;
521
522 ch->sr |= SR_BREAK;
523 dev->blk[block].isr |= ISR_BREAK(channel);
524 }
525
526 /* Put a zero character in the buffer */
527 hostdev_receive(ch, &zero, 1);
528 }
529 break;
530 default:
531 DPRINTF("Device %s received event %d\n", ch->dev->label, event);
532 }
533 }
534
535 static void ipoctal_realize(DeviceState *dev, Error **errp)
536 {
537 IPOctalState *s = IPOCTAL(dev);
538 unsigned i;
539
540 for (i = 0; i < N_CHANNELS; i++) {
541 SCC2698Channel *ch = &s->ch[i];
542 ch->ipoctal = s;
543
544 /* Redirect IP-Octal channels to host character devices */
545 if (qemu_chr_fe_get_driver(&ch->dev)) {
546 qemu_chr_fe_set_handlers(&ch->dev, hostdev_can_receive,
547 hostdev_receive, hostdev_event,
548 ch, NULL, true);
549 DPRINTF("Redirecting channel %u to %s\n", i, ch->dev->label);
550 } else {
551 DPRINTF("Could not redirect channel %u, no chardev set\n", i);
552 }
553 }
554 }
555
556 static Property ipoctal_properties[] = {
557 DEFINE_PROP_CHR("chardev0", IPOctalState, ch[0].dev),
558 DEFINE_PROP_CHR("chardev1", IPOctalState, ch[1].dev),
559 DEFINE_PROP_CHR("chardev2", IPOctalState, ch[2].dev),
560 DEFINE_PROP_CHR("chardev3", IPOctalState, ch[3].dev),
561 DEFINE_PROP_CHR("chardev4", IPOctalState, ch[4].dev),
562 DEFINE_PROP_CHR("chardev5", IPOctalState, ch[5].dev),
563 DEFINE_PROP_CHR("chardev6", IPOctalState, ch[6].dev),
564 DEFINE_PROP_CHR("chardev7", IPOctalState, ch[7].dev),
565 DEFINE_PROP_END_OF_LIST(),
566 };
567
568 static void ipoctal_class_init(ObjectClass *klass, void *data)
569 {
570 DeviceClass *dc = DEVICE_CLASS(klass);
571 IPackDeviceClass *ic = IPACK_DEVICE_CLASS(klass);
572
573 ic->realize = ipoctal_realize;
574 ic->io_read = io_read;
575 ic->io_write = io_write;
576 ic->id_read = id_read;
577 ic->id_write = id_write;
578 ic->int_read = int_read;
579 ic->int_write = int_write;
580 ic->mem_read16 = mem_read16;
581 ic->mem_write16 = mem_write16;
582 ic->mem_read8 = mem_read8;
583 ic->mem_write8 = mem_write8;
584
585 set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
586 dc->desc = "GE IP-Octal 232 8-channel RS-232 IndustryPack";
587 dc->props = ipoctal_properties;
588 dc->vmsd = &vmstate_ipoctal;
589 }
590
591 static const TypeInfo ipoctal_info = {
592 .name = TYPE_IPOCTAL,
593 .parent = TYPE_IPACK_DEVICE,
594 .instance_size = sizeof(IPOctalState),
595 .class_init = ipoctal_class_init,
596 };
597
598 static void ipoctal_register_types(void)
599 {
600 type_register_static(&ipoctal_info);
601 }
602
603 type_init(ipoctal_register_types)