Merge remote-tracking branch 'remotes/philmd-gitlab/tags/renesas-20201027' into staging
[qemu.git] / hw / char / milkymist-uart.c
1 /*
2 * QEMU model of the Milkymist UART block.
3 *
4 * Copyright (c) 2010 Michael Walle <michael@walle.cc>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 *
19 *
20 * Specification available at:
21 * http://milkymist.walle.cc/socdoc/uart.pdf
22 */
23
24 #include "qemu/osdep.h"
25 #include "hw/irq.h"
26 #include "hw/qdev-properties.h"
27 #include "hw/sysbus.h"
28 #include "migration/vmstate.h"
29 #include "trace.h"
30 #include "chardev/char-fe.h"
31 #include "qemu/error-report.h"
32 #include "qemu/module.h"
33 #include "qom/object.h"
34
35 enum {
36 R_RXTX = 0,
37 R_DIV,
38 R_STAT,
39 R_CTRL,
40 R_DBG,
41 R_MAX
42 };
43
44 enum {
45 STAT_THRE = (1<<0),
46 STAT_RX_EVT = (1<<1),
47 STAT_TX_EVT = (1<<2),
48 };
49
50 enum {
51 CTRL_RX_IRQ_EN = (1<<0),
52 CTRL_TX_IRQ_EN = (1<<1),
53 CTRL_THRU_EN = (1<<2),
54 };
55
56 enum {
57 DBG_BREAK_EN = (1<<0),
58 };
59
60 #define TYPE_MILKYMIST_UART "milkymist-uart"
61 OBJECT_DECLARE_SIMPLE_TYPE(MilkymistUartState, MILKYMIST_UART)
62
63 struct MilkymistUartState {
64 SysBusDevice parent_obj;
65
66 MemoryRegion regs_region;
67 CharBackend chr;
68 qemu_irq irq;
69
70 uint32_t regs[R_MAX];
71 };
72
73 static void uart_update_irq(MilkymistUartState *s)
74 {
75 int rx_event = s->regs[R_STAT] & STAT_RX_EVT;
76 int tx_event = s->regs[R_STAT] & STAT_TX_EVT;
77 int rx_irq_en = s->regs[R_CTRL] & CTRL_RX_IRQ_EN;
78 int tx_irq_en = s->regs[R_CTRL] & CTRL_TX_IRQ_EN;
79
80 if ((rx_irq_en && rx_event) || (tx_irq_en && tx_event)) {
81 trace_milkymist_uart_raise_irq();
82 qemu_irq_raise(s->irq);
83 } else {
84 trace_milkymist_uart_lower_irq();
85 qemu_irq_lower(s->irq);
86 }
87 }
88
89 static uint64_t uart_read(void *opaque, hwaddr addr,
90 unsigned size)
91 {
92 MilkymistUartState *s = opaque;
93 uint32_t r = 0;
94
95 addr >>= 2;
96 switch (addr) {
97 case R_RXTX:
98 r = s->regs[addr];
99 break;
100 case R_DIV:
101 case R_STAT:
102 case R_CTRL:
103 case R_DBG:
104 r = s->regs[addr];
105 break;
106
107 default:
108 error_report("milkymist_uart: read access to unknown register 0x"
109 TARGET_FMT_plx, addr << 2);
110 break;
111 }
112
113 trace_milkymist_uart_memory_read(addr << 2, r);
114
115 return r;
116 }
117
118 static void uart_write(void *opaque, hwaddr addr, uint64_t value,
119 unsigned size)
120 {
121 MilkymistUartState *s = opaque;
122 unsigned char ch = value;
123
124 trace_milkymist_uart_memory_write(addr, value);
125
126 addr >>= 2;
127 switch (addr) {
128 case R_RXTX:
129 qemu_chr_fe_write_all(&s->chr, &ch, 1);
130 s->regs[R_STAT] |= STAT_TX_EVT;
131 break;
132 case R_DIV:
133 case R_CTRL:
134 case R_DBG:
135 s->regs[addr] = value;
136 break;
137
138 case R_STAT:
139 /* write one to clear bits */
140 s->regs[addr] &= ~(value & (STAT_RX_EVT | STAT_TX_EVT));
141 qemu_chr_fe_accept_input(&s->chr);
142 break;
143
144 default:
145 error_report("milkymist_uart: write access to unknown register 0x"
146 TARGET_FMT_plx, addr << 2);
147 break;
148 }
149
150 uart_update_irq(s);
151 }
152
153 static const MemoryRegionOps uart_mmio_ops = {
154 .read = uart_read,
155 .write = uart_write,
156 .valid = {
157 .min_access_size = 4,
158 .max_access_size = 4,
159 },
160 .endianness = DEVICE_NATIVE_ENDIAN,
161 };
162
163 static void uart_rx(void *opaque, const uint8_t *buf, int size)
164 {
165 MilkymistUartState *s = opaque;
166
167 assert(!(s->regs[R_STAT] & STAT_RX_EVT));
168
169 s->regs[R_STAT] |= STAT_RX_EVT;
170 s->regs[R_RXTX] = *buf;
171
172 uart_update_irq(s);
173 }
174
175 static int uart_can_rx(void *opaque)
176 {
177 MilkymistUartState *s = opaque;
178
179 return !(s->regs[R_STAT] & STAT_RX_EVT);
180 }
181
182 static void uart_event(void *opaque, QEMUChrEvent event)
183 {
184 }
185
186 static void milkymist_uart_reset(DeviceState *d)
187 {
188 MilkymistUartState *s = MILKYMIST_UART(d);
189 int i;
190
191 for (i = 0; i < R_MAX; i++) {
192 s->regs[i] = 0;
193 }
194
195 /* THRE is always set */
196 s->regs[R_STAT] = STAT_THRE;
197 }
198
199 static void milkymist_uart_realize(DeviceState *dev, Error **errp)
200 {
201 MilkymistUartState *s = MILKYMIST_UART(dev);
202
203 qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
204 uart_event, NULL, s, NULL, true);
205 }
206
207 static void milkymist_uart_init(Object *obj)
208 {
209 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
210 MilkymistUartState *s = MILKYMIST_UART(obj);
211
212 sysbus_init_irq(sbd, &s->irq);
213
214 memory_region_init_io(&s->regs_region, OBJECT(s), &uart_mmio_ops, s,
215 "milkymist-uart", R_MAX * 4);
216 sysbus_init_mmio(sbd, &s->regs_region);
217 }
218
219 static const VMStateDescription vmstate_milkymist_uart = {
220 .name = "milkymist-uart",
221 .version_id = 1,
222 .minimum_version_id = 1,
223 .fields = (VMStateField[]) {
224 VMSTATE_UINT32_ARRAY(regs, MilkymistUartState, R_MAX),
225 VMSTATE_END_OF_LIST()
226 }
227 };
228
229 static Property milkymist_uart_properties[] = {
230 DEFINE_PROP_CHR("chardev", MilkymistUartState, chr),
231 DEFINE_PROP_END_OF_LIST(),
232 };
233
234 static void milkymist_uart_class_init(ObjectClass *klass, void *data)
235 {
236 DeviceClass *dc = DEVICE_CLASS(klass);
237
238 dc->realize = milkymist_uart_realize;
239 dc->reset = milkymist_uart_reset;
240 dc->vmsd = &vmstate_milkymist_uart;
241 device_class_set_props(dc, milkymist_uart_properties);
242 }
243
244 static const TypeInfo milkymist_uart_info = {
245 .name = TYPE_MILKYMIST_UART,
246 .parent = TYPE_SYS_BUS_DEVICE,
247 .instance_size = sizeof(MilkymistUartState),
248 .instance_init = milkymist_uart_init,
249 .class_init = milkymist_uart_class_init,
250 };
251
252 static void milkymist_uart_register_types(void)
253 {
254 type_register_static(&milkymist_uart_info);
255 }
256
257 type_init(milkymist_uart_register_types)