hw/char: QOM'ify milkymist-uart.c
[qemu.git] / hw / char / milkymist-uart.c
1 /*
2 * QEMU model of the Milkymist UART block.
3 *
4 * Copyright (c) 2010 Michael Walle <michael@walle.cc>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 *
19 *
20 * Specification available at:
21 * http://www.milkymist.org/socdoc/uart.pdf
22 */
23
24 #include "qemu/osdep.h"
25 #include "hw/hw.h"
26 #include "hw/sysbus.h"
27 #include "trace.h"
28 #include "sysemu/char.h"
29 #include "qemu/error-report.h"
30
31 enum {
32 R_RXTX = 0,
33 R_DIV,
34 R_STAT,
35 R_CTRL,
36 R_DBG,
37 R_MAX
38 };
39
40 enum {
41 STAT_THRE = (1<<0),
42 STAT_RX_EVT = (1<<1),
43 STAT_TX_EVT = (1<<2),
44 };
45
46 enum {
47 CTRL_RX_IRQ_EN = (1<<0),
48 CTRL_TX_IRQ_EN = (1<<1),
49 CTRL_THRU_EN = (1<<2),
50 };
51
52 enum {
53 DBG_BREAK_EN = (1<<0),
54 };
55
56 #define TYPE_MILKYMIST_UART "milkymist-uart"
57 #define MILKYMIST_UART(obj) \
58 OBJECT_CHECK(MilkymistUartState, (obj), TYPE_MILKYMIST_UART)
59
60 struct MilkymistUartState {
61 SysBusDevice parent_obj;
62
63 MemoryRegion regs_region;
64 CharDriverState *chr;
65 qemu_irq irq;
66
67 uint32_t regs[R_MAX];
68 };
69 typedef struct MilkymistUartState MilkymistUartState;
70
71 static void uart_update_irq(MilkymistUartState *s)
72 {
73 int rx_event = s->regs[R_STAT] & STAT_RX_EVT;
74 int tx_event = s->regs[R_STAT] & STAT_TX_EVT;
75 int rx_irq_en = s->regs[R_CTRL] & CTRL_RX_IRQ_EN;
76 int tx_irq_en = s->regs[R_CTRL] & CTRL_TX_IRQ_EN;
77
78 if ((rx_irq_en && rx_event) || (tx_irq_en && tx_event)) {
79 trace_milkymist_uart_raise_irq();
80 qemu_irq_raise(s->irq);
81 } else {
82 trace_milkymist_uart_lower_irq();
83 qemu_irq_lower(s->irq);
84 }
85 }
86
87 static uint64_t uart_read(void *opaque, hwaddr addr,
88 unsigned size)
89 {
90 MilkymistUartState *s = opaque;
91 uint32_t r = 0;
92
93 addr >>= 2;
94 switch (addr) {
95 case R_RXTX:
96 r = s->regs[addr];
97 break;
98 case R_DIV:
99 case R_STAT:
100 case R_CTRL:
101 case R_DBG:
102 r = s->regs[addr];
103 break;
104
105 default:
106 error_report("milkymist_uart: read access to unknown register 0x"
107 TARGET_FMT_plx, addr << 2);
108 break;
109 }
110
111 trace_milkymist_uart_memory_read(addr << 2, r);
112
113 return r;
114 }
115
116 static void uart_write(void *opaque, hwaddr addr, uint64_t value,
117 unsigned size)
118 {
119 MilkymistUartState *s = opaque;
120 unsigned char ch = value;
121
122 trace_milkymist_uart_memory_write(addr, value);
123
124 addr >>= 2;
125 switch (addr) {
126 case R_RXTX:
127 if (s->chr) {
128 qemu_chr_fe_write_all(s->chr, &ch, 1);
129 }
130 s->regs[R_STAT] |= STAT_TX_EVT;
131 break;
132 case R_DIV:
133 case R_CTRL:
134 case R_DBG:
135 s->regs[addr] = value;
136 break;
137
138 case R_STAT:
139 /* write one to clear bits */
140 s->regs[addr] &= ~(value & (STAT_RX_EVT | STAT_TX_EVT));
141 qemu_chr_accept_input(s->chr);
142 break;
143
144 default:
145 error_report("milkymist_uart: write access to unknown register 0x"
146 TARGET_FMT_plx, addr << 2);
147 break;
148 }
149
150 uart_update_irq(s);
151 }
152
153 static const MemoryRegionOps uart_mmio_ops = {
154 .read = uart_read,
155 .write = uart_write,
156 .valid = {
157 .min_access_size = 4,
158 .max_access_size = 4,
159 },
160 .endianness = DEVICE_NATIVE_ENDIAN,
161 };
162
163 static void uart_rx(void *opaque, const uint8_t *buf, int size)
164 {
165 MilkymistUartState *s = opaque;
166
167 assert(!(s->regs[R_STAT] & STAT_RX_EVT));
168
169 s->regs[R_STAT] |= STAT_RX_EVT;
170 s->regs[R_RXTX] = *buf;
171
172 uart_update_irq(s);
173 }
174
175 static int uart_can_rx(void *opaque)
176 {
177 MilkymistUartState *s = opaque;
178
179 return !(s->regs[R_STAT] & STAT_RX_EVT);
180 }
181
182 static void uart_event(void *opaque, int event)
183 {
184 }
185
186 static void milkymist_uart_reset(DeviceState *d)
187 {
188 MilkymistUartState *s = MILKYMIST_UART(d);
189 int i;
190
191 for (i = 0; i < R_MAX; i++) {
192 s->regs[i] = 0;
193 }
194
195 /* THRE is always set */
196 s->regs[R_STAT] = STAT_THRE;
197 }
198
199 static void milkymist_uart_realize(DeviceState *dev, Error **errp)
200 {
201 MilkymistUartState *s = MILKYMIST_UART(dev);
202
203 if (s->chr) {
204 qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
205 }
206 }
207
208 static void milkymist_uart_init(Object *obj)
209 {
210 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
211 MilkymistUartState *s = MILKYMIST_UART(obj);
212
213 sysbus_init_irq(sbd, &s->irq);
214
215 memory_region_init_io(&s->regs_region, OBJECT(s), &uart_mmio_ops, s,
216 "milkymist-uart", R_MAX * 4);
217 sysbus_init_mmio(sbd, &s->regs_region);
218 }
219
220 static const VMStateDescription vmstate_milkymist_uart = {
221 .name = "milkymist-uart",
222 .version_id = 1,
223 .minimum_version_id = 1,
224 .fields = (VMStateField[]) {
225 VMSTATE_UINT32_ARRAY(regs, MilkymistUartState, R_MAX),
226 VMSTATE_END_OF_LIST()
227 }
228 };
229
230 static Property milkymist_uart_properties[] = {
231 DEFINE_PROP_CHR("chardev", MilkymistUartState, chr),
232 DEFINE_PROP_END_OF_LIST(),
233 };
234
235 static void milkymist_uart_class_init(ObjectClass *klass, void *data)
236 {
237 DeviceClass *dc = DEVICE_CLASS(klass);
238
239 dc->realize = milkymist_uart_realize;
240 dc->reset = milkymist_uart_reset;
241 dc->vmsd = &vmstate_milkymist_uart;
242 dc->props = milkymist_uart_properties;
243 }
244
245 static const TypeInfo milkymist_uart_info = {
246 .name = TYPE_MILKYMIST_UART,
247 .parent = TYPE_SYS_BUS_DEVICE,
248 .instance_size = sizeof(MilkymistUartState),
249 .instance_init = milkymist_uart_init,
250 .class_init = milkymist_uart_class_init,
251 };
252
253 static void milkymist_uart_register_types(void)
254 {
255 type_register_static(&milkymist_uart_info);
256 }
257
258 type_init(milkymist_uart_register_types)