Merge remote-tracking branch 'remotes/philmd-gitlab/tags/renesas-20201027' into staging
[qemu.git] / hw / char / parallel.c
1 /*
2 * QEMU Parallel PORT emulation
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 * Copyright (c) 2007 Marko Kohtala
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "qemu/osdep.h"
27 #include "qapi/error.h"
28 #include "qemu/module.h"
29 #include "chardev/char-parallel.h"
30 #include "chardev/char-fe.h"
31 #include "hw/acpi/aml-build.h"
32 #include "hw/irq.h"
33 #include "hw/isa/isa.h"
34 #include "hw/qdev-properties.h"
35 #include "migration/vmstate.h"
36 #include "hw/char/parallel.h"
37 #include "sysemu/reset.h"
38 #include "sysemu/sysemu.h"
39 #include "trace.h"
40 #include "qom/object.h"
41
42 //#define DEBUG_PARALLEL
43
44 #ifdef DEBUG_PARALLEL
45 #define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__)
46 #else
47 #define pdebug(fmt, ...) ((void)0)
48 #endif
49
50 #define PARA_REG_DATA 0
51 #define PARA_REG_STS 1
52 #define PARA_REG_CTR 2
53 #define PARA_REG_EPP_ADDR 3
54 #define PARA_REG_EPP_DATA 4
55
56 /*
57 * These are the definitions for the Printer Status Register
58 */
59 #define PARA_STS_BUSY 0x80 /* Busy complement */
60 #define PARA_STS_ACK 0x40 /* Acknowledge */
61 #define PARA_STS_PAPER 0x20 /* Out of paper */
62 #define PARA_STS_ONLINE 0x10 /* Online */
63 #define PARA_STS_ERROR 0x08 /* Error complement */
64 #define PARA_STS_TMOUT 0x01 /* EPP timeout */
65
66 /*
67 * These are the definitions for the Printer Control Register
68 */
69 #define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */
70 #define PARA_CTR_INTEN 0x10 /* IRQ Enable */
71 #define PARA_CTR_SELECT 0x08 /* Select In complement */
72 #define PARA_CTR_INIT 0x04 /* Initialize Printer complement */
73 #define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */
74 #define PARA_CTR_STROBE 0x01 /* Strobe complement */
75
76 #define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)
77
78 typedef struct ParallelState {
79 MemoryRegion iomem;
80 uint8_t dataw;
81 uint8_t datar;
82 uint8_t status;
83 uint8_t control;
84 qemu_irq irq;
85 int irq_pending;
86 CharBackend chr;
87 int hw_driver;
88 int epp_timeout;
89 uint32_t last_read_offset; /* For debugging */
90 /* Memory-mapped interface */
91 int it_shift;
92 PortioList portio_list;
93 } ParallelState;
94
95 #define TYPE_ISA_PARALLEL "isa-parallel"
96 OBJECT_DECLARE_SIMPLE_TYPE(ISAParallelState, ISA_PARALLEL)
97
98 struct ISAParallelState {
99 ISADevice parent_obj;
100
101 uint32_t index;
102 uint32_t iobase;
103 uint32_t isairq;
104 ParallelState state;
105 };
106
107 static void parallel_update_irq(ParallelState *s)
108 {
109 if (s->irq_pending)
110 qemu_irq_raise(s->irq);
111 else
112 qemu_irq_lower(s->irq);
113 }
114
115 static void
116 parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
117 {
118 ParallelState *s = opaque;
119
120 addr &= 7;
121 trace_parallel_ioport_write("SW", addr, val);
122 switch(addr) {
123 case PARA_REG_DATA:
124 s->dataw = val;
125 parallel_update_irq(s);
126 break;
127 case PARA_REG_CTR:
128 val |= 0xc0;
129 if ((val & PARA_CTR_INIT) == 0 ) {
130 s->status = PARA_STS_BUSY;
131 s->status |= PARA_STS_ACK;
132 s->status |= PARA_STS_ONLINE;
133 s->status |= PARA_STS_ERROR;
134 }
135 else if (val & PARA_CTR_SELECT) {
136 if (val & PARA_CTR_STROBE) {
137 s->status &= ~PARA_STS_BUSY;
138 if ((s->control & PARA_CTR_STROBE) == 0)
139 /* XXX this blocks entire thread. Rewrite to use
140 * qemu_chr_fe_write and background I/O callbacks */
141 qemu_chr_fe_write_all(&s->chr, &s->dataw, 1);
142 } else {
143 if (s->control & PARA_CTR_INTEN) {
144 s->irq_pending = 1;
145 }
146 }
147 }
148 parallel_update_irq(s);
149 s->control = val;
150 break;
151 }
152 }
153
154 static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
155 {
156 ParallelState *s = opaque;
157 uint8_t parm = val;
158 int dir;
159
160 /* Sometimes programs do several writes for timing purposes on old
161 HW. Take care not to waste time on writes that do nothing. */
162
163 s->last_read_offset = ~0U;
164
165 addr &= 7;
166 trace_parallel_ioport_write("HW", addr, val);
167 switch(addr) {
168 case PARA_REG_DATA:
169 if (s->dataw == val)
170 return;
171 pdebug("wd%02x\n", val);
172 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
173 s->dataw = val;
174 break;
175 case PARA_REG_STS:
176 pdebug("ws%02x\n", val);
177 if (val & PARA_STS_TMOUT)
178 s->epp_timeout = 0;
179 break;
180 case PARA_REG_CTR:
181 val |= 0xc0;
182 if (s->control == val)
183 return;
184 pdebug("wc%02x\n", val);
185
186 if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) {
187 if (val & PARA_CTR_DIR) {
188 dir = 1;
189 } else {
190 dir = 0;
191 }
192 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_DATA_DIR, &dir);
193 parm &= ~PARA_CTR_DIR;
194 }
195
196 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
197 s->control = val;
198 break;
199 case PARA_REG_EPP_ADDR:
200 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
201 /* Controls not correct for EPP address cycle, so do nothing */
202 pdebug("wa%02x s\n", val);
203 else {
204 struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
205 if (qemu_chr_fe_ioctl(&s->chr,
206 CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
207 s->epp_timeout = 1;
208 pdebug("wa%02x t\n", val);
209 }
210 else
211 pdebug("wa%02x\n", val);
212 }
213 break;
214 case PARA_REG_EPP_DATA:
215 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
216 /* Controls not correct for EPP data cycle, so do nothing */
217 pdebug("we%02x s\n", val);
218 else {
219 struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
220 if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
221 s->epp_timeout = 1;
222 pdebug("we%02x t\n", val);
223 }
224 else
225 pdebug("we%02x\n", val);
226 }
227 break;
228 }
229 }
230
231 static void
232 parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
233 {
234 ParallelState *s = opaque;
235 uint16_t eppdata = cpu_to_le16(val);
236 int err;
237 struct ParallelIOArg ioarg = {
238 .buffer = &eppdata, .count = sizeof(eppdata)
239 };
240
241 trace_parallel_ioport_write("EPP", addr, val);
242 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
243 /* Controls not correct for EPP data cycle, so do nothing */
244 pdebug("we%04x s\n", val);
245 return;
246 }
247 err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
248 if (err) {
249 s->epp_timeout = 1;
250 pdebug("we%04x t\n", val);
251 }
252 else
253 pdebug("we%04x\n", val);
254 }
255
256 static void
257 parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
258 {
259 ParallelState *s = opaque;
260 uint32_t eppdata = cpu_to_le32(val);
261 int err;
262 struct ParallelIOArg ioarg = {
263 .buffer = &eppdata, .count = sizeof(eppdata)
264 };
265
266 trace_parallel_ioport_write("EPP", addr, val);
267 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
268 /* Controls not correct for EPP data cycle, so do nothing */
269 pdebug("we%08x s\n", val);
270 return;
271 }
272 err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
273 if (err) {
274 s->epp_timeout = 1;
275 pdebug("we%08x t\n", val);
276 }
277 else
278 pdebug("we%08x\n", val);
279 }
280
281 static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
282 {
283 ParallelState *s = opaque;
284 uint32_t ret = 0xff;
285
286 addr &= 7;
287 switch(addr) {
288 case PARA_REG_DATA:
289 if (s->control & PARA_CTR_DIR)
290 ret = s->datar;
291 else
292 ret = s->dataw;
293 break;
294 case PARA_REG_STS:
295 ret = s->status;
296 s->irq_pending = 0;
297 if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
298 /* XXX Fixme: wait 5 microseconds */
299 if (s->status & PARA_STS_ACK)
300 s->status &= ~PARA_STS_ACK;
301 else {
302 /* XXX Fixme: wait 5 microseconds */
303 s->status |= PARA_STS_ACK;
304 s->status |= PARA_STS_BUSY;
305 }
306 }
307 parallel_update_irq(s);
308 break;
309 case PARA_REG_CTR:
310 ret = s->control;
311 break;
312 }
313 trace_parallel_ioport_read("SW", addr, ret);
314 return ret;
315 }
316
317 static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
318 {
319 ParallelState *s = opaque;
320 uint8_t ret = 0xff;
321 addr &= 7;
322 switch(addr) {
323 case PARA_REG_DATA:
324 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
325 if (s->last_read_offset != addr || s->datar != ret)
326 pdebug("rd%02x\n", ret);
327 s->datar = ret;
328 break;
329 case PARA_REG_STS:
330 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
331 ret &= ~PARA_STS_TMOUT;
332 if (s->epp_timeout)
333 ret |= PARA_STS_TMOUT;
334 if (s->last_read_offset != addr || s->status != ret)
335 pdebug("rs%02x\n", ret);
336 s->status = ret;
337 break;
338 case PARA_REG_CTR:
339 /* s->control has some bits fixed to 1. It is zero only when
340 it has not been yet written to. */
341 if (s->control == 0) {
342 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
343 if (s->last_read_offset != addr)
344 pdebug("rc%02x\n", ret);
345 s->control = ret;
346 }
347 else {
348 ret = s->control;
349 if (s->last_read_offset != addr)
350 pdebug("rc%02x\n", ret);
351 }
352 break;
353 case PARA_REG_EPP_ADDR:
354 if ((s->control & (PARA_CTR_DIR | PARA_CTR_SIGNAL)) !=
355 (PARA_CTR_DIR | PARA_CTR_INIT))
356 /* Controls not correct for EPP addr cycle, so do nothing */
357 pdebug("ra%02x s\n", ret);
358 else {
359 struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
360 if (qemu_chr_fe_ioctl(&s->chr,
361 CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
362 s->epp_timeout = 1;
363 pdebug("ra%02x t\n", ret);
364 }
365 else
366 pdebug("ra%02x\n", ret);
367 }
368 break;
369 case PARA_REG_EPP_DATA:
370 if ((s->control & (PARA_CTR_DIR | PARA_CTR_SIGNAL)) !=
371 (PARA_CTR_DIR | PARA_CTR_INIT))
372 /* Controls not correct for EPP data cycle, so do nothing */
373 pdebug("re%02x s\n", ret);
374 else {
375 struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
376 if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
377 s->epp_timeout = 1;
378 pdebug("re%02x t\n", ret);
379 }
380 else
381 pdebug("re%02x\n", ret);
382 }
383 break;
384 }
385 trace_parallel_ioport_read("HW", addr, ret);
386 s->last_read_offset = addr;
387 return ret;
388 }
389
390 static uint32_t
391 parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
392 {
393 ParallelState *s = opaque;
394 uint32_t ret;
395 uint16_t eppdata = ~0;
396 int err;
397 struct ParallelIOArg ioarg = {
398 .buffer = &eppdata, .count = sizeof(eppdata)
399 };
400 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
401 /* Controls not correct for EPP data cycle, so do nothing */
402 pdebug("re%04x s\n", eppdata);
403 return eppdata;
404 }
405 err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
406 ret = le16_to_cpu(eppdata);
407
408 if (err) {
409 s->epp_timeout = 1;
410 pdebug("re%04x t\n", ret);
411 }
412 else
413 pdebug("re%04x\n", ret);
414 trace_parallel_ioport_read("EPP", addr, ret);
415 return ret;
416 }
417
418 static uint32_t
419 parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
420 {
421 ParallelState *s = opaque;
422 uint32_t ret;
423 uint32_t eppdata = ~0U;
424 int err;
425 struct ParallelIOArg ioarg = {
426 .buffer = &eppdata, .count = sizeof(eppdata)
427 };
428 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
429 /* Controls not correct for EPP data cycle, so do nothing */
430 pdebug("re%08x s\n", eppdata);
431 return eppdata;
432 }
433 err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
434 ret = le32_to_cpu(eppdata);
435
436 if (err) {
437 s->epp_timeout = 1;
438 pdebug("re%08x t\n", ret);
439 }
440 else
441 pdebug("re%08x\n", ret);
442 trace_parallel_ioport_read("EPP", addr, ret);
443 return ret;
444 }
445
446 static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
447 {
448 trace_parallel_ioport_write("ECP", addr & 7, val);
449 pdebug("wecp%d=%02x\n", addr & 7, val);
450 }
451
452 static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
453 {
454 uint8_t ret = 0xff;
455
456 trace_parallel_ioport_read("ECP", addr & 7, ret);
457 pdebug("recp%d:%02x\n", addr & 7, ret);
458 return ret;
459 }
460
461 static void parallel_reset(void *opaque)
462 {
463 ParallelState *s = opaque;
464
465 s->datar = ~0;
466 s->dataw = ~0;
467 s->status = PARA_STS_BUSY;
468 s->status |= PARA_STS_ACK;
469 s->status |= PARA_STS_ONLINE;
470 s->status |= PARA_STS_ERROR;
471 s->status |= PARA_STS_TMOUT;
472 s->control = PARA_CTR_SELECT;
473 s->control |= PARA_CTR_INIT;
474 s->control |= 0xc0;
475 s->irq_pending = 0;
476 s->hw_driver = 0;
477 s->epp_timeout = 0;
478 s->last_read_offset = ~0U;
479 }
480
481 static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
482
483 static const MemoryRegionPortio isa_parallel_portio_hw_list[] = {
484 { 0, 8, 1,
485 .read = parallel_ioport_read_hw,
486 .write = parallel_ioport_write_hw },
487 { 4, 1, 2,
488 .read = parallel_ioport_eppdata_read_hw2,
489 .write = parallel_ioport_eppdata_write_hw2 },
490 { 4, 1, 4,
491 .read = parallel_ioport_eppdata_read_hw4,
492 .write = parallel_ioport_eppdata_write_hw4 },
493 { 0x400, 8, 1,
494 .read = parallel_ioport_ecp_read,
495 .write = parallel_ioport_ecp_write },
496 PORTIO_END_OF_LIST(),
497 };
498
499 static const MemoryRegionPortio isa_parallel_portio_sw_list[] = {
500 { 0, 8, 1,
501 .read = parallel_ioport_read_sw,
502 .write = parallel_ioport_write_sw },
503 PORTIO_END_OF_LIST(),
504 };
505
506
507 static const VMStateDescription vmstate_parallel_isa = {
508 .name = "parallel_isa",
509 .version_id = 1,
510 .minimum_version_id = 1,
511 .fields = (VMStateField[]) {
512 VMSTATE_UINT8(state.dataw, ISAParallelState),
513 VMSTATE_UINT8(state.datar, ISAParallelState),
514 VMSTATE_UINT8(state.status, ISAParallelState),
515 VMSTATE_UINT8(state.control, ISAParallelState),
516 VMSTATE_INT32(state.irq_pending, ISAParallelState),
517 VMSTATE_INT32(state.epp_timeout, ISAParallelState),
518 VMSTATE_END_OF_LIST()
519 }
520 };
521
522 static int parallel_can_receive(void *opaque)
523 {
524 return 1;
525 }
526
527 static void parallel_isa_realizefn(DeviceState *dev, Error **errp)
528 {
529 static int index;
530 ISADevice *isadev = ISA_DEVICE(dev);
531 ISAParallelState *isa = ISA_PARALLEL(dev);
532 ParallelState *s = &isa->state;
533 int base;
534 uint8_t dummy;
535
536 if (!qemu_chr_fe_backend_connected(&s->chr)) {
537 error_setg(errp, "Can't create parallel device, empty char device");
538 return;
539 }
540
541 if (isa->index == -1) {
542 isa->index = index;
543 }
544 if (isa->index >= MAX_PARALLEL_PORTS) {
545 error_setg(errp, "Max. supported number of parallel ports is %d.",
546 MAX_PARALLEL_PORTS);
547 return;
548 }
549 if (isa->iobase == -1) {
550 isa->iobase = isa_parallel_io[isa->index];
551 }
552 index++;
553
554 base = isa->iobase;
555 isa_init_irq(isadev, &s->irq, isa->isairq);
556 qemu_register_reset(parallel_reset, s);
557
558 qemu_chr_fe_set_handlers(&s->chr, parallel_can_receive, NULL,
559 NULL, NULL, s, NULL, true);
560 if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
561 s->hw_driver = 1;
562 s->status = dummy;
563 }
564
565 isa_register_portio_list(isadev, &s->portio_list, base,
566 (s->hw_driver
567 ? &isa_parallel_portio_hw_list[0]
568 : &isa_parallel_portio_sw_list[0]),
569 s, "parallel");
570 }
571
572 static void parallel_isa_build_aml(ISADevice *isadev, Aml *scope)
573 {
574 ISAParallelState *isa = ISA_PARALLEL(isadev);
575 Aml *dev;
576 Aml *crs;
577
578 crs = aml_resource_template();
579 aml_append(crs, aml_io(AML_DECODE16, isa->iobase, isa->iobase, 0x08, 0x08));
580 aml_append(crs, aml_irq_no_flags(isa->isairq));
581
582 dev = aml_device("LPT%d", isa->index + 1);
583 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
584 aml_append(dev, aml_name_decl("_UID", aml_int(isa->index + 1)));
585 aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
586 aml_append(dev, aml_name_decl("_CRS", crs));
587
588 aml_append(scope, dev);
589 }
590
591 /* Memory mapped interface */
592 static uint64_t parallel_mm_readfn(void *opaque, hwaddr addr, unsigned size)
593 {
594 ParallelState *s = opaque;
595
596 return parallel_ioport_read_sw(s, addr >> s->it_shift) &
597 MAKE_64BIT_MASK(0, size * 8);
598 }
599
600 static void parallel_mm_writefn(void *opaque, hwaddr addr,
601 uint64_t value, unsigned size)
602 {
603 ParallelState *s = opaque;
604
605 parallel_ioport_write_sw(s, addr >> s->it_shift,
606 value & MAKE_64BIT_MASK(0, size * 8));
607 }
608
609 static const MemoryRegionOps parallel_mm_ops = {
610 .read = parallel_mm_readfn,
611 .write = parallel_mm_writefn,
612 .valid.min_access_size = 1,
613 .valid.max_access_size = 4,
614 .endianness = DEVICE_NATIVE_ENDIAN,
615 };
616
617 /* If fd is zero, it means that the parallel device uses the console */
618 bool parallel_mm_init(MemoryRegion *address_space,
619 hwaddr base, int it_shift, qemu_irq irq,
620 Chardev *chr)
621 {
622 ParallelState *s;
623
624 s = g_malloc0(sizeof(ParallelState));
625 s->irq = irq;
626 qemu_chr_fe_init(&s->chr, chr, &error_abort);
627 s->it_shift = it_shift;
628 qemu_register_reset(parallel_reset, s);
629
630 memory_region_init_io(&s->iomem, NULL, &parallel_mm_ops, s,
631 "parallel", 8 << it_shift);
632 memory_region_add_subregion(address_space, base, &s->iomem);
633 return true;
634 }
635
636 static Property parallel_isa_properties[] = {
637 DEFINE_PROP_UINT32("index", ISAParallelState, index, -1),
638 DEFINE_PROP_UINT32("iobase", ISAParallelState, iobase, -1),
639 DEFINE_PROP_UINT32("irq", ISAParallelState, isairq, 7),
640 DEFINE_PROP_CHR("chardev", ISAParallelState, state.chr),
641 DEFINE_PROP_END_OF_LIST(),
642 };
643
644 static void parallel_isa_class_initfn(ObjectClass *klass, void *data)
645 {
646 DeviceClass *dc = DEVICE_CLASS(klass);
647 ISADeviceClass *isa = ISA_DEVICE_CLASS(klass);
648
649 dc->realize = parallel_isa_realizefn;
650 dc->vmsd = &vmstate_parallel_isa;
651 isa->build_aml = parallel_isa_build_aml;
652 device_class_set_props(dc, parallel_isa_properties);
653 set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
654 }
655
656 static const TypeInfo parallel_isa_info = {
657 .name = TYPE_ISA_PARALLEL,
658 .parent = TYPE_ISA_DEVICE,
659 .instance_size = sizeof(ISAParallelState),
660 .class_init = parallel_isa_class_initfn,
661 };
662
663 static void parallel_register_types(void)
664 {
665 type_register_static(&parallel_isa_info);
666 }
667
668 type_init(parallel_register_types)