vga: make Cirrus ISA device optional
[qemu.git] / hw / cirrus_vga.c
1 /*
2 * QEMU Cirrus CLGD 54xx VGA Emulator.
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
29 #include "hw.h"
30 #include "pc.h"
31 #include "pci.h"
32 #include "console.h"
33 #include "vga_int.h"
34 #include "loader.h"
35
36 /*
37 * TODO:
38 * - destination write mask support not complete (bits 5..7)
39 * - optimize linear mappings
40 * - optimize bitblt functions
41 */
42
43 //#define DEBUG_CIRRUS
44 //#define DEBUG_BITBLT
45
46 /***************************************
47 *
48 * definitions
49 *
50 ***************************************/
51
52 // ID
53 #define CIRRUS_ID_CLGD5422 (0x23<<2)
54 #define CIRRUS_ID_CLGD5426 (0x24<<2)
55 #define CIRRUS_ID_CLGD5424 (0x25<<2)
56 #define CIRRUS_ID_CLGD5428 (0x26<<2)
57 #define CIRRUS_ID_CLGD5430 (0x28<<2)
58 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
59 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
60 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
61
62 // sequencer 0x07
63 #define CIRRUS_SR7_BPP_VGA 0x00
64 #define CIRRUS_SR7_BPP_SVGA 0x01
65 #define CIRRUS_SR7_BPP_MASK 0x0e
66 #define CIRRUS_SR7_BPP_8 0x00
67 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
68 #define CIRRUS_SR7_BPP_24 0x04
69 #define CIRRUS_SR7_BPP_16 0x06
70 #define CIRRUS_SR7_BPP_32 0x08
71 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
72
73 // sequencer 0x0f
74 #define CIRRUS_MEMSIZE_512k 0x08
75 #define CIRRUS_MEMSIZE_1M 0x10
76 #define CIRRUS_MEMSIZE_2M 0x18
77 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
78
79 // sequencer 0x12
80 #define CIRRUS_CURSOR_SHOW 0x01
81 #define CIRRUS_CURSOR_HIDDENPEL 0x02
82 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
83
84 // sequencer 0x17
85 #define CIRRUS_BUSTYPE_VLBFAST 0x10
86 #define CIRRUS_BUSTYPE_PCI 0x20
87 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
88 #define CIRRUS_BUSTYPE_ISA 0x38
89 #define CIRRUS_MMIO_ENABLE 0x04
90 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
91 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
92
93 // control 0x0b
94 #define CIRRUS_BANKING_DUAL 0x01
95 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
96
97 // control 0x30
98 #define CIRRUS_BLTMODE_BACKWARDS 0x01
99 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
100 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
101 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
102 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
103 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
104 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
105 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
106 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
107 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
108 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
109
110 // control 0x31
111 #define CIRRUS_BLT_BUSY 0x01
112 #define CIRRUS_BLT_START 0x02
113 #define CIRRUS_BLT_RESET 0x04
114 #define CIRRUS_BLT_FIFOUSED 0x10
115 #define CIRRUS_BLT_AUTOSTART 0x80
116
117 // control 0x32
118 #define CIRRUS_ROP_0 0x00
119 #define CIRRUS_ROP_SRC_AND_DST 0x05
120 #define CIRRUS_ROP_NOP 0x06
121 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
122 #define CIRRUS_ROP_NOTDST 0x0b
123 #define CIRRUS_ROP_SRC 0x0d
124 #define CIRRUS_ROP_1 0x0e
125 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
126 #define CIRRUS_ROP_SRC_XOR_DST 0x59
127 #define CIRRUS_ROP_SRC_OR_DST 0x6d
128 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
129 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
130 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
131 #define CIRRUS_ROP_NOTSRC 0xd0
132 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
133 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
134
135 #define CIRRUS_ROP_NOP_INDEX 2
136 #define CIRRUS_ROP_SRC_INDEX 5
137
138 // control 0x33
139 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
140 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
141 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
142
143 // memory-mapped IO
144 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
145 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
146 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
147 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
148 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
149 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
150 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
151 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
152 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
153 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
154 #define CIRRUS_MMIO_BLTROP 0x1a // byte
155 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
156 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
157 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
158 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
159 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
160 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
161 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
162 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
163 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
164 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
165 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
166 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
167 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
168 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
169 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
170 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
171 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
172 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
173
174 #define CIRRUS_PNPMMIO_SIZE 0x1000
175
176 #define BLTUNSAFE(s) \
177 ( \
178 ( /* check dst is within bounds */ \
179 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
180 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
181 (s)->vga.vram_size \
182 ) || \
183 ( /* check src is within bounds */ \
184 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
185 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
186 (s)->vga.vram_size \
187 ) \
188 )
189
190 struct CirrusVGAState;
191 typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
192 uint8_t * dst, const uint8_t * src,
193 int dstpitch, int srcpitch,
194 int bltwidth, int bltheight);
195 typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
196 uint8_t *dst, int dst_pitch, int width, int height);
197
198 typedef struct CirrusVGAState {
199 VGACommonState vga;
200
201 MemoryRegion cirrus_linear_io;
202 MemoryRegion cirrus_linear_bitblt_io;
203 MemoryRegion cirrus_mmio_io;
204 MemoryRegion pci_bar;
205 bool linear_vram; /* vga.vram mapped over cirrus_linear_io */
206 MemoryRegion low_mem_container; /* container for 0xa0000-0xc0000 */
207 MemoryRegion low_mem; /* always mapped, overridden by: */
208 MemoryRegion cirrus_bank[2]; /* aliases at 0xa0000-0xb0000 */
209 uint32_t cirrus_addr_mask;
210 uint32_t linear_mmio_mask;
211 uint8_t cirrus_shadow_gr0;
212 uint8_t cirrus_shadow_gr1;
213 uint8_t cirrus_hidden_dac_lockindex;
214 uint8_t cirrus_hidden_dac_data;
215 uint32_t cirrus_bank_base[2];
216 uint32_t cirrus_bank_limit[2];
217 uint8_t cirrus_hidden_palette[48];
218 uint32_t hw_cursor_x;
219 uint32_t hw_cursor_y;
220 int cirrus_blt_pixelwidth;
221 int cirrus_blt_width;
222 int cirrus_blt_height;
223 int cirrus_blt_dstpitch;
224 int cirrus_blt_srcpitch;
225 uint32_t cirrus_blt_fgcol;
226 uint32_t cirrus_blt_bgcol;
227 uint32_t cirrus_blt_dstaddr;
228 uint32_t cirrus_blt_srcaddr;
229 uint8_t cirrus_blt_mode;
230 uint8_t cirrus_blt_modeext;
231 cirrus_bitblt_rop_t cirrus_rop;
232 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
233 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
234 uint8_t *cirrus_srcptr;
235 uint8_t *cirrus_srcptr_end;
236 uint32_t cirrus_srccounter;
237 /* hwcursor display state */
238 int last_hw_cursor_size;
239 int last_hw_cursor_x;
240 int last_hw_cursor_y;
241 int last_hw_cursor_y_start;
242 int last_hw_cursor_y_end;
243 int real_vram_size; /* XXX: suppress that */
244 int device_id;
245 int bustype;
246 } CirrusVGAState;
247
248 typedef struct PCICirrusVGAState {
249 PCIDevice dev;
250 CirrusVGAState cirrus_vga;
251 } PCICirrusVGAState;
252
253 typedef struct ISACirrusVGAState {
254 ISADevice dev;
255 CirrusVGAState cirrus_vga;
256 } ISACirrusVGAState;
257
258 static uint8_t rop_to_index[256];
259
260 /***************************************
261 *
262 * prototypes.
263 *
264 ***************************************/
265
266
267 static void cirrus_bitblt_reset(CirrusVGAState *s);
268 static void cirrus_update_memory_access(CirrusVGAState *s);
269
270 /***************************************
271 *
272 * raster operations
273 *
274 ***************************************/
275
276 static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
277 uint8_t *dst,const uint8_t *src,
278 int dstpitch,int srcpitch,
279 int bltwidth,int bltheight)
280 {
281 }
282
283 static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
284 uint8_t *dst,
285 int dstpitch, int bltwidth,int bltheight)
286 {
287 }
288
289 #define ROP_NAME 0
290 #define ROP_FN(d, s) 0
291 #include "cirrus_vga_rop.h"
292
293 #define ROP_NAME src_and_dst
294 #define ROP_FN(d, s) (s) & (d)
295 #include "cirrus_vga_rop.h"
296
297 #define ROP_NAME src_and_notdst
298 #define ROP_FN(d, s) (s) & (~(d))
299 #include "cirrus_vga_rop.h"
300
301 #define ROP_NAME notdst
302 #define ROP_FN(d, s) ~(d)
303 #include "cirrus_vga_rop.h"
304
305 #define ROP_NAME src
306 #define ROP_FN(d, s) s
307 #include "cirrus_vga_rop.h"
308
309 #define ROP_NAME 1
310 #define ROP_FN(d, s) ~0
311 #include "cirrus_vga_rop.h"
312
313 #define ROP_NAME notsrc_and_dst
314 #define ROP_FN(d, s) (~(s)) & (d)
315 #include "cirrus_vga_rop.h"
316
317 #define ROP_NAME src_xor_dst
318 #define ROP_FN(d, s) (s) ^ (d)
319 #include "cirrus_vga_rop.h"
320
321 #define ROP_NAME src_or_dst
322 #define ROP_FN(d, s) (s) | (d)
323 #include "cirrus_vga_rop.h"
324
325 #define ROP_NAME notsrc_or_notdst
326 #define ROP_FN(d, s) (~(s)) | (~(d))
327 #include "cirrus_vga_rop.h"
328
329 #define ROP_NAME src_notxor_dst
330 #define ROP_FN(d, s) ~((s) ^ (d))
331 #include "cirrus_vga_rop.h"
332
333 #define ROP_NAME src_or_notdst
334 #define ROP_FN(d, s) (s) | (~(d))
335 #include "cirrus_vga_rop.h"
336
337 #define ROP_NAME notsrc
338 #define ROP_FN(d, s) (~(s))
339 #include "cirrus_vga_rop.h"
340
341 #define ROP_NAME notsrc_or_dst
342 #define ROP_FN(d, s) (~(s)) | (d)
343 #include "cirrus_vga_rop.h"
344
345 #define ROP_NAME notsrc_and_notdst
346 #define ROP_FN(d, s) (~(s)) & (~(d))
347 #include "cirrus_vga_rop.h"
348
349 static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
350 cirrus_bitblt_rop_fwd_0,
351 cirrus_bitblt_rop_fwd_src_and_dst,
352 cirrus_bitblt_rop_nop,
353 cirrus_bitblt_rop_fwd_src_and_notdst,
354 cirrus_bitblt_rop_fwd_notdst,
355 cirrus_bitblt_rop_fwd_src,
356 cirrus_bitblt_rop_fwd_1,
357 cirrus_bitblt_rop_fwd_notsrc_and_dst,
358 cirrus_bitblt_rop_fwd_src_xor_dst,
359 cirrus_bitblt_rop_fwd_src_or_dst,
360 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
361 cirrus_bitblt_rop_fwd_src_notxor_dst,
362 cirrus_bitblt_rop_fwd_src_or_notdst,
363 cirrus_bitblt_rop_fwd_notsrc,
364 cirrus_bitblt_rop_fwd_notsrc_or_dst,
365 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
366 };
367
368 static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
369 cirrus_bitblt_rop_bkwd_0,
370 cirrus_bitblt_rop_bkwd_src_and_dst,
371 cirrus_bitblt_rop_nop,
372 cirrus_bitblt_rop_bkwd_src_and_notdst,
373 cirrus_bitblt_rop_bkwd_notdst,
374 cirrus_bitblt_rop_bkwd_src,
375 cirrus_bitblt_rop_bkwd_1,
376 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
377 cirrus_bitblt_rop_bkwd_src_xor_dst,
378 cirrus_bitblt_rop_bkwd_src_or_dst,
379 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
380 cirrus_bitblt_rop_bkwd_src_notxor_dst,
381 cirrus_bitblt_rop_bkwd_src_or_notdst,
382 cirrus_bitblt_rop_bkwd_notsrc,
383 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
384 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
385 };
386
387 #define TRANSP_ROP(name) {\
388 name ## _8,\
389 name ## _16,\
390 }
391 #define TRANSP_NOP(func) {\
392 func,\
393 func,\
394 }
395
396 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
397 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
398 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
399 TRANSP_NOP(cirrus_bitblt_rop_nop),
400 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
401 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
402 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
403 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
404 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
405 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
406 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
407 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
408 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
409 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
410 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
411 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
412 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
413 };
414
415 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
416 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
417 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
418 TRANSP_NOP(cirrus_bitblt_rop_nop),
419 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
420 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
421 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
422 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
423 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
424 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
425 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
426 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
427 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
428 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
429 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
430 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
431 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
432 };
433
434 #define ROP2(name) {\
435 name ## _8,\
436 name ## _16,\
437 name ## _24,\
438 name ## _32,\
439 }
440
441 #define ROP_NOP2(func) {\
442 func,\
443 func,\
444 func,\
445 func,\
446 }
447
448 static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
449 ROP2(cirrus_patternfill_0),
450 ROP2(cirrus_patternfill_src_and_dst),
451 ROP_NOP2(cirrus_bitblt_rop_nop),
452 ROP2(cirrus_patternfill_src_and_notdst),
453 ROP2(cirrus_patternfill_notdst),
454 ROP2(cirrus_patternfill_src),
455 ROP2(cirrus_patternfill_1),
456 ROP2(cirrus_patternfill_notsrc_and_dst),
457 ROP2(cirrus_patternfill_src_xor_dst),
458 ROP2(cirrus_patternfill_src_or_dst),
459 ROP2(cirrus_patternfill_notsrc_or_notdst),
460 ROP2(cirrus_patternfill_src_notxor_dst),
461 ROP2(cirrus_patternfill_src_or_notdst),
462 ROP2(cirrus_patternfill_notsrc),
463 ROP2(cirrus_patternfill_notsrc_or_dst),
464 ROP2(cirrus_patternfill_notsrc_and_notdst),
465 };
466
467 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
468 ROP2(cirrus_colorexpand_transp_0),
469 ROP2(cirrus_colorexpand_transp_src_and_dst),
470 ROP_NOP2(cirrus_bitblt_rop_nop),
471 ROP2(cirrus_colorexpand_transp_src_and_notdst),
472 ROP2(cirrus_colorexpand_transp_notdst),
473 ROP2(cirrus_colorexpand_transp_src),
474 ROP2(cirrus_colorexpand_transp_1),
475 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
476 ROP2(cirrus_colorexpand_transp_src_xor_dst),
477 ROP2(cirrus_colorexpand_transp_src_or_dst),
478 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
479 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
480 ROP2(cirrus_colorexpand_transp_src_or_notdst),
481 ROP2(cirrus_colorexpand_transp_notsrc),
482 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
483 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
484 };
485
486 static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
487 ROP2(cirrus_colorexpand_0),
488 ROP2(cirrus_colorexpand_src_and_dst),
489 ROP_NOP2(cirrus_bitblt_rop_nop),
490 ROP2(cirrus_colorexpand_src_and_notdst),
491 ROP2(cirrus_colorexpand_notdst),
492 ROP2(cirrus_colorexpand_src),
493 ROP2(cirrus_colorexpand_1),
494 ROP2(cirrus_colorexpand_notsrc_and_dst),
495 ROP2(cirrus_colorexpand_src_xor_dst),
496 ROP2(cirrus_colorexpand_src_or_dst),
497 ROP2(cirrus_colorexpand_notsrc_or_notdst),
498 ROP2(cirrus_colorexpand_src_notxor_dst),
499 ROP2(cirrus_colorexpand_src_or_notdst),
500 ROP2(cirrus_colorexpand_notsrc),
501 ROP2(cirrus_colorexpand_notsrc_or_dst),
502 ROP2(cirrus_colorexpand_notsrc_and_notdst),
503 };
504
505 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
506 ROP2(cirrus_colorexpand_pattern_transp_0),
507 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
508 ROP_NOP2(cirrus_bitblt_rop_nop),
509 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
510 ROP2(cirrus_colorexpand_pattern_transp_notdst),
511 ROP2(cirrus_colorexpand_pattern_transp_src),
512 ROP2(cirrus_colorexpand_pattern_transp_1),
513 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
514 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
515 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
516 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
517 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
518 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
519 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
520 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
521 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
522 };
523
524 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
525 ROP2(cirrus_colorexpand_pattern_0),
526 ROP2(cirrus_colorexpand_pattern_src_and_dst),
527 ROP_NOP2(cirrus_bitblt_rop_nop),
528 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
529 ROP2(cirrus_colorexpand_pattern_notdst),
530 ROP2(cirrus_colorexpand_pattern_src),
531 ROP2(cirrus_colorexpand_pattern_1),
532 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
533 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
534 ROP2(cirrus_colorexpand_pattern_src_or_dst),
535 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
536 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
537 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
538 ROP2(cirrus_colorexpand_pattern_notsrc),
539 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
540 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
541 };
542
543 static const cirrus_fill_t cirrus_fill[16][4] = {
544 ROP2(cirrus_fill_0),
545 ROP2(cirrus_fill_src_and_dst),
546 ROP_NOP2(cirrus_bitblt_fill_nop),
547 ROP2(cirrus_fill_src_and_notdst),
548 ROP2(cirrus_fill_notdst),
549 ROP2(cirrus_fill_src),
550 ROP2(cirrus_fill_1),
551 ROP2(cirrus_fill_notsrc_and_dst),
552 ROP2(cirrus_fill_src_xor_dst),
553 ROP2(cirrus_fill_src_or_dst),
554 ROP2(cirrus_fill_notsrc_or_notdst),
555 ROP2(cirrus_fill_src_notxor_dst),
556 ROP2(cirrus_fill_src_or_notdst),
557 ROP2(cirrus_fill_notsrc),
558 ROP2(cirrus_fill_notsrc_or_dst),
559 ROP2(cirrus_fill_notsrc_and_notdst),
560 };
561
562 static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
563 {
564 unsigned int color;
565 switch (s->cirrus_blt_pixelwidth) {
566 case 1:
567 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
568 break;
569 case 2:
570 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
571 s->cirrus_blt_fgcol = le16_to_cpu(color);
572 break;
573 case 3:
574 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
575 (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
576 break;
577 default:
578 case 4:
579 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
580 (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
581 s->cirrus_blt_fgcol = le32_to_cpu(color);
582 break;
583 }
584 }
585
586 static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
587 {
588 unsigned int color;
589 switch (s->cirrus_blt_pixelwidth) {
590 case 1:
591 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
592 break;
593 case 2:
594 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
595 s->cirrus_blt_bgcol = le16_to_cpu(color);
596 break;
597 case 3:
598 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
599 (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
600 break;
601 default:
602 case 4:
603 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
604 (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
605 s->cirrus_blt_bgcol = le32_to_cpu(color);
606 break;
607 }
608 }
609
610 static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
611 int off_pitch, int bytesperline,
612 int lines)
613 {
614 int y;
615 int off_cur;
616 int off_cur_end;
617
618 for (y = 0; y < lines; y++) {
619 off_cur = off_begin;
620 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
621 off_cur &= TARGET_PAGE_MASK;
622 while (off_cur < off_cur_end) {
623 memory_region_set_dirty(&s->vga.vram, off_cur);
624 off_cur += TARGET_PAGE_SIZE;
625 }
626 off_begin += off_pitch;
627 }
628 }
629
630 static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
631 const uint8_t * src)
632 {
633 uint8_t *dst;
634
635 dst = s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
636
637 if (BLTUNSAFE(s))
638 return 0;
639
640 (*s->cirrus_rop) (s, dst, src,
641 s->cirrus_blt_dstpitch, 0,
642 s->cirrus_blt_width, s->cirrus_blt_height);
643 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
644 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
645 s->cirrus_blt_height);
646 return 1;
647 }
648
649 /* fill */
650
651 static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
652 {
653 cirrus_fill_t rop_func;
654
655 if (BLTUNSAFE(s))
656 return 0;
657 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
658 rop_func(s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
659 s->cirrus_blt_dstpitch,
660 s->cirrus_blt_width, s->cirrus_blt_height);
661 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
662 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
663 s->cirrus_blt_height);
664 cirrus_bitblt_reset(s);
665 return 1;
666 }
667
668 /***************************************
669 *
670 * bitblt (video-to-video)
671 *
672 ***************************************/
673
674 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
675 {
676 return cirrus_bitblt_common_patterncopy(s,
677 s->vga.vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
678 s->cirrus_addr_mask));
679 }
680
681 static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
682 {
683 int sx = 0, sy = 0;
684 int dx = 0, dy = 0;
685 int depth = 0;
686 int notify = 0;
687
688 /* make sure to only copy if it's a plain copy ROP */
689 if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src ||
690 *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) {
691
692 int width, height;
693
694 depth = s->vga.get_bpp(&s->vga) / 8;
695 s->vga.get_resolution(&s->vga, &width, &height);
696
697 /* extra x, y */
698 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
699 sy = (src / ABS(s->cirrus_blt_srcpitch));
700 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
701 dy = (dst / ABS(s->cirrus_blt_dstpitch));
702
703 /* normalize width */
704 w /= depth;
705
706 /* if we're doing a backward copy, we have to adjust
707 our x/y to be the upper left corner (instead of the lower
708 right corner) */
709 if (s->cirrus_blt_dstpitch < 0) {
710 sx -= (s->cirrus_blt_width / depth) - 1;
711 dx -= (s->cirrus_blt_width / depth) - 1;
712 sy -= s->cirrus_blt_height - 1;
713 dy -= s->cirrus_blt_height - 1;
714 }
715
716 /* are we in the visible portion of memory? */
717 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
718 (sx + w) <= width && (sy + h) <= height &&
719 (dx + w) <= width && (dy + h) <= height) {
720 notify = 1;
721 }
722 }
723
724 /* we have to flush all pending changes so that the copy
725 is generated at the appropriate moment in time */
726 if (notify)
727 vga_hw_update();
728
729 (*s->cirrus_rop) (s, s->vga.vram_ptr +
730 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
731 s->vga.vram_ptr +
732 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
733 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
734 s->cirrus_blt_width, s->cirrus_blt_height);
735
736 if (notify)
737 qemu_console_copy(s->vga.ds,
738 sx, sy, dx, dy,
739 s->cirrus_blt_width / depth,
740 s->cirrus_blt_height);
741
742 /* we don't have to notify the display that this portion has
743 changed since qemu_console_copy implies this */
744
745 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
746 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
747 s->cirrus_blt_height);
748 }
749
750 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
751 {
752 if (BLTUNSAFE(s))
753 return 0;
754
755 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
756 s->cirrus_blt_srcaddr - s->vga.start_addr,
757 s->cirrus_blt_width, s->cirrus_blt_height);
758
759 return 1;
760 }
761
762 /***************************************
763 *
764 * bitblt (cpu-to-video)
765 *
766 ***************************************/
767
768 static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
769 {
770 int copy_count;
771 uint8_t *end_ptr;
772
773 if (s->cirrus_srccounter > 0) {
774 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
775 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
776 the_end:
777 s->cirrus_srccounter = 0;
778 cirrus_bitblt_reset(s);
779 } else {
780 /* at least one scan line */
781 do {
782 (*s->cirrus_rop)(s, s->vga.vram_ptr +
783 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
784 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
785 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
786 s->cirrus_blt_width, 1);
787 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
788 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
789 if (s->cirrus_srccounter <= 0)
790 goto the_end;
791 /* more bytes than needed can be transferred because of
792 word alignment, so we keep them for the next line */
793 /* XXX: keep alignment to speed up transfer */
794 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
795 copy_count = s->cirrus_srcptr_end - end_ptr;
796 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
797 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
798 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
799 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
800 }
801 }
802 }
803
804 /***************************************
805 *
806 * bitblt wrapper
807 *
808 ***************************************/
809
810 static void cirrus_bitblt_reset(CirrusVGAState * s)
811 {
812 int need_update;
813
814 s->vga.gr[0x31] &=
815 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
816 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
817 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
818 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
819 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
820 s->cirrus_srccounter = 0;
821 if (!need_update)
822 return;
823 cirrus_update_memory_access(s);
824 }
825
826 static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
827 {
828 int w;
829
830 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
831 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
832 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
833
834 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
835 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
836 s->cirrus_blt_srcpitch = 8;
837 } else {
838 /* XXX: check for 24 bpp */
839 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
840 }
841 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
842 } else {
843 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
844 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
845 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
846 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
847 else
848 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
849 } else {
850 /* always align input size to 32 bits */
851 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
852 }
853 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
854 }
855 s->cirrus_srcptr = s->cirrus_bltbuf;
856 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
857 cirrus_update_memory_access(s);
858 return 1;
859 }
860
861 static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
862 {
863 /* XXX */
864 #ifdef DEBUG_BITBLT
865 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
866 #endif
867 return 0;
868 }
869
870 static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
871 {
872 int ret;
873
874 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
875 ret = cirrus_bitblt_videotovideo_patterncopy(s);
876 } else {
877 ret = cirrus_bitblt_videotovideo_copy(s);
878 }
879 if (ret)
880 cirrus_bitblt_reset(s);
881 return ret;
882 }
883
884 static void cirrus_bitblt_start(CirrusVGAState * s)
885 {
886 uint8_t blt_rop;
887
888 s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
889
890 s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
891 s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
892 s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
893 s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
894 s->cirrus_blt_dstaddr =
895 (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
896 s->cirrus_blt_srcaddr =
897 (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
898 s->cirrus_blt_mode = s->vga.gr[0x30];
899 s->cirrus_blt_modeext = s->vga.gr[0x33];
900 blt_rop = s->vga.gr[0x32];
901
902 #ifdef DEBUG_BITBLT
903 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
904 blt_rop,
905 s->cirrus_blt_mode,
906 s->cirrus_blt_modeext,
907 s->cirrus_blt_width,
908 s->cirrus_blt_height,
909 s->cirrus_blt_dstpitch,
910 s->cirrus_blt_srcpitch,
911 s->cirrus_blt_dstaddr,
912 s->cirrus_blt_srcaddr,
913 s->vga.gr[0x2f]);
914 #endif
915
916 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
917 case CIRRUS_BLTMODE_PIXELWIDTH8:
918 s->cirrus_blt_pixelwidth = 1;
919 break;
920 case CIRRUS_BLTMODE_PIXELWIDTH16:
921 s->cirrus_blt_pixelwidth = 2;
922 break;
923 case CIRRUS_BLTMODE_PIXELWIDTH24:
924 s->cirrus_blt_pixelwidth = 3;
925 break;
926 case CIRRUS_BLTMODE_PIXELWIDTH32:
927 s->cirrus_blt_pixelwidth = 4;
928 break;
929 default:
930 #ifdef DEBUG_BITBLT
931 printf("cirrus: bitblt - pixel width is unknown\n");
932 #endif
933 goto bitblt_ignore;
934 }
935 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
936
937 if ((s->
938 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
939 CIRRUS_BLTMODE_MEMSYSDEST))
940 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
941 #ifdef DEBUG_BITBLT
942 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
943 #endif
944 goto bitblt_ignore;
945 }
946
947 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
948 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
949 CIRRUS_BLTMODE_TRANSPARENTCOMP |
950 CIRRUS_BLTMODE_PATTERNCOPY |
951 CIRRUS_BLTMODE_COLOREXPAND)) ==
952 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
953 cirrus_bitblt_fgcol(s);
954 cirrus_bitblt_solidfill(s, blt_rop);
955 } else {
956 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
957 CIRRUS_BLTMODE_PATTERNCOPY)) ==
958 CIRRUS_BLTMODE_COLOREXPAND) {
959
960 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
961 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
962 cirrus_bitblt_bgcol(s);
963 else
964 cirrus_bitblt_fgcol(s);
965 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
966 } else {
967 cirrus_bitblt_fgcol(s);
968 cirrus_bitblt_bgcol(s);
969 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
970 }
971 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
972 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
973 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
974 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
975 cirrus_bitblt_bgcol(s);
976 else
977 cirrus_bitblt_fgcol(s);
978 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
979 } else {
980 cirrus_bitblt_fgcol(s);
981 cirrus_bitblt_bgcol(s);
982 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
983 }
984 } else {
985 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
986 }
987 } else {
988 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
989 if (s->cirrus_blt_pixelwidth > 2) {
990 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
991 goto bitblt_ignore;
992 }
993 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
994 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
995 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
996 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
997 } else {
998 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
999 }
1000 } else {
1001 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1002 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1003 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1004 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1005 } else {
1006 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1007 }
1008 }
1009 }
1010 // setup bitblt engine.
1011 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1012 if (!cirrus_bitblt_cputovideo(s))
1013 goto bitblt_ignore;
1014 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1015 if (!cirrus_bitblt_videotocpu(s))
1016 goto bitblt_ignore;
1017 } else {
1018 if (!cirrus_bitblt_videotovideo(s))
1019 goto bitblt_ignore;
1020 }
1021 }
1022 return;
1023 bitblt_ignore:;
1024 cirrus_bitblt_reset(s);
1025 }
1026
1027 static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1028 {
1029 unsigned old_value;
1030
1031 old_value = s->vga.gr[0x31];
1032 s->vga.gr[0x31] = reg_value;
1033
1034 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1035 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1036 cirrus_bitblt_reset(s);
1037 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1038 ((reg_value & CIRRUS_BLT_START) != 0)) {
1039 cirrus_bitblt_start(s);
1040 }
1041 }
1042
1043
1044 /***************************************
1045 *
1046 * basic parameters
1047 *
1048 ***************************************/
1049
1050 static void cirrus_get_offsets(VGACommonState *s1,
1051 uint32_t *pline_offset,
1052 uint32_t *pstart_addr,
1053 uint32_t *pline_compare)
1054 {
1055 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1056 uint32_t start_addr, line_offset, line_compare;
1057
1058 line_offset = s->vga.cr[0x13]
1059 | ((s->vga.cr[0x1b] & 0x10) << 4);
1060 line_offset <<= 3;
1061 *pline_offset = line_offset;
1062
1063 start_addr = (s->vga.cr[0x0c] << 8)
1064 | s->vga.cr[0x0d]
1065 | ((s->vga.cr[0x1b] & 0x01) << 16)
1066 | ((s->vga.cr[0x1b] & 0x0c) << 15)
1067 | ((s->vga.cr[0x1d] & 0x80) << 12);
1068 *pstart_addr = start_addr;
1069
1070 line_compare = s->vga.cr[0x18] |
1071 ((s->vga.cr[0x07] & 0x10) << 4) |
1072 ((s->vga.cr[0x09] & 0x40) << 3);
1073 *pline_compare = line_compare;
1074 }
1075
1076 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1077 {
1078 uint32_t ret = 16;
1079
1080 switch (s->cirrus_hidden_dac_data & 0xf) {
1081 case 0:
1082 ret = 15;
1083 break; /* Sierra HiColor */
1084 case 1:
1085 ret = 16;
1086 break; /* XGA HiColor */
1087 default:
1088 #ifdef DEBUG_CIRRUS
1089 printf("cirrus: invalid DAC value %x in 16bpp\n",
1090 (s->cirrus_hidden_dac_data & 0xf));
1091 #endif
1092 ret = 15; /* XXX */
1093 break;
1094 }
1095 return ret;
1096 }
1097
1098 static int cirrus_get_bpp(VGACommonState *s1)
1099 {
1100 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1101 uint32_t ret = 8;
1102
1103 if ((s->vga.sr[0x07] & 0x01) != 0) {
1104 /* Cirrus SVGA */
1105 switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1106 case CIRRUS_SR7_BPP_8:
1107 ret = 8;
1108 break;
1109 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1110 ret = cirrus_get_bpp16_depth(s);
1111 break;
1112 case CIRRUS_SR7_BPP_24:
1113 ret = 24;
1114 break;
1115 case CIRRUS_SR7_BPP_16:
1116 ret = cirrus_get_bpp16_depth(s);
1117 break;
1118 case CIRRUS_SR7_BPP_32:
1119 ret = 32;
1120 break;
1121 default:
1122 #ifdef DEBUG_CIRRUS
1123 printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
1124 #endif
1125 ret = 8;
1126 break;
1127 }
1128 } else {
1129 /* VGA */
1130 ret = 0;
1131 }
1132
1133 return ret;
1134 }
1135
1136 static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
1137 {
1138 int width, height;
1139
1140 width = (s->cr[0x01] + 1) * 8;
1141 height = s->cr[0x12] |
1142 ((s->cr[0x07] & 0x02) << 7) |
1143 ((s->cr[0x07] & 0x40) << 3);
1144 height = (height + 1);
1145 /* interlace support */
1146 if (s->cr[0x1a] & 0x01)
1147 height = height * 2;
1148 *pwidth = width;
1149 *pheight = height;
1150 }
1151
1152 /***************************************
1153 *
1154 * bank memory
1155 *
1156 ***************************************/
1157
1158 static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1159 {
1160 unsigned offset;
1161 unsigned limit;
1162
1163 if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */
1164 offset = s->vga.gr[0x09 + bank_index];
1165 else /* single bank */
1166 offset = s->vga.gr[0x09];
1167
1168 if ((s->vga.gr[0x0b] & 0x20) != 0)
1169 offset <<= 14;
1170 else
1171 offset <<= 12;
1172
1173 if (s->real_vram_size <= offset)
1174 limit = 0;
1175 else
1176 limit = s->real_vram_size - offset;
1177
1178 if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1179 if (limit > 0x8000) {
1180 offset += 0x8000;
1181 limit -= 0x8000;
1182 } else {
1183 limit = 0;
1184 }
1185 }
1186
1187 if (limit > 0) {
1188 s->cirrus_bank_base[bank_index] = offset;
1189 s->cirrus_bank_limit[bank_index] = limit;
1190 } else {
1191 s->cirrus_bank_base[bank_index] = 0;
1192 s->cirrus_bank_limit[bank_index] = 0;
1193 }
1194 }
1195
1196 /***************************************
1197 *
1198 * I/O access between 0x3c4-0x3c5
1199 *
1200 ***************************************/
1201
1202 static int cirrus_vga_read_sr(CirrusVGAState * s)
1203 {
1204 switch (s->vga.sr_index) {
1205 case 0x00: // Standard VGA
1206 case 0x01: // Standard VGA
1207 case 0x02: // Standard VGA
1208 case 0x03: // Standard VGA
1209 case 0x04: // Standard VGA
1210 return s->vga.sr[s->vga.sr_index];
1211 case 0x06: // Unlock Cirrus extensions
1212 return s->vga.sr[s->vga.sr_index];
1213 case 0x10:
1214 case 0x30:
1215 case 0x50:
1216 case 0x70: // Graphics Cursor X
1217 case 0x90:
1218 case 0xb0:
1219 case 0xd0:
1220 case 0xf0: // Graphics Cursor X
1221 return s->vga.sr[0x10];
1222 case 0x11:
1223 case 0x31:
1224 case 0x51:
1225 case 0x71: // Graphics Cursor Y
1226 case 0x91:
1227 case 0xb1:
1228 case 0xd1:
1229 case 0xf1: // Graphics Cursor Y
1230 return s->vga.sr[0x11];
1231 case 0x05: // ???
1232 case 0x07: // Extended Sequencer Mode
1233 case 0x08: // EEPROM Control
1234 case 0x09: // Scratch Register 0
1235 case 0x0a: // Scratch Register 1
1236 case 0x0b: // VCLK 0
1237 case 0x0c: // VCLK 1
1238 case 0x0d: // VCLK 2
1239 case 0x0e: // VCLK 3
1240 case 0x0f: // DRAM Control
1241 case 0x12: // Graphics Cursor Attribute
1242 case 0x13: // Graphics Cursor Pattern Address
1243 case 0x14: // Scratch Register 2
1244 case 0x15: // Scratch Register 3
1245 case 0x16: // Performance Tuning Register
1246 case 0x17: // Configuration Readback and Extended Control
1247 case 0x18: // Signature Generator Control
1248 case 0x19: // Signal Generator Result
1249 case 0x1a: // Signal Generator Result
1250 case 0x1b: // VCLK 0 Denominator & Post
1251 case 0x1c: // VCLK 1 Denominator & Post
1252 case 0x1d: // VCLK 2 Denominator & Post
1253 case 0x1e: // VCLK 3 Denominator & Post
1254 case 0x1f: // BIOS Write Enable and MCLK select
1255 #ifdef DEBUG_CIRRUS
1256 printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index);
1257 #endif
1258 return s->vga.sr[s->vga.sr_index];
1259 default:
1260 #ifdef DEBUG_CIRRUS
1261 printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
1262 #endif
1263 return 0xff;
1264 break;
1265 }
1266 }
1267
1268 static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
1269 {
1270 switch (s->vga.sr_index) {
1271 case 0x00: // Standard VGA
1272 case 0x01: // Standard VGA
1273 case 0x02: // Standard VGA
1274 case 0x03: // Standard VGA
1275 case 0x04: // Standard VGA
1276 s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
1277 if (s->vga.sr_index == 1)
1278 s->vga.update_retrace_info(&s->vga);
1279 break;
1280 case 0x06: // Unlock Cirrus extensions
1281 val &= 0x17;
1282 if (val == 0x12) {
1283 s->vga.sr[s->vga.sr_index] = 0x12;
1284 } else {
1285 s->vga.sr[s->vga.sr_index] = 0x0f;
1286 }
1287 break;
1288 case 0x10:
1289 case 0x30:
1290 case 0x50:
1291 case 0x70: // Graphics Cursor X
1292 case 0x90:
1293 case 0xb0:
1294 case 0xd0:
1295 case 0xf0: // Graphics Cursor X
1296 s->vga.sr[0x10] = val;
1297 s->hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5);
1298 break;
1299 case 0x11:
1300 case 0x31:
1301 case 0x51:
1302 case 0x71: // Graphics Cursor Y
1303 case 0x91:
1304 case 0xb1:
1305 case 0xd1:
1306 case 0xf1: // Graphics Cursor Y
1307 s->vga.sr[0x11] = val;
1308 s->hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5);
1309 break;
1310 case 0x07: // Extended Sequencer Mode
1311 cirrus_update_memory_access(s);
1312 case 0x08: // EEPROM Control
1313 case 0x09: // Scratch Register 0
1314 case 0x0a: // Scratch Register 1
1315 case 0x0b: // VCLK 0
1316 case 0x0c: // VCLK 1
1317 case 0x0d: // VCLK 2
1318 case 0x0e: // VCLK 3
1319 case 0x0f: // DRAM Control
1320 case 0x12: // Graphics Cursor Attribute
1321 case 0x13: // Graphics Cursor Pattern Address
1322 case 0x14: // Scratch Register 2
1323 case 0x15: // Scratch Register 3
1324 case 0x16: // Performance Tuning Register
1325 case 0x18: // Signature Generator Control
1326 case 0x19: // Signature Generator Result
1327 case 0x1a: // Signature Generator Result
1328 case 0x1b: // VCLK 0 Denominator & Post
1329 case 0x1c: // VCLK 1 Denominator & Post
1330 case 0x1d: // VCLK 2 Denominator & Post
1331 case 0x1e: // VCLK 3 Denominator & Post
1332 case 0x1f: // BIOS Write Enable and MCLK select
1333 s->vga.sr[s->vga.sr_index] = val;
1334 #ifdef DEBUG_CIRRUS
1335 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1336 s->vga.sr_index, val);
1337 #endif
1338 break;
1339 case 0x17: // Configuration Readback and Extended Control
1340 s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
1341 | (val & 0xc7);
1342 cirrus_update_memory_access(s);
1343 break;
1344 default:
1345 #ifdef DEBUG_CIRRUS
1346 printf("cirrus: outport sr_index %02x, sr_value %02x\n",
1347 s->vga.sr_index, val);
1348 #endif
1349 break;
1350 }
1351 }
1352
1353 /***************************************
1354 *
1355 * I/O access at 0x3c6
1356 *
1357 ***************************************/
1358
1359 static int cirrus_read_hidden_dac(CirrusVGAState * s)
1360 {
1361 if (++s->cirrus_hidden_dac_lockindex == 5) {
1362 s->cirrus_hidden_dac_lockindex = 0;
1363 return s->cirrus_hidden_dac_data;
1364 }
1365 return 0xff;
1366 }
1367
1368 static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1369 {
1370 if (s->cirrus_hidden_dac_lockindex == 4) {
1371 s->cirrus_hidden_dac_data = reg_value;
1372 #if defined(DEBUG_CIRRUS)
1373 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1374 #endif
1375 }
1376 s->cirrus_hidden_dac_lockindex = 0;
1377 }
1378
1379 /***************************************
1380 *
1381 * I/O access at 0x3c9
1382 *
1383 ***************************************/
1384
1385 static int cirrus_vga_read_palette(CirrusVGAState * s)
1386 {
1387 int val;
1388
1389 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1390 val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
1391 s->vga.dac_sub_index];
1392 } else {
1393 val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
1394 }
1395 if (++s->vga.dac_sub_index == 3) {
1396 s->vga.dac_sub_index = 0;
1397 s->vga.dac_read_index++;
1398 }
1399 return val;
1400 }
1401
1402 static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value)
1403 {
1404 s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
1405 if (++s->vga.dac_sub_index == 3) {
1406 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1407 memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
1408 s->vga.dac_cache, 3);
1409 } else {
1410 memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3);
1411 }
1412 /* XXX update cursor */
1413 s->vga.dac_sub_index = 0;
1414 s->vga.dac_write_index++;
1415 }
1416 }
1417
1418 /***************************************
1419 *
1420 * I/O access between 0x3ce-0x3cf
1421 *
1422 ***************************************/
1423
1424 static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
1425 {
1426 switch (reg_index) {
1427 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1428 return s->cirrus_shadow_gr0;
1429 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1430 return s->cirrus_shadow_gr1;
1431 case 0x02: // Standard VGA
1432 case 0x03: // Standard VGA
1433 case 0x04: // Standard VGA
1434 case 0x06: // Standard VGA
1435 case 0x07: // Standard VGA
1436 case 0x08: // Standard VGA
1437 return s->vga.gr[s->vga.gr_index];
1438 case 0x05: // Standard VGA, Cirrus extended mode
1439 default:
1440 break;
1441 }
1442
1443 if (reg_index < 0x3a) {
1444 return s->vga.gr[reg_index];
1445 } else {
1446 #ifdef DEBUG_CIRRUS
1447 printf("cirrus: inport gr_index %02x\n", reg_index);
1448 #endif
1449 return 0xff;
1450 }
1451 }
1452
1453 static void
1454 cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1455 {
1456 #if defined(DEBUG_BITBLT) && 0
1457 printf("gr%02x: %02x\n", reg_index, reg_value);
1458 #endif
1459 switch (reg_index) {
1460 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1461 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1462 s->cirrus_shadow_gr0 = reg_value;
1463 break;
1464 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1465 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1466 s->cirrus_shadow_gr1 = reg_value;
1467 break;
1468 case 0x02: // Standard VGA
1469 case 0x03: // Standard VGA
1470 case 0x04: // Standard VGA
1471 case 0x06: // Standard VGA
1472 case 0x07: // Standard VGA
1473 case 0x08: // Standard VGA
1474 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1475 break;
1476 case 0x05: // Standard VGA, Cirrus extended mode
1477 s->vga.gr[reg_index] = reg_value & 0x7f;
1478 cirrus_update_memory_access(s);
1479 break;
1480 case 0x09: // bank offset #0
1481 case 0x0A: // bank offset #1
1482 s->vga.gr[reg_index] = reg_value;
1483 cirrus_update_bank_ptr(s, 0);
1484 cirrus_update_bank_ptr(s, 1);
1485 cirrus_update_memory_access(s);
1486 break;
1487 case 0x0B:
1488 s->vga.gr[reg_index] = reg_value;
1489 cirrus_update_bank_ptr(s, 0);
1490 cirrus_update_bank_ptr(s, 1);
1491 cirrus_update_memory_access(s);
1492 break;
1493 case 0x10: // BGCOLOR 0x0000ff00
1494 case 0x11: // FGCOLOR 0x0000ff00
1495 case 0x12: // BGCOLOR 0x00ff0000
1496 case 0x13: // FGCOLOR 0x00ff0000
1497 case 0x14: // BGCOLOR 0xff000000
1498 case 0x15: // FGCOLOR 0xff000000
1499 case 0x20: // BLT WIDTH 0x0000ff
1500 case 0x22: // BLT HEIGHT 0x0000ff
1501 case 0x24: // BLT DEST PITCH 0x0000ff
1502 case 0x26: // BLT SRC PITCH 0x0000ff
1503 case 0x28: // BLT DEST ADDR 0x0000ff
1504 case 0x29: // BLT DEST ADDR 0x00ff00
1505 case 0x2c: // BLT SRC ADDR 0x0000ff
1506 case 0x2d: // BLT SRC ADDR 0x00ff00
1507 case 0x2f: // BLT WRITEMASK
1508 case 0x30: // BLT MODE
1509 case 0x32: // RASTER OP
1510 case 0x33: // BLT MODEEXT
1511 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1512 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1513 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1514 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1515 s->vga.gr[reg_index] = reg_value;
1516 break;
1517 case 0x21: // BLT WIDTH 0x001f00
1518 case 0x23: // BLT HEIGHT 0x001f00
1519 case 0x25: // BLT DEST PITCH 0x001f00
1520 case 0x27: // BLT SRC PITCH 0x001f00
1521 s->vga.gr[reg_index] = reg_value & 0x1f;
1522 break;
1523 case 0x2a: // BLT DEST ADDR 0x3f0000
1524 s->vga.gr[reg_index] = reg_value & 0x3f;
1525 /* if auto start mode, starts bit blt now */
1526 if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1527 cirrus_bitblt_start(s);
1528 }
1529 break;
1530 case 0x2e: // BLT SRC ADDR 0x3f0000
1531 s->vga.gr[reg_index] = reg_value & 0x3f;
1532 break;
1533 case 0x31: // BLT STATUS/START
1534 cirrus_write_bitblt(s, reg_value);
1535 break;
1536 default:
1537 #ifdef DEBUG_CIRRUS
1538 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1539 reg_value);
1540 #endif
1541 break;
1542 }
1543 }
1544
1545 /***************************************
1546 *
1547 * I/O access between 0x3d4-0x3d5
1548 *
1549 ***************************************/
1550
1551 static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index)
1552 {
1553 switch (reg_index) {
1554 case 0x00: // Standard VGA
1555 case 0x01: // Standard VGA
1556 case 0x02: // Standard VGA
1557 case 0x03: // Standard VGA
1558 case 0x04: // Standard VGA
1559 case 0x05: // Standard VGA
1560 case 0x06: // Standard VGA
1561 case 0x07: // Standard VGA
1562 case 0x08: // Standard VGA
1563 case 0x09: // Standard VGA
1564 case 0x0a: // Standard VGA
1565 case 0x0b: // Standard VGA
1566 case 0x0c: // Standard VGA
1567 case 0x0d: // Standard VGA
1568 case 0x0e: // Standard VGA
1569 case 0x0f: // Standard VGA
1570 case 0x10: // Standard VGA
1571 case 0x11: // Standard VGA
1572 case 0x12: // Standard VGA
1573 case 0x13: // Standard VGA
1574 case 0x14: // Standard VGA
1575 case 0x15: // Standard VGA
1576 case 0x16: // Standard VGA
1577 case 0x17: // Standard VGA
1578 case 0x18: // Standard VGA
1579 return s->vga.cr[s->vga.cr_index];
1580 case 0x24: // Attribute Controller Toggle Readback (R)
1581 return (s->vga.ar_flip_flop << 7);
1582 case 0x19: // Interlace End
1583 case 0x1a: // Miscellaneous Control
1584 case 0x1b: // Extended Display Control
1585 case 0x1c: // Sync Adjust and Genlock
1586 case 0x1d: // Overlay Extended Control
1587 case 0x22: // Graphics Data Latches Readback (R)
1588 case 0x25: // Part Status
1589 case 0x27: // Part ID (R)
1590 return s->vga.cr[s->vga.cr_index];
1591 case 0x26: // Attribute Controller Index Readback (R)
1592 return s->vga.ar_index & 0x3f;
1593 break;
1594 default:
1595 #ifdef DEBUG_CIRRUS
1596 printf("cirrus: inport cr_index %02x\n", reg_index);
1597 #endif
1598 return 0xff;
1599 }
1600 }
1601
1602 static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value)
1603 {
1604 switch (s->vga.cr_index) {
1605 case 0x00: // Standard VGA
1606 case 0x01: // Standard VGA
1607 case 0x02: // Standard VGA
1608 case 0x03: // Standard VGA
1609 case 0x04: // Standard VGA
1610 case 0x05: // Standard VGA
1611 case 0x06: // Standard VGA
1612 case 0x07: // Standard VGA
1613 case 0x08: // Standard VGA
1614 case 0x09: // Standard VGA
1615 case 0x0a: // Standard VGA
1616 case 0x0b: // Standard VGA
1617 case 0x0c: // Standard VGA
1618 case 0x0d: // Standard VGA
1619 case 0x0e: // Standard VGA
1620 case 0x0f: // Standard VGA
1621 case 0x10: // Standard VGA
1622 case 0x11: // Standard VGA
1623 case 0x12: // Standard VGA
1624 case 0x13: // Standard VGA
1625 case 0x14: // Standard VGA
1626 case 0x15: // Standard VGA
1627 case 0x16: // Standard VGA
1628 case 0x17: // Standard VGA
1629 case 0x18: // Standard VGA
1630 /* handle CR0-7 protection */
1631 if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
1632 /* can always write bit 4 of CR7 */
1633 if (s->vga.cr_index == 7)
1634 s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10);
1635 return;
1636 }
1637 s->vga.cr[s->vga.cr_index] = reg_value;
1638 switch(s->vga.cr_index) {
1639 case 0x00:
1640 case 0x04:
1641 case 0x05:
1642 case 0x06:
1643 case 0x07:
1644 case 0x11:
1645 case 0x17:
1646 s->vga.update_retrace_info(&s->vga);
1647 break;
1648 }
1649 break;
1650 case 0x19: // Interlace End
1651 case 0x1a: // Miscellaneous Control
1652 case 0x1b: // Extended Display Control
1653 case 0x1c: // Sync Adjust and Genlock
1654 case 0x1d: // Overlay Extended Control
1655 s->vga.cr[s->vga.cr_index] = reg_value;
1656 #ifdef DEBUG_CIRRUS
1657 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1658 s->vga.cr_index, reg_value);
1659 #endif
1660 break;
1661 case 0x22: // Graphics Data Latches Readback (R)
1662 case 0x24: // Attribute Controller Toggle Readback (R)
1663 case 0x26: // Attribute Controller Index Readback (R)
1664 case 0x27: // Part ID (R)
1665 break;
1666 case 0x25: // Part Status
1667 default:
1668 #ifdef DEBUG_CIRRUS
1669 printf("cirrus: outport cr_index %02x, cr_value %02x\n",
1670 s->vga.cr_index, reg_value);
1671 #endif
1672 break;
1673 }
1674 }
1675
1676 /***************************************
1677 *
1678 * memory-mapped I/O (bitblt)
1679 *
1680 ***************************************/
1681
1682 static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1683 {
1684 int value = 0xff;
1685
1686 switch (address) {
1687 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1688 value = cirrus_vga_read_gr(s, 0x00);
1689 break;
1690 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1691 value = cirrus_vga_read_gr(s, 0x10);
1692 break;
1693 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1694 value = cirrus_vga_read_gr(s, 0x12);
1695 break;
1696 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1697 value = cirrus_vga_read_gr(s, 0x14);
1698 break;
1699 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1700 value = cirrus_vga_read_gr(s, 0x01);
1701 break;
1702 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1703 value = cirrus_vga_read_gr(s, 0x11);
1704 break;
1705 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1706 value = cirrus_vga_read_gr(s, 0x13);
1707 break;
1708 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1709 value = cirrus_vga_read_gr(s, 0x15);
1710 break;
1711 case (CIRRUS_MMIO_BLTWIDTH + 0):
1712 value = cirrus_vga_read_gr(s, 0x20);
1713 break;
1714 case (CIRRUS_MMIO_BLTWIDTH + 1):
1715 value = cirrus_vga_read_gr(s, 0x21);
1716 break;
1717 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1718 value = cirrus_vga_read_gr(s, 0x22);
1719 break;
1720 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1721 value = cirrus_vga_read_gr(s, 0x23);
1722 break;
1723 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1724 value = cirrus_vga_read_gr(s, 0x24);
1725 break;
1726 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1727 value = cirrus_vga_read_gr(s, 0x25);
1728 break;
1729 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1730 value = cirrus_vga_read_gr(s, 0x26);
1731 break;
1732 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1733 value = cirrus_vga_read_gr(s, 0x27);
1734 break;
1735 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1736 value = cirrus_vga_read_gr(s, 0x28);
1737 break;
1738 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1739 value = cirrus_vga_read_gr(s, 0x29);
1740 break;
1741 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1742 value = cirrus_vga_read_gr(s, 0x2a);
1743 break;
1744 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1745 value = cirrus_vga_read_gr(s, 0x2c);
1746 break;
1747 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1748 value = cirrus_vga_read_gr(s, 0x2d);
1749 break;
1750 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1751 value = cirrus_vga_read_gr(s, 0x2e);
1752 break;
1753 case CIRRUS_MMIO_BLTWRITEMASK:
1754 value = cirrus_vga_read_gr(s, 0x2f);
1755 break;
1756 case CIRRUS_MMIO_BLTMODE:
1757 value = cirrus_vga_read_gr(s, 0x30);
1758 break;
1759 case CIRRUS_MMIO_BLTROP:
1760 value = cirrus_vga_read_gr(s, 0x32);
1761 break;
1762 case CIRRUS_MMIO_BLTMODEEXT:
1763 value = cirrus_vga_read_gr(s, 0x33);
1764 break;
1765 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1766 value = cirrus_vga_read_gr(s, 0x34);
1767 break;
1768 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1769 value = cirrus_vga_read_gr(s, 0x35);
1770 break;
1771 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1772 value = cirrus_vga_read_gr(s, 0x38);
1773 break;
1774 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1775 value = cirrus_vga_read_gr(s, 0x39);
1776 break;
1777 case CIRRUS_MMIO_BLTSTATUS:
1778 value = cirrus_vga_read_gr(s, 0x31);
1779 break;
1780 default:
1781 #ifdef DEBUG_CIRRUS
1782 printf("cirrus: mmio read - address 0x%04x\n", address);
1783 #endif
1784 break;
1785 }
1786
1787 return (uint8_t) value;
1788 }
1789
1790 static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1791 uint8_t value)
1792 {
1793 switch (address) {
1794 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1795 cirrus_vga_write_gr(s, 0x00, value);
1796 break;
1797 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1798 cirrus_vga_write_gr(s, 0x10, value);
1799 break;
1800 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1801 cirrus_vga_write_gr(s, 0x12, value);
1802 break;
1803 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1804 cirrus_vga_write_gr(s, 0x14, value);
1805 break;
1806 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1807 cirrus_vga_write_gr(s, 0x01, value);
1808 break;
1809 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1810 cirrus_vga_write_gr(s, 0x11, value);
1811 break;
1812 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1813 cirrus_vga_write_gr(s, 0x13, value);
1814 break;
1815 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1816 cirrus_vga_write_gr(s, 0x15, value);
1817 break;
1818 case (CIRRUS_MMIO_BLTWIDTH + 0):
1819 cirrus_vga_write_gr(s, 0x20, value);
1820 break;
1821 case (CIRRUS_MMIO_BLTWIDTH + 1):
1822 cirrus_vga_write_gr(s, 0x21, value);
1823 break;
1824 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1825 cirrus_vga_write_gr(s, 0x22, value);
1826 break;
1827 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1828 cirrus_vga_write_gr(s, 0x23, value);
1829 break;
1830 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1831 cirrus_vga_write_gr(s, 0x24, value);
1832 break;
1833 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1834 cirrus_vga_write_gr(s, 0x25, value);
1835 break;
1836 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1837 cirrus_vga_write_gr(s, 0x26, value);
1838 break;
1839 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1840 cirrus_vga_write_gr(s, 0x27, value);
1841 break;
1842 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1843 cirrus_vga_write_gr(s, 0x28, value);
1844 break;
1845 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1846 cirrus_vga_write_gr(s, 0x29, value);
1847 break;
1848 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1849 cirrus_vga_write_gr(s, 0x2a, value);
1850 break;
1851 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1852 /* ignored */
1853 break;
1854 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1855 cirrus_vga_write_gr(s, 0x2c, value);
1856 break;
1857 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1858 cirrus_vga_write_gr(s, 0x2d, value);
1859 break;
1860 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1861 cirrus_vga_write_gr(s, 0x2e, value);
1862 break;
1863 case CIRRUS_MMIO_BLTWRITEMASK:
1864 cirrus_vga_write_gr(s, 0x2f, value);
1865 break;
1866 case CIRRUS_MMIO_BLTMODE:
1867 cirrus_vga_write_gr(s, 0x30, value);
1868 break;
1869 case CIRRUS_MMIO_BLTROP:
1870 cirrus_vga_write_gr(s, 0x32, value);
1871 break;
1872 case CIRRUS_MMIO_BLTMODEEXT:
1873 cirrus_vga_write_gr(s, 0x33, value);
1874 break;
1875 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1876 cirrus_vga_write_gr(s, 0x34, value);
1877 break;
1878 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1879 cirrus_vga_write_gr(s, 0x35, value);
1880 break;
1881 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1882 cirrus_vga_write_gr(s, 0x38, value);
1883 break;
1884 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1885 cirrus_vga_write_gr(s, 0x39, value);
1886 break;
1887 case CIRRUS_MMIO_BLTSTATUS:
1888 cirrus_vga_write_gr(s, 0x31, value);
1889 break;
1890 default:
1891 #ifdef DEBUG_CIRRUS
1892 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1893 address, value);
1894 #endif
1895 break;
1896 }
1897 }
1898
1899 /***************************************
1900 *
1901 * write mode 4/5
1902 *
1903 * assume TARGET_PAGE_SIZE >= 16
1904 *
1905 ***************************************/
1906
1907 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1908 unsigned mode,
1909 unsigned offset,
1910 uint32_t mem_value)
1911 {
1912 int x;
1913 unsigned val = mem_value;
1914 uint8_t *dst;
1915
1916 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
1917 for (x = 0; x < 8; x++) {
1918 if (val & 0x80) {
1919 *dst = s->cirrus_shadow_gr1;
1920 } else if (mode == 5) {
1921 *dst = s->cirrus_shadow_gr0;
1922 }
1923 val <<= 1;
1924 dst++;
1925 }
1926 memory_region_set_dirty(&s->vga.vram, offset);
1927 memory_region_set_dirty(&s->vga.vram, offset + 7);
1928 }
1929
1930 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1931 unsigned mode,
1932 unsigned offset,
1933 uint32_t mem_value)
1934 {
1935 int x;
1936 unsigned val = mem_value;
1937 uint8_t *dst;
1938
1939 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
1940 for (x = 0; x < 8; x++) {
1941 if (val & 0x80) {
1942 *dst = s->cirrus_shadow_gr1;
1943 *(dst + 1) = s->vga.gr[0x11];
1944 } else if (mode == 5) {
1945 *dst = s->cirrus_shadow_gr0;
1946 *(dst + 1) = s->vga.gr[0x10];
1947 }
1948 val <<= 1;
1949 dst += 2;
1950 }
1951 memory_region_set_dirty(&s->vga.vram, offset);
1952 memory_region_set_dirty(&s->vga.vram, offset + 15);
1953 }
1954
1955 /***************************************
1956 *
1957 * memory access between 0xa0000-0xbffff
1958 *
1959 ***************************************/
1960
1961 static uint64_t cirrus_vga_mem_read(void *opaque,
1962 target_phys_addr_t addr,
1963 uint32_t size)
1964 {
1965 CirrusVGAState *s = opaque;
1966 unsigned bank_index;
1967 unsigned bank_offset;
1968 uint32_t val;
1969
1970 if ((s->vga.sr[0x07] & 0x01) == 0) {
1971 return vga_mem_readb(&s->vga, addr);
1972 }
1973
1974 if (addr < 0x10000) {
1975 /* XXX handle bitblt */
1976 /* video memory */
1977 bank_index = addr >> 15;
1978 bank_offset = addr & 0x7fff;
1979 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
1980 bank_offset += s->cirrus_bank_base[bank_index];
1981 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
1982 bank_offset <<= 4;
1983 } else if (s->vga.gr[0x0B] & 0x02) {
1984 bank_offset <<= 3;
1985 }
1986 bank_offset &= s->cirrus_addr_mask;
1987 val = *(s->vga.vram_ptr + bank_offset);
1988 } else
1989 val = 0xff;
1990 } else if (addr >= 0x18000 && addr < 0x18100) {
1991 /* memory-mapped I/O */
1992 val = 0xff;
1993 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
1994 val = cirrus_mmio_blt_read(s, addr & 0xff);
1995 }
1996 } else {
1997 val = 0xff;
1998 #ifdef DEBUG_CIRRUS
1999 printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr);
2000 #endif
2001 }
2002 return val;
2003 }
2004
2005 static void cirrus_vga_mem_write(void *opaque,
2006 target_phys_addr_t addr,
2007 uint64_t mem_value,
2008 uint32_t size)
2009 {
2010 CirrusVGAState *s = opaque;
2011 unsigned bank_index;
2012 unsigned bank_offset;
2013 unsigned mode;
2014
2015 if ((s->vga.sr[0x07] & 0x01) == 0) {
2016 vga_mem_writeb(&s->vga, addr, mem_value);
2017 return;
2018 }
2019
2020 if (addr < 0x10000) {
2021 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2022 /* bitblt */
2023 *s->cirrus_srcptr++ = (uint8_t) mem_value;
2024 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2025 cirrus_bitblt_cputovideo_next(s);
2026 }
2027 } else {
2028 /* video memory */
2029 bank_index = addr >> 15;
2030 bank_offset = addr & 0x7fff;
2031 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2032 bank_offset += s->cirrus_bank_base[bank_index];
2033 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2034 bank_offset <<= 4;
2035 } else if (s->vga.gr[0x0B] & 0x02) {
2036 bank_offset <<= 3;
2037 }
2038 bank_offset &= s->cirrus_addr_mask;
2039 mode = s->vga.gr[0x05] & 0x7;
2040 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2041 *(s->vga.vram_ptr + bank_offset) = mem_value;
2042 memory_region_set_dirty(&s->vga.vram, bank_offset);
2043 } else {
2044 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2045 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2046 bank_offset,
2047 mem_value);
2048 } else {
2049 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2050 bank_offset,
2051 mem_value);
2052 }
2053 }
2054 }
2055 }
2056 } else if (addr >= 0x18000 && addr < 0x18100) {
2057 /* memory-mapped I/O */
2058 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
2059 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2060 }
2061 } else {
2062 #ifdef DEBUG_CIRRUS
2063 printf("cirrus: mem_writeb " TARGET_FMT_plx " value %02x\n", addr,
2064 mem_value);
2065 #endif
2066 }
2067 }
2068
2069 static const MemoryRegionOps cirrus_vga_mem_ops = {
2070 .read = cirrus_vga_mem_read,
2071 .write = cirrus_vga_mem_write,
2072 .endianness = DEVICE_LITTLE_ENDIAN,
2073 .impl = {
2074 .min_access_size = 1,
2075 .max_access_size = 1,
2076 },
2077 };
2078
2079 /***************************************
2080 *
2081 * hardware cursor
2082 *
2083 ***************************************/
2084
2085 static inline void invalidate_cursor1(CirrusVGAState *s)
2086 {
2087 if (s->last_hw_cursor_size) {
2088 vga_invalidate_scanlines(&s->vga,
2089 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2090 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2091 }
2092 }
2093
2094 static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2095 {
2096 const uint8_t *src;
2097 uint32_t content;
2098 int y, y_min, y_max;
2099
2100 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2101 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2102 src += (s->vga.sr[0x13] & 0x3c) * 256;
2103 y_min = 64;
2104 y_max = -1;
2105 for(y = 0; y < 64; y++) {
2106 content = ((uint32_t *)src)[0] |
2107 ((uint32_t *)src)[1] |
2108 ((uint32_t *)src)[2] |
2109 ((uint32_t *)src)[3];
2110 if (content) {
2111 if (y < y_min)
2112 y_min = y;
2113 if (y > y_max)
2114 y_max = y;
2115 }
2116 src += 16;
2117 }
2118 } else {
2119 src += (s->vga.sr[0x13] & 0x3f) * 256;
2120 y_min = 32;
2121 y_max = -1;
2122 for(y = 0; y < 32; y++) {
2123 content = ((uint32_t *)src)[0] |
2124 ((uint32_t *)(src + 128))[0];
2125 if (content) {
2126 if (y < y_min)
2127 y_min = y;
2128 if (y > y_max)
2129 y_max = y;
2130 }
2131 src += 4;
2132 }
2133 }
2134 if (y_min > y_max) {
2135 s->last_hw_cursor_y_start = 0;
2136 s->last_hw_cursor_y_end = 0;
2137 } else {
2138 s->last_hw_cursor_y_start = y_min;
2139 s->last_hw_cursor_y_end = y_max + 1;
2140 }
2141 }
2142
2143 /* NOTE: we do not currently handle the cursor bitmap change, so we
2144 update the cursor only if it moves. */
2145 static void cirrus_cursor_invalidate(VGACommonState *s1)
2146 {
2147 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2148 int size;
2149
2150 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
2151 size = 0;
2152 } else {
2153 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
2154 size = 64;
2155 else
2156 size = 32;
2157 }
2158 /* invalidate last cursor and new cursor if any change */
2159 if (s->last_hw_cursor_size != size ||
2160 s->last_hw_cursor_x != s->hw_cursor_x ||
2161 s->last_hw_cursor_y != s->hw_cursor_y) {
2162
2163 invalidate_cursor1(s);
2164
2165 s->last_hw_cursor_size = size;
2166 s->last_hw_cursor_x = s->hw_cursor_x;
2167 s->last_hw_cursor_y = s->hw_cursor_y;
2168 /* compute the real cursor min and max y */
2169 cirrus_cursor_compute_yrange(s);
2170 invalidate_cursor1(s);
2171 }
2172 }
2173
2174 static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
2175 {
2176 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2177 int w, h, bpp, x1, x2, poffset;
2178 unsigned int color0, color1;
2179 const uint8_t *palette, *src;
2180 uint32_t content;
2181
2182 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
2183 return;
2184 /* fast test to see if the cursor intersects with the scan line */
2185 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2186 h = 64;
2187 } else {
2188 h = 32;
2189 }
2190 if (scr_y < s->hw_cursor_y ||
2191 scr_y >= (s->hw_cursor_y + h))
2192 return;
2193
2194 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2195 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2196 src += (s->vga.sr[0x13] & 0x3c) * 256;
2197 src += (scr_y - s->hw_cursor_y) * 16;
2198 poffset = 8;
2199 content = ((uint32_t *)src)[0] |
2200 ((uint32_t *)src)[1] |
2201 ((uint32_t *)src)[2] |
2202 ((uint32_t *)src)[3];
2203 } else {
2204 src += (s->vga.sr[0x13] & 0x3f) * 256;
2205 src += (scr_y - s->hw_cursor_y) * 4;
2206 poffset = 128;
2207 content = ((uint32_t *)src)[0] |
2208 ((uint32_t *)(src + 128))[0];
2209 }
2210 /* if nothing to draw, no need to continue */
2211 if (!content)
2212 return;
2213 w = h;
2214
2215 x1 = s->hw_cursor_x;
2216 if (x1 >= s->vga.last_scr_width)
2217 return;
2218 x2 = s->hw_cursor_x + w;
2219 if (x2 > s->vga.last_scr_width)
2220 x2 = s->vga.last_scr_width;
2221 w = x2 - x1;
2222 palette = s->cirrus_hidden_palette;
2223 color0 = s->vga.rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2224 c6_to_8(palette[0x0 * 3 + 1]),
2225 c6_to_8(palette[0x0 * 3 + 2]));
2226 color1 = s->vga.rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2227 c6_to_8(palette[0xf * 3 + 1]),
2228 c6_to_8(palette[0xf * 3 + 2]));
2229 bpp = ((ds_get_bits_per_pixel(s->vga.ds) + 7) >> 3);
2230 d1 += x1 * bpp;
2231 switch(ds_get_bits_per_pixel(s->vga.ds)) {
2232 default:
2233 break;
2234 case 8:
2235 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2236 break;
2237 case 15:
2238 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2239 break;
2240 case 16:
2241 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2242 break;
2243 case 32:
2244 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2245 break;
2246 }
2247 }
2248
2249 /***************************************
2250 *
2251 * LFB memory access
2252 *
2253 ***************************************/
2254
2255 static uint64_t cirrus_linear_read(void *opaque, target_phys_addr_t addr,
2256 unsigned size)
2257 {
2258 CirrusVGAState *s = opaque;
2259 uint32_t ret;
2260
2261 addr &= s->cirrus_addr_mask;
2262
2263 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2264 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2265 /* memory-mapped I/O */
2266 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2267 } else if (0) {
2268 /* XXX handle bitblt */
2269 ret = 0xff;
2270 } else {
2271 /* video memory */
2272 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2273 addr <<= 4;
2274 } else if (s->vga.gr[0x0B] & 0x02) {
2275 addr <<= 3;
2276 }
2277 addr &= s->cirrus_addr_mask;
2278 ret = *(s->vga.vram_ptr + addr);
2279 }
2280
2281 return ret;
2282 }
2283
2284 static void cirrus_linear_write(void *opaque, target_phys_addr_t addr,
2285 uint64_t val, unsigned size)
2286 {
2287 CirrusVGAState *s = opaque;
2288 unsigned mode;
2289
2290 addr &= s->cirrus_addr_mask;
2291
2292 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2293 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2294 /* memory-mapped I/O */
2295 cirrus_mmio_blt_write(s, addr & 0xff, val);
2296 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2297 /* bitblt */
2298 *s->cirrus_srcptr++ = (uint8_t) val;
2299 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2300 cirrus_bitblt_cputovideo_next(s);
2301 }
2302 } else {
2303 /* video memory */
2304 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2305 addr <<= 4;
2306 } else if (s->vga.gr[0x0B] & 0x02) {
2307 addr <<= 3;
2308 }
2309 addr &= s->cirrus_addr_mask;
2310
2311 mode = s->vga.gr[0x05] & 0x7;
2312 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2313 *(s->vga.vram_ptr + addr) = (uint8_t) val;
2314 memory_region_set_dirty(&s->vga.vram, addr);
2315 } else {
2316 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2317 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2318 } else {
2319 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2320 }
2321 }
2322 }
2323 }
2324
2325 /***************************************
2326 *
2327 * system to screen memory access
2328 *
2329 ***************************************/
2330
2331
2332 static uint64_t cirrus_linear_bitblt_read(void *opaque,
2333 target_phys_addr_t addr,
2334 unsigned size)
2335 {
2336 CirrusVGAState *s = opaque;
2337 uint32_t ret;
2338
2339 /* XXX handle bitblt */
2340 (void)s;
2341 ret = 0xff;
2342 return ret;
2343 }
2344
2345 static void cirrus_linear_bitblt_write(void *opaque,
2346 target_phys_addr_t addr,
2347 uint64_t val,
2348 unsigned size)
2349 {
2350 CirrusVGAState *s = opaque;
2351
2352 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2353 /* bitblt */
2354 *s->cirrus_srcptr++ = (uint8_t) val;
2355 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2356 cirrus_bitblt_cputovideo_next(s);
2357 }
2358 }
2359 }
2360
2361 static const MemoryRegionOps cirrus_linear_bitblt_io_ops = {
2362 .read = cirrus_linear_bitblt_read,
2363 .write = cirrus_linear_bitblt_write,
2364 .endianness = DEVICE_LITTLE_ENDIAN,
2365 .impl = {
2366 .min_access_size = 1,
2367 .max_access_size = 1,
2368 },
2369 };
2370
2371 static void map_linear_vram_bank(CirrusVGAState *s, unsigned bank)
2372 {
2373 MemoryRegion *mr = &s->cirrus_bank[bank];
2374 bool enabled = !(s->cirrus_srcptr != s->cirrus_srcptr_end)
2375 && !((s->vga.sr[0x07] & 0x01) == 0)
2376 && !((s->vga.gr[0x0B] & 0x14) == 0x14)
2377 && !(s->vga.gr[0x0B] & 0x02);
2378
2379 memory_region_set_enabled(mr, enabled);
2380 memory_region_set_alias_offset(mr, s->cirrus_bank_base[bank]);
2381 }
2382
2383 static void map_linear_vram(CirrusVGAState *s)
2384 {
2385 if (s->bustype == CIRRUS_BUSTYPE_PCI && !s->linear_vram) {
2386 s->linear_vram = true;
2387 memory_region_add_subregion_overlap(&s->pci_bar, 0, &s->vga.vram, 1);
2388 }
2389 map_linear_vram_bank(s, 0);
2390 map_linear_vram_bank(s, 1);
2391 }
2392
2393 static void unmap_linear_vram(CirrusVGAState *s)
2394 {
2395 if (s->bustype == CIRRUS_BUSTYPE_PCI && s->linear_vram) {
2396 s->linear_vram = false;
2397 memory_region_del_subregion(&s->pci_bar, &s->vga.vram);
2398 }
2399 memory_region_set_enabled(&s->cirrus_bank[0], false);
2400 memory_region_set_enabled(&s->cirrus_bank[1], false);
2401 }
2402
2403 /* Compute the memory access functions */
2404 static void cirrus_update_memory_access(CirrusVGAState *s)
2405 {
2406 unsigned mode;
2407
2408 memory_region_transaction_begin();
2409 if ((s->vga.sr[0x17] & 0x44) == 0x44) {
2410 goto generic_io;
2411 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2412 goto generic_io;
2413 } else {
2414 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2415 goto generic_io;
2416 } else if (s->vga.gr[0x0B] & 0x02) {
2417 goto generic_io;
2418 }
2419
2420 mode = s->vga.gr[0x05] & 0x7;
2421 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2422 map_linear_vram(s);
2423 } else {
2424 generic_io:
2425 unmap_linear_vram(s);
2426 }
2427 }
2428 memory_region_transaction_commit();
2429 }
2430
2431
2432 /* I/O ports */
2433
2434 static uint32_t cirrus_vga_ioport_read(void *opaque, uint32_t addr)
2435 {
2436 CirrusVGAState *c = opaque;
2437 VGACommonState *s = &c->vga;
2438 int val, index;
2439
2440 if (vga_ioport_invalid(s, addr)) {
2441 val = 0xff;
2442 } else {
2443 switch (addr) {
2444 case 0x3c0:
2445 if (s->ar_flip_flop == 0) {
2446 val = s->ar_index;
2447 } else {
2448 val = 0;
2449 }
2450 break;
2451 case 0x3c1:
2452 index = s->ar_index & 0x1f;
2453 if (index < 21)
2454 val = s->ar[index];
2455 else
2456 val = 0;
2457 break;
2458 case 0x3c2:
2459 val = s->st00;
2460 break;
2461 case 0x3c4:
2462 val = s->sr_index;
2463 break;
2464 case 0x3c5:
2465 val = cirrus_vga_read_sr(c);
2466 break;
2467 #ifdef DEBUG_VGA_REG
2468 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2469 #endif
2470 break;
2471 case 0x3c6:
2472 val = cirrus_read_hidden_dac(c);
2473 break;
2474 case 0x3c7:
2475 val = s->dac_state;
2476 break;
2477 case 0x3c8:
2478 val = s->dac_write_index;
2479 c->cirrus_hidden_dac_lockindex = 0;
2480 break;
2481 case 0x3c9:
2482 val = cirrus_vga_read_palette(c);
2483 break;
2484 case 0x3ca:
2485 val = s->fcr;
2486 break;
2487 case 0x3cc:
2488 val = s->msr;
2489 break;
2490 case 0x3ce:
2491 val = s->gr_index;
2492 break;
2493 case 0x3cf:
2494 val = cirrus_vga_read_gr(c, s->gr_index);
2495 #ifdef DEBUG_VGA_REG
2496 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2497 #endif
2498 break;
2499 case 0x3b4:
2500 case 0x3d4:
2501 val = s->cr_index;
2502 break;
2503 case 0x3b5:
2504 case 0x3d5:
2505 val = cirrus_vga_read_cr(c, s->cr_index);
2506 #ifdef DEBUG_VGA_REG
2507 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2508 #endif
2509 break;
2510 case 0x3ba:
2511 case 0x3da:
2512 /* just toggle to fool polling */
2513 val = s->st01 = s->retrace(s);
2514 s->ar_flip_flop = 0;
2515 break;
2516 default:
2517 val = 0x00;
2518 break;
2519 }
2520 }
2521 #if defined(DEBUG_VGA)
2522 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2523 #endif
2524 return val;
2525 }
2526
2527 static void cirrus_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2528 {
2529 CirrusVGAState *c = opaque;
2530 VGACommonState *s = &c->vga;
2531 int index;
2532
2533 /* check port range access depending on color/monochrome mode */
2534 if (vga_ioport_invalid(s, addr)) {
2535 return;
2536 }
2537 #ifdef DEBUG_VGA
2538 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2539 #endif
2540
2541 switch (addr) {
2542 case 0x3c0:
2543 if (s->ar_flip_flop == 0) {
2544 val &= 0x3f;
2545 s->ar_index = val;
2546 } else {
2547 index = s->ar_index & 0x1f;
2548 switch (index) {
2549 case 0x00 ... 0x0f:
2550 s->ar[index] = val & 0x3f;
2551 break;
2552 case 0x10:
2553 s->ar[index] = val & ~0x10;
2554 break;
2555 case 0x11:
2556 s->ar[index] = val;
2557 break;
2558 case 0x12:
2559 s->ar[index] = val & ~0xc0;
2560 break;
2561 case 0x13:
2562 s->ar[index] = val & ~0xf0;
2563 break;
2564 case 0x14:
2565 s->ar[index] = val & ~0xf0;
2566 break;
2567 default:
2568 break;
2569 }
2570 }
2571 s->ar_flip_flop ^= 1;
2572 break;
2573 case 0x3c2:
2574 s->msr = val & ~0x10;
2575 s->update_retrace_info(s);
2576 break;
2577 case 0x3c4:
2578 s->sr_index = val;
2579 break;
2580 case 0x3c5:
2581 #ifdef DEBUG_VGA_REG
2582 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
2583 #endif
2584 cirrus_vga_write_sr(c, val);
2585 break;
2586 break;
2587 case 0x3c6:
2588 cirrus_write_hidden_dac(c, val);
2589 break;
2590 case 0x3c7:
2591 s->dac_read_index = val;
2592 s->dac_sub_index = 0;
2593 s->dac_state = 3;
2594 break;
2595 case 0x3c8:
2596 s->dac_write_index = val;
2597 s->dac_sub_index = 0;
2598 s->dac_state = 0;
2599 break;
2600 case 0x3c9:
2601 cirrus_vga_write_palette(c, val);
2602 break;
2603 case 0x3ce:
2604 s->gr_index = val;
2605 break;
2606 case 0x3cf:
2607 #ifdef DEBUG_VGA_REG
2608 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
2609 #endif
2610 cirrus_vga_write_gr(c, s->gr_index, val);
2611 break;
2612 case 0x3b4:
2613 case 0x3d4:
2614 s->cr_index = val;
2615 break;
2616 case 0x3b5:
2617 case 0x3d5:
2618 #ifdef DEBUG_VGA_REG
2619 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
2620 #endif
2621 cirrus_vga_write_cr(c, val);
2622 break;
2623 case 0x3ba:
2624 case 0x3da:
2625 s->fcr = val & 0x10;
2626 break;
2627 }
2628 }
2629
2630 /***************************************
2631 *
2632 * memory-mapped I/O access
2633 *
2634 ***************************************/
2635
2636 static uint64_t cirrus_mmio_read(void *opaque, target_phys_addr_t addr,
2637 unsigned size)
2638 {
2639 CirrusVGAState *s = opaque;
2640
2641 if (addr >= 0x100) {
2642 return cirrus_mmio_blt_read(s, addr - 0x100);
2643 } else {
2644 return cirrus_vga_ioport_read(s, addr + 0x3c0);
2645 }
2646 }
2647
2648 static void cirrus_mmio_write(void *opaque, target_phys_addr_t addr,
2649 uint64_t val, unsigned size)
2650 {
2651 CirrusVGAState *s = opaque;
2652
2653 if (addr >= 0x100) {
2654 cirrus_mmio_blt_write(s, addr - 0x100, val);
2655 } else {
2656 cirrus_vga_ioport_write(s, addr + 0x3c0, val);
2657 }
2658 }
2659
2660 static const MemoryRegionOps cirrus_mmio_io_ops = {
2661 .read = cirrus_mmio_read,
2662 .write = cirrus_mmio_write,
2663 .endianness = DEVICE_LITTLE_ENDIAN,
2664 .impl = {
2665 .min_access_size = 1,
2666 .max_access_size = 1,
2667 },
2668 };
2669
2670 /* load/save state */
2671
2672 static int cirrus_post_load(void *opaque, int version_id)
2673 {
2674 CirrusVGAState *s = opaque;
2675
2676 s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
2677 s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
2678
2679 cirrus_update_memory_access(s);
2680 /* force refresh */
2681 s->vga.graphic_mode = -1;
2682 cirrus_update_bank_ptr(s, 0);
2683 cirrus_update_bank_ptr(s, 1);
2684 return 0;
2685 }
2686
2687 static const VMStateDescription vmstate_cirrus_vga = {
2688 .name = "cirrus_vga",
2689 .version_id = 2,
2690 .minimum_version_id = 1,
2691 .minimum_version_id_old = 1,
2692 .post_load = cirrus_post_load,
2693 .fields = (VMStateField []) {
2694 VMSTATE_UINT32(vga.latch, CirrusVGAState),
2695 VMSTATE_UINT8(vga.sr_index, CirrusVGAState),
2696 VMSTATE_BUFFER(vga.sr, CirrusVGAState),
2697 VMSTATE_UINT8(vga.gr_index, CirrusVGAState),
2698 VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState),
2699 VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState),
2700 VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2),
2701 VMSTATE_UINT8(vga.ar_index, CirrusVGAState),
2702 VMSTATE_BUFFER(vga.ar, CirrusVGAState),
2703 VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState),
2704 VMSTATE_UINT8(vga.cr_index, CirrusVGAState),
2705 VMSTATE_BUFFER(vga.cr, CirrusVGAState),
2706 VMSTATE_UINT8(vga.msr, CirrusVGAState),
2707 VMSTATE_UINT8(vga.fcr, CirrusVGAState),
2708 VMSTATE_UINT8(vga.st00, CirrusVGAState),
2709 VMSTATE_UINT8(vga.st01, CirrusVGAState),
2710 VMSTATE_UINT8(vga.dac_state, CirrusVGAState),
2711 VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState),
2712 VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState),
2713 VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState),
2714 VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState),
2715 VMSTATE_BUFFER(vga.palette, CirrusVGAState),
2716 VMSTATE_INT32(vga.bank_offset, CirrusVGAState),
2717 VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState),
2718 VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState),
2719 VMSTATE_UINT32(hw_cursor_x, CirrusVGAState),
2720 VMSTATE_UINT32(hw_cursor_y, CirrusVGAState),
2721 /* XXX: we do not save the bitblt state - we assume we do not save
2722 the state when the blitter is active */
2723 VMSTATE_END_OF_LIST()
2724 }
2725 };
2726
2727 static const VMStateDescription vmstate_pci_cirrus_vga = {
2728 .name = "cirrus_vga",
2729 .version_id = 2,
2730 .minimum_version_id = 2,
2731 .minimum_version_id_old = 2,
2732 .fields = (VMStateField []) {
2733 VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState),
2734 VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
2735 vmstate_cirrus_vga, CirrusVGAState),
2736 VMSTATE_END_OF_LIST()
2737 }
2738 };
2739
2740 /***************************************
2741 *
2742 * initialize
2743 *
2744 ***************************************/
2745
2746 static void cirrus_reset(void *opaque)
2747 {
2748 CirrusVGAState *s = opaque;
2749
2750 vga_common_reset(&s->vga);
2751 unmap_linear_vram(s);
2752 s->vga.sr[0x06] = 0x0f;
2753 if (s->device_id == CIRRUS_ID_CLGD5446) {
2754 /* 4MB 64 bit memory config, always PCI */
2755 s->vga.sr[0x1F] = 0x2d; // MemClock
2756 s->vga.gr[0x18] = 0x0f; // fastest memory configuration
2757 s->vga.sr[0x0f] = 0x98;
2758 s->vga.sr[0x17] = 0x20;
2759 s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
2760 } else {
2761 s->vga.sr[0x1F] = 0x22; // MemClock
2762 s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
2763 s->vga.sr[0x17] = s->bustype;
2764 s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
2765 }
2766 s->vga.cr[0x27] = s->device_id;
2767
2768 /* Win2K seems to assume that the pattern buffer is at 0xff
2769 initially ! */
2770 memset(s->vga.vram_ptr, 0xff, s->real_vram_size);
2771
2772 s->cirrus_hidden_dac_lockindex = 5;
2773 s->cirrus_hidden_dac_data = 0;
2774 }
2775
2776 static const MemoryRegionOps cirrus_linear_io_ops = {
2777 .read = cirrus_linear_read,
2778 .write = cirrus_linear_write,
2779 .endianness = DEVICE_LITTLE_ENDIAN,
2780 .impl = {
2781 .min_access_size = 1,
2782 .max_access_size = 1,
2783 },
2784 };
2785
2786 static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci,
2787 MemoryRegion *system_memory)
2788 {
2789 int i;
2790 static int inited;
2791
2792 if (!inited) {
2793 inited = 1;
2794 for(i = 0;i < 256; i++)
2795 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
2796 rop_to_index[CIRRUS_ROP_0] = 0;
2797 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
2798 rop_to_index[CIRRUS_ROP_NOP] = 2;
2799 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
2800 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
2801 rop_to_index[CIRRUS_ROP_SRC] = 5;
2802 rop_to_index[CIRRUS_ROP_1] = 6;
2803 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
2804 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
2805 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
2806 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
2807 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
2808 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
2809 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
2810 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
2811 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
2812 s->device_id = device_id;
2813 if (is_pci)
2814 s->bustype = CIRRUS_BUSTYPE_PCI;
2815 else
2816 s->bustype = CIRRUS_BUSTYPE_ISA;
2817 }
2818
2819 register_ioport_write(0x3c0, 16, 1, cirrus_vga_ioport_write, s);
2820
2821 register_ioport_write(0x3b4, 2, 1, cirrus_vga_ioport_write, s);
2822 register_ioport_write(0x3d4, 2, 1, cirrus_vga_ioport_write, s);
2823 register_ioport_write(0x3ba, 1, 1, cirrus_vga_ioport_write, s);
2824 register_ioport_write(0x3da, 1, 1, cirrus_vga_ioport_write, s);
2825
2826 register_ioport_read(0x3c0, 16, 1, cirrus_vga_ioport_read, s);
2827
2828 register_ioport_read(0x3b4, 2, 1, cirrus_vga_ioport_read, s);
2829 register_ioport_read(0x3d4, 2, 1, cirrus_vga_ioport_read, s);
2830 register_ioport_read(0x3ba, 1, 1, cirrus_vga_ioport_read, s);
2831 register_ioport_read(0x3da, 1, 1, cirrus_vga_ioport_read, s);
2832
2833 memory_region_init(&s->low_mem_container,
2834 "cirrus-lowmem-container",
2835 0x20000);
2836
2837 memory_region_init_io(&s->low_mem, &cirrus_vga_mem_ops, s,
2838 "cirrus-low-memory", 0x20000);
2839 memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem);
2840 for (i = 0; i < 2; ++i) {
2841 static const char *names[] = { "vga.bank0", "vga.bank1" };
2842 MemoryRegion *bank = &s->cirrus_bank[i];
2843 memory_region_init_alias(bank, names[i], &s->vga.vram, 0, 0x8000);
2844 memory_region_set_enabled(bank, false);
2845 memory_region_add_subregion_overlap(&s->low_mem_container, i * 0x8000,
2846 bank, 1);
2847 }
2848 memory_region_add_subregion_overlap(system_memory,
2849 isa_mem_base + 0x000a0000,
2850 &s->low_mem_container,
2851 1);
2852 memory_region_set_coalescing(&s->low_mem);
2853
2854 /* I/O handler for LFB */
2855 memory_region_init_io(&s->cirrus_linear_io, &cirrus_linear_io_ops, s,
2856 "cirrus-linear-io", VGA_RAM_SIZE);
2857
2858 /* I/O handler for LFB */
2859 memory_region_init_io(&s->cirrus_linear_bitblt_io,
2860 &cirrus_linear_bitblt_io_ops,
2861 s,
2862 "cirrus-bitblt-mmio",
2863 0x400000);
2864
2865 /* I/O handler for memory-mapped I/O */
2866 memory_region_init_io(&s->cirrus_mmio_io, &cirrus_mmio_io_ops, s,
2867 "cirrus-mmio", CIRRUS_PNPMMIO_SIZE);
2868
2869 s->real_vram_size =
2870 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
2871
2872 /* XXX: s->vga.vram_size must be a power of two */
2873 s->cirrus_addr_mask = s->real_vram_size - 1;
2874 s->linear_mmio_mask = s->real_vram_size - 256;
2875
2876 s->vga.get_bpp = cirrus_get_bpp;
2877 s->vga.get_offsets = cirrus_get_offsets;
2878 s->vga.get_resolution = cirrus_get_resolution;
2879 s->vga.cursor_invalidate = cirrus_cursor_invalidate;
2880 s->vga.cursor_draw_line = cirrus_cursor_draw_line;
2881
2882 qemu_register_reset(cirrus_reset, s);
2883 }
2884
2885 /***************************************
2886 *
2887 * ISA bus support
2888 *
2889 ***************************************/
2890
2891 static int vga_initfn(ISADevice *dev)
2892 {
2893 ISACirrusVGAState *d = DO_UPCAST(ISACirrusVGAState, dev, dev);
2894 VGACommonState *s = &d->cirrus_vga.vga;
2895
2896 vga_common_init(s, VGA_RAM_SIZE);
2897 cirrus_init_common(&d->cirrus_vga, CIRRUS_ID_CLGD5430, 0,
2898 isa_address_space(dev));
2899 s->ds = graphic_console_init(s->update, s->invalidate,
2900 s->screen_dump, s->text_update,
2901 s);
2902 rom_add_vga(VGABIOS_CIRRUS_FILENAME);
2903 /* XXX ISA-LFB support */
2904 /* FIXME not qdev yet */
2905 return 0;
2906 }
2907
2908 static ISADeviceInfo isa_cirrus_vga_info = {
2909 .qdev.name = "isa-cirrus-vga",
2910 .qdev.size = sizeof(ISACirrusVGAState),
2911 .qdev.vmsd = &vmstate_cirrus_vga,
2912 .init = vga_initfn,
2913 };
2914
2915 static void isa_cirrus_vga_register(void)
2916 {
2917 isa_qdev_register(&isa_cirrus_vga_info);
2918 }
2919 device_init(isa_cirrus_vga_register)
2920
2921 /***************************************
2922 *
2923 * PCI bus support
2924 *
2925 ***************************************/
2926
2927 static int pci_cirrus_vga_initfn(PCIDevice *dev)
2928 {
2929 PCICirrusVGAState *d = DO_UPCAST(PCICirrusVGAState, dev, dev);
2930 CirrusVGAState *s = &d->cirrus_vga;
2931 PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->qdev.info);
2932 int16_t device_id = info->device_id;
2933
2934 /* setup VGA */
2935 vga_common_init(&s->vga, VGA_RAM_SIZE);
2936 cirrus_init_common(s, device_id, 1, pci_address_space(dev));
2937 s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
2938 s->vga.screen_dump, s->vga.text_update,
2939 &s->vga);
2940
2941 /* setup PCI */
2942
2943 memory_region_init(&s->pci_bar, "cirrus-pci-bar0", 0x2000000);
2944
2945 /* XXX: add byte swapping apertures */
2946 memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io);
2947 memory_region_add_subregion(&s->pci_bar, 0x1000000,
2948 &s->cirrus_linear_bitblt_io);
2949
2950 /* setup memory space */
2951 /* memory #0 LFB */
2952 /* memory #1 memory-mapped I/O */
2953 /* XXX: s->vga.vram_size must be a power of two */
2954 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->pci_bar);
2955 if (device_id == CIRRUS_ID_CLGD5446) {
2956 pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io);
2957 }
2958 return 0;
2959 }
2960
2961 DeviceState *pci_cirrus_vga_init(PCIBus *bus)
2962 {
2963 return &pci_create_simple(bus, -1, "cirrus-vga")->qdev;
2964 }
2965
2966 static PCIDeviceInfo cirrus_vga_info = {
2967 .qdev.name = "cirrus-vga",
2968 .qdev.desc = "Cirrus CLGD 54xx VGA",
2969 .qdev.size = sizeof(PCICirrusVGAState),
2970 .qdev.vmsd = &vmstate_pci_cirrus_vga,
2971 .no_hotplug = 1,
2972 .init = pci_cirrus_vga_initfn,
2973 .romfile = VGABIOS_CIRRUS_FILENAME,
2974 .vendor_id = PCI_VENDOR_ID_CIRRUS,
2975 .device_id = CIRRUS_ID_CLGD5446,
2976 .class_id = PCI_CLASS_DISPLAY_VGA,
2977 };
2978
2979 static void cirrus_vga_register(void)
2980 {
2981 pci_qdev_register(&cirrus_vga_info);
2982 }
2983 device_init(cirrus_vga_register);