Merge tag 'pull-testing-gdbstub-plugins-gitdm-061022-3' of https://github.com/stsquad...
[qemu.git] / hw / core / machine.c
1 /*
2 * QEMU Machine
3 *
4 * Copyright (C) 2014 Red Hat Inc
5 *
6 * Authors:
7 * Marcel Apfelbaum <marcel.a@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
10 * See the COPYING file in the top-level directory.
11 */
12
13 #include "qemu/osdep.h"
14 #include "qemu/option.h"
15 #include "qapi/qmp/qerror.h"
16 #include "sysemu/replay.h"
17 #include "qemu/units.h"
18 #include "hw/boards.h"
19 #include "hw/loader.h"
20 #include "qapi/error.h"
21 #include "qapi/qapi-visit-common.h"
22 #include "qapi/qapi-visit-machine.h"
23 #include "qapi/visitor.h"
24 #include "hw/sysbus.h"
25 #include "sysemu/cpus.h"
26 #include "sysemu/sysemu.h"
27 #include "sysemu/reset.h"
28 #include "sysemu/runstate.h"
29 #include "sysemu/numa.h"
30 #include "qemu/error-report.h"
31 #include "sysemu/qtest.h"
32 #include "hw/pci/pci.h"
33 #include "hw/mem/nvdimm.h"
34 #include "migration/global_state.h"
35 #include "migration/vmstate.h"
36 #include "exec/confidential-guest-support.h"
37 #include "hw/virtio/virtio.h"
38 #include "hw/virtio/virtio-pci.h"
39
40 GlobalProperty hw_compat_6_2[] = {};
41 const size_t hw_compat_6_2_len = G_N_ELEMENTS(hw_compat_6_2);
42
43 GlobalProperty hw_compat_6_1[] = {
44 { "vhost-user-vsock-device", "seqpacket", "off" },
45 { "nvme-ns", "shared", "off" },
46 };
47 const size_t hw_compat_6_1_len = G_N_ELEMENTS(hw_compat_6_1);
48
49 GlobalProperty hw_compat_6_0[] = {
50 { "gpex-pcihost", "allow-unmapped-accesses", "false" },
51 { "i8042", "extended-state", "false"},
52 { "nvme-ns", "eui64-default", "off"},
53 { "e1000", "init-vet", "off" },
54 { "e1000e", "init-vet", "off" },
55 { "vhost-vsock-device", "seqpacket", "off" },
56 };
57 const size_t hw_compat_6_0_len = G_N_ELEMENTS(hw_compat_6_0);
58
59 GlobalProperty hw_compat_5_2[] = {
60 { "ICH9-LPC", "smm-compat", "on"},
61 { "PIIX4_PM", "smm-compat", "on"},
62 { "virtio-blk-device", "report-discard-granularity", "off" },
63 { "virtio-net-pci-base", "vectors", "3"},
64 };
65 const size_t hw_compat_5_2_len = G_N_ELEMENTS(hw_compat_5_2);
66
67 GlobalProperty hw_compat_5_1[] = {
68 { "vhost-scsi", "num_queues", "1"},
69 { "vhost-user-blk", "num-queues", "1"},
70 { "vhost-user-scsi", "num_queues", "1"},
71 { "virtio-blk-device", "num-queues", "1"},
72 { "virtio-scsi-device", "num_queues", "1"},
73 { "nvme", "use-intel-id", "on"},
74 { "pvpanic", "events", "1"}, /* PVPANIC_PANICKED */
75 { "pl011", "migrate-clk", "off" },
76 { "virtio-pci", "x-ats-page-aligned", "off"},
77 };
78 const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1);
79
80 GlobalProperty hw_compat_5_0[] = {
81 { "pci-host-bridge", "x-config-reg-migration-enabled", "off" },
82 { "virtio-balloon-device", "page-poison", "false" },
83 { "vmport", "x-read-set-eax", "off" },
84 { "vmport", "x-signal-unsupported-cmd", "off" },
85 { "vmport", "x-report-vmx-type", "off" },
86 { "vmport", "x-cmds-v2", "off" },
87 { "virtio-device", "x-disable-legacy-check", "true" },
88 };
89 const size_t hw_compat_5_0_len = G_N_ELEMENTS(hw_compat_5_0);
90
91 GlobalProperty hw_compat_4_2[] = {
92 { "virtio-blk-device", "queue-size", "128"},
93 { "virtio-scsi-device", "virtqueue_size", "128"},
94 { "virtio-blk-device", "x-enable-wce-if-config-wce", "off" },
95 { "virtio-blk-device", "seg-max-adjust", "off"},
96 { "virtio-scsi-device", "seg_max_adjust", "off"},
97 { "vhost-blk-device", "seg_max_adjust", "off"},
98 { "usb-host", "suppress-remote-wake", "off" },
99 { "usb-redir", "suppress-remote-wake", "off" },
100 { "qxl", "revision", "4" },
101 { "qxl-vga", "revision", "4" },
102 { "fw_cfg", "acpi-mr-restore", "false" },
103 { "virtio-device", "use-disabled-flag", "false" },
104 };
105 const size_t hw_compat_4_2_len = G_N_ELEMENTS(hw_compat_4_2);
106
107 GlobalProperty hw_compat_4_1[] = {
108 { "virtio-pci", "x-pcie-flr-init", "off" },
109 };
110 const size_t hw_compat_4_1_len = G_N_ELEMENTS(hw_compat_4_1);
111
112 GlobalProperty hw_compat_4_0[] = {
113 { "VGA", "edid", "false" },
114 { "secondary-vga", "edid", "false" },
115 { "bochs-display", "edid", "false" },
116 { "virtio-vga", "edid", "false" },
117 { "virtio-gpu-device", "edid", "false" },
118 { "virtio-device", "use-started", "false" },
119 { "virtio-balloon-device", "qemu-4-0-config-size", "true" },
120 { "pl031", "migrate-tick-offset", "false" },
121 };
122 const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0);
123
124 GlobalProperty hw_compat_3_1[] = {
125 { "pcie-root-port", "x-speed", "2_5" },
126 { "pcie-root-port", "x-width", "1" },
127 { "memory-backend-file", "x-use-canonical-path-for-ramblock-id", "true" },
128 { "memory-backend-memfd", "x-use-canonical-path-for-ramblock-id", "true" },
129 { "tpm-crb", "ppi", "false" },
130 { "tpm-tis", "ppi", "false" },
131 { "usb-kbd", "serial", "42" },
132 { "usb-mouse", "serial", "42" },
133 { "usb-tablet", "serial", "42" },
134 { "virtio-blk-device", "discard", "false" },
135 { "virtio-blk-device", "write-zeroes", "false" },
136 { "virtio-balloon-device", "qemu-4-0-config-size", "false" },
137 { "pcie-root-port-base", "disable-acs", "true" }, /* Added in 4.1 */
138 };
139 const size_t hw_compat_3_1_len = G_N_ELEMENTS(hw_compat_3_1);
140
141 GlobalProperty hw_compat_3_0[] = {};
142 const size_t hw_compat_3_0_len = G_N_ELEMENTS(hw_compat_3_0);
143
144 GlobalProperty hw_compat_2_12[] = {
145 { "migration", "decompress-error-check", "off" },
146 { "hda-audio", "use-timer", "false" },
147 { "cirrus-vga", "global-vmstate", "true" },
148 { "VGA", "global-vmstate", "true" },
149 { "vmware-svga", "global-vmstate", "true" },
150 { "qxl-vga", "global-vmstate", "true" },
151 };
152 const size_t hw_compat_2_12_len = G_N_ELEMENTS(hw_compat_2_12);
153
154 GlobalProperty hw_compat_2_11[] = {
155 { "hpet", "hpet-offset-saved", "false" },
156 { "virtio-blk-pci", "vectors", "2" },
157 { "vhost-user-blk-pci", "vectors", "2" },
158 { "e1000", "migrate_tso_props", "off" },
159 };
160 const size_t hw_compat_2_11_len = G_N_ELEMENTS(hw_compat_2_11);
161
162 GlobalProperty hw_compat_2_10[] = {
163 { "virtio-mouse-device", "wheel-axis", "false" },
164 { "virtio-tablet-device", "wheel-axis", "false" },
165 };
166 const size_t hw_compat_2_10_len = G_N_ELEMENTS(hw_compat_2_10);
167
168 GlobalProperty hw_compat_2_9[] = {
169 { "pci-bridge", "shpc", "off" },
170 { "intel-iommu", "pt", "off" },
171 { "virtio-net-device", "x-mtu-bypass-backend", "off" },
172 { "pcie-root-port", "x-migrate-msix", "false" },
173 };
174 const size_t hw_compat_2_9_len = G_N_ELEMENTS(hw_compat_2_9);
175
176 GlobalProperty hw_compat_2_8[] = {
177 { "fw_cfg_mem", "x-file-slots", "0x10" },
178 { "fw_cfg_io", "x-file-slots", "0x10" },
179 { "pflash_cfi01", "old-multiple-chip-handling", "on" },
180 { "pci-bridge", "shpc", "on" },
181 { TYPE_PCI_DEVICE, "x-pcie-extcap-init", "off" },
182 { "virtio-pci", "x-pcie-deverr-init", "off" },
183 { "virtio-pci", "x-pcie-lnkctl-init", "off" },
184 { "virtio-pci", "x-pcie-pm-init", "off" },
185 { "cirrus-vga", "vgamem_mb", "8" },
186 { "isa-cirrus-vga", "vgamem_mb", "8" },
187 };
188 const size_t hw_compat_2_8_len = G_N_ELEMENTS(hw_compat_2_8);
189
190 GlobalProperty hw_compat_2_7[] = {
191 { "virtio-pci", "page-per-vq", "on" },
192 { "virtio-serial-device", "emergency-write", "off" },
193 { "ioapic", "version", "0x11" },
194 { "intel-iommu", "x-buggy-eim", "true" },
195 { "virtio-pci", "x-ignore-backend-features", "on" },
196 };
197 const size_t hw_compat_2_7_len = G_N_ELEMENTS(hw_compat_2_7);
198
199 GlobalProperty hw_compat_2_6[] = {
200 { "virtio-mmio", "format_transport_address", "off" },
201 /* Optional because not all virtio-pci devices support legacy mode */
202 { "virtio-pci", "disable-modern", "on", .optional = true },
203 { "virtio-pci", "disable-legacy", "off", .optional = true },
204 };
205 const size_t hw_compat_2_6_len = G_N_ELEMENTS(hw_compat_2_6);
206
207 GlobalProperty hw_compat_2_5[] = {
208 { "isa-fdc", "fallback", "144" },
209 { "pvscsi", "x-old-pci-configuration", "on" },
210 { "pvscsi", "x-disable-pcie", "on" },
211 { "vmxnet3", "x-old-msi-offsets", "on" },
212 { "vmxnet3", "x-disable-pcie", "on" },
213 };
214 const size_t hw_compat_2_5_len = G_N_ELEMENTS(hw_compat_2_5);
215
216 GlobalProperty hw_compat_2_4[] = {
217 /* Optional because the 'scsi' property is Linux-only */
218 { "virtio-blk-device", "scsi", "true", .optional = true },
219 { "e1000", "extra_mac_registers", "off" },
220 { "virtio-pci", "x-disable-pcie", "on" },
221 { "virtio-pci", "migrate-extra", "off" },
222 { "fw_cfg_mem", "dma_enabled", "off" },
223 { "fw_cfg_io", "dma_enabled", "off" }
224 };
225 const size_t hw_compat_2_4_len = G_N_ELEMENTS(hw_compat_2_4);
226
227 GlobalProperty hw_compat_2_3[] = {
228 { "virtio-blk-pci", "any_layout", "off" },
229 { "virtio-balloon-pci", "any_layout", "off" },
230 { "virtio-serial-pci", "any_layout", "off" },
231 { "virtio-9p-pci", "any_layout", "off" },
232 { "virtio-rng-pci", "any_layout", "off" },
233 { TYPE_PCI_DEVICE, "x-pcie-lnksta-dllla", "off" },
234 { "migration", "send-configuration", "off" },
235 { "migration", "send-section-footer", "off" },
236 { "migration", "store-global-state", "off" },
237 };
238 const size_t hw_compat_2_3_len = G_N_ELEMENTS(hw_compat_2_3);
239
240 GlobalProperty hw_compat_2_2[] = {};
241 const size_t hw_compat_2_2_len = G_N_ELEMENTS(hw_compat_2_2);
242
243 GlobalProperty hw_compat_2_1[] = {
244 { "intel-hda", "old_msi_addr", "on" },
245 { "VGA", "qemu-extended-regs", "off" },
246 { "secondary-vga", "qemu-extended-regs", "off" },
247 { "virtio-scsi-pci", "any_layout", "off" },
248 { "usb-mouse", "usb_version", "1" },
249 { "usb-kbd", "usb_version", "1" },
250 { "virtio-pci", "virtio-pci-bus-master-bug-migration", "on" },
251 };
252 const size_t hw_compat_2_1_len = G_N_ELEMENTS(hw_compat_2_1);
253
254 MachineState *current_machine;
255
256 static char *machine_get_kernel(Object *obj, Error **errp)
257 {
258 MachineState *ms = MACHINE(obj);
259
260 return g_strdup(ms->kernel_filename);
261 }
262
263 static void machine_set_kernel(Object *obj, const char *value, Error **errp)
264 {
265 MachineState *ms = MACHINE(obj);
266
267 g_free(ms->kernel_filename);
268 ms->kernel_filename = g_strdup(value);
269 }
270
271 static char *machine_get_initrd(Object *obj, Error **errp)
272 {
273 MachineState *ms = MACHINE(obj);
274
275 return g_strdup(ms->initrd_filename);
276 }
277
278 static void machine_set_initrd(Object *obj, const char *value, Error **errp)
279 {
280 MachineState *ms = MACHINE(obj);
281
282 g_free(ms->initrd_filename);
283 ms->initrd_filename = g_strdup(value);
284 }
285
286 static char *machine_get_append(Object *obj, Error **errp)
287 {
288 MachineState *ms = MACHINE(obj);
289
290 return g_strdup(ms->kernel_cmdline);
291 }
292
293 static void machine_set_append(Object *obj, const char *value, Error **errp)
294 {
295 MachineState *ms = MACHINE(obj);
296
297 g_free(ms->kernel_cmdline);
298 ms->kernel_cmdline = g_strdup(value);
299 }
300
301 static char *machine_get_dtb(Object *obj, Error **errp)
302 {
303 MachineState *ms = MACHINE(obj);
304
305 return g_strdup(ms->dtb);
306 }
307
308 static void machine_set_dtb(Object *obj, const char *value, Error **errp)
309 {
310 MachineState *ms = MACHINE(obj);
311
312 g_free(ms->dtb);
313 ms->dtb = g_strdup(value);
314 }
315
316 static char *machine_get_dumpdtb(Object *obj, Error **errp)
317 {
318 MachineState *ms = MACHINE(obj);
319
320 return g_strdup(ms->dumpdtb);
321 }
322
323 static void machine_set_dumpdtb(Object *obj, const char *value, Error **errp)
324 {
325 MachineState *ms = MACHINE(obj);
326
327 g_free(ms->dumpdtb);
328 ms->dumpdtb = g_strdup(value);
329 }
330
331 static void machine_get_phandle_start(Object *obj, Visitor *v,
332 const char *name, void *opaque,
333 Error **errp)
334 {
335 MachineState *ms = MACHINE(obj);
336 int64_t value = ms->phandle_start;
337
338 visit_type_int(v, name, &value, errp);
339 }
340
341 static void machine_set_phandle_start(Object *obj, Visitor *v,
342 const char *name, void *opaque,
343 Error **errp)
344 {
345 MachineState *ms = MACHINE(obj);
346 int64_t value;
347
348 if (!visit_type_int(v, name, &value, errp)) {
349 return;
350 }
351
352 ms->phandle_start = value;
353 }
354
355 static char *machine_get_dt_compatible(Object *obj, Error **errp)
356 {
357 MachineState *ms = MACHINE(obj);
358
359 return g_strdup(ms->dt_compatible);
360 }
361
362 static void machine_set_dt_compatible(Object *obj, const char *value, Error **errp)
363 {
364 MachineState *ms = MACHINE(obj);
365
366 g_free(ms->dt_compatible);
367 ms->dt_compatible = g_strdup(value);
368 }
369
370 static bool machine_get_dump_guest_core(Object *obj, Error **errp)
371 {
372 MachineState *ms = MACHINE(obj);
373
374 return ms->dump_guest_core;
375 }
376
377 static void machine_set_dump_guest_core(Object *obj, bool value, Error **errp)
378 {
379 MachineState *ms = MACHINE(obj);
380
381 ms->dump_guest_core = value;
382 }
383
384 static bool machine_get_mem_merge(Object *obj, Error **errp)
385 {
386 MachineState *ms = MACHINE(obj);
387
388 return ms->mem_merge;
389 }
390
391 static void machine_set_mem_merge(Object *obj, bool value, Error **errp)
392 {
393 MachineState *ms = MACHINE(obj);
394
395 ms->mem_merge = value;
396 }
397
398 static bool machine_get_usb(Object *obj, Error **errp)
399 {
400 MachineState *ms = MACHINE(obj);
401
402 return ms->usb;
403 }
404
405 static void machine_set_usb(Object *obj, bool value, Error **errp)
406 {
407 MachineState *ms = MACHINE(obj);
408
409 ms->usb = value;
410 ms->usb_disabled = !value;
411 }
412
413 static bool machine_get_graphics(Object *obj, Error **errp)
414 {
415 MachineState *ms = MACHINE(obj);
416
417 return ms->enable_graphics;
418 }
419
420 static void machine_set_graphics(Object *obj, bool value, Error **errp)
421 {
422 MachineState *ms = MACHINE(obj);
423
424 ms->enable_graphics = value;
425 }
426
427 static char *machine_get_firmware(Object *obj, Error **errp)
428 {
429 MachineState *ms = MACHINE(obj);
430
431 return g_strdup(ms->firmware);
432 }
433
434 static void machine_set_firmware(Object *obj, const char *value, Error **errp)
435 {
436 MachineState *ms = MACHINE(obj);
437
438 g_free(ms->firmware);
439 ms->firmware = g_strdup(value);
440 }
441
442 static void machine_set_suppress_vmdesc(Object *obj, bool value, Error **errp)
443 {
444 MachineState *ms = MACHINE(obj);
445
446 ms->suppress_vmdesc = value;
447 }
448
449 static bool machine_get_suppress_vmdesc(Object *obj, Error **errp)
450 {
451 MachineState *ms = MACHINE(obj);
452
453 return ms->suppress_vmdesc;
454 }
455
456 static char *machine_get_memory_encryption(Object *obj, Error **errp)
457 {
458 MachineState *ms = MACHINE(obj);
459
460 if (ms->cgs) {
461 return g_strdup(object_get_canonical_path_component(OBJECT(ms->cgs)));
462 }
463
464 return NULL;
465 }
466
467 static void machine_set_memory_encryption(Object *obj, const char *value,
468 Error **errp)
469 {
470 Object *cgs =
471 object_resolve_path_component(object_get_objects_root(), value);
472
473 if (!cgs) {
474 error_setg(errp, "No such memory encryption object '%s'", value);
475 return;
476 }
477
478 object_property_set_link(obj, "confidential-guest-support", cgs, errp);
479 }
480
481 static void machine_check_confidential_guest_support(const Object *obj,
482 const char *name,
483 Object *new_target,
484 Error **errp)
485 {
486 /*
487 * So far the only constraint is that the target has the
488 * TYPE_CONFIDENTIAL_GUEST_SUPPORT interface, and that's checked
489 * by the QOM core
490 */
491 }
492
493 static bool machine_get_nvdimm(Object *obj, Error **errp)
494 {
495 MachineState *ms = MACHINE(obj);
496
497 return ms->nvdimms_state->is_enabled;
498 }
499
500 static void machine_set_nvdimm(Object *obj, bool value, Error **errp)
501 {
502 MachineState *ms = MACHINE(obj);
503
504 ms->nvdimms_state->is_enabled = value;
505 }
506
507 static bool machine_get_hmat(Object *obj, Error **errp)
508 {
509 MachineState *ms = MACHINE(obj);
510
511 return ms->numa_state->hmat_enabled;
512 }
513
514 static void machine_set_hmat(Object *obj, bool value, Error **errp)
515 {
516 MachineState *ms = MACHINE(obj);
517
518 ms->numa_state->hmat_enabled = value;
519 }
520
521 static char *machine_get_nvdimm_persistence(Object *obj, Error **errp)
522 {
523 MachineState *ms = MACHINE(obj);
524
525 return g_strdup(ms->nvdimms_state->persistence_string);
526 }
527
528 static void machine_set_nvdimm_persistence(Object *obj, const char *value,
529 Error **errp)
530 {
531 MachineState *ms = MACHINE(obj);
532 NVDIMMState *nvdimms_state = ms->nvdimms_state;
533
534 if (strcmp(value, "cpu") == 0) {
535 nvdimms_state->persistence = 3;
536 } else if (strcmp(value, "mem-ctrl") == 0) {
537 nvdimms_state->persistence = 2;
538 } else {
539 error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option",
540 value);
541 return;
542 }
543
544 g_free(nvdimms_state->persistence_string);
545 nvdimms_state->persistence_string = g_strdup(value);
546 }
547
548 void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type)
549 {
550 QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type));
551 }
552
553 bool device_is_dynamic_sysbus(MachineClass *mc, DeviceState *dev)
554 {
555 Object *obj = OBJECT(dev);
556
557 if (!object_dynamic_cast(obj, TYPE_SYS_BUS_DEVICE)) {
558 return false;
559 }
560
561 return device_type_is_dynamic_sysbus(mc, object_get_typename(obj));
562 }
563
564 bool device_type_is_dynamic_sysbus(MachineClass *mc, const char *type)
565 {
566 bool allowed = false;
567 strList *wl;
568 ObjectClass *klass = object_class_by_name(type);
569
570 for (wl = mc->allowed_dynamic_sysbus_devices;
571 !allowed && wl;
572 wl = wl->next) {
573 allowed |= !!object_class_dynamic_cast(klass, wl->value);
574 }
575
576 return allowed;
577 }
578
579 static char *machine_get_memdev(Object *obj, Error **errp)
580 {
581 MachineState *ms = MACHINE(obj);
582
583 return g_strdup(ms->ram_memdev_id);
584 }
585
586 static void machine_set_memdev(Object *obj, const char *value, Error **errp)
587 {
588 MachineState *ms = MACHINE(obj);
589
590 g_free(ms->ram_memdev_id);
591 ms->ram_memdev_id = g_strdup(value);
592 }
593
594 HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine)
595 {
596 int i;
597 HotpluggableCPUList *head = NULL;
598 MachineClass *mc = MACHINE_GET_CLASS(machine);
599
600 /* force board to initialize possible_cpus if it hasn't been done yet */
601 mc->possible_cpu_arch_ids(machine);
602
603 for (i = 0; i < machine->possible_cpus->len; i++) {
604 Object *cpu;
605 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
606
607 cpu_item->type = g_strdup(machine->possible_cpus->cpus[i].type);
608 cpu_item->vcpus_count = machine->possible_cpus->cpus[i].vcpus_count;
609 cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props,
610 sizeof(*cpu_item->props));
611
612 cpu = machine->possible_cpus->cpus[i].cpu;
613 if (cpu) {
614 cpu_item->has_qom_path = true;
615 cpu_item->qom_path = object_get_canonical_path(cpu);
616 }
617 QAPI_LIST_PREPEND(head, cpu_item);
618 }
619 return head;
620 }
621
622 /**
623 * machine_set_cpu_numa_node:
624 * @machine: machine object to modify
625 * @props: specifies which cpu objects to assign to
626 * numa node specified by @props.node_id
627 * @errp: if an error occurs, a pointer to an area to store the error
628 *
629 * Associate NUMA node specified by @props.node_id with cpu slots that
630 * match socket/core/thread-ids specified by @props. It's recommended to use
631 * query-hotpluggable-cpus.props values to specify affected cpu slots,
632 * which would lead to exact 1:1 mapping of cpu slots to NUMA node.
633 *
634 * However for CLI convenience it's possible to pass in subset of properties,
635 * which would affect all cpu slots that match it.
636 * Ex for pc machine:
637 * -smp 4,cores=2,sockets=2 -numa node,nodeid=0 -numa node,nodeid=1 \
638 * -numa cpu,node-id=0,socket_id=0 \
639 * -numa cpu,node-id=1,socket_id=1
640 * will assign all child cores of socket 0 to node 0 and
641 * of socket 1 to node 1.
642 *
643 * On attempt of reassigning (already assigned) cpu slot to another NUMA node,
644 * return error.
645 * Empty subset is disallowed and function will return with error in this case.
646 */
647 void machine_set_cpu_numa_node(MachineState *machine,
648 const CpuInstanceProperties *props, Error **errp)
649 {
650 MachineClass *mc = MACHINE_GET_CLASS(machine);
651 NodeInfo *numa_info = machine->numa_state->nodes;
652 bool match = false;
653 int i;
654
655 if (!mc->possible_cpu_arch_ids) {
656 error_setg(errp, "mapping of CPUs to NUMA node is not supported");
657 return;
658 }
659
660 /* disabling node mapping is not supported, forbid it */
661 assert(props->has_node_id);
662
663 /* force board to initialize possible_cpus if it hasn't been done yet */
664 mc->possible_cpu_arch_ids(machine);
665
666 for (i = 0; i < machine->possible_cpus->len; i++) {
667 CPUArchId *slot = &machine->possible_cpus->cpus[i];
668
669 /* reject unsupported by board properties */
670 if (props->has_thread_id && !slot->props.has_thread_id) {
671 error_setg(errp, "thread-id is not supported");
672 return;
673 }
674
675 if (props->has_core_id && !slot->props.has_core_id) {
676 error_setg(errp, "core-id is not supported");
677 return;
678 }
679
680 if (props->has_socket_id && !slot->props.has_socket_id) {
681 error_setg(errp, "socket-id is not supported");
682 return;
683 }
684
685 if (props->has_die_id && !slot->props.has_die_id) {
686 error_setg(errp, "die-id is not supported");
687 return;
688 }
689
690 /* skip slots with explicit mismatch */
691 if (props->has_thread_id && props->thread_id != slot->props.thread_id) {
692 continue;
693 }
694
695 if (props->has_core_id && props->core_id != slot->props.core_id) {
696 continue;
697 }
698
699 if (props->has_die_id && props->die_id != slot->props.die_id) {
700 continue;
701 }
702
703 if (props->has_socket_id && props->socket_id != slot->props.socket_id) {
704 continue;
705 }
706
707 /* reject assignment if slot is already assigned, for compatibility
708 * of legacy cpu_index mapping with SPAPR core based mapping do not
709 * error out if cpu thread and matched core have the same node-id */
710 if (slot->props.has_node_id &&
711 slot->props.node_id != props->node_id) {
712 error_setg(errp, "CPU is already assigned to node-id: %" PRId64,
713 slot->props.node_id);
714 return;
715 }
716
717 /* assign slot to node as it's matched '-numa cpu' key */
718 match = true;
719 slot->props.node_id = props->node_id;
720 slot->props.has_node_id = props->has_node_id;
721
722 if (machine->numa_state->hmat_enabled) {
723 if ((numa_info[props->node_id].initiator < MAX_NODES) &&
724 (props->node_id != numa_info[props->node_id].initiator)) {
725 error_setg(errp, "The initiator of CPU NUMA node %" PRId64
726 " should be itself (got %" PRIu16 ")",
727 props->node_id, numa_info[props->node_id].initiator);
728 return;
729 }
730 numa_info[props->node_id].has_cpu = true;
731 numa_info[props->node_id].initiator = props->node_id;
732 }
733 }
734
735 if (!match) {
736 error_setg(errp, "no match found");
737 }
738 }
739
740 static void machine_get_smp(Object *obj, Visitor *v, const char *name,
741 void *opaque, Error **errp)
742 {
743 MachineState *ms = MACHINE(obj);
744 SMPConfiguration *config = &(SMPConfiguration){
745 .has_cpus = true, .cpus = ms->smp.cpus,
746 .has_sockets = true, .sockets = ms->smp.sockets,
747 .has_dies = true, .dies = ms->smp.dies,
748 .has_clusters = true, .clusters = ms->smp.clusters,
749 .has_cores = true, .cores = ms->smp.cores,
750 .has_threads = true, .threads = ms->smp.threads,
751 .has_maxcpus = true, .maxcpus = ms->smp.max_cpus,
752 };
753
754 if (!visit_type_SMPConfiguration(v, name, &config, &error_abort)) {
755 return;
756 }
757 }
758
759 static void machine_set_smp(Object *obj, Visitor *v, const char *name,
760 void *opaque, Error **errp)
761 {
762 MachineState *ms = MACHINE(obj);
763 g_autoptr(SMPConfiguration) config = NULL;
764
765 if (!visit_type_SMPConfiguration(v, name, &config, errp)) {
766 return;
767 }
768
769 machine_parse_smp_config(ms, config, errp);
770 }
771
772 static void machine_class_init(ObjectClass *oc, void *data)
773 {
774 MachineClass *mc = MACHINE_CLASS(oc);
775
776 /* Default 128 MB as guest ram size */
777 mc->default_ram_size = 128 * MiB;
778 mc->rom_file_has_mr = true;
779
780 /* numa node memory size aligned on 8MB by default.
781 * On Linux, each node's border has to be 8MB aligned
782 */
783 mc->numa_mem_align_shift = 23;
784
785 object_class_property_add_str(oc, "kernel",
786 machine_get_kernel, machine_set_kernel);
787 object_class_property_set_description(oc, "kernel",
788 "Linux kernel image file");
789
790 object_class_property_add_str(oc, "initrd",
791 machine_get_initrd, machine_set_initrd);
792 object_class_property_set_description(oc, "initrd",
793 "Linux initial ramdisk file");
794
795 object_class_property_add_str(oc, "append",
796 machine_get_append, machine_set_append);
797 object_class_property_set_description(oc, "append",
798 "Linux kernel command line");
799
800 object_class_property_add_str(oc, "dtb",
801 machine_get_dtb, machine_set_dtb);
802 object_class_property_set_description(oc, "dtb",
803 "Linux kernel device tree file");
804
805 object_class_property_add_str(oc, "dumpdtb",
806 machine_get_dumpdtb, machine_set_dumpdtb);
807 object_class_property_set_description(oc, "dumpdtb",
808 "Dump current dtb to a file and quit");
809
810 object_class_property_add(oc, "smp", "SMPConfiguration",
811 machine_get_smp, machine_set_smp,
812 NULL, NULL);
813 object_class_property_set_description(oc, "smp",
814 "CPU topology");
815
816 object_class_property_add(oc, "phandle-start", "int",
817 machine_get_phandle_start, machine_set_phandle_start,
818 NULL, NULL);
819 object_class_property_set_description(oc, "phandle-start",
820 "The first phandle ID we may generate dynamically");
821
822 object_class_property_add_str(oc, "dt-compatible",
823 machine_get_dt_compatible, machine_set_dt_compatible);
824 object_class_property_set_description(oc, "dt-compatible",
825 "Overrides the \"compatible\" property of the dt root node");
826
827 object_class_property_add_bool(oc, "dump-guest-core",
828 machine_get_dump_guest_core, machine_set_dump_guest_core);
829 object_class_property_set_description(oc, "dump-guest-core",
830 "Include guest memory in a core dump");
831
832 object_class_property_add_bool(oc, "mem-merge",
833 machine_get_mem_merge, machine_set_mem_merge);
834 object_class_property_set_description(oc, "mem-merge",
835 "Enable/disable memory merge support");
836
837 object_class_property_add_bool(oc, "usb",
838 machine_get_usb, machine_set_usb);
839 object_class_property_set_description(oc, "usb",
840 "Set on/off to enable/disable usb");
841
842 object_class_property_add_bool(oc, "graphics",
843 machine_get_graphics, machine_set_graphics);
844 object_class_property_set_description(oc, "graphics",
845 "Set on/off to enable/disable graphics emulation");
846
847 object_class_property_add_str(oc, "firmware",
848 machine_get_firmware, machine_set_firmware);
849 object_class_property_set_description(oc, "firmware",
850 "Firmware image");
851
852 object_class_property_add_bool(oc, "suppress-vmdesc",
853 machine_get_suppress_vmdesc, machine_set_suppress_vmdesc);
854 object_class_property_set_description(oc, "suppress-vmdesc",
855 "Set on to disable self-describing migration");
856
857 object_class_property_add_link(oc, "confidential-guest-support",
858 TYPE_CONFIDENTIAL_GUEST_SUPPORT,
859 offsetof(MachineState, cgs),
860 machine_check_confidential_guest_support,
861 OBJ_PROP_LINK_STRONG);
862 object_class_property_set_description(oc, "confidential-guest-support",
863 "Set confidential guest scheme to support");
864
865 /* For compatibility */
866 object_class_property_add_str(oc, "memory-encryption",
867 machine_get_memory_encryption, machine_set_memory_encryption);
868 object_class_property_set_description(oc, "memory-encryption",
869 "Set memory encryption object to use");
870
871 object_class_property_add_str(oc, "memory-backend",
872 machine_get_memdev, machine_set_memdev);
873 object_class_property_set_description(oc, "memory-backend",
874 "Set RAM backend"
875 "Valid value is ID of hostmem based backend");
876 }
877
878 static void machine_class_base_init(ObjectClass *oc, void *data)
879 {
880 MachineClass *mc = MACHINE_CLASS(oc);
881 mc->max_cpus = mc->max_cpus ?: 1;
882 mc->min_cpus = mc->min_cpus ?: 1;
883 mc->default_cpus = mc->default_cpus ?: 1;
884
885 if (!object_class_is_abstract(oc)) {
886 const char *cname = object_class_get_name(oc);
887 assert(g_str_has_suffix(cname, TYPE_MACHINE_SUFFIX));
888 mc->name = g_strndup(cname,
889 strlen(cname) - strlen(TYPE_MACHINE_SUFFIX));
890 mc->compat_props = g_ptr_array_new();
891 }
892 }
893
894 static void machine_initfn(Object *obj)
895 {
896 MachineState *ms = MACHINE(obj);
897 MachineClass *mc = MACHINE_GET_CLASS(obj);
898
899 container_get(obj, "/peripheral");
900 container_get(obj, "/peripheral-anon");
901
902 ms->dump_guest_core = true;
903 ms->mem_merge = true;
904 ms->enable_graphics = true;
905 ms->kernel_cmdline = g_strdup("");
906
907 if (mc->nvdimm_supported) {
908 Object *obj = OBJECT(ms);
909
910 ms->nvdimms_state = g_new0(NVDIMMState, 1);
911 object_property_add_bool(obj, "nvdimm",
912 machine_get_nvdimm, machine_set_nvdimm);
913 object_property_set_description(obj, "nvdimm",
914 "Set on/off to enable/disable "
915 "NVDIMM instantiation");
916
917 object_property_add_str(obj, "nvdimm-persistence",
918 machine_get_nvdimm_persistence,
919 machine_set_nvdimm_persistence);
920 object_property_set_description(obj, "nvdimm-persistence",
921 "Set NVDIMM persistence"
922 "Valid values are cpu, mem-ctrl");
923 }
924
925 if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) {
926 ms->numa_state = g_new0(NumaState, 1);
927 object_property_add_bool(obj, "hmat",
928 machine_get_hmat, machine_set_hmat);
929 object_property_set_description(obj, "hmat",
930 "Set on/off to enable/disable "
931 "ACPI Heterogeneous Memory Attribute "
932 "Table (HMAT)");
933 }
934
935 /* default to mc->default_cpus */
936 ms->smp.cpus = mc->default_cpus;
937 ms->smp.max_cpus = mc->default_cpus;
938 ms->smp.sockets = 1;
939 ms->smp.dies = 1;
940 ms->smp.clusters = 1;
941 ms->smp.cores = 1;
942 ms->smp.threads = 1;
943 }
944
945 static void machine_finalize(Object *obj)
946 {
947 MachineState *ms = MACHINE(obj);
948
949 g_free(ms->kernel_filename);
950 g_free(ms->initrd_filename);
951 g_free(ms->kernel_cmdline);
952 g_free(ms->dtb);
953 g_free(ms->dumpdtb);
954 g_free(ms->dt_compatible);
955 g_free(ms->firmware);
956 g_free(ms->device_memory);
957 g_free(ms->nvdimms_state);
958 g_free(ms->numa_state);
959 }
960
961 bool machine_usb(MachineState *machine)
962 {
963 return machine->usb;
964 }
965
966 int machine_phandle_start(MachineState *machine)
967 {
968 return machine->phandle_start;
969 }
970
971 bool machine_dump_guest_core(MachineState *machine)
972 {
973 return machine->dump_guest_core;
974 }
975
976 bool machine_mem_merge(MachineState *machine)
977 {
978 return machine->mem_merge;
979 }
980
981 static char *cpu_slot_to_string(const CPUArchId *cpu)
982 {
983 GString *s = g_string_new(NULL);
984 if (cpu->props.has_socket_id) {
985 g_string_append_printf(s, "socket-id: %"PRId64, cpu->props.socket_id);
986 }
987 if (cpu->props.has_die_id) {
988 if (s->len) {
989 g_string_append_printf(s, ", ");
990 }
991 g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id);
992 }
993 if (cpu->props.has_core_id) {
994 if (s->len) {
995 g_string_append_printf(s, ", ");
996 }
997 g_string_append_printf(s, "core-id: %"PRId64, cpu->props.core_id);
998 }
999 if (cpu->props.has_thread_id) {
1000 if (s->len) {
1001 g_string_append_printf(s, ", ");
1002 }
1003 g_string_append_printf(s, "thread-id: %"PRId64, cpu->props.thread_id);
1004 }
1005 return g_string_free(s, false);
1006 }
1007
1008 static void numa_validate_initiator(NumaState *numa_state)
1009 {
1010 int i;
1011 NodeInfo *numa_info = numa_state->nodes;
1012
1013 for (i = 0; i < numa_state->num_nodes; i++) {
1014 if (numa_info[i].initiator == MAX_NODES) {
1015 error_report("The initiator of NUMA node %d is missing, use "
1016 "'-numa node,initiator' option to declare it", i);
1017 exit(1);
1018 }
1019
1020 if (!numa_info[numa_info[i].initiator].present) {
1021 error_report("NUMA node %" PRIu16 " is missing, use "
1022 "'-numa node' option to declare it first",
1023 numa_info[i].initiator);
1024 exit(1);
1025 }
1026
1027 if (!numa_info[numa_info[i].initiator].has_cpu) {
1028 error_report("The initiator of NUMA node %d is invalid", i);
1029 exit(1);
1030 }
1031 }
1032 }
1033
1034 static void machine_numa_finish_cpu_init(MachineState *machine)
1035 {
1036 int i;
1037 bool default_mapping;
1038 GString *s = g_string_new(NULL);
1039 MachineClass *mc = MACHINE_GET_CLASS(machine);
1040 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(machine);
1041
1042 assert(machine->numa_state->num_nodes);
1043 for (i = 0; i < possible_cpus->len; i++) {
1044 if (possible_cpus->cpus[i].props.has_node_id) {
1045 break;
1046 }
1047 }
1048 default_mapping = (i == possible_cpus->len);
1049
1050 for (i = 0; i < possible_cpus->len; i++) {
1051 const CPUArchId *cpu_slot = &possible_cpus->cpus[i];
1052
1053 if (!cpu_slot->props.has_node_id) {
1054 /* fetch default mapping from board and enable it */
1055 CpuInstanceProperties props = cpu_slot->props;
1056
1057 props.node_id = mc->get_default_cpu_node_id(machine, i);
1058 if (!default_mapping) {
1059 /* record slots with not set mapping,
1060 * TODO: make it hard error in future */
1061 char *cpu_str = cpu_slot_to_string(cpu_slot);
1062 g_string_append_printf(s, "%sCPU %d [%s]",
1063 s->len ? ", " : "", i, cpu_str);
1064 g_free(cpu_str);
1065
1066 /* non mapped cpus used to fallback to node 0 */
1067 props.node_id = 0;
1068 }
1069
1070 props.has_node_id = true;
1071 machine_set_cpu_numa_node(machine, &props, &error_fatal);
1072 }
1073 }
1074
1075 if (machine->numa_state->hmat_enabled) {
1076 numa_validate_initiator(machine->numa_state);
1077 }
1078
1079 if (s->len && !qtest_enabled()) {
1080 warn_report("CPU(s) not present in any NUMA nodes: %s",
1081 s->str);
1082 warn_report("All CPU(s) up to maxcpus should be described "
1083 "in NUMA config, ability to start up with partial NUMA "
1084 "mappings is obsoleted and will be removed in future");
1085 }
1086 g_string_free(s, true);
1087 }
1088
1089 MemoryRegion *machine_consume_memdev(MachineState *machine,
1090 HostMemoryBackend *backend)
1091 {
1092 MemoryRegion *ret = host_memory_backend_get_memory(backend);
1093
1094 if (host_memory_backend_is_mapped(backend)) {
1095 error_report("memory backend %s can't be used multiple times.",
1096 object_get_canonical_path_component(OBJECT(backend)));
1097 exit(EXIT_FAILURE);
1098 }
1099 host_memory_backend_set_mapped(backend, true);
1100 vmstate_register_ram_global(ret);
1101 return ret;
1102 }
1103
1104 void machine_run_board_init(MachineState *machine)
1105 {
1106 MachineClass *machine_class = MACHINE_GET_CLASS(machine);
1107 ObjectClass *oc = object_class_by_name(machine->cpu_type);
1108 CPUClass *cc;
1109
1110 /* This checkpoint is required by replay to separate prior clock
1111 reading from the other reads, because timer polling functions query
1112 clock values from the log. */
1113 replay_checkpoint(CHECKPOINT_INIT);
1114
1115 if (machine->ram_memdev_id) {
1116 Object *o;
1117 o = object_resolve_path_type(machine->ram_memdev_id,
1118 TYPE_MEMORY_BACKEND, NULL);
1119 machine->ram = machine_consume_memdev(machine, MEMORY_BACKEND(o));
1120 }
1121
1122 if (machine->numa_state) {
1123 numa_complete_configuration(machine);
1124 if (machine->numa_state->num_nodes) {
1125 machine_numa_finish_cpu_init(machine);
1126 }
1127 }
1128
1129 /* If the machine supports the valid_cpu_types check and the user
1130 * specified a CPU with -cpu check here that the user CPU is supported.
1131 */
1132 if (machine_class->valid_cpu_types && machine->cpu_type) {
1133 int i;
1134
1135 for (i = 0; machine_class->valid_cpu_types[i]; i++) {
1136 if (object_class_dynamic_cast(oc,
1137 machine_class->valid_cpu_types[i])) {
1138 /* The user specificed CPU is in the valid field, we are
1139 * good to go.
1140 */
1141 break;
1142 }
1143 }
1144
1145 if (!machine_class->valid_cpu_types[i]) {
1146 /* The user specified CPU is not valid */
1147 error_report("Invalid CPU type: %s", machine->cpu_type);
1148 error_printf("The valid types are: %s",
1149 machine_class->valid_cpu_types[0]);
1150 for (i = 1; machine_class->valid_cpu_types[i]; i++) {
1151 error_printf(", %s", machine_class->valid_cpu_types[i]);
1152 }
1153 error_printf("\n");
1154
1155 exit(1);
1156 }
1157 }
1158
1159 /* Check if CPU type is deprecated and warn if so */
1160 cc = CPU_CLASS(oc);
1161 if (cc && cc->deprecation_note) {
1162 warn_report("CPU model %s is deprecated -- %s", machine->cpu_type,
1163 cc->deprecation_note);
1164 }
1165
1166 if (machine->cgs) {
1167 /*
1168 * With confidential guests, the host can't see the real
1169 * contents of RAM, so there's no point in it trying to merge
1170 * areas.
1171 */
1172 machine_set_mem_merge(OBJECT(machine), false, &error_abort);
1173
1174 /*
1175 * Virtio devices can't count on directly accessing guest
1176 * memory, so they need iommu_platform=on to use normal DMA
1177 * mechanisms. That requires also disabling legacy virtio
1178 * support for those virtio pci devices which allow it.
1179 */
1180 object_register_sugar_prop(TYPE_VIRTIO_PCI, "disable-legacy",
1181 "on", true);
1182 object_register_sugar_prop(TYPE_VIRTIO_DEVICE, "iommu_platform",
1183 "on", false);
1184 }
1185
1186 accel_init_interfaces(ACCEL_GET_CLASS(machine->accelerator));
1187 machine_class->init(machine);
1188 phase_advance(PHASE_MACHINE_INITIALIZED);
1189 }
1190
1191 static NotifierList machine_init_done_notifiers =
1192 NOTIFIER_LIST_INITIALIZER(machine_init_done_notifiers);
1193
1194 void qemu_add_machine_init_done_notifier(Notifier *notify)
1195 {
1196 notifier_list_add(&machine_init_done_notifiers, notify);
1197 if (phase_check(PHASE_MACHINE_READY)) {
1198 notify->notify(notify, NULL);
1199 }
1200 }
1201
1202 void qemu_remove_machine_init_done_notifier(Notifier *notify)
1203 {
1204 notifier_remove(notify);
1205 }
1206
1207 void qdev_machine_creation_done(void)
1208 {
1209 cpu_synchronize_all_post_init();
1210
1211 if (current_machine->boot_once) {
1212 qemu_boot_set(current_machine->boot_once, &error_fatal);
1213 qemu_register_reset(restore_boot_order, g_strdup(current_machine->boot_order));
1214 }
1215
1216 /*
1217 * ok, initial machine setup is done, starting from now we can
1218 * only create hotpluggable devices
1219 */
1220 phase_advance(PHASE_MACHINE_READY);
1221 qdev_assert_realized_properly();
1222
1223 /* TODO: once all bus devices are qdevified, this should be done
1224 * when bus is created by qdev.c */
1225 /*
1226 * TODO: If we had a main 'reset container' that the whole system
1227 * lived in, we could reset that using the multi-phase reset
1228 * APIs. For the moment, we just reset the sysbus, which will cause
1229 * all devices hanging off it (and all their child buses, recursively)
1230 * to be reset. Note that this will *not* reset any Device objects
1231 * which are not attached to some part of the qbus tree!
1232 */
1233 qemu_register_reset(resettable_cold_reset_fn, sysbus_get_default());
1234
1235 notifier_list_notify(&machine_init_done_notifiers, NULL);
1236
1237 if (rom_check_and_register_reset() != 0) {
1238 exit(1);
1239 }
1240
1241 replay_start();
1242
1243 /* This checkpoint is required by replay to separate prior clock
1244 reading from the other reads, because timer polling functions query
1245 clock values from the log. */
1246 replay_checkpoint(CHECKPOINT_RESET);
1247 qemu_system_reset(SHUTDOWN_CAUSE_NONE);
1248 register_global_state();
1249 }
1250
1251 static const TypeInfo machine_info = {
1252 .name = TYPE_MACHINE,
1253 .parent = TYPE_OBJECT,
1254 .abstract = true,
1255 .class_size = sizeof(MachineClass),
1256 .class_init = machine_class_init,
1257 .class_base_init = machine_class_base_init,
1258 .instance_size = sizeof(MachineState),
1259 .instance_init = machine_initfn,
1260 .instance_finalize = machine_finalize,
1261 };
1262
1263 static void machine_register_types(void)
1264 {
1265 type_register_static(&machine_info);
1266 }
1267
1268 type_init(machine_register_types)