hw/cris: Use the IEC binary prefix definitions
[qemu.git] / hw / cris / axis_dev88.c
1 /*
2 * QEMU model for the AXIS devboard 88.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qapi/error.h"
28 #include "qemu-common.h"
29 #include "cpu.h"
30 #include "hw/sysbus.h"
31 #include "net/net.h"
32 #include "hw/block/flash.h"
33 #include "hw/boards.h"
34 #include "hw/cris/etraxfs.h"
35 #include "hw/loader.h"
36 #include "elf.h"
37 #include "boot.h"
38 #include "exec/address-spaces.h"
39 #include "sysemu/qtest.h"
40 #include "sysemu/sysemu.h"
41
42 #define D(x)
43 #define DNAND(x)
44
45 struct nand_state_t
46 {
47 DeviceState *nand;
48 MemoryRegion iomem;
49 unsigned int rdy:1;
50 unsigned int ale:1;
51 unsigned int cle:1;
52 unsigned int ce:1;
53 };
54
55 static struct nand_state_t nand_state;
56 static uint64_t nand_read(void *opaque, hwaddr addr, unsigned size)
57 {
58 struct nand_state_t *s = opaque;
59 uint32_t r;
60 int rdy;
61
62 r = nand_getio(s->nand);
63 nand_getpins(s->nand, &rdy);
64 s->rdy = rdy;
65
66 DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r));
67 return r;
68 }
69
70 static void
71 nand_write(void *opaque, hwaddr addr, uint64_t value,
72 unsigned size)
73 {
74 struct nand_state_t *s = opaque;
75 int rdy;
76
77 DNAND(printf("%s addr=%x v=%x\n", __func__, addr, (unsigned)value));
78 nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
79 nand_setio(s->nand, value);
80 nand_getpins(s->nand, &rdy);
81 s->rdy = rdy;
82 }
83
84 static const MemoryRegionOps nand_ops = {
85 .read = nand_read,
86 .write = nand_write,
87 .endianness = DEVICE_NATIVE_ENDIAN,
88 };
89
90 struct tempsensor_t
91 {
92 unsigned int shiftreg;
93 unsigned int count;
94 enum {
95 ST_OUT, ST_IN, ST_Z
96 } state;
97
98 uint16_t regs[3];
99 };
100
101 static void tempsensor_clkedge(struct tempsensor_t *s,
102 unsigned int clk, unsigned int data_in)
103 {
104 D(printf("%s clk=%d state=%d sr=%x\n", __func__,
105 clk, s->state, s->shiftreg));
106 if (s->count == 0) {
107 s->count = 16;
108 s->state = ST_OUT;
109 }
110 switch (s->state) {
111 case ST_OUT:
112 /* Output reg is clocked at negedge. */
113 if (!clk) {
114 s->count--;
115 s->shiftreg <<= 1;
116 if (s->count == 0) {
117 s->shiftreg = 0;
118 s->state = ST_IN;
119 s->count = 16;
120 }
121 }
122 break;
123 case ST_Z:
124 if (clk) {
125 s->count--;
126 if (s->count == 0) {
127 s->shiftreg = 0;
128 s->state = ST_OUT;
129 s->count = 16;
130 }
131 }
132 break;
133 case ST_IN:
134 /* Indata is sampled at posedge. */
135 if (clk) {
136 s->count--;
137 s->shiftreg <<= 1;
138 s->shiftreg |= data_in & 1;
139 if (s->count == 0) {
140 D(printf("%s cfgreg=%x\n", __func__, s->shiftreg));
141 s->regs[0] = s->shiftreg;
142 s->state = ST_OUT;
143 s->count = 16;
144
145 if ((s->regs[0] & 0xff) == 0) {
146 /* 25 degrees celsius. */
147 s->shiftreg = 0x0b9f;
148 } else if ((s->regs[0] & 0xff) == 0xff) {
149 /* Sensor ID, 0x8100 LM70. */
150 s->shiftreg = 0x8100;
151 } else
152 printf("Invalid tempsens state %x\n", s->regs[0]);
153 }
154 }
155 break;
156 }
157 }
158
159
160 #define RW_PA_DOUT 0x00
161 #define R_PA_DIN 0x01
162 #define RW_PA_OE 0x02
163 #define RW_PD_DOUT 0x10
164 #define R_PD_DIN 0x11
165 #define RW_PD_OE 0x12
166
167 static struct gpio_state_t
168 {
169 MemoryRegion iomem;
170 struct nand_state_t *nand;
171 struct tempsensor_t tempsensor;
172 uint32_t regs[0x5c / 4];
173 } gpio_state;
174
175 static uint64_t gpio_read(void *opaque, hwaddr addr, unsigned size)
176 {
177 struct gpio_state_t *s = opaque;
178 uint32_t r = 0;
179
180 addr >>= 2;
181 switch (addr)
182 {
183 case R_PA_DIN:
184 r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE];
185
186 /* Encode pins from the nand. */
187 r |= s->nand->rdy << 7;
188 break;
189 case R_PD_DIN:
190 r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE];
191
192 /* Encode temp sensor pins. */
193 r |= (!!(s->tempsensor.shiftreg & 0x10000)) << 4;
194 break;
195
196 default:
197 r = s->regs[addr];
198 break;
199 }
200 return r;
201 D(printf("%s %x=%x\n", __func__, addr, r));
202 }
203
204 static void gpio_write(void *opaque, hwaddr addr, uint64_t value,
205 unsigned size)
206 {
207 struct gpio_state_t *s = opaque;
208 D(printf("%s %x=%x\n", __func__, addr, (unsigned)value));
209
210 addr >>= 2;
211 switch (addr)
212 {
213 case RW_PA_DOUT:
214 /* Decode nand pins. */
215 s->nand->ale = !!(value & (1 << 6));
216 s->nand->cle = !!(value & (1 << 5));
217 s->nand->ce = !!(value & (1 << 4));
218
219 s->regs[addr] = value;
220 break;
221
222 case RW_PD_DOUT:
223 /* Temp sensor clk. */
224 if ((s->regs[addr] ^ value) & 2)
225 tempsensor_clkedge(&s->tempsensor, !!(value & 2),
226 !!(value & 16));
227 s->regs[addr] = value;
228 break;
229
230 default:
231 s->regs[addr] = value;
232 break;
233 }
234 }
235
236 static const MemoryRegionOps gpio_ops = {
237 .read = gpio_read,
238 .write = gpio_write,
239 .endianness = DEVICE_NATIVE_ENDIAN,
240 .valid = {
241 .min_access_size = 4,
242 .max_access_size = 4,
243 },
244 };
245
246 #define INTMEM_SIZE (128 * KiB)
247
248 static struct cris_load_info li;
249
250 static
251 void axisdev88_init(MachineState *machine)
252 {
253 ram_addr_t ram_size = machine->ram_size;
254 const char *kernel_filename = machine->kernel_filename;
255 const char *kernel_cmdline = machine->kernel_cmdline;
256 CRISCPU *cpu;
257 CPUCRISState *env;
258 DeviceState *dev;
259 SysBusDevice *s;
260 DriveInfo *nand;
261 qemu_irq irq[30], nmi[2];
262 void *etraxfs_dmac;
263 struct etraxfs_dma_client *dma_eth;
264 int i;
265 MemoryRegion *address_space_mem = get_system_memory();
266 MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
267 MemoryRegion *phys_intmem = g_new(MemoryRegion, 1);
268
269 /* init CPUs */
270 cpu = CRIS_CPU(cpu_create(machine->cpu_type));
271 env = &cpu->env;
272
273 /* allocate RAM */
274 memory_region_allocate_system_memory(phys_ram, NULL, "axisdev88.ram",
275 ram_size);
276 memory_region_add_subregion(address_space_mem, 0x40000000, phys_ram);
277
278 /* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
279 internal memory. */
280 memory_region_init_ram(phys_intmem, NULL, "axisdev88.chipram",
281 INTMEM_SIZE, &error_fatal);
282 memory_region_add_subregion(address_space_mem, 0x38000000, phys_intmem);
283
284 /* Attach a NAND flash to CS1. */
285 nand = drive_get(IF_MTD, 0, 0);
286 nand_state.nand = nand_init(nand ? blk_by_legacy_dinfo(nand) : NULL,
287 NAND_MFR_STMICRO, 0x39);
288 memory_region_init_io(&nand_state.iomem, NULL, &nand_ops, &nand_state,
289 "nand", 0x05000000);
290 memory_region_add_subregion(address_space_mem, 0x10000000,
291 &nand_state.iomem);
292
293 gpio_state.nand = &nand_state;
294 memory_region_init_io(&gpio_state.iomem, NULL, &gpio_ops, &gpio_state,
295 "gpio", 0x5c);
296 memory_region_add_subregion(address_space_mem, 0x3001a000,
297 &gpio_state.iomem);
298
299
300 dev = qdev_create(NULL, "etraxfs,pic");
301 /* FIXME: Is there a proper way to signal vectors to the CPU core? */
302 qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
303 qdev_init_nofail(dev);
304 s = SYS_BUS_DEVICE(dev);
305 sysbus_mmio_map(s, 0, 0x3001c000);
306 sysbus_connect_irq(s, 0, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_IRQ));
307 sysbus_connect_irq(s, 1, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_NMI));
308 for (i = 0; i < 30; i++) {
309 irq[i] = qdev_get_gpio_in(dev, i);
310 }
311 nmi[0] = qdev_get_gpio_in(dev, 30);
312 nmi[1] = qdev_get_gpio_in(dev, 31);
313
314 etraxfs_dmac = etraxfs_dmac_init(0x30000000, 10);
315 for (i = 0; i < 10; i++) {
316 /* On ETRAX, odd numbered channels are inputs. */
317 etraxfs_dmac_connect(etraxfs_dmac, i, irq + 7 + i, i & 1);
318 }
319
320 /* Add the two ethernet blocks. */
321 dma_eth = g_malloc0(sizeof dma_eth[0] * 4); /* Allocate 4 channels. */
322 etraxfs_eth_init(&nd_table[0], 0x30034000, 1, &dma_eth[0], &dma_eth[1]);
323 if (nb_nics > 1) {
324 etraxfs_eth_init(&nd_table[1], 0x30036000, 2, &dma_eth[2], &dma_eth[3]);
325 }
326
327 /* The DMA Connector block is missing, hardwire things for now. */
328 etraxfs_dmac_connect_client(etraxfs_dmac, 0, &dma_eth[0]);
329 etraxfs_dmac_connect_client(etraxfs_dmac, 1, &dma_eth[1]);
330 if (nb_nics > 1) {
331 etraxfs_dmac_connect_client(etraxfs_dmac, 6, &dma_eth[2]);
332 etraxfs_dmac_connect_client(etraxfs_dmac, 7, &dma_eth[3]);
333 }
334
335 /* 2 timers. */
336 sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq[0x1b], nmi[1], NULL);
337 sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL);
338
339 for (i = 0; i < 4; i++) {
340 etraxfs_ser_create(0x30026000 + i * 0x2000, irq[0x14 + i], serial_hd(i));
341 }
342
343 if (kernel_filename) {
344 li.image_filename = kernel_filename;
345 li.cmdline = kernel_cmdline;
346 cris_load_image(cpu, &li);
347 } else if (!qtest_enabled()) {
348 fprintf(stderr, "Kernel image must be specified\n");
349 exit(1);
350 }
351 }
352
353 static void axisdev88_machine_init(MachineClass *mc)
354 {
355 mc->desc = "AXIS devboard 88";
356 mc->init = axisdev88_init;
357 mc->is_default = 1;
358 mc->default_cpu_type = CRIS_CPU_TYPE_NAME("crisv32");
359 }
360
361 DEFINE_MACHINE("axis-dev88", axisdev88_machine_init)