linux-user: stack_base is now mandatory on all targets
[qemu.git] / hw / cs4231.c
1 /*
2 * QEMU Crystal CS4231 audio chip emulation
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "sysbus.h"
26 #include "trace.h"
27
28 /*
29 * In addition to Crystal CS4231 there is a DMA controller on Sparc.
30 */
31 #define CS_SIZE 0x40
32 #define CS_REGS 16
33 #define CS_DREGS 32
34 #define CS_MAXDREG (CS_DREGS - 1)
35
36 typedef struct CSState {
37 SysBusDevice busdev;
38 MemoryRegion iomem;
39 qemu_irq irq;
40 uint32_t regs[CS_REGS];
41 uint8_t dregs[CS_DREGS];
42 } CSState;
43
44 #define CS_RAP(s) ((s)->regs[0] & CS_MAXDREG)
45 #define CS_VER 0xa0
46 #define CS_CDC_VER 0x8a
47
48 static void cs_reset(DeviceState *d)
49 {
50 CSState *s = container_of(d, CSState, busdev.qdev);
51
52 memset(s->regs, 0, CS_REGS * 4);
53 memset(s->dregs, 0, CS_DREGS);
54 s->dregs[12] = CS_CDC_VER;
55 s->dregs[25] = CS_VER;
56 }
57
58 static uint64_t cs_mem_read(void *opaque, target_phys_addr_t addr,
59 unsigned size)
60 {
61 CSState *s = opaque;
62 uint32_t saddr, ret;
63
64 saddr = addr >> 2;
65 switch (saddr) {
66 case 1:
67 switch (CS_RAP(s)) {
68 case 3: // Write only
69 ret = 0;
70 break;
71 default:
72 ret = s->dregs[CS_RAP(s)];
73 break;
74 }
75 trace_cs4231_mem_readl_dreg(CS_RAP(s), ret);
76 break;
77 default:
78 ret = s->regs[saddr];
79 trace_cs4231_mem_readl_reg(saddr, ret);
80 break;
81 }
82 return ret;
83 }
84
85 static void cs_mem_write(void *opaque, target_phys_addr_t addr,
86 uint64_t val, unsigned size)
87 {
88 CSState *s = opaque;
89 uint32_t saddr;
90
91 saddr = addr >> 2;
92 trace_cs4231_mem_writel_reg(saddr, s->regs[saddr], val);
93 switch (saddr) {
94 case 1:
95 trace_cs4231_mem_writel_dreg(CS_RAP(s), s->dregs[CS_RAP(s)], val);
96 switch(CS_RAP(s)) {
97 case 11:
98 case 25: // Read only
99 break;
100 case 12:
101 val &= 0x40;
102 val |= CS_CDC_VER; // Codec version
103 s->dregs[CS_RAP(s)] = val;
104 break;
105 default:
106 s->dregs[CS_RAP(s)] = val;
107 break;
108 }
109 break;
110 case 2: // Read only
111 break;
112 case 4:
113 if (val & 1) {
114 cs_reset(&s->busdev.qdev);
115 }
116 val &= 0x7f;
117 s->regs[saddr] = val;
118 break;
119 default:
120 s->regs[saddr] = val;
121 break;
122 }
123 }
124
125 static const MemoryRegionOps cs_mem_ops = {
126 .read = cs_mem_read,
127 .write = cs_mem_write,
128 .endianness = DEVICE_NATIVE_ENDIAN,
129 };
130
131 static const VMStateDescription vmstate_cs4231 = {
132 .name ="cs4231",
133 .version_id = 1,
134 .minimum_version_id = 1,
135 .minimum_version_id_old = 1,
136 .fields = (VMStateField []) {
137 VMSTATE_UINT32_ARRAY(regs, CSState, CS_REGS),
138 VMSTATE_UINT8_ARRAY(dregs, CSState, CS_DREGS),
139 VMSTATE_END_OF_LIST()
140 }
141 };
142
143 static int cs4231_init1(SysBusDevice *dev)
144 {
145 CSState *s = FROM_SYSBUS(CSState, dev);
146
147 memory_region_init_io(&s->iomem, &cs_mem_ops, s, "cs4321", CS_SIZE);
148 sysbus_init_mmio(dev, &s->iomem);
149 sysbus_init_irq(dev, &s->irq);
150
151 return 0;
152 }
153
154 static Property cs4231_properties[] = {
155 {.name = NULL},
156 };
157
158 static void cs4231_class_init(ObjectClass *klass, void *data)
159 {
160 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
161
162 k->init = cs4231_init1;
163 }
164
165 static DeviceInfo cs4231_info = {
166 .name = "SUNW,CS4231",
167 .size = sizeof(CSState),
168 .vmsd = &vmstate_cs4231,
169 .reset = cs_reset,
170 .props = cs4231_properties,
171 .class_init = cs4231_class_init,
172 };
173
174 static void cs4231_register_devices(void)
175 {
176 sysbus_register_withprop(&cs4231_info);
177 }
178
179 device_init(cs4231_register_devices)