hw/arm/bcm2836: Only provide "enabled-cpus" property to multicore SoCs
[qemu.git] / hw / display / ati_2d.c
1 /*
2 * QEMU ATI SVGA emulation
3 * 2D engine functions
4 *
5 * Copyright (c) 2019 BALATON Zoltan
6 *
7 * This work is licensed under the GNU GPL license version 2 or later.
8 */
9
10 #include "qemu/osdep.h"
11 #include "ati_int.h"
12 #include "ati_regs.h"
13 #include "qemu/log.h"
14 #include "ui/pixel_ops.h"
15
16 /*
17 * NOTE:
18 * This is 2D _acceleration_ and supposed to be fast. Therefore, don't try to
19 * reinvent the wheel (unlikely to get better with a naive implementation than
20 * existing libraries) and avoid (poorly) reimplementing gfx primitives.
21 * That is unnecessary and would become a performance problem. Instead, try to
22 * map to and reuse existing optimised facilities (e.g. pixman) wherever
23 * possible.
24 */
25
26 static int ati_bpp_from_datatype(ATIVGAState *s)
27 {
28 switch (s->regs.dp_datatype & 0xf) {
29 case 2:
30 return 8;
31 case 3:
32 case 4:
33 return 16;
34 case 5:
35 return 24;
36 case 6:
37 return 32;
38 default:
39 qemu_log_mask(LOG_UNIMP, "Unknown dst datatype %d\n",
40 s->regs.dp_datatype & 0xf);
41 return 0;
42 }
43 }
44
45 #define DEFAULT_CNTL (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL)
46
47 void ati_2d_blt(ATIVGAState *s)
48 {
49 /* FIXME it is probably more complex than this and may need to be */
50 /* rewritten but for now as a start just to get some output: */
51 DisplaySurface *ds = qemu_console_surface(s->vga.con);
52 DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr,
53 s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds),
54 surface_bits_per_pixel(ds),
55 (s->regs.dp_mix & GMC_ROP3_MASK) >> 16);
56 unsigned dst_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ?
57 s->regs.dst_x : s->regs.dst_x + 1 - s->regs.dst_width);
58 unsigned dst_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?
59 s->regs.dst_y : s->regs.dst_y + 1 - s->regs.dst_height);
60 int bpp = ati_bpp_from_datatype(s);
61 if (!bpp) {
62 qemu_log_mask(LOG_GUEST_ERROR, "Invalid bpp\n");
63 return;
64 }
65 int dst_stride = DEFAULT_CNTL ? s->regs.dst_pitch : s->regs.default_pitch;
66 if (!dst_stride) {
67 qemu_log_mask(LOG_GUEST_ERROR, "Zero dest pitch\n");
68 return;
69 }
70 uint8_t *dst_bits = s->vga.vram_ptr + (DEFAULT_CNTL ?
71 s->regs.dst_offset : s->regs.default_offset);
72
73 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
74 dst_bits += s->regs.crtc_offset & 0x07ffffff;
75 dst_stride *= bpp;
76 }
77 uint8_t *end = s->vga.vram_ptr + s->vga.vram_size;
78 if (dst_bits >= end || dst_bits + dst_x + (dst_y + s->regs.dst_height) *
79 dst_stride >= end) {
80 qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n");
81 return;
82 }
83 DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d %c %c\n",
84 s->regs.src_offset, s->regs.dst_offset, s->regs.default_offset,
85 s->regs.src_pitch, s->regs.dst_pitch, s->regs.default_pitch,
86 s->regs.src_x, s->regs.src_y, s->regs.dst_x, s->regs.dst_y,
87 s->regs.dst_width, s->regs.dst_height,
88 (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? '>' : '<'),
89 (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? 'v' : '^'));
90 switch (s->regs.dp_mix & GMC_ROP3_MASK) {
91 case ROP3_SRCCOPY:
92 {
93 unsigned src_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ?
94 s->regs.src_x : s->regs.src_x + 1 - s->regs.dst_width);
95 unsigned src_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?
96 s->regs.src_y : s->regs.src_y + 1 - s->regs.dst_height);
97 int src_stride = DEFAULT_CNTL ?
98 s->regs.src_pitch : s->regs.default_pitch;
99 if (!src_stride) {
100 qemu_log_mask(LOG_GUEST_ERROR, "Zero source pitch\n");
101 return;
102 }
103 uint8_t *src_bits = s->vga.vram_ptr + (DEFAULT_CNTL ?
104 s->regs.src_offset : s->regs.default_offset);
105
106 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
107 src_bits += s->regs.crtc_offset & 0x07ffffff;
108 src_stride *= bpp;
109 }
110 if (src_bits >= end || src_bits + src_x +
111 (src_y + s->regs.dst_height) * src_stride >= end) {
112 qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n");
113 return;
114 }
115
116 src_stride /= sizeof(uint32_t);
117 dst_stride /= sizeof(uint32_t);
118 DPRINTF("pixman_blt(%p, %p, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d)\n",
119 src_bits, dst_bits, src_stride, dst_stride, bpp, bpp,
120 src_x, src_y, dst_x, dst_y,
121 s->regs.dst_width, s->regs.dst_height);
122 if (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT &&
123 s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM) {
124 pixman_blt((uint32_t *)src_bits, (uint32_t *)dst_bits,
125 src_stride, dst_stride, bpp, bpp,
126 src_x, src_y, dst_x, dst_y,
127 s->regs.dst_width, s->regs.dst_height);
128 } else {
129 /* FIXME: We only really need a temporary if src and dst overlap */
130 int llb = s->regs.dst_width * (bpp / 8);
131 int tmp_stride = DIV_ROUND_UP(llb, sizeof(uint32_t));
132 uint32_t *tmp = g_malloc(tmp_stride * sizeof(uint32_t) *
133 s->regs.dst_height);
134 pixman_blt((uint32_t *)src_bits, tmp,
135 src_stride, tmp_stride, bpp, bpp,
136 src_x, src_y, 0, 0,
137 s->regs.dst_width, s->regs.dst_height);
138 pixman_blt(tmp, (uint32_t *)dst_bits,
139 tmp_stride, dst_stride, bpp, bpp,
140 0, 0, dst_x, dst_y,
141 s->regs.dst_width, s->regs.dst_height);
142 g_free(tmp);
143 }
144 if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr &&
145 dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr +
146 s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) {
147 memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr +
148 s->regs.dst_offset +
149 dst_y * surface_stride(ds),
150 s->regs.dst_height * surface_stride(ds));
151 }
152 s->regs.dst_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ?
153 dst_x + s->regs.dst_width : dst_x);
154 s->regs.dst_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?
155 dst_y + s->regs.dst_height : dst_y);
156 break;
157 }
158 case ROP3_PATCOPY:
159 case ROP3_BLACKNESS:
160 case ROP3_WHITENESS:
161 {
162 uint32_t filler = 0;
163
164 switch (s->regs.dp_mix & GMC_ROP3_MASK) {
165 case ROP3_PATCOPY:
166 filler = s->regs.dp_brush_frgd_clr;
167 break;
168 case ROP3_BLACKNESS:
169 filler = 0xffUL << 24 | rgb_to_pixel32(s->vga.palette[0],
170 s->vga.palette[1], s->vga.palette[2]);
171 break;
172 case ROP3_WHITENESS:
173 filler = 0xffUL << 24 | rgb_to_pixel32(s->vga.palette[3],
174 s->vga.palette[4], s->vga.palette[5]);
175 break;
176 }
177
178 dst_stride /= sizeof(uint32_t);
179 DPRINTF("pixman_fill(%p, %d, %d, %d, %d, %d, %d, %x)\n",
180 dst_bits, dst_stride, bpp,
181 s->regs.dst_x, s->regs.dst_y,
182 s->regs.dst_width, s->regs.dst_height,
183 filler);
184 pixman_fill((uint32_t *)dst_bits, dst_stride, bpp,
185 s->regs.dst_x, s->regs.dst_y,
186 s->regs.dst_width, s->regs.dst_height,
187 filler);
188 if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr &&
189 dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr +
190 s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) {
191 memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr +
192 s->regs.dst_offset +
193 dst_y * surface_stride(ds),
194 s->regs.dst_height * surface_stride(ds));
195 }
196 s->regs.dst_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?
197 dst_y + s->regs.dst_height : dst_y);
198 break;
199 }
200 default:
201 qemu_log_mask(LOG_UNIMP, "Unimplemented ati_2d blt op %x\n",
202 (s->regs.dp_mix & GMC_ROP3_MASK) >> 16);
203 }
204 }