Merge remote-tracking branch 'remotes/elmarco/tags/slirp-pull-request' into staging
[qemu.git] / hw / display / ati_regs.h
1 /*
2 * ATI VGA register definitions
3 *
4 * based on:
5 * linux/include/video/aty128.h
6 * Register definitions for ATI Rage128 boards
7 * Anthony Tong <atong@uiuc.edu>, 1999
8 * Brad Douglas <brad@neruo.com>, 2000
9 *
10 * and linux/include/video/radeon.h
11 *
12 * This work is licensed under the GNU GPL license version 2.
13 */
14
15 /*
16 * Register mapping:
17 * 0x0000-0x00ff Misc regs also accessible via io and mmio space
18 * 0x0100-0x0eff Misc regs only accessible via mmio
19 * 0x0f00-0x0fff Read-only copy of PCI config regs
20 * 0x1000-0x13ff Concurrent Command Engine (CCE) regs
21 * 0x1400-0x1fff GUI (drawing engine) regs
22 */
23
24 #ifndef ATI_REGS_H
25 #define ATI_REGS_H
26
27 #undef DEFAULT_PITCH /* needed for mingw builds */
28
29 #define MM_INDEX 0x0000
30 #define MM_DATA 0x0004
31 #define CLOCK_CNTL_INDEX 0x0008
32 #define CLOCK_CNTL_DATA 0x000c
33 #define BIOS_0_SCRATCH 0x0010
34 #define BUS_CNTL 0x0030
35 #define BUS_CNTL1 0x0034
36 #define GEN_INT_CNTL 0x0040
37 #define GEN_INT_STATUS 0x0044
38 #define CRTC_GEN_CNTL 0x0050
39 #define CRTC_EXT_CNTL 0x0054
40 #define DAC_CNTL 0x0058
41 #define GPIO_VGA_DDC 0x0060
42 #define GPIO_DVI_DDC 0x0064
43 #define GPIO_MONID 0x0068
44 #define I2C_CNTL_1 0x0094
45 #define AMCGPIO_MASK_MIR 0x009c
46 #define AMCGPIO_A_MIR 0x00a0
47 #define AMCGPIO_Y_MIR 0x00a4
48 #define AMCGPIO_EN_MIR 0x00a8
49 #define PALETTE_INDEX 0x00b0
50 #define PALETTE_DATA 0x00b4
51 #define CNFG_CNTL 0x00e0
52 #define GEN_RESET_CNTL 0x00f0
53 #define CNFG_MEMSIZE 0x00f8
54 #define CONFIG_APER_0_BASE 0x0100
55 #define CONFIG_APER_1_BASE 0x0104
56 #define CONFIG_APER_SIZE 0x0108
57 #define CONFIG_REG_1_BASE 0x010c
58 #define CONFIG_REG_APER_SIZE 0x0110
59 #define MEM_CNTL 0x0140
60 #define MC_FB_LOCATION 0x0148
61 #define MC_AGP_LOCATION 0x014C
62 #define MC_STATUS 0x0150
63 #define MEM_POWER_MISC 0x015c
64 #define AGP_BASE 0x0170
65 #define AGP_CNTL 0x0174
66 #define AGP_APER_OFFSET 0x0178
67 #define PCI_GART_PAGE 0x017c
68 #define PC_NGUI_MODE 0x0180
69 #define PC_NGUI_CTLSTAT 0x0184
70 #define MPP_TB_CONFIG 0x01C0
71 #define MPP_GP_CONFIG 0x01C8
72 #define VIPH_CONTROL 0x01D0
73 #define CRTC_H_TOTAL_DISP 0x0200
74 #define CRTC_H_SYNC_STRT_WID 0x0204
75 #define CRTC_V_TOTAL_DISP 0x0208
76 #define CRTC_V_SYNC_STRT_WID 0x020c
77 #define CRTC_VLINE_CRNT_VLINE 0x0210
78 #define CRTC_CRNT_FRAME 0x0214
79 #define CRTC_GUI_TRIG_VLINE 0x0218
80 #define CRTC_OFFSET 0x0224
81 #define CRTC_OFFSET_CNTL 0x0228
82 #define CRTC_PITCH 0x022c
83 #define OVR_CLR 0x0230
84 #define OVR_WID_LEFT_RIGHT 0x0234
85 #define OVR_WID_TOP_BOTTOM 0x0238
86 #define CUR_OFFSET 0x0260
87 #define CUR_HORZ_VERT_POSN 0x0264
88 #define CUR_HORZ_VERT_OFF 0x0268
89 #define CUR_CLR0 0x026c
90 #define CUR_CLR1 0x0270
91 #define LVDS_GEN_CNTL 0x02d0
92 #define DDA_CONFIG 0x02e0
93 #define DDA_ON_OFF 0x02e4
94 #define VGA_DDA_CONFIG 0x02e8
95 #define VGA_DDA_ON_OFF 0x02ec
96 #define CRTC2_H_TOTAL_DISP 0x0300
97 #define CRTC2_H_SYNC_STRT_WID 0x0304
98 #define CRTC2_V_TOTAL_DISP 0x0308
99 #define CRTC2_V_SYNC_STRT_WID 0x030c
100 #define CRTC2_VLINE_CRNT_VLINE 0x0310
101 #define CRTC2_CRNT_FRAME 0x0314
102 #define CRTC2_GUI_TRIG_VLINE 0x0318
103 #define CRTC2_OFFSET 0x0324
104 #define CRTC2_OFFSET_CNTL 0x0328
105 #define CRTC2_PITCH 0x032c
106 #define DDA2_CONFIG 0x03e0
107 #define DDA2_ON_OFF 0x03e4
108 #define CRTC2_GEN_CNTL 0x03f8
109 #define CRTC2_STATUS 0x03fc
110 #define OV0_SCALE_CNTL 0x0420
111 #define SUBPIC_CNTL 0x0540
112 #define PM4_BUFFER_OFFSET 0x0700
113 #define PM4_BUFFER_CNTL 0x0704
114 #define PM4_BUFFER_WM_CNTL 0x0708
115 #define PM4_BUFFER_DL_RPTR_ADDR 0x070c
116 #define PM4_BUFFER_DL_RPTR 0x0710
117 #define PM4_BUFFER_DL_WPTR 0x0714
118 #define PM4_VC_FPU_SETUP 0x071c
119 #define PM4_FPU_CNTL 0x0720
120 #define PM4_VC_FORMAT 0x0724
121 #define PM4_VC_CNTL 0x0728
122 #define PM4_VC_I01 0x072c
123 #define PM4_VC_VLOFF 0x0730
124 #define PM4_VC_VLSIZE 0x0734
125 #define PM4_IW_INDOFF 0x0738
126 #define PM4_IW_INDSIZE 0x073c
127 #define PM4_FPU_FPX0 0x0740
128 #define PM4_FPU_FPY0 0x0744
129 #define PM4_FPU_FPX1 0x0748
130 #define PM4_FPU_FPY1 0x074c
131 #define PM4_FPU_FPX2 0x0750
132 #define PM4_FPU_FPY2 0x0754
133 #define PM4_FPU_FPY3 0x0758
134 #define PM4_FPU_FPY4 0x075c
135 #define PM4_FPU_FPY5 0x0760
136 #define PM4_FPU_FPY6 0x0764
137 #define PM4_FPU_FPR 0x0768
138 #define PM4_FPU_FPG 0x076c
139 #define PM4_FPU_FPB 0x0770
140 #define PM4_FPU_FPA 0x0774
141 #define PM4_FPU_INTXY0 0x0780
142 #define PM4_FPU_INTXY1 0x0784
143 #define PM4_FPU_INTXY2 0x0788
144 #define PM4_FPU_INTARGB 0x078c
145 #define PM4_FPU_FPTWICEAREA 0x0790
146 #define PM4_FPU_DMAJOR01 0x0794
147 #define PM4_FPU_DMAJOR12 0x0798
148 #define PM4_FPU_DMAJOR02 0x079c
149 #define PM4_FPU_STAT 0x07a0
150 #define PM4_STAT 0x07b8
151 #define PM4_TEST_CNTL 0x07d0
152 #define PM4_MICROCODE_ADDR 0x07d4
153 #define PM4_MICROCODE_RADDR 0x07d8
154 #define PM4_MICROCODE_DATAH 0x07dc
155 #define PM4_MICROCODE_DATAL 0x07e0
156 #define PM4_CMDFIFO_ADDR 0x07e4
157 #define PM4_CMDFIFO_DATAH 0x07e8
158 #define PM4_CMDFIFO_DATAL 0x07ec
159 #define PM4_BUFFER_ADDR 0x07f0
160 #define PM4_BUFFER_DATAH 0x07f4
161 #define PM4_BUFFER_DATAL 0x07f8
162 #define PM4_MICRO_CNTL 0x07fc
163 #define CAP0_TRIG_CNTL 0x0950
164 #define CAP1_TRIG_CNTL 0x09c0
165
166 #define RBBM_STATUS 0x0e40
167
168 /*
169 * GUI Block Memory Mapped Registers
170 * These registers are FIFOed.
171 */
172 #define PM4_FIFO_DATA_EVEN 0x1000
173 #define PM4_FIFO_DATA_ODD 0x1004
174
175 #define DST_OFFSET 0x1404
176 #define DST_PITCH 0x1408
177 #define DST_WIDTH 0x140c
178 #define DST_HEIGHT 0x1410
179 #define SRC_X 0x1414
180 #define SRC_Y 0x1418
181 #define DST_X 0x141c
182 #define DST_Y 0x1420
183 #define SRC_PITCH_OFFSET 0x1428
184 #define DST_PITCH_OFFSET 0x142c
185 #define SRC_Y_X 0x1434
186 #define DST_Y_X 0x1438
187 #define DST_HEIGHT_WIDTH 0x143c
188 #define DP_GUI_MASTER_CNTL 0x146c
189 #define BRUSH_SCALE 0x1470
190 #define BRUSH_Y_X 0x1474
191 #define DP_BRUSH_BKGD_CLR 0x1478
192 #define DP_BRUSH_FRGD_CLR 0x147c
193 #define DST_WIDTH_X 0x1588
194 #define DST_HEIGHT_WIDTH_8 0x158c
195 #define SRC_X_Y 0x1590
196 #define DST_X_Y 0x1594
197 #define DST_WIDTH_HEIGHT 0x1598
198 #define DST_WIDTH_X_INCY 0x159c
199 #define DST_HEIGHT_Y 0x15a0
200 #define DST_X_SUB 0x15a4
201 #define DST_Y_SUB 0x15a8
202 #define SRC_OFFSET 0x15ac
203 #define SRC_PITCH 0x15b0
204 #define DST_HEIGHT_WIDTH_BW 0x15b4
205 #define CLR_CMP_CNTL 0x15c0
206 #define CLR_CMP_CLR_SRC 0x15c4
207 #define CLR_CMP_CLR_DST 0x15c8
208 #define CLR_CMP_MASK 0x15cc
209 #define DP_SRC_FRGD_CLR 0x15d8
210 #define DP_SRC_BKGD_CLR 0x15dc
211 #define DST_BRES_ERR 0x1628
212 #define DST_BRES_INC 0x162c
213 #define DST_BRES_DEC 0x1630
214 #define DST_BRES_LNTH 0x1634
215 #define DST_BRES_LNTH_SUB 0x1638
216 #define SC_LEFT 0x1640
217 #define SC_RIGHT 0x1644
218 #define SC_TOP 0x1648
219 #define SC_BOTTOM 0x164c
220 #define SRC_SC_RIGHT 0x1654
221 #define SRC_SC_BOTTOM 0x165c
222 #define GUI_DEBUG0 0x16a0
223 #define GUI_DEBUG1 0x16a4
224 #define GUI_TIMEOUT 0x16b0
225 #define GUI_TIMEOUT0 0x16b4
226 #define GUI_TIMEOUT1 0x16b8
227 #define GUI_PROBE 0x16bc
228 #define DP_CNTL 0x16c0
229 #define DP_DATATYPE 0x16c4
230 #define DP_MIX 0x16c8
231 #define DP_WRITE_MASK 0x16cc
232 #define DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0
233 #define DEFAULT_OFFSET 0x16e0
234 #define DEFAULT_PITCH 0x16e4
235 #define DEFAULT_SC_BOTTOM_RIGHT 0x16e8
236 #define SC_TOP_LEFT 0x16ec
237 #define SC_BOTTOM_RIGHT 0x16f0
238 #define SRC_SC_BOTTOM_RIGHT 0x16f4
239 #define DST_TILE 0x1700
240 #define WAIT_UNTIL 0x1720
241 #define CACHE_CNTL 0x1724
242 #define GUI_STAT 0x1740
243 #define PC_GUI_MODE 0x1744
244 #define PC_GUI_CTLSTAT 0x1748
245 #define PC_DEBUG_MODE 0x1760
246 #define BRES_DST_ERR_DEC 0x1780
247 #define TRAIL_BRES_T12_ERR_DEC 0x1784
248 #define TRAIL_BRES_T12_INC 0x1788
249 #define DP_T12_CNTL 0x178c
250 #define DST_BRES_T1_LNTH 0x1790
251 #define DST_BRES_T2_LNTH 0x1794
252 #define SCALE_SRC_HEIGHT_WIDTH 0x1994
253 #define SCALE_OFFSET_0 0x1998
254 #define SCALE_PITCH 0x199c
255 #define SCALE_X_INC 0x19a0
256 #define SCALE_Y_INC 0x19a4
257 #define SCALE_HACC 0x19a8
258 #define SCALE_VACC 0x19ac
259 #define SCALE_DST_X_Y 0x19b0
260 #define SCALE_DST_HEIGHT_WIDTH 0x19b4
261 #define SCALE_3D_CNTL 0x1a00
262 #define SCALE_3D_DATATYPE 0x1a20
263 #define SETUP_CNTL 0x1bc4
264 #define SOLID_COLOR 0x1bc8
265 #define WINDOW_XY_OFFSET 0x1bcc
266 #define DRAW_LINE_POINT 0x1bd0
267 #define SETUP_CNTL_PM4 0x1bd4
268 #define DST_PITCH_OFFSET_C 0x1c80
269 #define DP_GUI_MASTER_CNTL_C 0x1c84
270 #define SC_TOP_LEFT_C 0x1c88
271 #define SC_BOTTOM_RIGHT_C 0x1c8c
272
273 #define CLR_CMP_MASK_3D 0x1A28
274 #define MISC_3D_STATE_CNTL_REG 0x1CA0
275 #define MC_SRC1_CNTL 0x19D8
276 #define TEX_CNTL 0x1800
277
278 /* CONSTANTS */
279 #define GUI_ACTIVE 0x80000000
280 #define ENGINE_IDLE 0x0
281
282 #define PLL_WR_EN 0x00000080
283
284 #define CLK_PIN_CNTL 0x01
285 #define PPLL_CNTL 0x02
286 #define PPLL_REF_DIV 0x03
287 #define PPLL_DIV_0 0x04
288 #define PPLL_DIV_1 0x05
289 #define PPLL_DIV_2 0x06
290 #define PPLL_DIV_3 0x07
291 #define VCLK_ECP_CNTL 0x08
292 #define HTOTAL_CNTL 0x09
293 #define X_MPLL_REF_FB_DIV 0x0a
294 #define XPLL_CNTL 0x0b
295 #define XDLL_CNTL 0x0c
296 #define XCLK_CNTL 0x0d
297 #define MPLL_CNTL 0x0e
298 #define MCLK_CNTL 0x0f
299 #define AGP_PLL_CNTL 0x10
300 #define FCP_CNTL 0x12
301 #define PLL_TEST_CNTL 0x13
302 #define P2PLL_CNTL 0x2a
303 #define P2PLL_REF_DIV 0x2b
304 #define P2PLL_DIV_0 0x2b
305 #define POWER_MANAGEMENT 0x2f
306
307 #define PPLL_RESET 0x00000001
308 #define PPLL_ATOMIC_UPDATE_EN 0x00010000
309 #define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000
310 #define PPLL_REF_DIV_MASK 0x000003FF
311 #define PPLL_FB3_DIV_MASK 0x000007FF
312 #define PPLL_POST3_DIV_MASK 0x00070000
313 #define PPLL_ATOMIC_UPDATE_R 0x00008000
314 #define PPLL_ATOMIC_UPDATE_W 0x00008000
315 #define MEM_CFG_TYPE_MASK 0x00000003
316 #define XCLK_SRC_SEL_MASK 0x00000007
317 #define XPLL_FB_DIV_MASK 0x0000FF00
318 #define X_MPLL_REF_DIV_MASK 0x000000FF
319
320 /* GEN_INT_CNTL) */
321 #define CRTC_VBLANK_INT 0x00000001
322 #define CRTC_VLINE_INT 0x00000002
323 #define CRTC_VSYNC_INT 0x00000004
324
325 /* Config control values (CONFIG_CNTL) */
326 #define APER_0_ENDIAN 0x00000003
327 #define APER_1_ENDIAN 0x0000000c
328 #define CFG_VGA_IO_DIS 0x00000400
329
330 /* CRTC control values (CRTC_GEN_CNTL) */
331 #define CRTC_CSYNC_EN 0x00000010
332
333 #define CRTC2_DBL_SCAN_EN 0x00000001
334 #define CRTC2_DISPLAY_DIS 0x00800000
335 #define CRTC2_FIFO_EXTSENSE 0x00200000
336 #define CRTC2_ICON_EN 0x00100000
337 #define CRTC2_CUR_EN 0x00010000
338 #define CRTC2_EXT_DISP_EN 0x01000000
339 #define CRTC2_EN 0x02000000
340 #define CRTC2_DISP_REQ_EN_B 0x04000000
341
342 #define CRTC_PIX_WIDTH_MASK 0x00000700
343 #define CRTC_PIX_WIDTH_4BPP 0x00000100
344 #define CRTC_PIX_WIDTH_8BPP 0x00000200
345 #define CRTC_PIX_WIDTH_15BPP 0x00000300
346 #define CRTC_PIX_WIDTH_16BPP 0x00000400
347 #define CRTC_PIX_WIDTH_24BPP 0x00000500
348 #define CRTC_PIX_WIDTH_32BPP 0x00000600
349
350 /* DAC_CNTL bit constants */
351 #define DAC_8BIT_EN 0x00000100
352 #define DAC_MASK 0xFF000000
353 #define DAC_BLANKING 0x00000004
354 #define DAC_RANGE_CNTL 0x00000003
355 #define DAC_CLK_SEL 0x00000010
356 #define DAC_PALETTE_ACCESS_CNTL 0x00000020
357 #define DAC_PALETTE2_SNOOP_EN 0x00000040
358 #define DAC_PDWN 0x00008000
359
360 /* CRTC_EXT_CNTL */
361 #define CRT_CRTC_DISPLAY_DIS 0x00000400
362 #define CRT_CRTC_ON 0x00008000
363
364 /* GEN_RESET_CNTL bit constants */
365 #define SOFT_RESET_GUI 0x00000001
366 #define SOFT_RESET_VCLK 0x00000100
367 #define SOFT_RESET_PCLK 0x00000200
368 #define SOFT_RESET_ECP 0x00000400
369 #define SOFT_RESET_DISPENG_XCLK 0x00000800
370
371 /* PC_GUI_CTLSTAT bit constants */
372 #define PC_BUSY_INIT 0x10000000
373 #define PC_BUSY_GUI 0x20000000
374 #define PC_BUSY_NGUI 0x40000000
375 #define PC_BUSY 0x80000000
376
377 #define BUS_MASTER_DIS 0x00000040
378 #define PM4_BUFFER_CNTL_NONPM4 0x00000000
379
380 /* DP_DATATYPE bit constants */
381 #define DST_8BPP 0x00000002
382 #define DST_15BPP 0x00000003
383 #define DST_16BPP 0x00000004
384 #define DST_24BPP 0x00000005
385 #define DST_32BPP 0x00000006
386
387 #define BRUSH_SOLIDCOLOR 0x00000d00
388
389 /* DP_GUI_MASTER_CNTL bit constants */
390 #define GMC_SRC_PITCH_OFFSET_CNTL 0x00000001
391 #define GMC_DST_PITCH_OFFSET_CNTL 0x00000002
392 #define GMC_SRC_CLIP_DEFAULT 0x00000000
393 #define GMC_DST_CLIP_DEFAULT 0x00000000
394 #define GMC_BRUSH_SOLIDCOLOR 0x000000d0
395 #define GMC_SRC_DSTCOLOR 0x00003000
396 #define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000
397 #define GMC_DP_SRC_RECT 0x02000000
398 #define GMC_3D_FCN_EN_CLR 0x00000000
399 #define GMC_AUX_CLIP_CLEAR 0x20000000
400 #define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000
401 #define GMC_WRITE_MASK_SET 0x40000000
402 #define GMC_DP_CONVERSION_TEMP_6500 0x00000000
403
404 /* DP_GUI_MASTER_CNTL ROP3 named constants */
405 #define GMC_ROP3_MASK 0x00ff0000
406 #define ROP3_BLACKNESS 0x00000000
407 #define ROP3_SRCCOPY 0x00cc0000
408 #define ROP3_PATCOPY 0x00f00000
409 #define ROP3_WHITENESS 0x00ff0000
410
411 #define SRC_DSTCOLOR 0x00030000
412
413 /* DP_CNTL bit constants */
414 #define DST_X_RIGHT_TO_LEFT 0x00000000
415 #define DST_X_LEFT_TO_RIGHT 0x00000001
416 #define DST_Y_BOTTOM_TO_TOP 0x00000000
417 #define DST_Y_TOP_TO_BOTTOM 0x00000002
418 #define DST_X_MAJOR 0x00000000
419 #define DST_Y_MAJOR 0x00000004
420 #define DST_X_TILE 0x00000008
421 #define DST_Y_TILE 0x00000010
422 #define DST_LAST_PEL 0x00000020
423 #define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000
424 #define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040
425 #define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000
426 #define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080
427 #define DST_BRES_SIGN 0x00000100
428 #define DST_HOST_BIG_ENDIAN_EN 0x00000200
429 #define DST_POLYLINE_NONLAST 0x00008000
430 #define DST_RASTER_STALL 0x00010000
431 #define DST_POLY_EDGE 0x00040000
432
433 /* DP_MIX bit constants */
434 #define DP_SRC_RECT 0x00000200
435 #define DP_SRC_HOST 0x00000300
436 #define DP_SRC_HOST_BYTEALIGN 0x00000400
437
438 /* LVDS_GEN_CNTL constants */
439 #define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00
440 #define LVDS_BL_MOD_LEVEL_SHIFT 8
441 #define LVDS_BL_MOD_EN 0x00010000
442 #define LVDS_DIGION 0x00040000
443 #define LVDS_BLON 0x00080000
444 #define LVDS_ON 0x00000001
445 #define LVDS_DISPLAY_DIS 0x00000002
446 #define LVDS_PANEL_TYPE_2PIX_PER_CLK 0x00000004
447 #define LVDS_PANEL_24BITS_TFT 0x00000008
448 #define LVDS_FRAME_MOD_NO 0x00000000
449 #define LVDS_FRAME_MOD_2_LEVELS 0x00000010
450 #define LVDS_FRAME_MOD_4_LEVELS 0x00000020
451 #define LVDS_RST_FM 0x00000040
452 #define LVDS_EN 0x00000080
453
454 /* CRTC2_GEN_CNTL constants */
455 #define CRTC2_EN 0x02000000
456
457 /* POWER_MANAGEMENT constants */
458 #define PWR_MGT_ON 0x00000001
459 #define PWR_MGT_MODE_MASK 0x00000006
460 #define PWR_MGT_MODE_PIN 0x00000000
461 #define PWR_MGT_MODE_REGISTER 0x00000002
462 #define PWR_MGT_MODE_TIMER 0x00000004
463 #define PWR_MGT_MODE_PCI 0x00000006
464 #define PWR_MGT_AUTO_PWR_UP_EN 0x00000008
465 #define PWR_MGT_ACTIVITY_PIN_ON 0x00000010
466 #define PWR_MGT_STANDBY_POL 0x00000020
467 #define PWR_MGT_SUSPEND_POL 0x00000040
468 #define PWR_MGT_SELF_REFRESH 0x00000080
469 #define PWR_MGT_ACTIVITY_PIN_EN 0x00000100
470 #define PWR_MGT_KEYBD_SNOOP 0x00000200
471 #define PWR_MGT_TRISTATE_MEM_EN 0x00000800
472 #define PWR_MGT_SELW4MS 0x00001000
473 #define PWR_MGT_SLOWDOWN_MCLK 0x00002000
474
475 #define PMI_PMSCR_REG 0x60
476
477 /* used by ATI bug fix for hardware ROM */
478 #define RAGE128_MPP_TB_CONFIG 0x01c0
479
480 #endif /* ATI_REGS_H */