cirrus: handle negative pitch in cirrus_invalidate_region()
[qemu.git] / hw / display / cirrus_vga.c
1 /*
2 * QEMU Cirrus CLGD 54xx VGA Emulator.
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
29 #include "qemu/osdep.h"
30 #include "qapi/error.h"
31 #include "hw/hw.h"
32 #include "hw/pci/pci.h"
33 #include "ui/console.h"
34 #include "ui/pixel_ops.h"
35 #include "vga_int.h"
36 #include "hw/loader.h"
37
38 /*
39 * TODO:
40 * - destination write mask support not complete (bits 5..7)
41 * - optimize linear mappings
42 * - optimize bitblt functions
43 */
44
45 //#define DEBUG_CIRRUS
46 //#define DEBUG_BITBLT
47
48 /***************************************
49 *
50 * definitions
51 *
52 ***************************************/
53
54 // ID
55 #define CIRRUS_ID_CLGD5422 (0x23<<2)
56 #define CIRRUS_ID_CLGD5426 (0x24<<2)
57 #define CIRRUS_ID_CLGD5424 (0x25<<2)
58 #define CIRRUS_ID_CLGD5428 (0x26<<2)
59 #define CIRRUS_ID_CLGD5430 (0x28<<2)
60 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
61 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
62 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
63
64 // sequencer 0x07
65 #define CIRRUS_SR7_BPP_VGA 0x00
66 #define CIRRUS_SR7_BPP_SVGA 0x01
67 #define CIRRUS_SR7_BPP_MASK 0x0e
68 #define CIRRUS_SR7_BPP_8 0x00
69 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
70 #define CIRRUS_SR7_BPP_24 0x04
71 #define CIRRUS_SR7_BPP_16 0x06
72 #define CIRRUS_SR7_BPP_32 0x08
73 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
74
75 // sequencer 0x0f
76 #define CIRRUS_MEMSIZE_512k 0x08
77 #define CIRRUS_MEMSIZE_1M 0x10
78 #define CIRRUS_MEMSIZE_2M 0x18
79 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
80
81 // sequencer 0x12
82 #define CIRRUS_CURSOR_SHOW 0x01
83 #define CIRRUS_CURSOR_HIDDENPEL 0x02
84 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
85
86 // sequencer 0x17
87 #define CIRRUS_BUSTYPE_VLBFAST 0x10
88 #define CIRRUS_BUSTYPE_PCI 0x20
89 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
90 #define CIRRUS_BUSTYPE_ISA 0x38
91 #define CIRRUS_MMIO_ENABLE 0x04
92 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
93 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
94
95 // control 0x0b
96 #define CIRRUS_BANKING_DUAL 0x01
97 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
98
99 // control 0x30
100 #define CIRRUS_BLTMODE_BACKWARDS 0x01
101 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
102 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
103 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
104 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
105 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
106 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
107 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
108 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
109 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
110 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
111
112 // control 0x31
113 #define CIRRUS_BLT_BUSY 0x01
114 #define CIRRUS_BLT_START 0x02
115 #define CIRRUS_BLT_RESET 0x04
116 #define CIRRUS_BLT_FIFOUSED 0x10
117 #define CIRRUS_BLT_AUTOSTART 0x80
118
119 // control 0x32
120 #define CIRRUS_ROP_0 0x00
121 #define CIRRUS_ROP_SRC_AND_DST 0x05
122 #define CIRRUS_ROP_NOP 0x06
123 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
124 #define CIRRUS_ROP_NOTDST 0x0b
125 #define CIRRUS_ROP_SRC 0x0d
126 #define CIRRUS_ROP_1 0x0e
127 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
128 #define CIRRUS_ROP_SRC_XOR_DST 0x59
129 #define CIRRUS_ROP_SRC_OR_DST 0x6d
130 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
131 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
132 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
133 #define CIRRUS_ROP_NOTSRC 0xd0
134 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
135 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
136
137 #define CIRRUS_ROP_NOP_INDEX 2
138 #define CIRRUS_ROP_SRC_INDEX 5
139
140 // control 0x33
141 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
142 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
143 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
144
145 // memory-mapped IO
146 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
147 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
148 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
149 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
150 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
151 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
152 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
153 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
154 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
155 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
156 #define CIRRUS_MMIO_BLTROP 0x1a // byte
157 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
158 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
159 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
160 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
161 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
162 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
163 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
164 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
165 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
166 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
167 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
168 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
169 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
170 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
171 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
172 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
173 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
174 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
175
176 #define CIRRUS_PNPMMIO_SIZE 0x1000
177
178 struct CirrusVGAState;
179 typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
180 uint8_t * dst, const uint8_t * src,
181 int dstpitch, int srcpitch,
182 int bltwidth, int bltheight);
183 typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
184 uint8_t *dst, int dst_pitch, int width, int height);
185
186 typedef struct CirrusVGAState {
187 VGACommonState vga;
188
189 MemoryRegion cirrus_vga_io;
190 MemoryRegion cirrus_linear_io;
191 MemoryRegion cirrus_linear_bitblt_io;
192 MemoryRegion cirrus_mmio_io;
193 MemoryRegion pci_bar;
194 bool linear_vram; /* vga.vram mapped over cirrus_linear_io */
195 MemoryRegion low_mem_container; /* container for 0xa0000-0xc0000 */
196 MemoryRegion low_mem; /* always mapped, overridden by: */
197 MemoryRegion cirrus_bank[2]; /* aliases at 0xa0000-0xb0000 */
198 uint32_t cirrus_addr_mask;
199 uint32_t linear_mmio_mask;
200 uint8_t cirrus_shadow_gr0;
201 uint8_t cirrus_shadow_gr1;
202 uint8_t cirrus_hidden_dac_lockindex;
203 uint8_t cirrus_hidden_dac_data;
204 uint32_t cirrus_bank_base[2];
205 uint32_t cirrus_bank_limit[2];
206 uint8_t cirrus_hidden_palette[48];
207 int cirrus_blt_pixelwidth;
208 int cirrus_blt_width;
209 int cirrus_blt_height;
210 int cirrus_blt_dstpitch;
211 int cirrus_blt_srcpitch;
212 uint32_t cirrus_blt_fgcol;
213 uint32_t cirrus_blt_bgcol;
214 uint32_t cirrus_blt_dstaddr;
215 uint32_t cirrus_blt_srcaddr;
216 uint8_t cirrus_blt_mode;
217 uint8_t cirrus_blt_modeext;
218 cirrus_bitblt_rop_t cirrus_rop;
219 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
220 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
221 uint8_t *cirrus_srcptr;
222 uint8_t *cirrus_srcptr_end;
223 uint32_t cirrus_srccounter;
224 /* hwcursor display state */
225 int last_hw_cursor_size;
226 int last_hw_cursor_x;
227 int last_hw_cursor_y;
228 int last_hw_cursor_y_start;
229 int last_hw_cursor_y_end;
230 int real_vram_size; /* XXX: suppress that */
231 int device_id;
232 int bustype;
233 } CirrusVGAState;
234
235 typedef struct PCICirrusVGAState {
236 PCIDevice dev;
237 CirrusVGAState cirrus_vga;
238 } PCICirrusVGAState;
239
240 #define TYPE_PCI_CIRRUS_VGA "cirrus-vga"
241 #define PCI_CIRRUS_VGA(obj) \
242 OBJECT_CHECK(PCICirrusVGAState, (obj), TYPE_PCI_CIRRUS_VGA)
243
244 #define TYPE_ISA_CIRRUS_VGA "isa-cirrus-vga"
245 #define ISA_CIRRUS_VGA(obj) \
246 OBJECT_CHECK(ISACirrusVGAState, (obj), TYPE_ISA_CIRRUS_VGA)
247
248 typedef struct ISACirrusVGAState {
249 ISADevice parent_obj;
250
251 CirrusVGAState cirrus_vga;
252 } ISACirrusVGAState;
253
254 static uint8_t rop_to_index[256];
255
256 /***************************************
257 *
258 * prototypes.
259 *
260 ***************************************/
261
262
263 static void cirrus_bitblt_reset(CirrusVGAState *s);
264 static void cirrus_update_memory_access(CirrusVGAState *s);
265
266 /***************************************
267 *
268 * raster operations
269 *
270 ***************************************/
271
272 static bool blit_region_is_unsafe(struct CirrusVGAState *s,
273 int32_t pitch, int32_t addr)
274 {
275 if (!pitch) {
276 return true;
277 }
278 if (pitch < 0) {
279 int64_t min = addr
280 + ((int64_t)s->cirrus_blt_height-1) * pitch;
281 int32_t max = addr
282 + s->cirrus_blt_width;
283 if (min < 0 || max > s->vga.vram_size) {
284 return true;
285 }
286 } else {
287 int64_t max = addr
288 + ((int64_t)s->cirrus_blt_height-1) * pitch
289 + s->cirrus_blt_width;
290 if (max > s->vga.vram_size) {
291 return true;
292 }
293 }
294 return false;
295 }
296
297 static bool blit_is_unsafe(struct CirrusVGAState *s, bool dst_only)
298 {
299 /* should be the case, see cirrus_bitblt_start */
300 assert(s->cirrus_blt_width > 0);
301 assert(s->cirrus_blt_height > 0);
302
303 if (s->cirrus_blt_width > CIRRUS_BLTBUFSIZE) {
304 return true;
305 }
306
307 if (blit_region_is_unsafe(s, s->cirrus_blt_dstpitch,
308 s->cirrus_blt_dstaddr & s->cirrus_addr_mask)) {
309 return true;
310 }
311 if (dst_only) {
312 return false;
313 }
314 if (blit_region_is_unsafe(s, s->cirrus_blt_srcpitch,
315 s->cirrus_blt_srcaddr & s->cirrus_addr_mask)) {
316 return true;
317 }
318
319 return false;
320 }
321
322 static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
323 uint8_t *dst,const uint8_t *src,
324 int dstpitch,int srcpitch,
325 int bltwidth,int bltheight)
326 {
327 }
328
329 static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
330 uint8_t *dst,
331 int dstpitch, int bltwidth,int bltheight)
332 {
333 }
334
335 #define ROP_NAME 0
336 #define ROP_FN(d, s) 0
337 #include "cirrus_vga_rop.h"
338
339 #define ROP_NAME src_and_dst
340 #define ROP_FN(d, s) (s) & (d)
341 #include "cirrus_vga_rop.h"
342
343 #define ROP_NAME src_and_notdst
344 #define ROP_FN(d, s) (s) & (~(d))
345 #include "cirrus_vga_rop.h"
346
347 #define ROP_NAME notdst
348 #define ROP_FN(d, s) ~(d)
349 #include "cirrus_vga_rop.h"
350
351 #define ROP_NAME src
352 #define ROP_FN(d, s) s
353 #include "cirrus_vga_rop.h"
354
355 #define ROP_NAME 1
356 #define ROP_FN(d, s) ~0
357 #include "cirrus_vga_rop.h"
358
359 #define ROP_NAME notsrc_and_dst
360 #define ROP_FN(d, s) (~(s)) & (d)
361 #include "cirrus_vga_rop.h"
362
363 #define ROP_NAME src_xor_dst
364 #define ROP_FN(d, s) (s) ^ (d)
365 #include "cirrus_vga_rop.h"
366
367 #define ROP_NAME src_or_dst
368 #define ROP_FN(d, s) (s) | (d)
369 #include "cirrus_vga_rop.h"
370
371 #define ROP_NAME notsrc_or_notdst
372 #define ROP_FN(d, s) (~(s)) | (~(d))
373 #include "cirrus_vga_rop.h"
374
375 #define ROP_NAME src_notxor_dst
376 #define ROP_FN(d, s) ~((s) ^ (d))
377 #include "cirrus_vga_rop.h"
378
379 #define ROP_NAME src_or_notdst
380 #define ROP_FN(d, s) (s) | (~(d))
381 #include "cirrus_vga_rop.h"
382
383 #define ROP_NAME notsrc
384 #define ROP_FN(d, s) (~(s))
385 #include "cirrus_vga_rop.h"
386
387 #define ROP_NAME notsrc_or_dst
388 #define ROP_FN(d, s) (~(s)) | (d)
389 #include "cirrus_vga_rop.h"
390
391 #define ROP_NAME notsrc_and_notdst
392 #define ROP_FN(d, s) (~(s)) & (~(d))
393 #include "cirrus_vga_rop.h"
394
395 static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
396 cirrus_bitblt_rop_fwd_0,
397 cirrus_bitblt_rop_fwd_src_and_dst,
398 cirrus_bitblt_rop_nop,
399 cirrus_bitblt_rop_fwd_src_and_notdst,
400 cirrus_bitblt_rop_fwd_notdst,
401 cirrus_bitblt_rop_fwd_src,
402 cirrus_bitblt_rop_fwd_1,
403 cirrus_bitblt_rop_fwd_notsrc_and_dst,
404 cirrus_bitblt_rop_fwd_src_xor_dst,
405 cirrus_bitblt_rop_fwd_src_or_dst,
406 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
407 cirrus_bitblt_rop_fwd_src_notxor_dst,
408 cirrus_bitblt_rop_fwd_src_or_notdst,
409 cirrus_bitblt_rop_fwd_notsrc,
410 cirrus_bitblt_rop_fwd_notsrc_or_dst,
411 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
412 };
413
414 static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
415 cirrus_bitblt_rop_bkwd_0,
416 cirrus_bitblt_rop_bkwd_src_and_dst,
417 cirrus_bitblt_rop_nop,
418 cirrus_bitblt_rop_bkwd_src_and_notdst,
419 cirrus_bitblt_rop_bkwd_notdst,
420 cirrus_bitblt_rop_bkwd_src,
421 cirrus_bitblt_rop_bkwd_1,
422 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
423 cirrus_bitblt_rop_bkwd_src_xor_dst,
424 cirrus_bitblt_rop_bkwd_src_or_dst,
425 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
426 cirrus_bitblt_rop_bkwd_src_notxor_dst,
427 cirrus_bitblt_rop_bkwd_src_or_notdst,
428 cirrus_bitblt_rop_bkwd_notsrc,
429 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
430 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
431 };
432
433 #define TRANSP_ROP(name) {\
434 name ## _8,\
435 name ## _16,\
436 }
437 #define TRANSP_NOP(func) {\
438 func,\
439 func,\
440 }
441
442 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
443 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
444 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
445 TRANSP_NOP(cirrus_bitblt_rop_nop),
446 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
447 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
448 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
449 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
450 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
451 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
452 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
453 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
454 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
455 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
456 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
457 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
458 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
459 };
460
461 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
462 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
463 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
464 TRANSP_NOP(cirrus_bitblt_rop_nop),
465 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
466 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
467 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
468 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
469 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
470 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
471 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
472 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
473 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
474 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
475 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
476 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
477 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
478 };
479
480 #define ROP2(name) {\
481 name ## _8,\
482 name ## _16,\
483 name ## _24,\
484 name ## _32,\
485 }
486
487 #define ROP_NOP2(func) {\
488 func,\
489 func,\
490 func,\
491 func,\
492 }
493
494 static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
495 ROP2(cirrus_patternfill_0),
496 ROP2(cirrus_patternfill_src_and_dst),
497 ROP_NOP2(cirrus_bitblt_rop_nop),
498 ROP2(cirrus_patternfill_src_and_notdst),
499 ROP2(cirrus_patternfill_notdst),
500 ROP2(cirrus_patternfill_src),
501 ROP2(cirrus_patternfill_1),
502 ROP2(cirrus_patternfill_notsrc_and_dst),
503 ROP2(cirrus_patternfill_src_xor_dst),
504 ROP2(cirrus_patternfill_src_or_dst),
505 ROP2(cirrus_patternfill_notsrc_or_notdst),
506 ROP2(cirrus_patternfill_src_notxor_dst),
507 ROP2(cirrus_patternfill_src_or_notdst),
508 ROP2(cirrus_patternfill_notsrc),
509 ROP2(cirrus_patternfill_notsrc_or_dst),
510 ROP2(cirrus_patternfill_notsrc_and_notdst),
511 };
512
513 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
514 ROP2(cirrus_colorexpand_transp_0),
515 ROP2(cirrus_colorexpand_transp_src_and_dst),
516 ROP_NOP2(cirrus_bitblt_rop_nop),
517 ROP2(cirrus_colorexpand_transp_src_and_notdst),
518 ROP2(cirrus_colorexpand_transp_notdst),
519 ROP2(cirrus_colorexpand_transp_src),
520 ROP2(cirrus_colorexpand_transp_1),
521 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
522 ROP2(cirrus_colorexpand_transp_src_xor_dst),
523 ROP2(cirrus_colorexpand_transp_src_or_dst),
524 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
525 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
526 ROP2(cirrus_colorexpand_transp_src_or_notdst),
527 ROP2(cirrus_colorexpand_transp_notsrc),
528 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
529 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
530 };
531
532 static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
533 ROP2(cirrus_colorexpand_0),
534 ROP2(cirrus_colorexpand_src_and_dst),
535 ROP_NOP2(cirrus_bitblt_rop_nop),
536 ROP2(cirrus_colorexpand_src_and_notdst),
537 ROP2(cirrus_colorexpand_notdst),
538 ROP2(cirrus_colorexpand_src),
539 ROP2(cirrus_colorexpand_1),
540 ROP2(cirrus_colorexpand_notsrc_and_dst),
541 ROP2(cirrus_colorexpand_src_xor_dst),
542 ROP2(cirrus_colorexpand_src_or_dst),
543 ROP2(cirrus_colorexpand_notsrc_or_notdst),
544 ROP2(cirrus_colorexpand_src_notxor_dst),
545 ROP2(cirrus_colorexpand_src_or_notdst),
546 ROP2(cirrus_colorexpand_notsrc),
547 ROP2(cirrus_colorexpand_notsrc_or_dst),
548 ROP2(cirrus_colorexpand_notsrc_and_notdst),
549 };
550
551 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
552 ROP2(cirrus_colorexpand_pattern_transp_0),
553 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
554 ROP_NOP2(cirrus_bitblt_rop_nop),
555 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
556 ROP2(cirrus_colorexpand_pattern_transp_notdst),
557 ROP2(cirrus_colorexpand_pattern_transp_src),
558 ROP2(cirrus_colorexpand_pattern_transp_1),
559 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
560 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
561 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
562 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
563 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
564 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
565 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
566 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
567 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
568 };
569
570 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
571 ROP2(cirrus_colorexpand_pattern_0),
572 ROP2(cirrus_colorexpand_pattern_src_and_dst),
573 ROP_NOP2(cirrus_bitblt_rop_nop),
574 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
575 ROP2(cirrus_colorexpand_pattern_notdst),
576 ROP2(cirrus_colorexpand_pattern_src),
577 ROP2(cirrus_colorexpand_pattern_1),
578 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
579 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
580 ROP2(cirrus_colorexpand_pattern_src_or_dst),
581 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
582 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
583 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
584 ROP2(cirrus_colorexpand_pattern_notsrc),
585 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
586 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
587 };
588
589 static const cirrus_fill_t cirrus_fill[16][4] = {
590 ROP2(cirrus_fill_0),
591 ROP2(cirrus_fill_src_and_dst),
592 ROP_NOP2(cirrus_bitblt_fill_nop),
593 ROP2(cirrus_fill_src_and_notdst),
594 ROP2(cirrus_fill_notdst),
595 ROP2(cirrus_fill_src),
596 ROP2(cirrus_fill_1),
597 ROP2(cirrus_fill_notsrc_and_dst),
598 ROP2(cirrus_fill_src_xor_dst),
599 ROP2(cirrus_fill_src_or_dst),
600 ROP2(cirrus_fill_notsrc_or_notdst),
601 ROP2(cirrus_fill_src_notxor_dst),
602 ROP2(cirrus_fill_src_or_notdst),
603 ROP2(cirrus_fill_notsrc),
604 ROP2(cirrus_fill_notsrc_or_dst),
605 ROP2(cirrus_fill_notsrc_and_notdst),
606 };
607
608 static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
609 {
610 unsigned int color;
611 switch (s->cirrus_blt_pixelwidth) {
612 case 1:
613 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
614 break;
615 case 2:
616 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
617 s->cirrus_blt_fgcol = le16_to_cpu(color);
618 break;
619 case 3:
620 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
621 (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
622 break;
623 default:
624 case 4:
625 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
626 (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
627 s->cirrus_blt_fgcol = le32_to_cpu(color);
628 break;
629 }
630 }
631
632 static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
633 {
634 unsigned int color;
635 switch (s->cirrus_blt_pixelwidth) {
636 case 1:
637 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
638 break;
639 case 2:
640 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
641 s->cirrus_blt_bgcol = le16_to_cpu(color);
642 break;
643 case 3:
644 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
645 (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
646 break;
647 default:
648 case 4:
649 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
650 (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
651 s->cirrus_blt_bgcol = le32_to_cpu(color);
652 break;
653 }
654 }
655
656 static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
657 int off_pitch, int bytesperline,
658 int lines)
659 {
660 int y;
661 int off_cur;
662 int off_cur_end;
663
664 if (off_pitch < 0) {
665 off_begin -= bytesperline - 1;
666 }
667
668 for (y = 0; y < lines; y++) {
669 off_cur = off_begin;
670 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
671 assert(off_cur_end >= off_cur);
672 memory_region_set_dirty(&s->vga.vram, off_cur, off_cur_end - off_cur);
673 off_begin += off_pitch;
674 }
675 }
676
677 static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
678 const uint8_t * src)
679 {
680 uint8_t *dst;
681
682 dst = s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
683
684 if (blit_is_unsafe(s, false))
685 return 0;
686
687 (*s->cirrus_rop) (s, dst, src,
688 s->cirrus_blt_dstpitch, 0,
689 s->cirrus_blt_width, s->cirrus_blt_height);
690 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
691 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
692 s->cirrus_blt_height);
693 return 1;
694 }
695
696 /* fill */
697
698 static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
699 {
700 cirrus_fill_t rop_func;
701
702 if (blit_is_unsafe(s, true)) {
703 return 0;
704 }
705 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
706 rop_func(s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
707 s->cirrus_blt_dstpitch,
708 s->cirrus_blt_width, s->cirrus_blt_height);
709 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
710 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
711 s->cirrus_blt_height);
712 cirrus_bitblt_reset(s);
713 return 1;
714 }
715
716 /***************************************
717 *
718 * bitblt (video-to-video)
719 *
720 ***************************************/
721
722 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
723 {
724 return cirrus_bitblt_common_patterncopy(s,
725 s->vga.vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
726 s->cirrus_addr_mask));
727 }
728
729 static int cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
730 {
731 int sx = 0, sy = 0;
732 int dx = 0, dy = 0;
733 int depth = 0;
734 int notify = 0;
735
736 /* make sure to only copy if it's a plain copy ROP */
737 if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src ||
738 *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) {
739
740 int width, height;
741
742 depth = s->vga.get_bpp(&s->vga) / 8;
743 if (!depth) {
744 return 0;
745 }
746 s->vga.get_resolution(&s->vga, &width, &height);
747
748 /* extra x, y */
749 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
750 sy = (src / ABS(s->cirrus_blt_srcpitch));
751 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
752 dy = (dst / ABS(s->cirrus_blt_dstpitch));
753
754 /* normalize width */
755 w /= depth;
756
757 /* if we're doing a backward copy, we have to adjust
758 our x/y to be the upper left corner (instead of the lower
759 right corner) */
760 if (s->cirrus_blt_dstpitch < 0) {
761 sx -= (s->cirrus_blt_width / depth) - 1;
762 dx -= (s->cirrus_blt_width / depth) - 1;
763 sy -= s->cirrus_blt_height - 1;
764 dy -= s->cirrus_blt_height - 1;
765 }
766
767 /* are we in the visible portion of memory? */
768 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
769 (sx + w) <= width && (sy + h) <= height &&
770 (dx + w) <= width && (dy + h) <= height) {
771 notify = 1;
772 }
773 }
774
775 /* we have to flush all pending changes so that the copy
776 is generated at the appropriate moment in time */
777 if (notify)
778 graphic_hw_update(s->vga.con);
779
780 (*s->cirrus_rop) (s, s->vga.vram_ptr +
781 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
782 s->vga.vram_ptr +
783 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
784 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
785 s->cirrus_blt_width, s->cirrus_blt_height);
786
787 if (notify) {
788 qemu_console_copy(s->vga.con,
789 sx, sy, dx, dy,
790 s->cirrus_blt_width / depth,
791 s->cirrus_blt_height);
792 }
793
794 /* we don't have to notify the display that this portion has
795 changed since qemu_console_copy implies this */
796
797 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
798 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
799 s->cirrus_blt_height);
800
801 return 1;
802 }
803
804 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
805 {
806 if (blit_is_unsafe(s, false))
807 return 0;
808
809 return cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
810 s->cirrus_blt_srcaddr - s->vga.start_addr,
811 s->cirrus_blt_width, s->cirrus_blt_height);
812 }
813
814 /***************************************
815 *
816 * bitblt (cpu-to-video)
817 *
818 ***************************************/
819
820 static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
821 {
822 int copy_count;
823 uint8_t *end_ptr;
824
825 if (s->cirrus_srccounter > 0) {
826 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
827 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
828 the_end:
829 s->cirrus_srccounter = 0;
830 cirrus_bitblt_reset(s);
831 } else {
832 /* at least one scan line */
833 do {
834 (*s->cirrus_rop)(s, s->vga.vram_ptr +
835 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
836 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
837 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
838 s->cirrus_blt_width, 1);
839 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
840 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
841 if (s->cirrus_srccounter <= 0)
842 goto the_end;
843 /* more bytes than needed can be transferred because of
844 word alignment, so we keep them for the next line */
845 /* XXX: keep alignment to speed up transfer */
846 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
847 copy_count = s->cirrus_srcptr_end - end_ptr;
848 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
849 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
850 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
851 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
852 }
853 }
854 }
855
856 /***************************************
857 *
858 * bitblt wrapper
859 *
860 ***************************************/
861
862 static void cirrus_bitblt_reset(CirrusVGAState * s)
863 {
864 int need_update;
865
866 s->vga.gr[0x31] &=
867 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
868 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
869 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
870 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
871 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
872 s->cirrus_srccounter = 0;
873 if (!need_update)
874 return;
875 cirrus_update_memory_access(s);
876 }
877
878 static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
879 {
880 int w;
881
882 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
883 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
884 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
885
886 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
887 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
888 s->cirrus_blt_srcpitch = 8;
889 } else {
890 /* XXX: check for 24 bpp */
891 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
892 }
893 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
894 } else {
895 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
896 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
897 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
898 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
899 else
900 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
901 } else {
902 /* always align input size to 32 bits */
903 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
904 }
905 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
906 }
907 s->cirrus_srcptr = s->cirrus_bltbuf;
908 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
909 cirrus_update_memory_access(s);
910 return 1;
911 }
912
913 static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
914 {
915 /* XXX */
916 #ifdef DEBUG_BITBLT
917 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
918 #endif
919 return 0;
920 }
921
922 static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
923 {
924 int ret;
925
926 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
927 ret = cirrus_bitblt_videotovideo_patterncopy(s);
928 } else {
929 ret = cirrus_bitblt_videotovideo_copy(s);
930 }
931 if (ret)
932 cirrus_bitblt_reset(s);
933 return ret;
934 }
935
936 static void cirrus_bitblt_start(CirrusVGAState * s)
937 {
938 uint8_t blt_rop;
939
940 s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
941
942 s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
943 s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
944 s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
945 s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
946 s->cirrus_blt_dstaddr =
947 (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
948 s->cirrus_blt_srcaddr =
949 (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
950 s->cirrus_blt_mode = s->vga.gr[0x30];
951 s->cirrus_blt_modeext = s->vga.gr[0x33];
952 blt_rop = s->vga.gr[0x32];
953
954 #ifdef DEBUG_BITBLT
955 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
956 blt_rop,
957 s->cirrus_blt_mode,
958 s->cirrus_blt_modeext,
959 s->cirrus_blt_width,
960 s->cirrus_blt_height,
961 s->cirrus_blt_dstpitch,
962 s->cirrus_blt_srcpitch,
963 s->cirrus_blt_dstaddr,
964 s->cirrus_blt_srcaddr,
965 s->vga.gr[0x2f]);
966 #endif
967
968 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
969 case CIRRUS_BLTMODE_PIXELWIDTH8:
970 s->cirrus_blt_pixelwidth = 1;
971 break;
972 case CIRRUS_BLTMODE_PIXELWIDTH16:
973 s->cirrus_blt_pixelwidth = 2;
974 break;
975 case CIRRUS_BLTMODE_PIXELWIDTH24:
976 s->cirrus_blt_pixelwidth = 3;
977 break;
978 case CIRRUS_BLTMODE_PIXELWIDTH32:
979 s->cirrus_blt_pixelwidth = 4;
980 break;
981 default:
982 #ifdef DEBUG_BITBLT
983 printf("cirrus: bitblt - pixel width is unknown\n");
984 #endif
985 goto bitblt_ignore;
986 }
987 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
988
989 if ((s->
990 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
991 CIRRUS_BLTMODE_MEMSYSDEST))
992 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
993 #ifdef DEBUG_BITBLT
994 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
995 #endif
996 goto bitblt_ignore;
997 }
998
999 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
1000 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
1001 CIRRUS_BLTMODE_TRANSPARENTCOMP |
1002 CIRRUS_BLTMODE_PATTERNCOPY |
1003 CIRRUS_BLTMODE_COLOREXPAND)) ==
1004 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
1005 cirrus_bitblt_fgcol(s);
1006 cirrus_bitblt_solidfill(s, blt_rop);
1007 } else {
1008 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
1009 CIRRUS_BLTMODE_PATTERNCOPY)) ==
1010 CIRRUS_BLTMODE_COLOREXPAND) {
1011
1012 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1013 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1014 cirrus_bitblt_bgcol(s);
1015 else
1016 cirrus_bitblt_fgcol(s);
1017 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1018 } else {
1019 cirrus_bitblt_fgcol(s);
1020 cirrus_bitblt_bgcol(s);
1021 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1022 }
1023 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
1024 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
1025 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1026 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1027 cirrus_bitblt_bgcol(s);
1028 else
1029 cirrus_bitblt_fgcol(s);
1030 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1031 } else {
1032 cirrus_bitblt_fgcol(s);
1033 cirrus_bitblt_bgcol(s);
1034 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1035 }
1036 } else {
1037 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1038 }
1039 } else {
1040 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1041 if (s->cirrus_blt_pixelwidth > 2) {
1042 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1043 goto bitblt_ignore;
1044 }
1045 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1046 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1047 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1048 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1049 } else {
1050 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1051 }
1052 } else {
1053 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1054 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1055 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1056 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1057 } else {
1058 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1059 }
1060 }
1061 }
1062 // setup bitblt engine.
1063 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1064 if (!cirrus_bitblt_cputovideo(s))
1065 goto bitblt_ignore;
1066 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1067 if (!cirrus_bitblt_videotocpu(s))
1068 goto bitblt_ignore;
1069 } else {
1070 if (!cirrus_bitblt_videotovideo(s))
1071 goto bitblt_ignore;
1072 }
1073 }
1074 return;
1075 bitblt_ignore:;
1076 cirrus_bitblt_reset(s);
1077 }
1078
1079 static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1080 {
1081 unsigned old_value;
1082
1083 old_value = s->vga.gr[0x31];
1084 s->vga.gr[0x31] = reg_value;
1085
1086 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1087 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1088 cirrus_bitblt_reset(s);
1089 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1090 ((reg_value & CIRRUS_BLT_START) != 0)) {
1091 cirrus_bitblt_start(s);
1092 }
1093 }
1094
1095
1096 /***************************************
1097 *
1098 * basic parameters
1099 *
1100 ***************************************/
1101
1102 static void cirrus_get_offsets(VGACommonState *s1,
1103 uint32_t *pline_offset,
1104 uint32_t *pstart_addr,
1105 uint32_t *pline_compare)
1106 {
1107 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1108 uint32_t start_addr, line_offset, line_compare;
1109
1110 line_offset = s->vga.cr[0x13]
1111 | ((s->vga.cr[0x1b] & 0x10) << 4);
1112 line_offset <<= 3;
1113 *pline_offset = line_offset;
1114
1115 start_addr = (s->vga.cr[0x0c] << 8)
1116 | s->vga.cr[0x0d]
1117 | ((s->vga.cr[0x1b] & 0x01) << 16)
1118 | ((s->vga.cr[0x1b] & 0x0c) << 15)
1119 | ((s->vga.cr[0x1d] & 0x80) << 12);
1120 *pstart_addr = start_addr;
1121
1122 line_compare = s->vga.cr[0x18] |
1123 ((s->vga.cr[0x07] & 0x10) << 4) |
1124 ((s->vga.cr[0x09] & 0x40) << 3);
1125 *pline_compare = line_compare;
1126 }
1127
1128 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1129 {
1130 uint32_t ret = 16;
1131
1132 switch (s->cirrus_hidden_dac_data & 0xf) {
1133 case 0:
1134 ret = 15;
1135 break; /* Sierra HiColor */
1136 case 1:
1137 ret = 16;
1138 break; /* XGA HiColor */
1139 default:
1140 #ifdef DEBUG_CIRRUS
1141 printf("cirrus: invalid DAC value %x in 16bpp\n",
1142 (s->cirrus_hidden_dac_data & 0xf));
1143 #endif
1144 ret = 15; /* XXX */
1145 break;
1146 }
1147 return ret;
1148 }
1149
1150 static int cirrus_get_bpp(VGACommonState *s1)
1151 {
1152 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1153 uint32_t ret = 8;
1154
1155 if ((s->vga.sr[0x07] & 0x01) != 0) {
1156 /* Cirrus SVGA */
1157 switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1158 case CIRRUS_SR7_BPP_8:
1159 ret = 8;
1160 break;
1161 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1162 ret = cirrus_get_bpp16_depth(s);
1163 break;
1164 case CIRRUS_SR7_BPP_24:
1165 ret = 24;
1166 break;
1167 case CIRRUS_SR7_BPP_16:
1168 ret = cirrus_get_bpp16_depth(s);
1169 break;
1170 case CIRRUS_SR7_BPP_32:
1171 ret = 32;
1172 break;
1173 default:
1174 #ifdef DEBUG_CIRRUS
1175 printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
1176 #endif
1177 ret = 8;
1178 break;
1179 }
1180 } else {
1181 /* VGA */
1182 ret = 0;
1183 }
1184
1185 return ret;
1186 }
1187
1188 static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
1189 {
1190 int width, height;
1191
1192 width = (s->cr[0x01] + 1) * 8;
1193 height = s->cr[0x12] |
1194 ((s->cr[0x07] & 0x02) << 7) |
1195 ((s->cr[0x07] & 0x40) << 3);
1196 height = (height + 1);
1197 /* interlace support */
1198 if (s->cr[0x1a] & 0x01)
1199 height = height * 2;
1200 *pwidth = width;
1201 *pheight = height;
1202 }
1203
1204 /***************************************
1205 *
1206 * bank memory
1207 *
1208 ***************************************/
1209
1210 static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1211 {
1212 unsigned offset;
1213 unsigned limit;
1214
1215 if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */
1216 offset = s->vga.gr[0x09 + bank_index];
1217 else /* single bank */
1218 offset = s->vga.gr[0x09];
1219
1220 if ((s->vga.gr[0x0b] & 0x20) != 0)
1221 offset <<= 14;
1222 else
1223 offset <<= 12;
1224
1225 if (s->real_vram_size <= offset)
1226 limit = 0;
1227 else
1228 limit = s->real_vram_size - offset;
1229
1230 if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1231 if (limit > 0x8000) {
1232 offset += 0x8000;
1233 limit -= 0x8000;
1234 } else {
1235 limit = 0;
1236 }
1237 }
1238
1239 if (limit > 0) {
1240 s->cirrus_bank_base[bank_index] = offset;
1241 s->cirrus_bank_limit[bank_index] = limit;
1242 } else {
1243 s->cirrus_bank_base[bank_index] = 0;
1244 s->cirrus_bank_limit[bank_index] = 0;
1245 }
1246 }
1247
1248 /***************************************
1249 *
1250 * I/O access between 0x3c4-0x3c5
1251 *
1252 ***************************************/
1253
1254 static int cirrus_vga_read_sr(CirrusVGAState * s)
1255 {
1256 switch (s->vga.sr_index) {
1257 case 0x00: // Standard VGA
1258 case 0x01: // Standard VGA
1259 case 0x02: // Standard VGA
1260 case 0x03: // Standard VGA
1261 case 0x04: // Standard VGA
1262 return s->vga.sr[s->vga.sr_index];
1263 case 0x06: // Unlock Cirrus extensions
1264 return s->vga.sr[s->vga.sr_index];
1265 case 0x10:
1266 case 0x30:
1267 case 0x50:
1268 case 0x70: // Graphics Cursor X
1269 case 0x90:
1270 case 0xb0:
1271 case 0xd0:
1272 case 0xf0: // Graphics Cursor X
1273 return s->vga.sr[0x10];
1274 case 0x11:
1275 case 0x31:
1276 case 0x51:
1277 case 0x71: // Graphics Cursor Y
1278 case 0x91:
1279 case 0xb1:
1280 case 0xd1:
1281 case 0xf1: // Graphics Cursor Y
1282 return s->vga.sr[0x11];
1283 case 0x05: // ???
1284 case 0x07: // Extended Sequencer Mode
1285 case 0x08: // EEPROM Control
1286 case 0x09: // Scratch Register 0
1287 case 0x0a: // Scratch Register 1
1288 case 0x0b: // VCLK 0
1289 case 0x0c: // VCLK 1
1290 case 0x0d: // VCLK 2
1291 case 0x0e: // VCLK 3
1292 case 0x0f: // DRAM Control
1293 case 0x12: // Graphics Cursor Attribute
1294 case 0x13: // Graphics Cursor Pattern Address
1295 case 0x14: // Scratch Register 2
1296 case 0x15: // Scratch Register 3
1297 case 0x16: // Performance Tuning Register
1298 case 0x17: // Configuration Readback and Extended Control
1299 case 0x18: // Signature Generator Control
1300 case 0x19: // Signal Generator Result
1301 case 0x1a: // Signal Generator Result
1302 case 0x1b: // VCLK 0 Denominator & Post
1303 case 0x1c: // VCLK 1 Denominator & Post
1304 case 0x1d: // VCLK 2 Denominator & Post
1305 case 0x1e: // VCLK 3 Denominator & Post
1306 case 0x1f: // BIOS Write Enable and MCLK select
1307 #ifdef DEBUG_CIRRUS
1308 printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index);
1309 #endif
1310 return s->vga.sr[s->vga.sr_index];
1311 default:
1312 #ifdef DEBUG_CIRRUS
1313 printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
1314 #endif
1315 return 0xff;
1316 break;
1317 }
1318 }
1319
1320 static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
1321 {
1322 switch (s->vga.sr_index) {
1323 case 0x00: // Standard VGA
1324 case 0x01: // Standard VGA
1325 case 0x02: // Standard VGA
1326 case 0x03: // Standard VGA
1327 case 0x04: // Standard VGA
1328 s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
1329 if (s->vga.sr_index == 1)
1330 s->vga.update_retrace_info(&s->vga);
1331 break;
1332 case 0x06: // Unlock Cirrus extensions
1333 val &= 0x17;
1334 if (val == 0x12) {
1335 s->vga.sr[s->vga.sr_index] = 0x12;
1336 } else {
1337 s->vga.sr[s->vga.sr_index] = 0x0f;
1338 }
1339 break;
1340 case 0x10:
1341 case 0x30:
1342 case 0x50:
1343 case 0x70: // Graphics Cursor X
1344 case 0x90:
1345 case 0xb0:
1346 case 0xd0:
1347 case 0xf0: // Graphics Cursor X
1348 s->vga.sr[0x10] = val;
1349 s->vga.hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5);
1350 break;
1351 case 0x11:
1352 case 0x31:
1353 case 0x51:
1354 case 0x71: // Graphics Cursor Y
1355 case 0x91:
1356 case 0xb1:
1357 case 0xd1:
1358 case 0xf1: // Graphics Cursor Y
1359 s->vga.sr[0x11] = val;
1360 s->vga.hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5);
1361 break;
1362 case 0x07: // Extended Sequencer Mode
1363 cirrus_update_memory_access(s);
1364 case 0x08: // EEPROM Control
1365 case 0x09: // Scratch Register 0
1366 case 0x0a: // Scratch Register 1
1367 case 0x0b: // VCLK 0
1368 case 0x0c: // VCLK 1
1369 case 0x0d: // VCLK 2
1370 case 0x0e: // VCLK 3
1371 case 0x0f: // DRAM Control
1372 case 0x13: // Graphics Cursor Pattern Address
1373 case 0x14: // Scratch Register 2
1374 case 0x15: // Scratch Register 3
1375 case 0x16: // Performance Tuning Register
1376 case 0x18: // Signature Generator Control
1377 case 0x19: // Signature Generator Result
1378 case 0x1a: // Signature Generator Result
1379 case 0x1b: // VCLK 0 Denominator & Post
1380 case 0x1c: // VCLK 1 Denominator & Post
1381 case 0x1d: // VCLK 2 Denominator & Post
1382 case 0x1e: // VCLK 3 Denominator & Post
1383 case 0x1f: // BIOS Write Enable and MCLK select
1384 s->vga.sr[s->vga.sr_index] = val;
1385 #ifdef DEBUG_CIRRUS
1386 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1387 s->vga.sr_index, val);
1388 #endif
1389 break;
1390 case 0x12: // Graphics Cursor Attribute
1391 s->vga.sr[0x12] = val;
1392 s->vga.force_shadow = !!(val & CIRRUS_CURSOR_SHOW);
1393 #ifdef DEBUG_CIRRUS
1394 printf("cirrus: cursor ctl SR12=%02x (force shadow: %d)\n",
1395 val, s->vga.force_shadow);
1396 #endif
1397 break;
1398 case 0x17: // Configuration Readback and Extended Control
1399 s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
1400 | (val & 0xc7);
1401 cirrus_update_memory_access(s);
1402 break;
1403 default:
1404 #ifdef DEBUG_CIRRUS
1405 printf("cirrus: outport sr_index %02x, sr_value %02x\n",
1406 s->vga.sr_index, val);
1407 #endif
1408 break;
1409 }
1410 }
1411
1412 /***************************************
1413 *
1414 * I/O access at 0x3c6
1415 *
1416 ***************************************/
1417
1418 static int cirrus_read_hidden_dac(CirrusVGAState * s)
1419 {
1420 if (++s->cirrus_hidden_dac_lockindex == 5) {
1421 s->cirrus_hidden_dac_lockindex = 0;
1422 return s->cirrus_hidden_dac_data;
1423 }
1424 return 0xff;
1425 }
1426
1427 static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1428 {
1429 if (s->cirrus_hidden_dac_lockindex == 4) {
1430 s->cirrus_hidden_dac_data = reg_value;
1431 #if defined(DEBUG_CIRRUS)
1432 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1433 #endif
1434 }
1435 s->cirrus_hidden_dac_lockindex = 0;
1436 }
1437
1438 /***************************************
1439 *
1440 * I/O access at 0x3c9
1441 *
1442 ***************************************/
1443
1444 static int cirrus_vga_read_palette(CirrusVGAState * s)
1445 {
1446 int val;
1447
1448 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1449 val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
1450 s->vga.dac_sub_index];
1451 } else {
1452 val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
1453 }
1454 if (++s->vga.dac_sub_index == 3) {
1455 s->vga.dac_sub_index = 0;
1456 s->vga.dac_read_index++;
1457 }
1458 return val;
1459 }
1460
1461 static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value)
1462 {
1463 s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
1464 if (++s->vga.dac_sub_index == 3) {
1465 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1466 memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
1467 s->vga.dac_cache, 3);
1468 } else {
1469 memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3);
1470 }
1471 /* XXX update cursor */
1472 s->vga.dac_sub_index = 0;
1473 s->vga.dac_write_index++;
1474 }
1475 }
1476
1477 /***************************************
1478 *
1479 * I/O access between 0x3ce-0x3cf
1480 *
1481 ***************************************/
1482
1483 static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
1484 {
1485 switch (reg_index) {
1486 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1487 return s->cirrus_shadow_gr0;
1488 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1489 return s->cirrus_shadow_gr1;
1490 case 0x02: // Standard VGA
1491 case 0x03: // Standard VGA
1492 case 0x04: // Standard VGA
1493 case 0x06: // Standard VGA
1494 case 0x07: // Standard VGA
1495 case 0x08: // Standard VGA
1496 return s->vga.gr[s->vga.gr_index];
1497 case 0x05: // Standard VGA, Cirrus extended mode
1498 default:
1499 break;
1500 }
1501
1502 if (reg_index < 0x3a) {
1503 return s->vga.gr[reg_index];
1504 } else {
1505 #ifdef DEBUG_CIRRUS
1506 printf("cirrus: inport gr_index %02x\n", reg_index);
1507 #endif
1508 return 0xff;
1509 }
1510 }
1511
1512 static void
1513 cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1514 {
1515 #if defined(DEBUG_BITBLT) && 0
1516 printf("gr%02x: %02x\n", reg_index, reg_value);
1517 #endif
1518 switch (reg_index) {
1519 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1520 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1521 s->cirrus_shadow_gr0 = reg_value;
1522 break;
1523 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1524 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1525 s->cirrus_shadow_gr1 = reg_value;
1526 break;
1527 case 0x02: // Standard VGA
1528 case 0x03: // Standard VGA
1529 case 0x04: // Standard VGA
1530 case 0x06: // Standard VGA
1531 case 0x07: // Standard VGA
1532 case 0x08: // Standard VGA
1533 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1534 break;
1535 case 0x05: // Standard VGA, Cirrus extended mode
1536 s->vga.gr[reg_index] = reg_value & 0x7f;
1537 cirrus_update_memory_access(s);
1538 break;
1539 case 0x09: // bank offset #0
1540 case 0x0A: // bank offset #1
1541 s->vga.gr[reg_index] = reg_value;
1542 cirrus_update_bank_ptr(s, 0);
1543 cirrus_update_bank_ptr(s, 1);
1544 cirrus_update_memory_access(s);
1545 break;
1546 case 0x0B:
1547 s->vga.gr[reg_index] = reg_value;
1548 cirrus_update_bank_ptr(s, 0);
1549 cirrus_update_bank_ptr(s, 1);
1550 cirrus_update_memory_access(s);
1551 break;
1552 case 0x10: // BGCOLOR 0x0000ff00
1553 case 0x11: // FGCOLOR 0x0000ff00
1554 case 0x12: // BGCOLOR 0x00ff0000
1555 case 0x13: // FGCOLOR 0x00ff0000
1556 case 0x14: // BGCOLOR 0xff000000
1557 case 0x15: // FGCOLOR 0xff000000
1558 case 0x20: // BLT WIDTH 0x0000ff
1559 case 0x22: // BLT HEIGHT 0x0000ff
1560 case 0x24: // BLT DEST PITCH 0x0000ff
1561 case 0x26: // BLT SRC PITCH 0x0000ff
1562 case 0x28: // BLT DEST ADDR 0x0000ff
1563 case 0x29: // BLT DEST ADDR 0x00ff00
1564 case 0x2c: // BLT SRC ADDR 0x0000ff
1565 case 0x2d: // BLT SRC ADDR 0x00ff00
1566 case 0x2f: // BLT WRITEMASK
1567 case 0x30: // BLT MODE
1568 case 0x32: // RASTER OP
1569 case 0x33: // BLT MODEEXT
1570 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1571 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1572 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1573 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1574 s->vga.gr[reg_index] = reg_value;
1575 break;
1576 case 0x21: // BLT WIDTH 0x001f00
1577 case 0x23: // BLT HEIGHT 0x001f00
1578 case 0x25: // BLT DEST PITCH 0x001f00
1579 case 0x27: // BLT SRC PITCH 0x001f00
1580 s->vga.gr[reg_index] = reg_value & 0x1f;
1581 break;
1582 case 0x2a: // BLT DEST ADDR 0x3f0000
1583 s->vga.gr[reg_index] = reg_value & 0x3f;
1584 /* if auto start mode, starts bit blt now */
1585 if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1586 cirrus_bitblt_start(s);
1587 }
1588 break;
1589 case 0x2e: // BLT SRC ADDR 0x3f0000
1590 s->vga.gr[reg_index] = reg_value & 0x3f;
1591 break;
1592 case 0x31: // BLT STATUS/START
1593 cirrus_write_bitblt(s, reg_value);
1594 break;
1595 default:
1596 #ifdef DEBUG_CIRRUS
1597 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1598 reg_value);
1599 #endif
1600 break;
1601 }
1602 }
1603
1604 /***************************************
1605 *
1606 * I/O access between 0x3d4-0x3d5
1607 *
1608 ***************************************/
1609
1610 static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index)
1611 {
1612 switch (reg_index) {
1613 case 0x00: // Standard VGA
1614 case 0x01: // Standard VGA
1615 case 0x02: // Standard VGA
1616 case 0x03: // Standard VGA
1617 case 0x04: // Standard VGA
1618 case 0x05: // Standard VGA
1619 case 0x06: // Standard VGA
1620 case 0x07: // Standard VGA
1621 case 0x08: // Standard VGA
1622 case 0x09: // Standard VGA
1623 case 0x0a: // Standard VGA
1624 case 0x0b: // Standard VGA
1625 case 0x0c: // Standard VGA
1626 case 0x0d: // Standard VGA
1627 case 0x0e: // Standard VGA
1628 case 0x0f: // Standard VGA
1629 case 0x10: // Standard VGA
1630 case 0x11: // Standard VGA
1631 case 0x12: // Standard VGA
1632 case 0x13: // Standard VGA
1633 case 0x14: // Standard VGA
1634 case 0x15: // Standard VGA
1635 case 0x16: // Standard VGA
1636 case 0x17: // Standard VGA
1637 case 0x18: // Standard VGA
1638 return s->vga.cr[s->vga.cr_index];
1639 case 0x24: // Attribute Controller Toggle Readback (R)
1640 return (s->vga.ar_flip_flop << 7);
1641 case 0x19: // Interlace End
1642 case 0x1a: // Miscellaneous Control
1643 case 0x1b: // Extended Display Control
1644 case 0x1c: // Sync Adjust and Genlock
1645 case 0x1d: // Overlay Extended Control
1646 case 0x22: // Graphics Data Latches Readback (R)
1647 case 0x25: // Part Status
1648 case 0x27: // Part ID (R)
1649 return s->vga.cr[s->vga.cr_index];
1650 case 0x26: // Attribute Controller Index Readback (R)
1651 return s->vga.ar_index & 0x3f;
1652 break;
1653 default:
1654 #ifdef DEBUG_CIRRUS
1655 printf("cirrus: inport cr_index %02x\n", reg_index);
1656 #endif
1657 return 0xff;
1658 }
1659 }
1660
1661 static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value)
1662 {
1663 switch (s->vga.cr_index) {
1664 case 0x00: // Standard VGA
1665 case 0x01: // Standard VGA
1666 case 0x02: // Standard VGA
1667 case 0x03: // Standard VGA
1668 case 0x04: // Standard VGA
1669 case 0x05: // Standard VGA
1670 case 0x06: // Standard VGA
1671 case 0x07: // Standard VGA
1672 case 0x08: // Standard VGA
1673 case 0x09: // Standard VGA
1674 case 0x0a: // Standard VGA
1675 case 0x0b: // Standard VGA
1676 case 0x0c: // Standard VGA
1677 case 0x0d: // Standard VGA
1678 case 0x0e: // Standard VGA
1679 case 0x0f: // Standard VGA
1680 case 0x10: // Standard VGA
1681 case 0x11: // Standard VGA
1682 case 0x12: // Standard VGA
1683 case 0x13: // Standard VGA
1684 case 0x14: // Standard VGA
1685 case 0x15: // Standard VGA
1686 case 0x16: // Standard VGA
1687 case 0x17: // Standard VGA
1688 case 0x18: // Standard VGA
1689 /* handle CR0-7 protection */
1690 if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
1691 /* can always write bit 4 of CR7 */
1692 if (s->vga.cr_index == 7)
1693 s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10);
1694 return;
1695 }
1696 s->vga.cr[s->vga.cr_index] = reg_value;
1697 switch(s->vga.cr_index) {
1698 case 0x00:
1699 case 0x04:
1700 case 0x05:
1701 case 0x06:
1702 case 0x07:
1703 case 0x11:
1704 case 0x17:
1705 s->vga.update_retrace_info(&s->vga);
1706 break;
1707 }
1708 break;
1709 case 0x19: // Interlace End
1710 case 0x1a: // Miscellaneous Control
1711 case 0x1b: // Extended Display Control
1712 case 0x1c: // Sync Adjust and Genlock
1713 case 0x1d: // Overlay Extended Control
1714 s->vga.cr[s->vga.cr_index] = reg_value;
1715 #ifdef DEBUG_CIRRUS
1716 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1717 s->vga.cr_index, reg_value);
1718 #endif
1719 break;
1720 case 0x22: // Graphics Data Latches Readback (R)
1721 case 0x24: // Attribute Controller Toggle Readback (R)
1722 case 0x26: // Attribute Controller Index Readback (R)
1723 case 0x27: // Part ID (R)
1724 break;
1725 case 0x25: // Part Status
1726 default:
1727 #ifdef DEBUG_CIRRUS
1728 printf("cirrus: outport cr_index %02x, cr_value %02x\n",
1729 s->vga.cr_index, reg_value);
1730 #endif
1731 break;
1732 }
1733 }
1734
1735 /***************************************
1736 *
1737 * memory-mapped I/O (bitblt)
1738 *
1739 ***************************************/
1740
1741 static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1742 {
1743 int value = 0xff;
1744
1745 switch (address) {
1746 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1747 value = cirrus_vga_read_gr(s, 0x00);
1748 break;
1749 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1750 value = cirrus_vga_read_gr(s, 0x10);
1751 break;
1752 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1753 value = cirrus_vga_read_gr(s, 0x12);
1754 break;
1755 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1756 value = cirrus_vga_read_gr(s, 0x14);
1757 break;
1758 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1759 value = cirrus_vga_read_gr(s, 0x01);
1760 break;
1761 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1762 value = cirrus_vga_read_gr(s, 0x11);
1763 break;
1764 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1765 value = cirrus_vga_read_gr(s, 0x13);
1766 break;
1767 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1768 value = cirrus_vga_read_gr(s, 0x15);
1769 break;
1770 case (CIRRUS_MMIO_BLTWIDTH + 0):
1771 value = cirrus_vga_read_gr(s, 0x20);
1772 break;
1773 case (CIRRUS_MMIO_BLTWIDTH + 1):
1774 value = cirrus_vga_read_gr(s, 0x21);
1775 break;
1776 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1777 value = cirrus_vga_read_gr(s, 0x22);
1778 break;
1779 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1780 value = cirrus_vga_read_gr(s, 0x23);
1781 break;
1782 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1783 value = cirrus_vga_read_gr(s, 0x24);
1784 break;
1785 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1786 value = cirrus_vga_read_gr(s, 0x25);
1787 break;
1788 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1789 value = cirrus_vga_read_gr(s, 0x26);
1790 break;
1791 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1792 value = cirrus_vga_read_gr(s, 0x27);
1793 break;
1794 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1795 value = cirrus_vga_read_gr(s, 0x28);
1796 break;
1797 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1798 value = cirrus_vga_read_gr(s, 0x29);
1799 break;
1800 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1801 value = cirrus_vga_read_gr(s, 0x2a);
1802 break;
1803 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1804 value = cirrus_vga_read_gr(s, 0x2c);
1805 break;
1806 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1807 value = cirrus_vga_read_gr(s, 0x2d);
1808 break;
1809 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1810 value = cirrus_vga_read_gr(s, 0x2e);
1811 break;
1812 case CIRRUS_MMIO_BLTWRITEMASK:
1813 value = cirrus_vga_read_gr(s, 0x2f);
1814 break;
1815 case CIRRUS_MMIO_BLTMODE:
1816 value = cirrus_vga_read_gr(s, 0x30);
1817 break;
1818 case CIRRUS_MMIO_BLTROP:
1819 value = cirrus_vga_read_gr(s, 0x32);
1820 break;
1821 case CIRRUS_MMIO_BLTMODEEXT:
1822 value = cirrus_vga_read_gr(s, 0x33);
1823 break;
1824 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1825 value = cirrus_vga_read_gr(s, 0x34);
1826 break;
1827 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1828 value = cirrus_vga_read_gr(s, 0x35);
1829 break;
1830 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1831 value = cirrus_vga_read_gr(s, 0x38);
1832 break;
1833 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1834 value = cirrus_vga_read_gr(s, 0x39);
1835 break;
1836 case CIRRUS_MMIO_BLTSTATUS:
1837 value = cirrus_vga_read_gr(s, 0x31);
1838 break;
1839 default:
1840 #ifdef DEBUG_CIRRUS
1841 printf("cirrus: mmio read - address 0x%04x\n", address);
1842 #endif
1843 break;
1844 }
1845
1846 return (uint8_t) value;
1847 }
1848
1849 static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1850 uint8_t value)
1851 {
1852 switch (address) {
1853 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1854 cirrus_vga_write_gr(s, 0x00, value);
1855 break;
1856 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1857 cirrus_vga_write_gr(s, 0x10, value);
1858 break;
1859 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1860 cirrus_vga_write_gr(s, 0x12, value);
1861 break;
1862 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1863 cirrus_vga_write_gr(s, 0x14, value);
1864 break;
1865 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1866 cirrus_vga_write_gr(s, 0x01, value);
1867 break;
1868 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1869 cirrus_vga_write_gr(s, 0x11, value);
1870 break;
1871 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1872 cirrus_vga_write_gr(s, 0x13, value);
1873 break;
1874 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1875 cirrus_vga_write_gr(s, 0x15, value);
1876 break;
1877 case (CIRRUS_MMIO_BLTWIDTH + 0):
1878 cirrus_vga_write_gr(s, 0x20, value);
1879 break;
1880 case (CIRRUS_MMIO_BLTWIDTH + 1):
1881 cirrus_vga_write_gr(s, 0x21, value);
1882 break;
1883 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1884 cirrus_vga_write_gr(s, 0x22, value);
1885 break;
1886 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1887 cirrus_vga_write_gr(s, 0x23, value);
1888 break;
1889 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1890 cirrus_vga_write_gr(s, 0x24, value);
1891 break;
1892 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1893 cirrus_vga_write_gr(s, 0x25, value);
1894 break;
1895 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1896 cirrus_vga_write_gr(s, 0x26, value);
1897 break;
1898 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1899 cirrus_vga_write_gr(s, 0x27, value);
1900 break;
1901 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1902 cirrus_vga_write_gr(s, 0x28, value);
1903 break;
1904 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1905 cirrus_vga_write_gr(s, 0x29, value);
1906 break;
1907 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1908 cirrus_vga_write_gr(s, 0x2a, value);
1909 break;
1910 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1911 /* ignored */
1912 break;
1913 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1914 cirrus_vga_write_gr(s, 0x2c, value);
1915 break;
1916 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1917 cirrus_vga_write_gr(s, 0x2d, value);
1918 break;
1919 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1920 cirrus_vga_write_gr(s, 0x2e, value);
1921 break;
1922 case CIRRUS_MMIO_BLTWRITEMASK:
1923 cirrus_vga_write_gr(s, 0x2f, value);
1924 break;
1925 case CIRRUS_MMIO_BLTMODE:
1926 cirrus_vga_write_gr(s, 0x30, value);
1927 break;
1928 case CIRRUS_MMIO_BLTROP:
1929 cirrus_vga_write_gr(s, 0x32, value);
1930 break;
1931 case CIRRUS_MMIO_BLTMODEEXT:
1932 cirrus_vga_write_gr(s, 0x33, value);
1933 break;
1934 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1935 cirrus_vga_write_gr(s, 0x34, value);
1936 break;
1937 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1938 cirrus_vga_write_gr(s, 0x35, value);
1939 break;
1940 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1941 cirrus_vga_write_gr(s, 0x38, value);
1942 break;
1943 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1944 cirrus_vga_write_gr(s, 0x39, value);
1945 break;
1946 case CIRRUS_MMIO_BLTSTATUS:
1947 cirrus_vga_write_gr(s, 0x31, value);
1948 break;
1949 default:
1950 #ifdef DEBUG_CIRRUS
1951 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1952 address, value);
1953 #endif
1954 break;
1955 }
1956 }
1957
1958 /***************************************
1959 *
1960 * write mode 4/5
1961 *
1962 ***************************************/
1963
1964 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1965 unsigned mode,
1966 unsigned offset,
1967 uint32_t mem_value)
1968 {
1969 int x;
1970 unsigned val = mem_value;
1971 uint8_t *dst;
1972
1973 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
1974 for (x = 0; x < 8; x++) {
1975 if (val & 0x80) {
1976 *dst = s->cirrus_shadow_gr1;
1977 } else if (mode == 5) {
1978 *dst = s->cirrus_shadow_gr0;
1979 }
1980 val <<= 1;
1981 dst++;
1982 }
1983 memory_region_set_dirty(&s->vga.vram, offset, 8);
1984 }
1985
1986 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1987 unsigned mode,
1988 unsigned offset,
1989 uint32_t mem_value)
1990 {
1991 int x;
1992 unsigned val = mem_value;
1993 uint8_t *dst;
1994
1995 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
1996 for (x = 0; x < 8; x++) {
1997 if (val & 0x80) {
1998 *dst = s->cirrus_shadow_gr1;
1999 *(dst + 1) = s->vga.gr[0x11];
2000 } else if (mode == 5) {
2001 *dst = s->cirrus_shadow_gr0;
2002 *(dst + 1) = s->vga.gr[0x10];
2003 }
2004 val <<= 1;
2005 dst += 2;
2006 }
2007 memory_region_set_dirty(&s->vga.vram, offset, 16);
2008 }
2009
2010 /***************************************
2011 *
2012 * memory access between 0xa0000-0xbffff
2013 *
2014 ***************************************/
2015
2016 static uint64_t cirrus_vga_mem_read(void *opaque,
2017 hwaddr addr,
2018 uint32_t size)
2019 {
2020 CirrusVGAState *s = opaque;
2021 unsigned bank_index;
2022 unsigned bank_offset;
2023 uint32_t val;
2024
2025 if ((s->vga.sr[0x07] & 0x01) == 0) {
2026 return vga_mem_readb(&s->vga, addr);
2027 }
2028
2029 if (addr < 0x10000) {
2030 /* XXX handle bitblt */
2031 /* video memory */
2032 bank_index = addr >> 15;
2033 bank_offset = addr & 0x7fff;
2034 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2035 bank_offset += s->cirrus_bank_base[bank_index];
2036 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2037 bank_offset <<= 4;
2038 } else if (s->vga.gr[0x0B] & 0x02) {
2039 bank_offset <<= 3;
2040 }
2041 bank_offset &= s->cirrus_addr_mask;
2042 val = *(s->vga.vram_ptr + bank_offset);
2043 } else
2044 val = 0xff;
2045 } else if (addr >= 0x18000 && addr < 0x18100) {
2046 /* memory-mapped I/O */
2047 val = 0xff;
2048 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
2049 val = cirrus_mmio_blt_read(s, addr & 0xff);
2050 }
2051 } else {
2052 val = 0xff;
2053 #ifdef DEBUG_CIRRUS
2054 printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr);
2055 #endif
2056 }
2057 return val;
2058 }
2059
2060 static void cirrus_vga_mem_write(void *opaque,
2061 hwaddr addr,
2062 uint64_t mem_value,
2063 uint32_t size)
2064 {
2065 CirrusVGAState *s = opaque;
2066 unsigned bank_index;
2067 unsigned bank_offset;
2068 unsigned mode;
2069
2070 if ((s->vga.sr[0x07] & 0x01) == 0) {
2071 vga_mem_writeb(&s->vga, addr, mem_value);
2072 return;
2073 }
2074
2075 if (addr < 0x10000) {
2076 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2077 /* bitblt */
2078 *s->cirrus_srcptr++ = (uint8_t) mem_value;
2079 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2080 cirrus_bitblt_cputovideo_next(s);
2081 }
2082 } else {
2083 /* video memory */
2084 bank_index = addr >> 15;
2085 bank_offset = addr & 0x7fff;
2086 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2087 bank_offset += s->cirrus_bank_base[bank_index];
2088 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2089 bank_offset <<= 4;
2090 } else if (s->vga.gr[0x0B] & 0x02) {
2091 bank_offset <<= 3;
2092 }
2093 bank_offset &= s->cirrus_addr_mask;
2094 mode = s->vga.gr[0x05] & 0x7;
2095 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2096 *(s->vga.vram_ptr + bank_offset) = mem_value;
2097 memory_region_set_dirty(&s->vga.vram, bank_offset,
2098 sizeof(mem_value));
2099 } else {
2100 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2101 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2102 bank_offset,
2103 mem_value);
2104 } else {
2105 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2106 bank_offset,
2107 mem_value);
2108 }
2109 }
2110 }
2111 }
2112 } else if (addr >= 0x18000 && addr < 0x18100) {
2113 /* memory-mapped I/O */
2114 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
2115 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2116 }
2117 } else {
2118 #ifdef DEBUG_CIRRUS
2119 printf("cirrus: mem_writeb " TARGET_FMT_plx " value 0x%02" PRIu64 "\n", addr,
2120 mem_value);
2121 #endif
2122 }
2123 }
2124
2125 static const MemoryRegionOps cirrus_vga_mem_ops = {
2126 .read = cirrus_vga_mem_read,
2127 .write = cirrus_vga_mem_write,
2128 .endianness = DEVICE_LITTLE_ENDIAN,
2129 .impl = {
2130 .min_access_size = 1,
2131 .max_access_size = 1,
2132 },
2133 };
2134
2135 /***************************************
2136 *
2137 * hardware cursor
2138 *
2139 ***************************************/
2140
2141 static inline void invalidate_cursor1(CirrusVGAState *s)
2142 {
2143 if (s->last_hw_cursor_size) {
2144 vga_invalidate_scanlines(&s->vga,
2145 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2146 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2147 }
2148 }
2149
2150 static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2151 {
2152 const uint8_t *src;
2153 uint32_t content;
2154 int y, y_min, y_max;
2155
2156 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2157 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2158 src += (s->vga.sr[0x13] & 0x3c) * 256;
2159 y_min = 64;
2160 y_max = -1;
2161 for(y = 0; y < 64; y++) {
2162 content = ((uint32_t *)src)[0] |
2163 ((uint32_t *)src)[1] |
2164 ((uint32_t *)src)[2] |
2165 ((uint32_t *)src)[3];
2166 if (content) {
2167 if (y < y_min)
2168 y_min = y;
2169 if (y > y_max)
2170 y_max = y;
2171 }
2172 src += 16;
2173 }
2174 } else {
2175 src += (s->vga.sr[0x13] & 0x3f) * 256;
2176 y_min = 32;
2177 y_max = -1;
2178 for(y = 0; y < 32; y++) {
2179 content = ((uint32_t *)src)[0] |
2180 ((uint32_t *)(src + 128))[0];
2181 if (content) {
2182 if (y < y_min)
2183 y_min = y;
2184 if (y > y_max)
2185 y_max = y;
2186 }
2187 src += 4;
2188 }
2189 }
2190 if (y_min > y_max) {
2191 s->last_hw_cursor_y_start = 0;
2192 s->last_hw_cursor_y_end = 0;
2193 } else {
2194 s->last_hw_cursor_y_start = y_min;
2195 s->last_hw_cursor_y_end = y_max + 1;
2196 }
2197 }
2198
2199 /* NOTE: we do not currently handle the cursor bitmap change, so we
2200 update the cursor only if it moves. */
2201 static void cirrus_cursor_invalidate(VGACommonState *s1)
2202 {
2203 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2204 int size;
2205
2206 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
2207 size = 0;
2208 } else {
2209 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
2210 size = 64;
2211 else
2212 size = 32;
2213 }
2214 /* invalidate last cursor and new cursor if any change */
2215 if (s->last_hw_cursor_size != size ||
2216 s->last_hw_cursor_x != s->vga.hw_cursor_x ||
2217 s->last_hw_cursor_y != s->vga.hw_cursor_y) {
2218
2219 invalidate_cursor1(s);
2220
2221 s->last_hw_cursor_size = size;
2222 s->last_hw_cursor_x = s->vga.hw_cursor_x;
2223 s->last_hw_cursor_y = s->vga.hw_cursor_y;
2224 /* compute the real cursor min and max y */
2225 cirrus_cursor_compute_yrange(s);
2226 invalidate_cursor1(s);
2227 }
2228 }
2229
2230 static void vga_draw_cursor_line(uint8_t *d1,
2231 const uint8_t *src1,
2232 int poffset, int w,
2233 unsigned int color0,
2234 unsigned int color1,
2235 unsigned int color_xor)
2236 {
2237 const uint8_t *plane0, *plane1;
2238 int x, b0, b1;
2239 uint8_t *d;
2240
2241 d = d1;
2242 plane0 = src1;
2243 plane1 = src1 + poffset;
2244 for (x = 0; x < w; x++) {
2245 b0 = (plane0[x >> 3] >> (7 - (x & 7))) & 1;
2246 b1 = (plane1[x >> 3] >> (7 - (x & 7))) & 1;
2247 switch (b0 | (b1 << 1)) {
2248 case 0:
2249 break;
2250 case 1:
2251 ((uint32_t *)d)[0] ^= color_xor;
2252 break;
2253 case 2:
2254 ((uint32_t *)d)[0] = color0;
2255 break;
2256 case 3:
2257 ((uint32_t *)d)[0] = color1;
2258 break;
2259 }
2260 d += 4;
2261 }
2262 }
2263
2264 static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
2265 {
2266 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2267 int w, h, x1, x2, poffset;
2268 unsigned int color0, color1;
2269 const uint8_t *palette, *src;
2270 uint32_t content;
2271
2272 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
2273 return;
2274 /* fast test to see if the cursor intersects with the scan line */
2275 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2276 h = 64;
2277 } else {
2278 h = 32;
2279 }
2280 if (scr_y < s->vga.hw_cursor_y ||
2281 scr_y >= (s->vga.hw_cursor_y + h)) {
2282 return;
2283 }
2284
2285 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2286 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2287 src += (s->vga.sr[0x13] & 0x3c) * 256;
2288 src += (scr_y - s->vga.hw_cursor_y) * 16;
2289 poffset = 8;
2290 content = ((uint32_t *)src)[0] |
2291 ((uint32_t *)src)[1] |
2292 ((uint32_t *)src)[2] |
2293 ((uint32_t *)src)[3];
2294 } else {
2295 src += (s->vga.sr[0x13] & 0x3f) * 256;
2296 src += (scr_y - s->vga.hw_cursor_y) * 4;
2297
2298
2299 poffset = 128;
2300 content = ((uint32_t *)src)[0] |
2301 ((uint32_t *)(src + 128))[0];
2302 }
2303 /* if nothing to draw, no need to continue */
2304 if (!content)
2305 return;
2306 w = h;
2307
2308 x1 = s->vga.hw_cursor_x;
2309 if (x1 >= s->vga.last_scr_width)
2310 return;
2311 x2 = s->vga.hw_cursor_x + w;
2312 if (x2 > s->vga.last_scr_width)
2313 x2 = s->vga.last_scr_width;
2314 w = x2 - x1;
2315 palette = s->cirrus_hidden_palette;
2316 color0 = rgb_to_pixel32(c6_to_8(palette[0x0 * 3]),
2317 c6_to_8(palette[0x0 * 3 + 1]),
2318 c6_to_8(palette[0x0 * 3 + 2]));
2319 color1 = rgb_to_pixel32(c6_to_8(palette[0xf * 3]),
2320 c6_to_8(palette[0xf * 3 + 1]),
2321 c6_to_8(palette[0xf * 3 + 2]));
2322 d1 += x1 * 4;
2323 vga_draw_cursor_line(d1, src, poffset, w, color0, color1, 0xffffff);
2324 }
2325
2326 /***************************************
2327 *
2328 * LFB memory access
2329 *
2330 ***************************************/
2331
2332 static uint64_t cirrus_linear_read(void *opaque, hwaddr addr,
2333 unsigned size)
2334 {
2335 CirrusVGAState *s = opaque;
2336 uint32_t ret;
2337
2338 addr &= s->cirrus_addr_mask;
2339
2340 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2341 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2342 /* memory-mapped I/O */
2343 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2344 } else if (0) {
2345 /* XXX handle bitblt */
2346 ret = 0xff;
2347 } else {
2348 /* video memory */
2349 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2350 addr <<= 4;
2351 } else if (s->vga.gr[0x0B] & 0x02) {
2352 addr <<= 3;
2353 }
2354 addr &= s->cirrus_addr_mask;
2355 ret = *(s->vga.vram_ptr + addr);
2356 }
2357
2358 return ret;
2359 }
2360
2361 static void cirrus_linear_write(void *opaque, hwaddr addr,
2362 uint64_t val, unsigned size)
2363 {
2364 CirrusVGAState *s = opaque;
2365 unsigned mode;
2366
2367 addr &= s->cirrus_addr_mask;
2368
2369 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2370 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2371 /* memory-mapped I/O */
2372 cirrus_mmio_blt_write(s, addr & 0xff, val);
2373 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2374 /* bitblt */
2375 *s->cirrus_srcptr++ = (uint8_t) val;
2376 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2377 cirrus_bitblt_cputovideo_next(s);
2378 }
2379 } else {
2380 /* video memory */
2381 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2382 addr <<= 4;
2383 } else if (s->vga.gr[0x0B] & 0x02) {
2384 addr <<= 3;
2385 }
2386 addr &= s->cirrus_addr_mask;
2387
2388 mode = s->vga.gr[0x05] & 0x7;
2389 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2390 *(s->vga.vram_ptr + addr) = (uint8_t) val;
2391 memory_region_set_dirty(&s->vga.vram, addr, 1);
2392 } else {
2393 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2394 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2395 } else {
2396 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2397 }
2398 }
2399 }
2400 }
2401
2402 /***************************************
2403 *
2404 * system to screen memory access
2405 *
2406 ***************************************/
2407
2408
2409 static uint64_t cirrus_linear_bitblt_read(void *opaque,
2410 hwaddr addr,
2411 unsigned size)
2412 {
2413 CirrusVGAState *s = opaque;
2414 uint32_t ret;
2415
2416 /* XXX handle bitblt */
2417 (void)s;
2418 ret = 0xff;
2419 return ret;
2420 }
2421
2422 static void cirrus_linear_bitblt_write(void *opaque,
2423 hwaddr addr,
2424 uint64_t val,
2425 unsigned size)
2426 {
2427 CirrusVGAState *s = opaque;
2428
2429 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2430 /* bitblt */
2431 *s->cirrus_srcptr++ = (uint8_t) val;
2432 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2433 cirrus_bitblt_cputovideo_next(s);
2434 }
2435 }
2436 }
2437
2438 static const MemoryRegionOps cirrus_linear_bitblt_io_ops = {
2439 .read = cirrus_linear_bitblt_read,
2440 .write = cirrus_linear_bitblt_write,
2441 .endianness = DEVICE_LITTLE_ENDIAN,
2442 .impl = {
2443 .min_access_size = 1,
2444 .max_access_size = 1,
2445 },
2446 };
2447
2448 static void map_linear_vram_bank(CirrusVGAState *s, unsigned bank)
2449 {
2450 MemoryRegion *mr = &s->cirrus_bank[bank];
2451 bool enabled = !(s->cirrus_srcptr != s->cirrus_srcptr_end)
2452 && !((s->vga.sr[0x07] & 0x01) == 0)
2453 && !((s->vga.gr[0x0B] & 0x14) == 0x14)
2454 && !(s->vga.gr[0x0B] & 0x02);
2455
2456 memory_region_set_enabled(mr, enabled);
2457 memory_region_set_alias_offset(mr, s->cirrus_bank_base[bank]);
2458 }
2459
2460 static void map_linear_vram(CirrusVGAState *s)
2461 {
2462 if (s->bustype == CIRRUS_BUSTYPE_PCI && !s->linear_vram) {
2463 s->linear_vram = true;
2464 memory_region_add_subregion_overlap(&s->pci_bar, 0, &s->vga.vram, 1);
2465 }
2466 map_linear_vram_bank(s, 0);
2467 map_linear_vram_bank(s, 1);
2468 }
2469
2470 static void unmap_linear_vram(CirrusVGAState *s)
2471 {
2472 if (s->bustype == CIRRUS_BUSTYPE_PCI && s->linear_vram) {
2473 s->linear_vram = false;
2474 memory_region_del_subregion(&s->pci_bar, &s->vga.vram);
2475 }
2476 memory_region_set_enabled(&s->cirrus_bank[0], false);
2477 memory_region_set_enabled(&s->cirrus_bank[1], false);
2478 }
2479
2480 /* Compute the memory access functions */
2481 static void cirrus_update_memory_access(CirrusVGAState *s)
2482 {
2483 unsigned mode;
2484
2485 memory_region_transaction_begin();
2486 if ((s->vga.sr[0x17] & 0x44) == 0x44) {
2487 goto generic_io;
2488 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2489 goto generic_io;
2490 } else {
2491 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2492 goto generic_io;
2493 } else if (s->vga.gr[0x0B] & 0x02) {
2494 goto generic_io;
2495 }
2496
2497 mode = s->vga.gr[0x05] & 0x7;
2498 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2499 map_linear_vram(s);
2500 } else {
2501 generic_io:
2502 unmap_linear_vram(s);
2503 }
2504 }
2505 memory_region_transaction_commit();
2506 }
2507
2508
2509 /* I/O ports */
2510
2511 static uint64_t cirrus_vga_ioport_read(void *opaque, hwaddr addr,
2512 unsigned size)
2513 {
2514 CirrusVGAState *c = opaque;
2515 VGACommonState *s = &c->vga;
2516 int val, index;
2517
2518 addr += 0x3b0;
2519
2520 if (vga_ioport_invalid(s, addr)) {
2521 val = 0xff;
2522 } else {
2523 switch (addr) {
2524 case 0x3c0:
2525 if (s->ar_flip_flop == 0) {
2526 val = s->ar_index;
2527 } else {
2528 val = 0;
2529 }
2530 break;
2531 case 0x3c1:
2532 index = s->ar_index & 0x1f;
2533 if (index < 21)
2534 val = s->ar[index];
2535 else
2536 val = 0;
2537 break;
2538 case 0x3c2:
2539 val = s->st00;
2540 break;
2541 case 0x3c4:
2542 val = s->sr_index;
2543 break;
2544 case 0x3c5:
2545 val = cirrus_vga_read_sr(c);
2546 break;
2547 #ifdef DEBUG_VGA_REG
2548 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2549 #endif
2550 break;
2551 case 0x3c6:
2552 val = cirrus_read_hidden_dac(c);
2553 break;
2554 case 0x3c7:
2555 val = s->dac_state;
2556 break;
2557 case 0x3c8:
2558 val = s->dac_write_index;
2559 c->cirrus_hidden_dac_lockindex = 0;
2560 break;
2561 case 0x3c9:
2562 val = cirrus_vga_read_palette(c);
2563 break;
2564 case 0x3ca:
2565 val = s->fcr;
2566 break;
2567 case 0x3cc:
2568 val = s->msr;
2569 break;
2570 case 0x3ce:
2571 val = s->gr_index;
2572 break;
2573 case 0x3cf:
2574 val = cirrus_vga_read_gr(c, s->gr_index);
2575 #ifdef DEBUG_VGA_REG
2576 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2577 #endif
2578 break;
2579 case 0x3b4:
2580 case 0x3d4:
2581 val = s->cr_index;
2582 break;
2583 case 0x3b5:
2584 case 0x3d5:
2585 val = cirrus_vga_read_cr(c, s->cr_index);
2586 #ifdef DEBUG_VGA_REG
2587 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2588 #endif
2589 break;
2590 case 0x3ba:
2591 case 0x3da:
2592 /* just toggle to fool polling */
2593 val = s->st01 = s->retrace(s);
2594 s->ar_flip_flop = 0;
2595 break;
2596 default:
2597 val = 0x00;
2598 break;
2599 }
2600 }
2601 #if defined(DEBUG_VGA)
2602 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2603 #endif
2604 return val;
2605 }
2606
2607 static void cirrus_vga_ioport_write(void *opaque, hwaddr addr, uint64_t val,
2608 unsigned size)
2609 {
2610 CirrusVGAState *c = opaque;
2611 VGACommonState *s = &c->vga;
2612 int index;
2613
2614 addr += 0x3b0;
2615
2616 /* check port range access depending on color/monochrome mode */
2617 if (vga_ioport_invalid(s, addr)) {
2618 return;
2619 }
2620 #ifdef DEBUG_VGA
2621 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2622 #endif
2623
2624 switch (addr) {
2625 case 0x3c0:
2626 if (s->ar_flip_flop == 0) {
2627 val &= 0x3f;
2628 s->ar_index = val;
2629 } else {
2630 index = s->ar_index & 0x1f;
2631 switch (index) {
2632 case 0x00 ... 0x0f:
2633 s->ar[index] = val & 0x3f;
2634 break;
2635 case 0x10:
2636 s->ar[index] = val & ~0x10;
2637 break;
2638 case 0x11:
2639 s->ar[index] = val;
2640 break;
2641 case 0x12:
2642 s->ar[index] = val & ~0xc0;
2643 break;
2644 case 0x13:
2645 s->ar[index] = val & ~0xf0;
2646 break;
2647 case 0x14:
2648 s->ar[index] = val & ~0xf0;
2649 break;
2650 default:
2651 break;
2652 }
2653 }
2654 s->ar_flip_flop ^= 1;
2655 break;
2656 case 0x3c2:
2657 s->msr = val & ~0x10;
2658 s->update_retrace_info(s);
2659 break;
2660 case 0x3c4:
2661 s->sr_index = val;
2662 break;
2663 case 0x3c5:
2664 #ifdef DEBUG_VGA_REG
2665 printf("vga: write SR%x = 0x%02" PRIu64 "\n", s->sr_index, val);
2666 #endif
2667 cirrus_vga_write_sr(c, val);
2668 break;
2669 case 0x3c6:
2670 cirrus_write_hidden_dac(c, val);
2671 break;
2672 case 0x3c7:
2673 s->dac_read_index = val;
2674 s->dac_sub_index = 0;
2675 s->dac_state = 3;
2676 break;
2677 case 0x3c8:
2678 s->dac_write_index = val;
2679 s->dac_sub_index = 0;
2680 s->dac_state = 0;
2681 break;
2682 case 0x3c9:
2683 cirrus_vga_write_palette(c, val);
2684 break;
2685 case 0x3ce:
2686 s->gr_index = val;
2687 break;
2688 case 0x3cf:
2689 #ifdef DEBUG_VGA_REG
2690 printf("vga: write GR%x = 0x%02" PRIu64 "\n", s->gr_index, val);
2691 #endif
2692 cirrus_vga_write_gr(c, s->gr_index, val);
2693 break;
2694 case 0x3b4:
2695 case 0x3d4:
2696 s->cr_index = val;
2697 break;
2698 case 0x3b5:
2699 case 0x3d5:
2700 #ifdef DEBUG_VGA_REG
2701 printf("vga: write CR%x = 0x%02"PRIu64"\n", s->cr_index, val);
2702 #endif
2703 cirrus_vga_write_cr(c, val);
2704 break;
2705 case 0x3ba:
2706 case 0x3da:
2707 s->fcr = val & 0x10;
2708 break;
2709 }
2710 }
2711
2712 /***************************************
2713 *
2714 * memory-mapped I/O access
2715 *
2716 ***************************************/
2717
2718 static uint64_t cirrus_mmio_read(void *opaque, hwaddr addr,
2719 unsigned size)
2720 {
2721 CirrusVGAState *s = opaque;
2722
2723 if (addr >= 0x100) {
2724 return cirrus_mmio_blt_read(s, addr - 0x100);
2725 } else {
2726 return cirrus_vga_ioport_read(s, addr + 0x10, size);
2727 }
2728 }
2729
2730 static void cirrus_mmio_write(void *opaque, hwaddr addr,
2731 uint64_t val, unsigned size)
2732 {
2733 CirrusVGAState *s = opaque;
2734
2735 if (addr >= 0x100) {
2736 cirrus_mmio_blt_write(s, addr - 0x100, val);
2737 } else {
2738 cirrus_vga_ioport_write(s, addr + 0x10, val, size);
2739 }
2740 }
2741
2742 static const MemoryRegionOps cirrus_mmio_io_ops = {
2743 .read = cirrus_mmio_read,
2744 .write = cirrus_mmio_write,
2745 .endianness = DEVICE_LITTLE_ENDIAN,
2746 .impl = {
2747 .min_access_size = 1,
2748 .max_access_size = 1,
2749 },
2750 };
2751
2752 /* load/save state */
2753
2754 static int cirrus_post_load(void *opaque, int version_id)
2755 {
2756 CirrusVGAState *s = opaque;
2757
2758 s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
2759 s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
2760
2761 cirrus_update_memory_access(s);
2762 /* force refresh */
2763 s->vga.graphic_mode = -1;
2764 cirrus_update_bank_ptr(s, 0);
2765 cirrus_update_bank_ptr(s, 1);
2766 return 0;
2767 }
2768
2769 static const VMStateDescription vmstate_cirrus_vga = {
2770 .name = "cirrus_vga",
2771 .version_id = 2,
2772 .minimum_version_id = 1,
2773 .post_load = cirrus_post_load,
2774 .fields = (VMStateField[]) {
2775 VMSTATE_UINT32(vga.latch, CirrusVGAState),
2776 VMSTATE_UINT8(vga.sr_index, CirrusVGAState),
2777 VMSTATE_BUFFER(vga.sr, CirrusVGAState),
2778 VMSTATE_UINT8(vga.gr_index, CirrusVGAState),
2779 VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState),
2780 VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState),
2781 VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2),
2782 VMSTATE_UINT8(vga.ar_index, CirrusVGAState),
2783 VMSTATE_BUFFER(vga.ar, CirrusVGAState),
2784 VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState),
2785 VMSTATE_UINT8(vga.cr_index, CirrusVGAState),
2786 VMSTATE_BUFFER(vga.cr, CirrusVGAState),
2787 VMSTATE_UINT8(vga.msr, CirrusVGAState),
2788 VMSTATE_UINT8(vga.fcr, CirrusVGAState),
2789 VMSTATE_UINT8(vga.st00, CirrusVGAState),
2790 VMSTATE_UINT8(vga.st01, CirrusVGAState),
2791 VMSTATE_UINT8(vga.dac_state, CirrusVGAState),
2792 VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState),
2793 VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState),
2794 VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState),
2795 VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState),
2796 VMSTATE_BUFFER(vga.palette, CirrusVGAState),
2797 VMSTATE_INT32(vga.bank_offset, CirrusVGAState),
2798 VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState),
2799 VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState),
2800 VMSTATE_UINT32(vga.hw_cursor_x, CirrusVGAState),
2801 VMSTATE_UINT32(vga.hw_cursor_y, CirrusVGAState),
2802 /* XXX: we do not save the bitblt state - we assume we do not save
2803 the state when the blitter is active */
2804 VMSTATE_END_OF_LIST()
2805 }
2806 };
2807
2808 static const VMStateDescription vmstate_pci_cirrus_vga = {
2809 .name = "cirrus_vga",
2810 .version_id = 2,
2811 .minimum_version_id = 2,
2812 .fields = (VMStateField[]) {
2813 VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState),
2814 VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
2815 vmstate_cirrus_vga, CirrusVGAState),
2816 VMSTATE_END_OF_LIST()
2817 }
2818 };
2819
2820 /***************************************
2821 *
2822 * initialize
2823 *
2824 ***************************************/
2825
2826 static void cirrus_reset(void *opaque)
2827 {
2828 CirrusVGAState *s = opaque;
2829
2830 vga_common_reset(&s->vga);
2831 unmap_linear_vram(s);
2832 s->vga.sr[0x06] = 0x0f;
2833 if (s->device_id == CIRRUS_ID_CLGD5446) {
2834 /* 4MB 64 bit memory config, always PCI */
2835 s->vga.sr[0x1F] = 0x2d; // MemClock
2836 s->vga.gr[0x18] = 0x0f; // fastest memory configuration
2837 s->vga.sr[0x0f] = 0x98;
2838 s->vga.sr[0x17] = 0x20;
2839 s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
2840 } else {
2841 s->vga.sr[0x1F] = 0x22; // MemClock
2842 s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
2843 s->vga.sr[0x17] = s->bustype;
2844 s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
2845 }
2846 s->vga.cr[0x27] = s->device_id;
2847
2848 s->cirrus_hidden_dac_lockindex = 5;
2849 s->cirrus_hidden_dac_data = 0;
2850 }
2851
2852 static const MemoryRegionOps cirrus_linear_io_ops = {
2853 .read = cirrus_linear_read,
2854 .write = cirrus_linear_write,
2855 .endianness = DEVICE_LITTLE_ENDIAN,
2856 .impl = {
2857 .min_access_size = 1,
2858 .max_access_size = 1,
2859 },
2860 };
2861
2862 static const MemoryRegionOps cirrus_vga_io_ops = {
2863 .read = cirrus_vga_ioport_read,
2864 .write = cirrus_vga_ioport_write,
2865 .endianness = DEVICE_LITTLE_ENDIAN,
2866 .impl = {
2867 .min_access_size = 1,
2868 .max_access_size = 1,
2869 },
2870 };
2871
2872 static void cirrus_init_common(CirrusVGAState *s, Object *owner,
2873 int device_id, int is_pci,
2874 MemoryRegion *system_memory,
2875 MemoryRegion *system_io)
2876 {
2877 int i;
2878 static int inited;
2879
2880 if (!inited) {
2881 inited = 1;
2882 for(i = 0;i < 256; i++)
2883 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
2884 rop_to_index[CIRRUS_ROP_0] = 0;
2885 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
2886 rop_to_index[CIRRUS_ROP_NOP] = 2;
2887 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
2888 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
2889 rop_to_index[CIRRUS_ROP_SRC] = 5;
2890 rop_to_index[CIRRUS_ROP_1] = 6;
2891 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
2892 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
2893 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
2894 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
2895 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
2896 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
2897 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
2898 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
2899 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
2900 s->device_id = device_id;
2901 if (is_pci)
2902 s->bustype = CIRRUS_BUSTYPE_PCI;
2903 else
2904 s->bustype = CIRRUS_BUSTYPE_ISA;
2905 }
2906
2907 /* Register ioport 0x3b0 - 0x3df */
2908 memory_region_init_io(&s->cirrus_vga_io, owner, &cirrus_vga_io_ops, s,
2909 "cirrus-io", 0x30);
2910 memory_region_set_flush_coalesced(&s->cirrus_vga_io);
2911 memory_region_add_subregion(system_io, 0x3b0, &s->cirrus_vga_io);
2912
2913 memory_region_init(&s->low_mem_container, owner,
2914 "cirrus-lowmem-container",
2915 0x20000);
2916
2917 memory_region_init_io(&s->low_mem, owner, &cirrus_vga_mem_ops, s,
2918 "cirrus-low-memory", 0x20000);
2919 memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem);
2920 for (i = 0; i < 2; ++i) {
2921 static const char *names[] = { "vga.bank0", "vga.bank1" };
2922 MemoryRegion *bank = &s->cirrus_bank[i];
2923 memory_region_init_alias(bank, owner, names[i], &s->vga.vram,
2924 0, 0x8000);
2925 memory_region_set_enabled(bank, false);
2926 memory_region_add_subregion_overlap(&s->low_mem_container, i * 0x8000,
2927 bank, 1);
2928 }
2929 memory_region_add_subregion_overlap(system_memory,
2930 0x000a0000,
2931 &s->low_mem_container,
2932 1);
2933 memory_region_set_coalescing(&s->low_mem);
2934
2935 /* I/O handler for LFB */
2936 memory_region_init_io(&s->cirrus_linear_io, owner, &cirrus_linear_io_ops, s,
2937 "cirrus-linear-io", s->vga.vram_size_mb
2938 * 1024 * 1024);
2939 memory_region_set_flush_coalesced(&s->cirrus_linear_io);
2940
2941 /* I/O handler for LFB */
2942 memory_region_init_io(&s->cirrus_linear_bitblt_io, owner,
2943 &cirrus_linear_bitblt_io_ops,
2944 s,
2945 "cirrus-bitblt-mmio",
2946 0x400000);
2947 memory_region_set_flush_coalesced(&s->cirrus_linear_bitblt_io);
2948
2949 /* I/O handler for memory-mapped I/O */
2950 memory_region_init_io(&s->cirrus_mmio_io, owner, &cirrus_mmio_io_ops, s,
2951 "cirrus-mmio", CIRRUS_PNPMMIO_SIZE);
2952 memory_region_set_flush_coalesced(&s->cirrus_mmio_io);
2953
2954 s->real_vram_size =
2955 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
2956
2957 /* XXX: s->vga.vram_size must be a power of two */
2958 s->cirrus_addr_mask = s->real_vram_size - 1;
2959 s->linear_mmio_mask = s->real_vram_size - 256;
2960
2961 s->vga.get_bpp = cirrus_get_bpp;
2962 s->vga.get_offsets = cirrus_get_offsets;
2963 s->vga.get_resolution = cirrus_get_resolution;
2964 s->vga.cursor_invalidate = cirrus_cursor_invalidate;
2965 s->vga.cursor_draw_line = cirrus_cursor_draw_line;
2966
2967 qemu_register_reset(cirrus_reset, s);
2968 }
2969
2970 /***************************************
2971 *
2972 * ISA bus support
2973 *
2974 ***************************************/
2975
2976 static void isa_cirrus_vga_realizefn(DeviceState *dev, Error **errp)
2977 {
2978 ISADevice *isadev = ISA_DEVICE(dev);
2979 ISACirrusVGAState *d = ISA_CIRRUS_VGA(dev);
2980 VGACommonState *s = &d->cirrus_vga.vga;
2981
2982 /* follow real hardware, cirrus card emulated has 4 MB video memory.
2983 Also accept 8 MB/16 MB for backward compatibility. */
2984 if (s->vram_size_mb != 4 && s->vram_size_mb != 8 &&
2985 s->vram_size_mb != 16) {
2986 error_setg(errp, "Invalid cirrus_vga ram size '%u'",
2987 s->vram_size_mb);
2988 return;
2989 }
2990 vga_common_init(s, OBJECT(dev), true);
2991 cirrus_init_common(&d->cirrus_vga, OBJECT(dev), CIRRUS_ID_CLGD5430, 0,
2992 isa_address_space(isadev),
2993 isa_address_space_io(isadev));
2994 s->con = graphic_console_init(dev, 0, s->hw_ops, s);
2995 rom_add_vga(VGABIOS_CIRRUS_FILENAME);
2996 /* XXX ISA-LFB support */
2997 /* FIXME not qdev yet */
2998 }
2999
3000 static Property isa_cirrus_vga_properties[] = {
3001 DEFINE_PROP_UINT32("vgamem_mb", struct ISACirrusVGAState,
3002 cirrus_vga.vga.vram_size_mb, 8),
3003 DEFINE_PROP_END_OF_LIST(),
3004 };
3005
3006 static void isa_cirrus_vga_class_init(ObjectClass *klass, void *data)
3007 {
3008 DeviceClass *dc = DEVICE_CLASS(klass);
3009
3010 dc->vmsd = &vmstate_cirrus_vga;
3011 dc->realize = isa_cirrus_vga_realizefn;
3012 dc->props = isa_cirrus_vga_properties;
3013 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
3014 }
3015
3016 static const TypeInfo isa_cirrus_vga_info = {
3017 .name = TYPE_ISA_CIRRUS_VGA,
3018 .parent = TYPE_ISA_DEVICE,
3019 .instance_size = sizeof(ISACirrusVGAState),
3020 .class_init = isa_cirrus_vga_class_init,
3021 };
3022
3023 /***************************************
3024 *
3025 * PCI bus support
3026 *
3027 ***************************************/
3028
3029 static void pci_cirrus_vga_realize(PCIDevice *dev, Error **errp)
3030 {
3031 PCICirrusVGAState *d = PCI_CIRRUS_VGA(dev);
3032 CirrusVGAState *s = &d->cirrus_vga;
3033 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
3034 int16_t device_id = pc->device_id;
3035
3036 /* follow real hardware, cirrus card emulated has 4 MB video memory.
3037 Also accept 8 MB/16 MB for backward compatibility. */
3038 if (s->vga.vram_size_mb != 4 && s->vga.vram_size_mb != 8 &&
3039 s->vga.vram_size_mb != 16) {
3040 error_setg(errp, "Invalid cirrus_vga ram size '%u'",
3041 s->vga.vram_size_mb);
3042 return;
3043 }
3044 /* setup VGA */
3045 vga_common_init(&s->vga, OBJECT(dev), true);
3046 cirrus_init_common(s, OBJECT(dev), device_id, 1, pci_address_space(dev),
3047 pci_address_space_io(dev));
3048 s->vga.con = graphic_console_init(DEVICE(dev), 0, s->vga.hw_ops, &s->vga);
3049
3050 /* setup PCI */
3051
3052 memory_region_init(&s->pci_bar, OBJECT(dev), "cirrus-pci-bar0", 0x2000000);
3053
3054 /* XXX: add byte swapping apertures */
3055 memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io);
3056 memory_region_add_subregion(&s->pci_bar, 0x1000000,
3057 &s->cirrus_linear_bitblt_io);
3058
3059 /* setup memory space */
3060 /* memory #0 LFB */
3061 /* memory #1 memory-mapped I/O */
3062 /* XXX: s->vga.vram_size must be a power of two */
3063 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->pci_bar);
3064 if (device_id == CIRRUS_ID_CLGD5446) {
3065 pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io);
3066 }
3067 }
3068
3069 static Property pci_vga_cirrus_properties[] = {
3070 DEFINE_PROP_UINT32("vgamem_mb", struct PCICirrusVGAState,
3071 cirrus_vga.vga.vram_size_mb, 8),
3072 DEFINE_PROP_END_OF_LIST(),
3073 };
3074
3075 static void cirrus_vga_class_init(ObjectClass *klass, void *data)
3076 {
3077 DeviceClass *dc = DEVICE_CLASS(klass);
3078 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3079
3080 k->realize = pci_cirrus_vga_realize;
3081 k->romfile = VGABIOS_CIRRUS_FILENAME;
3082 k->vendor_id = PCI_VENDOR_ID_CIRRUS;
3083 k->device_id = CIRRUS_ID_CLGD5446;
3084 k->class_id = PCI_CLASS_DISPLAY_VGA;
3085 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
3086 dc->desc = "Cirrus CLGD 54xx VGA";
3087 dc->vmsd = &vmstate_pci_cirrus_vga;
3088 dc->props = pci_vga_cirrus_properties;
3089 dc->hotpluggable = false;
3090 }
3091
3092 static const TypeInfo cirrus_vga_info = {
3093 .name = TYPE_PCI_CIRRUS_VGA,
3094 .parent = TYPE_PCI_DEVICE,
3095 .instance_size = sizeof(PCICirrusVGAState),
3096 .class_init = cirrus_vga_class_init,
3097 };
3098
3099 static void cirrus_vga_register_types(void)
3100 {
3101 type_register_static(&isa_cirrus_vga_info);
3102 type_register_static(&cirrus_vga_info);
3103 }
3104
3105 type_init(cirrus_vga_register_types)