cirrus: stop passing around dst pointers in the blitter
[qemu.git] / hw / display / cirrus_vga.c
1 /*
2 * QEMU Cirrus CLGD 54xx VGA Emulator.
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
29 #include "qemu/osdep.h"
30 #include "qapi/error.h"
31 #include "trace.h"
32 #include "hw/hw.h"
33 #include "hw/pci/pci.h"
34 #include "ui/console.h"
35 #include "ui/pixel_ops.h"
36 #include "vga_int.h"
37 #include "hw/loader.h"
38
39 /*
40 * TODO:
41 * - destination write mask support not complete (bits 5..7)
42 * - optimize linear mappings
43 * - optimize bitblt functions
44 */
45
46 //#define DEBUG_CIRRUS
47 //#define DEBUG_BITBLT
48
49 /***************************************
50 *
51 * definitions
52 *
53 ***************************************/
54
55 // ID
56 #define CIRRUS_ID_CLGD5422 (0x23<<2)
57 #define CIRRUS_ID_CLGD5426 (0x24<<2)
58 #define CIRRUS_ID_CLGD5424 (0x25<<2)
59 #define CIRRUS_ID_CLGD5428 (0x26<<2)
60 #define CIRRUS_ID_CLGD5430 (0x28<<2)
61 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
62 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
63 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
64
65 // sequencer 0x07
66 #define CIRRUS_SR7_BPP_VGA 0x00
67 #define CIRRUS_SR7_BPP_SVGA 0x01
68 #define CIRRUS_SR7_BPP_MASK 0x0e
69 #define CIRRUS_SR7_BPP_8 0x00
70 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
71 #define CIRRUS_SR7_BPP_24 0x04
72 #define CIRRUS_SR7_BPP_16 0x06
73 #define CIRRUS_SR7_BPP_32 0x08
74 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
75
76 // sequencer 0x0f
77 #define CIRRUS_MEMSIZE_512k 0x08
78 #define CIRRUS_MEMSIZE_1M 0x10
79 #define CIRRUS_MEMSIZE_2M 0x18
80 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
81
82 // sequencer 0x12
83 #define CIRRUS_CURSOR_SHOW 0x01
84 #define CIRRUS_CURSOR_HIDDENPEL 0x02
85 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
86
87 // sequencer 0x17
88 #define CIRRUS_BUSTYPE_VLBFAST 0x10
89 #define CIRRUS_BUSTYPE_PCI 0x20
90 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
91 #define CIRRUS_BUSTYPE_ISA 0x38
92 #define CIRRUS_MMIO_ENABLE 0x04
93 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
94 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
95
96 // control 0x0b
97 #define CIRRUS_BANKING_DUAL 0x01
98 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
99
100 // control 0x30
101 #define CIRRUS_BLTMODE_BACKWARDS 0x01
102 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
103 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
104 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
105 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
106 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
107 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
108 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
109 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
110 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
111 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
112
113 // control 0x31
114 #define CIRRUS_BLT_BUSY 0x01
115 #define CIRRUS_BLT_START 0x02
116 #define CIRRUS_BLT_RESET 0x04
117 #define CIRRUS_BLT_FIFOUSED 0x10
118 #define CIRRUS_BLT_AUTOSTART 0x80
119
120 // control 0x32
121 #define CIRRUS_ROP_0 0x00
122 #define CIRRUS_ROP_SRC_AND_DST 0x05
123 #define CIRRUS_ROP_NOP 0x06
124 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
125 #define CIRRUS_ROP_NOTDST 0x0b
126 #define CIRRUS_ROP_SRC 0x0d
127 #define CIRRUS_ROP_1 0x0e
128 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
129 #define CIRRUS_ROP_SRC_XOR_DST 0x59
130 #define CIRRUS_ROP_SRC_OR_DST 0x6d
131 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
132 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
133 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
134 #define CIRRUS_ROP_NOTSRC 0xd0
135 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
136 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
137
138 #define CIRRUS_ROP_NOP_INDEX 2
139 #define CIRRUS_ROP_SRC_INDEX 5
140
141 // control 0x33
142 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
143 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
144 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
145
146 // memory-mapped IO
147 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
148 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
149 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
150 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
151 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
152 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
153 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
154 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
155 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
156 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
157 #define CIRRUS_MMIO_BLTROP 0x1a // byte
158 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
159 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
160 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
161 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
162 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
163 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
164 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
165 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
166 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
167 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
168 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
169 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
170 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
171 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
172 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
173 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
174 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
175 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
176
177 #define CIRRUS_PNPMMIO_SIZE 0x1000
178
179 struct CirrusVGAState;
180 typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
181 uint32_t dstaddr, const uint8_t *src,
182 int dstpitch, int srcpitch,
183 int bltwidth, int bltheight);
184 typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
185 uint32_t dstaddr, int dst_pitch,
186 int width, int height);
187
188 typedef struct CirrusVGAState {
189 VGACommonState vga;
190
191 MemoryRegion cirrus_vga_io;
192 MemoryRegion cirrus_linear_io;
193 MemoryRegion cirrus_linear_bitblt_io;
194 MemoryRegion cirrus_mmio_io;
195 MemoryRegion pci_bar;
196 bool linear_vram; /* vga.vram mapped over cirrus_linear_io */
197 MemoryRegion low_mem_container; /* container for 0xa0000-0xc0000 */
198 MemoryRegion low_mem; /* always mapped, overridden by: */
199 MemoryRegion cirrus_bank[2]; /* aliases at 0xa0000-0xb0000 */
200 uint32_t cirrus_addr_mask;
201 uint32_t linear_mmio_mask;
202 uint8_t cirrus_shadow_gr0;
203 uint8_t cirrus_shadow_gr1;
204 uint8_t cirrus_hidden_dac_lockindex;
205 uint8_t cirrus_hidden_dac_data;
206 uint32_t cirrus_bank_base[2];
207 uint32_t cirrus_bank_limit[2];
208 uint8_t cirrus_hidden_palette[48];
209 bool enable_blitter;
210 int cirrus_blt_pixelwidth;
211 int cirrus_blt_width;
212 int cirrus_blt_height;
213 int cirrus_blt_dstpitch;
214 int cirrus_blt_srcpitch;
215 uint32_t cirrus_blt_fgcol;
216 uint32_t cirrus_blt_bgcol;
217 uint32_t cirrus_blt_dstaddr;
218 uint32_t cirrus_blt_srcaddr;
219 uint8_t cirrus_blt_mode;
220 uint8_t cirrus_blt_modeext;
221 cirrus_bitblt_rop_t cirrus_rop;
222 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
223 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
224 uint8_t *cirrus_srcptr;
225 uint8_t *cirrus_srcptr_end;
226 uint32_t cirrus_srccounter;
227 /* hwcursor display state */
228 int last_hw_cursor_size;
229 int last_hw_cursor_x;
230 int last_hw_cursor_y;
231 int last_hw_cursor_y_start;
232 int last_hw_cursor_y_end;
233 int real_vram_size; /* XXX: suppress that */
234 int device_id;
235 int bustype;
236 } CirrusVGAState;
237
238 typedef struct PCICirrusVGAState {
239 PCIDevice dev;
240 CirrusVGAState cirrus_vga;
241 } PCICirrusVGAState;
242
243 #define TYPE_PCI_CIRRUS_VGA "cirrus-vga"
244 #define PCI_CIRRUS_VGA(obj) \
245 OBJECT_CHECK(PCICirrusVGAState, (obj), TYPE_PCI_CIRRUS_VGA)
246
247 #define TYPE_ISA_CIRRUS_VGA "isa-cirrus-vga"
248 #define ISA_CIRRUS_VGA(obj) \
249 OBJECT_CHECK(ISACirrusVGAState, (obj), TYPE_ISA_CIRRUS_VGA)
250
251 typedef struct ISACirrusVGAState {
252 ISADevice parent_obj;
253
254 CirrusVGAState cirrus_vga;
255 } ISACirrusVGAState;
256
257 static uint8_t rop_to_index[256];
258
259 /***************************************
260 *
261 * prototypes.
262 *
263 ***************************************/
264
265
266 static void cirrus_bitblt_reset(CirrusVGAState *s);
267 static void cirrus_update_memory_access(CirrusVGAState *s);
268
269 /***************************************
270 *
271 * raster operations
272 *
273 ***************************************/
274
275 static bool blit_region_is_unsafe(struct CirrusVGAState *s,
276 int32_t pitch, int32_t addr)
277 {
278 if (!pitch) {
279 return true;
280 }
281 if (pitch < 0) {
282 int64_t min = addr
283 + ((int64_t)s->cirrus_blt_height - 1) * pitch
284 - s->cirrus_blt_width;
285 if (min < -1 || addr >= s->vga.vram_size) {
286 return true;
287 }
288 } else {
289 int64_t max = addr
290 + ((int64_t)s->cirrus_blt_height-1) * pitch
291 + s->cirrus_blt_width;
292 if (max > s->vga.vram_size) {
293 return true;
294 }
295 }
296 return false;
297 }
298
299 static bool blit_is_unsafe(struct CirrusVGAState *s, bool dst_only)
300 {
301 /* should be the case, see cirrus_bitblt_start */
302 assert(s->cirrus_blt_width > 0);
303 assert(s->cirrus_blt_height > 0);
304
305 if (s->cirrus_blt_width > CIRRUS_BLTBUFSIZE) {
306 return true;
307 }
308
309 if (blit_region_is_unsafe(s, s->cirrus_blt_dstpitch,
310 s->cirrus_blt_dstaddr)) {
311 return true;
312 }
313 if (dst_only) {
314 return false;
315 }
316 if (blit_region_is_unsafe(s, s->cirrus_blt_srcpitch,
317 s->cirrus_blt_srcaddr)) {
318 return true;
319 }
320
321 return false;
322 }
323
324 static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
325 uint32_t dstaddr, const uint8_t *src,
326 int dstpitch,int srcpitch,
327 int bltwidth,int bltheight)
328 {
329 }
330
331 static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
332 uint32_t dstaddr,
333 int dstpitch, int bltwidth,int bltheight)
334 {
335 }
336
337 #define ROP_NAME 0
338 #define ROP_FN(d, s) 0
339 #include "cirrus_vga_rop.h"
340
341 #define ROP_NAME src_and_dst
342 #define ROP_FN(d, s) (s) & (d)
343 #include "cirrus_vga_rop.h"
344
345 #define ROP_NAME src_and_notdst
346 #define ROP_FN(d, s) (s) & (~(d))
347 #include "cirrus_vga_rop.h"
348
349 #define ROP_NAME notdst
350 #define ROP_FN(d, s) ~(d)
351 #include "cirrus_vga_rop.h"
352
353 #define ROP_NAME src
354 #define ROP_FN(d, s) s
355 #include "cirrus_vga_rop.h"
356
357 #define ROP_NAME 1
358 #define ROP_FN(d, s) ~0
359 #include "cirrus_vga_rop.h"
360
361 #define ROP_NAME notsrc_and_dst
362 #define ROP_FN(d, s) (~(s)) & (d)
363 #include "cirrus_vga_rop.h"
364
365 #define ROP_NAME src_xor_dst
366 #define ROP_FN(d, s) (s) ^ (d)
367 #include "cirrus_vga_rop.h"
368
369 #define ROP_NAME src_or_dst
370 #define ROP_FN(d, s) (s) | (d)
371 #include "cirrus_vga_rop.h"
372
373 #define ROP_NAME notsrc_or_notdst
374 #define ROP_FN(d, s) (~(s)) | (~(d))
375 #include "cirrus_vga_rop.h"
376
377 #define ROP_NAME src_notxor_dst
378 #define ROP_FN(d, s) ~((s) ^ (d))
379 #include "cirrus_vga_rop.h"
380
381 #define ROP_NAME src_or_notdst
382 #define ROP_FN(d, s) (s) | (~(d))
383 #include "cirrus_vga_rop.h"
384
385 #define ROP_NAME notsrc
386 #define ROP_FN(d, s) (~(s))
387 #include "cirrus_vga_rop.h"
388
389 #define ROP_NAME notsrc_or_dst
390 #define ROP_FN(d, s) (~(s)) | (d)
391 #include "cirrus_vga_rop.h"
392
393 #define ROP_NAME notsrc_and_notdst
394 #define ROP_FN(d, s) (~(s)) & (~(d))
395 #include "cirrus_vga_rop.h"
396
397 static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
398 cirrus_bitblt_rop_fwd_0,
399 cirrus_bitblt_rop_fwd_src_and_dst,
400 cirrus_bitblt_rop_nop,
401 cirrus_bitblt_rop_fwd_src_and_notdst,
402 cirrus_bitblt_rop_fwd_notdst,
403 cirrus_bitblt_rop_fwd_src,
404 cirrus_bitblt_rop_fwd_1,
405 cirrus_bitblt_rop_fwd_notsrc_and_dst,
406 cirrus_bitblt_rop_fwd_src_xor_dst,
407 cirrus_bitblt_rop_fwd_src_or_dst,
408 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
409 cirrus_bitblt_rop_fwd_src_notxor_dst,
410 cirrus_bitblt_rop_fwd_src_or_notdst,
411 cirrus_bitblt_rop_fwd_notsrc,
412 cirrus_bitblt_rop_fwd_notsrc_or_dst,
413 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
414 };
415
416 static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
417 cirrus_bitblt_rop_bkwd_0,
418 cirrus_bitblt_rop_bkwd_src_and_dst,
419 cirrus_bitblt_rop_nop,
420 cirrus_bitblt_rop_bkwd_src_and_notdst,
421 cirrus_bitblt_rop_bkwd_notdst,
422 cirrus_bitblt_rop_bkwd_src,
423 cirrus_bitblt_rop_bkwd_1,
424 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
425 cirrus_bitblt_rop_bkwd_src_xor_dst,
426 cirrus_bitblt_rop_bkwd_src_or_dst,
427 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
428 cirrus_bitblt_rop_bkwd_src_notxor_dst,
429 cirrus_bitblt_rop_bkwd_src_or_notdst,
430 cirrus_bitblt_rop_bkwd_notsrc,
431 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
432 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
433 };
434
435 #define TRANSP_ROP(name) {\
436 name ## _8,\
437 name ## _16,\
438 }
439 #define TRANSP_NOP(func) {\
440 func,\
441 func,\
442 }
443
444 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
445 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
446 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
447 TRANSP_NOP(cirrus_bitblt_rop_nop),
448 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
449 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
450 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
451 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
452 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
453 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
454 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
455 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
456 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
457 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
458 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
459 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
460 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
461 };
462
463 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
464 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
465 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
466 TRANSP_NOP(cirrus_bitblt_rop_nop),
467 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
468 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
469 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
470 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
471 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
472 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
473 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
474 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
475 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
476 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
477 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
478 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
479 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
480 };
481
482 #define ROP2(name) {\
483 name ## _8,\
484 name ## _16,\
485 name ## _24,\
486 name ## _32,\
487 }
488
489 #define ROP_NOP2(func) {\
490 func,\
491 func,\
492 func,\
493 func,\
494 }
495
496 static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
497 ROP2(cirrus_patternfill_0),
498 ROP2(cirrus_patternfill_src_and_dst),
499 ROP_NOP2(cirrus_bitblt_rop_nop),
500 ROP2(cirrus_patternfill_src_and_notdst),
501 ROP2(cirrus_patternfill_notdst),
502 ROP2(cirrus_patternfill_src),
503 ROP2(cirrus_patternfill_1),
504 ROP2(cirrus_patternfill_notsrc_and_dst),
505 ROP2(cirrus_patternfill_src_xor_dst),
506 ROP2(cirrus_patternfill_src_or_dst),
507 ROP2(cirrus_patternfill_notsrc_or_notdst),
508 ROP2(cirrus_patternfill_src_notxor_dst),
509 ROP2(cirrus_patternfill_src_or_notdst),
510 ROP2(cirrus_patternfill_notsrc),
511 ROP2(cirrus_patternfill_notsrc_or_dst),
512 ROP2(cirrus_patternfill_notsrc_and_notdst),
513 };
514
515 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
516 ROP2(cirrus_colorexpand_transp_0),
517 ROP2(cirrus_colorexpand_transp_src_and_dst),
518 ROP_NOP2(cirrus_bitblt_rop_nop),
519 ROP2(cirrus_colorexpand_transp_src_and_notdst),
520 ROP2(cirrus_colorexpand_transp_notdst),
521 ROP2(cirrus_colorexpand_transp_src),
522 ROP2(cirrus_colorexpand_transp_1),
523 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
524 ROP2(cirrus_colorexpand_transp_src_xor_dst),
525 ROP2(cirrus_colorexpand_transp_src_or_dst),
526 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
527 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
528 ROP2(cirrus_colorexpand_transp_src_or_notdst),
529 ROP2(cirrus_colorexpand_transp_notsrc),
530 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
531 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
532 };
533
534 static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
535 ROP2(cirrus_colorexpand_0),
536 ROP2(cirrus_colorexpand_src_and_dst),
537 ROP_NOP2(cirrus_bitblt_rop_nop),
538 ROP2(cirrus_colorexpand_src_and_notdst),
539 ROP2(cirrus_colorexpand_notdst),
540 ROP2(cirrus_colorexpand_src),
541 ROP2(cirrus_colorexpand_1),
542 ROP2(cirrus_colorexpand_notsrc_and_dst),
543 ROP2(cirrus_colorexpand_src_xor_dst),
544 ROP2(cirrus_colorexpand_src_or_dst),
545 ROP2(cirrus_colorexpand_notsrc_or_notdst),
546 ROP2(cirrus_colorexpand_src_notxor_dst),
547 ROP2(cirrus_colorexpand_src_or_notdst),
548 ROP2(cirrus_colorexpand_notsrc),
549 ROP2(cirrus_colorexpand_notsrc_or_dst),
550 ROP2(cirrus_colorexpand_notsrc_and_notdst),
551 };
552
553 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
554 ROP2(cirrus_colorexpand_pattern_transp_0),
555 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
556 ROP_NOP2(cirrus_bitblt_rop_nop),
557 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
558 ROP2(cirrus_colorexpand_pattern_transp_notdst),
559 ROP2(cirrus_colorexpand_pattern_transp_src),
560 ROP2(cirrus_colorexpand_pattern_transp_1),
561 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
562 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
563 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
564 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
565 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
566 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
567 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
568 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
569 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
570 };
571
572 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
573 ROP2(cirrus_colorexpand_pattern_0),
574 ROP2(cirrus_colorexpand_pattern_src_and_dst),
575 ROP_NOP2(cirrus_bitblt_rop_nop),
576 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
577 ROP2(cirrus_colorexpand_pattern_notdst),
578 ROP2(cirrus_colorexpand_pattern_src),
579 ROP2(cirrus_colorexpand_pattern_1),
580 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
581 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
582 ROP2(cirrus_colorexpand_pattern_src_or_dst),
583 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
584 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
585 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
586 ROP2(cirrus_colorexpand_pattern_notsrc),
587 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
588 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
589 };
590
591 static const cirrus_fill_t cirrus_fill[16][4] = {
592 ROP2(cirrus_fill_0),
593 ROP2(cirrus_fill_src_and_dst),
594 ROP_NOP2(cirrus_bitblt_fill_nop),
595 ROP2(cirrus_fill_src_and_notdst),
596 ROP2(cirrus_fill_notdst),
597 ROP2(cirrus_fill_src),
598 ROP2(cirrus_fill_1),
599 ROP2(cirrus_fill_notsrc_and_dst),
600 ROP2(cirrus_fill_src_xor_dst),
601 ROP2(cirrus_fill_src_or_dst),
602 ROP2(cirrus_fill_notsrc_or_notdst),
603 ROP2(cirrus_fill_src_notxor_dst),
604 ROP2(cirrus_fill_src_or_notdst),
605 ROP2(cirrus_fill_notsrc),
606 ROP2(cirrus_fill_notsrc_or_dst),
607 ROP2(cirrus_fill_notsrc_and_notdst),
608 };
609
610 static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
611 {
612 unsigned int color;
613 switch (s->cirrus_blt_pixelwidth) {
614 case 1:
615 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
616 break;
617 case 2:
618 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
619 s->cirrus_blt_fgcol = le16_to_cpu(color);
620 break;
621 case 3:
622 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
623 (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
624 break;
625 default:
626 case 4:
627 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
628 (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
629 s->cirrus_blt_fgcol = le32_to_cpu(color);
630 break;
631 }
632 }
633
634 static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
635 {
636 unsigned int color;
637 switch (s->cirrus_blt_pixelwidth) {
638 case 1:
639 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
640 break;
641 case 2:
642 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
643 s->cirrus_blt_bgcol = le16_to_cpu(color);
644 break;
645 case 3:
646 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
647 (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
648 break;
649 default:
650 case 4:
651 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
652 (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
653 s->cirrus_blt_bgcol = le32_to_cpu(color);
654 break;
655 }
656 }
657
658 static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
659 int off_pitch, int bytesperline,
660 int lines)
661 {
662 int y;
663 int off_cur;
664 int off_cur_end;
665
666 if (off_pitch < 0) {
667 off_begin -= bytesperline - 1;
668 }
669
670 for (y = 0; y < lines; y++) {
671 off_cur = off_begin;
672 off_cur_end = ((off_cur + bytesperline - 1) & s->cirrus_addr_mask) + 1;
673 assert(off_cur_end >= off_cur);
674 memory_region_set_dirty(&s->vga.vram, off_cur, off_cur_end - off_cur);
675 off_begin += off_pitch;
676 }
677 }
678
679 static int cirrus_bitblt_common_patterncopy(CirrusVGAState *s, bool videosrc)
680 {
681 uint32_t patternsize;
682 uint8_t *src;
683
684 if (videosrc) {
685 switch (s->vga.get_bpp(&s->vga)) {
686 case 8:
687 patternsize = 64;
688 break;
689 case 15:
690 case 16:
691 patternsize = 128;
692 break;
693 case 24:
694 case 32:
695 default:
696 patternsize = 256;
697 break;
698 }
699 s->cirrus_blt_srcaddr &= ~(patternsize - 1);
700 if (s->cirrus_blt_srcaddr + patternsize > s->vga.vram_size) {
701 return 0;
702 }
703 src = s->vga.vram_ptr + s->cirrus_blt_srcaddr;
704 } else {
705 src = s->cirrus_bltbuf;
706 }
707
708 if (blit_is_unsafe(s, true)) {
709 return 0;
710 }
711
712 (*s->cirrus_rop) (s, s->cirrus_blt_dstaddr, src,
713 s->cirrus_blt_dstpitch, 0,
714 s->cirrus_blt_width, s->cirrus_blt_height);
715 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
716 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
717 s->cirrus_blt_height);
718 return 1;
719 }
720
721 /* fill */
722
723 static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
724 {
725 cirrus_fill_t rop_func;
726
727 if (blit_is_unsafe(s, true)) {
728 return 0;
729 }
730 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
731 rop_func(s, s->cirrus_blt_dstaddr,
732 s->cirrus_blt_dstpitch,
733 s->cirrus_blt_width, s->cirrus_blt_height);
734 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
735 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
736 s->cirrus_blt_height);
737 cirrus_bitblt_reset(s);
738 return 1;
739 }
740
741 /***************************************
742 *
743 * bitblt (video-to-video)
744 *
745 ***************************************/
746
747 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
748 {
749 return cirrus_bitblt_common_patterncopy(s, true);
750 }
751
752 static int cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
753 {
754 int sx = 0, sy = 0;
755 int dx = 0, dy = 0;
756 int depth = 0;
757 int notify = 0;
758
759 /* make sure to only copy if it's a plain copy ROP */
760 if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src ||
761 *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) {
762
763 int width, height;
764
765 depth = s->vga.get_bpp(&s->vga) / 8;
766 if (!depth) {
767 return 0;
768 }
769 s->vga.get_resolution(&s->vga, &width, &height);
770
771 /* extra x, y */
772 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
773 sy = (src / ABS(s->cirrus_blt_srcpitch));
774 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
775 dy = (dst / ABS(s->cirrus_blt_dstpitch));
776
777 /* normalize width */
778 w /= depth;
779
780 /* if we're doing a backward copy, we have to adjust
781 our x/y to be the upper left corner (instead of the lower
782 right corner) */
783 if (s->cirrus_blt_dstpitch < 0) {
784 sx -= (s->cirrus_blt_width / depth) - 1;
785 dx -= (s->cirrus_blt_width / depth) - 1;
786 sy -= s->cirrus_blt_height - 1;
787 dy -= s->cirrus_blt_height - 1;
788 }
789
790 /* are we in the visible portion of memory? */
791 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
792 (sx + w) <= width && (sy + h) <= height &&
793 (dx + w) <= width && (dy + h) <= height) {
794 notify = 1;
795 }
796 }
797
798 (*s->cirrus_rop) (s, s->cirrus_blt_dstaddr,
799 s->vga.vram_ptr + s->cirrus_blt_srcaddr,
800 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
801 s->cirrus_blt_width, s->cirrus_blt_height);
802
803 if (notify) {
804 dpy_gfx_update(s->vga.con, dx, dy,
805 s->cirrus_blt_width / depth,
806 s->cirrus_blt_height);
807 }
808
809 /* we don't have to notify the display that this portion has
810 changed since qemu_console_copy implies this */
811
812 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
813 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
814 s->cirrus_blt_height);
815
816 return 1;
817 }
818
819 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
820 {
821 if (blit_is_unsafe(s, false))
822 return 0;
823
824 return cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
825 s->cirrus_blt_srcaddr - s->vga.start_addr,
826 s->cirrus_blt_width, s->cirrus_blt_height);
827 }
828
829 /***************************************
830 *
831 * bitblt (cpu-to-video)
832 *
833 ***************************************/
834
835 static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
836 {
837 int copy_count;
838 uint8_t *end_ptr;
839
840 if (s->cirrus_srccounter > 0) {
841 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
842 cirrus_bitblt_common_patterncopy(s, false);
843 the_end:
844 s->cirrus_srccounter = 0;
845 cirrus_bitblt_reset(s);
846 } else {
847 /* at least one scan line */
848 do {
849 (*s->cirrus_rop)(s, s->cirrus_blt_dstaddr,
850 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
851 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
852 s->cirrus_blt_width, 1);
853 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
854 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
855 if (s->cirrus_srccounter <= 0)
856 goto the_end;
857 /* more bytes than needed can be transferred because of
858 word alignment, so we keep them for the next line */
859 /* XXX: keep alignment to speed up transfer */
860 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
861 copy_count = s->cirrus_srcptr_end - end_ptr;
862 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
863 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
864 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
865 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
866 }
867 }
868 }
869
870 /***************************************
871 *
872 * bitblt wrapper
873 *
874 ***************************************/
875
876 static void cirrus_bitblt_reset(CirrusVGAState * s)
877 {
878 int need_update;
879
880 s->vga.gr[0x31] &=
881 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
882 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
883 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
884 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
885 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
886 s->cirrus_srccounter = 0;
887 if (!need_update)
888 return;
889 cirrus_update_memory_access(s);
890 }
891
892 static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
893 {
894 int w;
895
896 if (blit_is_unsafe(s, true)) {
897 return 0;
898 }
899
900 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
901 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
902 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
903
904 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
905 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
906 s->cirrus_blt_srcpitch = 8;
907 } else {
908 /* XXX: check for 24 bpp */
909 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
910 }
911 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
912 } else {
913 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
914 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
915 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
916 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
917 else
918 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
919 } else {
920 /* always align input size to 32 bits */
921 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
922 }
923 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
924 }
925
926 /* the blit_is_unsafe call above should catch this */
927 assert(s->cirrus_blt_srcpitch <= CIRRUS_BLTBUFSIZE);
928
929 s->cirrus_srcptr = s->cirrus_bltbuf;
930 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
931 cirrus_update_memory_access(s);
932 return 1;
933 }
934
935 static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
936 {
937 /* XXX */
938 #ifdef DEBUG_BITBLT
939 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
940 #endif
941 return 0;
942 }
943
944 static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
945 {
946 int ret;
947
948 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
949 ret = cirrus_bitblt_videotovideo_patterncopy(s);
950 } else {
951 ret = cirrus_bitblt_videotovideo_copy(s);
952 }
953 if (ret)
954 cirrus_bitblt_reset(s);
955 return ret;
956 }
957
958 static void cirrus_bitblt_start(CirrusVGAState * s)
959 {
960 uint8_t blt_rop;
961
962 if (!s->enable_blitter) {
963 goto bitblt_ignore;
964 }
965
966 s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
967
968 s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
969 s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
970 s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
971 s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
972 s->cirrus_blt_dstaddr =
973 (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
974 s->cirrus_blt_srcaddr =
975 (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
976 s->cirrus_blt_mode = s->vga.gr[0x30];
977 s->cirrus_blt_modeext = s->vga.gr[0x33];
978 blt_rop = s->vga.gr[0x32];
979
980 s->cirrus_blt_dstaddr &= s->cirrus_addr_mask;
981 s->cirrus_blt_srcaddr &= s->cirrus_addr_mask;
982
983 #ifdef DEBUG_BITBLT
984 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
985 blt_rop,
986 s->cirrus_blt_mode,
987 s->cirrus_blt_modeext,
988 s->cirrus_blt_width,
989 s->cirrus_blt_height,
990 s->cirrus_blt_dstpitch,
991 s->cirrus_blt_srcpitch,
992 s->cirrus_blt_dstaddr,
993 s->cirrus_blt_srcaddr,
994 s->vga.gr[0x2f]);
995 #endif
996
997 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
998 case CIRRUS_BLTMODE_PIXELWIDTH8:
999 s->cirrus_blt_pixelwidth = 1;
1000 break;
1001 case CIRRUS_BLTMODE_PIXELWIDTH16:
1002 s->cirrus_blt_pixelwidth = 2;
1003 break;
1004 case CIRRUS_BLTMODE_PIXELWIDTH24:
1005 s->cirrus_blt_pixelwidth = 3;
1006 break;
1007 case CIRRUS_BLTMODE_PIXELWIDTH32:
1008 s->cirrus_blt_pixelwidth = 4;
1009 break;
1010 default:
1011 #ifdef DEBUG_BITBLT
1012 printf("cirrus: bitblt - pixel width is unknown\n");
1013 #endif
1014 goto bitblt_ignore;
1015 }
1016 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
1017
1018 if ((s->
1019 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
1020 CIRRUS_BLTMODE_MEMSYSDEST))
1021 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
1022 #ifdef DEBUG_BITBLT
1023 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
1024 #endif
1025 goto bitblt_ignore;
1026 }
1027
1028 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
1029 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
1030 CIRRUS_BLTMODE_TRANSPARENTCOMP |
1031 CIRRUS_BLTMODE_PATTERNCOPY |
1032 CIRRUS_BLTMODE_COLOREXPAND)) ==
1033 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
1034 cirrus_bitblt_fgcol(s);
1035 cirrus_bitblt_solidfill(s, blt_rop);
1036 } else {
1037 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
1038 CIRRUS_BLTMODE_PATTERNCOPY)) ==
1039 CIRRUS_BLTMODE_COLOREXPAND) {
1040
1041 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1042 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1043 cirrus_bitblt_bgcol(s);
1044 else
1045 cirrus_bitblt_fgcol(s);
1046 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1047 } else {
1048 cirrus_bitblt_fgcol(s);
1049 cirrus_bitblt_bgcol(s);
1050 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1051 }
1052 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
1053 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
1054 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1055 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1056 cirrus_bitblt_bgcol(s);
1057 else
1058 cirrus_bitblt_fgcol(s);
1059 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1060 } else {
1061 cirrus_bitblt_fgcol(s);
1062 cirrus_bitblt_bgcol(s);
1063 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1064 }
1065 } else {
1066 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1067 }
1068 } else {
1069 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1070 if (s->cirrus_blt_pixelwidth > 2) {
1071 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1072 goto bitblt_ignore;
1073 }
1074 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1075 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1076 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1077 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1078 } else {
1079 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1080 }
1081 } else {
1082 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1083 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1084 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1085 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1086 } else {
1087 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1088 }
1089 }
1090 }
1091 // setup bitblt engine.
1092 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1093 if (!cirrus_bitblt_cputovideo(s))
1094 goto bitblt_ignore;
1095 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1096 if (!cirrus_bitblt_videotocpu(s))
1097 goto bitblt_ignore;
1098 } else {
1099 if (!cirrus_bitblt_videotovideo(s))
1100 goto bitblt_ignore;
1101 }
1102 }
1103 return;
1104 bitblt_ignore:;
1105 cirrus_bitblt_reset(s);
1106 }
1107
1108 static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1109 {
1110 unsigned old_value;
1111
1112 old_value = s->vga.gr[0x31];
1113 s->vga.gr[0x31] = reg_value;
1114
1115 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1116 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1117 cirrus_bitblt_reset(s);
1118 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1119 ((reg_value & CIRRUS_BLT_START) != 0)) {
1120 cirrus_bitblt_start(s);
1121 }
1122 }
1123
1124
1125 /***************************************
1126 *
1127 * basic parameters
1128 *
1129 ***************************************/
1130
1131 static void cirrus_get_offsets(VGACommonState *s1,
1132 uint32_t *pline_offset,
1133 uint32_t *pstart_addr,
1134 uint32_t *pline_compare)
1135 {
1136 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1137 uint32_t start_addr, line_offset, line_compare;
1138
1139 line_offset = s->vga.cr[0x13]
1140 | ((s->vga.cr[0x1b] & 0x10) << 4);
1141 line_offset <<= 3;
1142 *pline_offset = line_offset;
1143
1144 start_addr = (s->vga.cr[0x0c] << 8)
1145 | s->vga.cr[0x0d]
1146 | ((s->vga.cr[0x1b] & 0x01) << 16)
1147 | ((s->vga.cr[0x1b] & 0x0c) << 15)
1148 | ((s->vga.cr[0x1d] & 0x80) << 12);
1149 *pstart_addr = start_addr;
1150
1151 line_compare = s->vga.cr[0x18] |
1152 ((s->vga.cr[0x07] & 0x10) << 4) |
1153 ((s->vga.cr[0x09] & 0x40) << 3);
1154 *pline_compare = line_compare;
1155 }
1156
1157 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1158 {
1159 uint32_t ret = 16;
1160
1161 switch (s->cirrus_hidden_dac_data & 0xf) {
1162 case 0:
1163 ret = 15;
1164 break; /* Sierra HiColor */
1165 case 1:
1166 ret = 16;
1167 break; /* XGA HiColor */
1168 default:
1169 #ifdef DEBUG_CIRRUS
1170 printf("cirrus: invalid DAC value %x in 16bpp\n",
1171 (s->cirrus_hidden_dac_data & 0xf));
1172 #endif
1173 ret = 15; /* XXX */
1174 break;
1175 }
1176 return ret;
1177 }
1178
1179 static int cirrus_get_bpp(VGACommonState *s1)
1180 {
1181 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1182 uint32_t ret = 8;
1183
1184 if ((s->vga.sr[0x07] & 0x01) != 0) {
1185 /* Cirrus SVGA */
1186 switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1187 case CIRRUS_SR7_BPP_8:
1188 ret = 8;
1189 break;
1190 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1191 ret = cirrus_get_bpp16_depth(s);
1192 break;
1193 case CIRRUS_SR7_BPP_24:
1194 ret = 24;
1195 break;
1196 case CIRRUS_SR7_BPP_16:
1197 ret = cirrus_get_bpp16_depth(s);
1198 break;
1199 case CIRRUS_SR7_BPP_32:
1200 ret = 32;
1201 break;
1202 default:
1203 #ifdef DEBUG_CIRRUS
1204 printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
1205 #endif
1206 ret = 8;
1207 break;
1208 }
1209 } else {
1210 /* VGA */
1211 ret = 0;
1212 }
1213
1214 return ret;
1215 }
1216
1217 static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
1218 {
1219 int width, height;
1220
1221 width = (s->cr[0x01] + 1) * 8;
1222 height = s->cr[0x12] |
1223 ((s->cr[0x07] & 0x02) << 7) |
1224 ((s->cr[0x07] & 0x40) << 3);
1225 height = (height + 1);
1226 /* interlace support */
1227 if (s->cr[0x1a] & 0x01)
1228 height = height * 2;
1229 *pwidth = width;
1230 *pheight = height;
1231 }
1232
1233 /***************************************
1234 *
1235 * bank memory
1236 *
1237 ***************************************/
1238
1239 static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1240 {
1241 unsigned offset;
1242 unsigned limit;
1243
1244 if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */
1245 offset = s->vga.gr[0x09 + bank_index];
1246 else /* single bank */
1247 offset = s->vga.gr[0x09];
1248
1249 if ((s->vga.gr[0x0b] & 0x20) != 0)
1250 offset <<= 14;
1251 else
1252 offset <<= 12;
1253
1254 if (s->real_vram_size <= offset)
1255 limit = 0;
1256 else
1257 limit = s->real_vram_size - offset;
1258
1259 if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1260 if (limit > 0x8000) {
1261 offset += 0x8000;
1262 limit -= 0x8000;
1263 } else {
1264 limit = 0;
1265 }
1266 }
1267
1268 if (limit > 0) {
1269 s->cirrus_bank_base[bank_index] = offset;
1270 s->cirrus_bank_limit[bank_index] = limit;
1271 } else {
1272 s->cirrus_bank_base[bank_index] = 0;
1273 s->cirrus_bank_limit[bank_index] = 0;
1274 }
1275 }
1276
1277 /***************************************
1278 *
1279 * I/O access between 0x3c4-0x3c5
1280 *
1281 ***************************************/
1282
1283 static int cirrus_vga_read_sr(CirrusVGAState * s)
1284 {
1285 switch (s->vga.sr_index) {
1286 case 0x00: // Standard VGA
1287 case 0x01: // Standard VGA
1288 case 0x02: // Standard VGA
1289 case 0x03: // Standard VGA
1290 case 0x04: // Standard VGA
1291 return s->vga.sr[s->vga.sr_index];
1292 case 0x06: // Unlock Cirrus extensions
1293 return s->vga.sr[s->vga.sr_index];
1294 case 0x10:
1295 case 0x30:
1296 case 0x50:
1297 case 0x70: // Graphics Cursor X
1298 case 0x90:
1299 case 0xb0:
1300 case 0xd0:
1301 case 0xf0: // Graphics Cursor X
1302 return s->vga.sr[0x10];
1303 case 0x11:
1304 case 0x31:
1305 case 0x51:
1306 case 0x71: // Graphics Cursor Y
1307 case 0x91:
1308 case 0xb1:
1309 case 0xd1:
1310 case 0xf1: // Graphics Cursor Y
1311 return s->vga.sr[0x11];
1312 case 0x05: // ???
1313 case 0x07: // Extended Sequencer Mode
1314 case 0x08: // EEPROM Control
1315 case 0x09: // Scratch Register 0
1316 case 0x0a: // Scratch Register 1
1317 case 0x0b: // VCLK 0
1318 case 0x0c: // VCLK 1
1319 case 0x0d: // VCLK 2
1320 case 0x0e: // VCLK 3
1321 case 0x0f: // DRAM Control
1322 case 0x12: // Graphics Cursor Attribute
1323 case 0x13: // Graphics Cursor Pattern Address
1324 case 0x14: // Scratch Register 2
1325 case 0x15: // Scratch Register 3
1326 case 0x16: // Performance Tuning Register
1327 case 0x17: // Configuration Readback and Extended Control
1328 case 0x18: // Signature Generator Control
1329 case 0x19: // Signal Generator Result
1330 case 0x1a: // Signal Generator Result
1331 case 0x1b: // VCLK 0 Denominator & Post
1332 case 0x1c: // VCLK 1 Denominator & Post
1333 case 0x1d: // VCLK 2 Denominator & Post
1334 case 0x1e: // VCLK 3 Denominator & Post
1335 case 0x1f: // BIOS Write Enable and MCLK select
1336 #ifdef DEBUG_CIRRUS
1337 printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index);
1338 #endif
1339 return s->vga.sr[s->vga.sr_index];
1340 default:
1341 #ifdef DEBUG_CIRRUS
1342 printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
1343 #endif
1344 return 0xff;
1345 break;
1346 }
1347 }
1348
1349 static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
1350 {
1351 switch (s->vga.sr_index) {
1352 case 0x00: // Standard VGA
1353 case 0x01: // Standard VGA
1354 case 0x02: // Standard VGA
1355 case 0x03: // Standard VGA
1356 case 0x04: // Standard VGA
1357 s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
1358 if (s->vga.sr_index == 1)
1359 s->vga.update_retrace_info(&s->vga);
1360 break;
1361 case 0x06: // Unlock Cirrus extensions
1362 val &= 0x17;
1363 if (val == 0x12) {
1364 s->vga.sr[s->vga.sr_index] = 0x12;
1365 } else {
1366 s->vga.sr[s->vga.sr_index] = 0x0f;
1367 }
1368 break;
1369 case 0x10:
1370 case 0x30:
1371 case 0x50:
1372 case 0x70: // Graphics Cursor X
1373 case 0x90:
1374 case 0xb0:
1375 case 0xd0:
1376 case 0xf0: // Graphics Cursor X
1377 s->vga.sr[0x10] = val;
1378 s->vga.hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5);
1379 break;
1380 case 0x11:
1381 case 0x31:
1382 case 0x51:
1383 case 0x71: // Graphics Cursor Y
1384 case 0x91:
1385 case 0xb1:
1386 case 0xd1:
1387 case 0xf1: // Graphics Cursor Y
1388 s->vga.sr[0x11] = val;
1389 s->vga.hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5);
1390 break;
1391 case 0x07: // Extended Sequencer Mode
1392 cirrus_update_memory_access(s);
1393 case 0x08: // EEPROM Control
1394 case 0x09: // Scratch Register 0
1395 case 0x0a: // Scratch Register 1
1396 case 0x0b: // VCLK 0
1397 case 0x0c: // VCLK 1
1398 case 0x0d: // VCLK 2
1399 case 0x0e: // VCLK 3
1400 case 0x0f: // DRAM Control
1401 case 0x13: // Graphics Cursor Pattern Address
1402 case 0x14: // Scratch Register 2
1403 case 0x15: // Scratch Register 3
1404 case 0x16: // Performance Tuning Register
1405 case 0x18: // Signature Generator Control
1406 case 0x19: // Signature Generator Result
1407 case 0x1a: // Signature Generator Result
1408 case 0x1b: // VCLK 0 Denominator & Post
1409 case 0x1c: // VCLK 1 Denominator & Post
1410 case 0x1d: // VCLK 2 Denominator & Post
1411 case 0x1e: // VCLK 3 Denominator & Post
1412 case 0x1f: // BIOS Write Enable and MCLK select
1413 s->vga.sr[s->vga.sr_index] = val;
1414 #ifdef DEBUG_CIRRUS
1415 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1416 s->vga.sr_index, val);
1417 #endif
1418 break;
1419 case 0x12: // Graphics Cursor Attribute
1420 s->vga.sr[0x12] = val;
1421 s->vga.force_shadow = !!(val & CIRRUS_CURSOR_SHOW);
1422 #ifdef DEBUG_CIRRUS
1423 printf("cirrus: cursor ctl SR12=%02x (force shadow: %d)\n",
1424 val, s->vga.force_shadow);
1425 #endif
1426 break;
1427 case 0x17: // Configuration Readback and Extended Control
1428 s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
1429 | (val & 0xc7);
1430 cirrus_update_memory_access(s);
1431 break;
1432 default:
1433 #ifdef DEBUG_CIRRUS
1434 printf("cirrus: outport sr_index %02x, sr_value %02x\n",
1435 s->vga.sr_index, val);
1436 #endif
1437 break;
1438 }
1439 }
1440
1441 /***************************************
1442 *
1443 * I/O access at 0x3c6
1444 *
1445 ***************************************/
1446
1447 static int cirrus_read_hidden_dac(CirrusVGAState * s)
1448 {
1449 if (++s->cirrus_hidden_dac_lockindex == 5) {
1450 s->cirrus_hidden_dac_lockindex = 0;
1451 return s->cirrus_hidden_dac_data;
1452 }
1453 return 0xff;
1454 }
1455
1456 static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1457 {
1458 if (s->cirrus_hidden_dac_lockindex == 4) {
1459 s->cirrus_hidden_dac_data = reg_value;
1460 #if defined(DEBUG_CIRRUS)
1461 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1462 #endif
1463 }
1464 s->cirrus_hidden_dac_lockindex = 0;
1465 }
1466
1467 /***************************************
1468 *
1469 * I/O access at 0x3c9
1470 *
1471 ***************************************/
1472
1473 static int cirrus_vga_read_palette(CirrusVGAState * s)
1474 {
1475 int val;
1476
1477 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1478 val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
1479 s->vga.dac_sub_index];
1480 } else {
1481 val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
1482 }
1483 if (++s->vga.dac_sub_index == 3) {
1484 s->vga.dac_sub_index = 0;
1485 s->vga.dac_read_index++;
1486 }
1487 return val;
1488 }
1489
1490 static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value)
1491 {
1492 s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
1493 if (++s->vga.dac_sub_index == 3) {
1494 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1495 memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
1496 s->vga.dac_cache, 3);
1497 } else {
1498 memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3);
1499 }
1500 /* XXX update cursor */
1501 s->vga.dac_sub_index = 0;
1502 s->vga.dac_write_index++;
1503 }
1504 }
1505
1506 /***************************************
1507 *
1508 * I/O access between 0x3ce-0x3cf
1509 *
1510 ***************************************/
1511
1512 static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
1513 {
1514 switch (reg_index) {
1515 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1516 return s->cirrus_shadow_gr0;
1517 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1518 return s->cirrus_shadow_gr1;
1519 case 0x02: // Standard VGA
1520 case 0x03: // Standard VGA
1521 case 0x04: // Standard VGA
1522 case 0x06: // Standard VGA
1523 case 0x07: // Standard VGA
1524 case 0x08: // Standard VGA
1525 return s->vga.gr[s->vga.gr_index];
1526 case 0x05: // Standard VGA, Cirrus extended mode
1527 default:
1528 break;
1529 }
1530
1531 if (reg_index < 0x3a) {
1532 return s->vga.gr[reg_index];
1533 } else {
1534 #ifdef DEBUG_CIRRUS
1535 printf("cirrus: inport gr_index %02x\n", reg_index);
1536 #endif
1537 return 0xff;
1538 }
1539 }
1540
1541 static void
1542 cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1543 {
1544 #if defined(DEBUG_BITBLT) && 0
1545 printf("gr%02x: %02x\n", reg_index, reg_value);
1546 #endif
1547 switch (reg_index) {
1548 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1549 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1550 s->cirrus_shadow_gr0 = reg_value;
1551 break;
1552 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1553 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1554 s->cirrus_shadow_gr1 = reg_value;
1555 break;
1556 case 0x02: // Standard VGA
1557 case 0x03: // Standard VGA
1558 case 0x04: // Standard VGA
1559 case 0x06: // Standard VGA
1560 case 0x07: // Standard VGA
1561 case 0x08: // Standard VGA
1562 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1563 break;
1564 case 0x05: // Standard VGA, Cirrus extended mode
1565 s->vga.gr[reg_index] = reg_value & 0x7f;
1566 cirrus_update_memory_access(s);
1567 break;
1568 case 0x09: // bank offset #0
1569 case 0x0A: // bank offset #1
1570 s->vga.gr[reg_index] = reg_value;
1571 cirrus_update_bank_ptr(s, 0);
1572 cirrus_update_bank_ptr(s, 1);
1573 cirrus_update_memory_access(s);
1574 break;
1575 case 0x0B:
1576 s->vga.gr[reg_index] = reg_value;
1577 cirrus_update_bank_ptr(s, 0);
1578 cirrus_update_bank_ptr(s, 1);
1579 cirrus_update_memory_access(s);
1580 break;
1581 case 0x10: // BGCOLOR 0x0000ff00
1582 case 0x11: // FGCOLOR 0x0000ff00
1583 case 0x12: // BGCOLOR 0x00ff0000
1584 case 0x13: // FGCOLOR 0x00ff0000
1585 case 0x14: // BGCOLOR 0xff000000
1586 case 0x15: // FGCOLOR 0xff000000
1587 case 0x20: // BLT WIDTH 0x0000ff
1588 case 0x22: // BLT HEIGHT 0x0000ff
1589 case 0x24: // BLT DEST PITCH 0x0000ff
1590 case 0x26: // BLT SRC PITCH 0x0000ff
1591 case 0x28: // BLT DEST ADDR 0x0000ff
1592 case 0x29: // BLT DEST ADDR 0x00ff00
1593 case 0x2c: // BLT SRC ADDR 0x0000ff
1594 case 0x2d: // BLT SRC ADDR 0x00ff00
1595 case 0x2f: // BLT WRITEMASK
1596 case 0x30: // BLT MODE
1597 case 0x32: // RASTER OP
1598 case 0x33: // BLT MODEEXT
1599 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1600 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1601 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1602 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1603 s->vga.gr[reg_index] = reg_value;
1604 break;
1605 case 0x21: // BLT WIDTH 0x001f00
1606 case 0x23: // BLT HEIGHT 0x001f00
1607 case 0x25: // BLT DEST PITCH 0x001f00
1608 case 0x27: // BLT SRC PITCH 0x001f00
1609 s->vga.gr[reg_index] = reg_value & 0x1f;
1610 break;
1611 case 0x2a: // BLT DEST ADDR 0x3f0000
1612 s->vga.gr[reg_index] = reg_value & 0x3f;
1613 /* if auto start mode, starts bit blt now */
1614 if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1615 cirrus_bitblt_start(s);
1616 }
1617 break;
1618 case 0x2e: // BLT SRC ADDR 0x3f0000
1619 s->vga.gr[reg_index] = reg_value & 0x3f;
1620 break;
1621 case 0x31: // BLT STATUS/START
1622 cirrus_write_bitblt(s, reg_value);
1623 break;
1624 default:
1625 #ifdef DEBUG_CIRRUS
1626 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1627 reg_value);
1628 #endif
1629 break;
1630 }
1631 }
1632
1633 /***************************************
1634 *
1635 * I/O access between 0x3d4-0x3d5
1636 *
1637 ***************************************/
1638
1639 static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index)
1640 {
1641 switch (reg_index) {
1642 case 0x00: // Standard VGA
1643 case 0x01: // Standard VGA
1644 case 0x02: // Standard VGA
1645 case 0x03: // Standard VGA
1646 case 0x04: // Standard VGA
1647 case 0x05: // Standard VGA
1648 case 0x06: // Standard VGA
1649 case 0x07: // Standard VGA
1650 case 0x08: // Standard VGA
1651 case 0x09: // Standard VGA
1652 case 0x0a: // Standard VGA
1653 case 0x0b: // Standard VGA
1654 case 0x0c: // Standard VGA
1655 case 0x0d: // Standard VGA
1656 case 0x0e: // Standard VGA
1657 case 0x0f: // Standard VGA
1658 case 0x10: // Standard VGA
1659 case 0x11: // Standard VGA
1660 case 0x12: // Standard VGA
1661 case 0x13: // Standard VGA
1662 case 0x14: // Standard VGA
1663 case 0x15: // Standard VGA
1664 case 0x16: // Standard VGA
1665 case 0x17: // Standard VGA
1666 case 0x18: // Standard VGA
1667 return s->vga.cr[s->vga.cr_index];
1668 case 0x24: // Attribute Controller Toggle Readback (R)
1669 return (s->vga.ar_flip_flop << 7);
1670 case 0x19: // Interlace End
1671 case 0x1a: // Miscellaneous Control
1672 case 0x1b: // Extended Display Control
1673 case 0x1c: // Sync Adjust and Genlock
1674 case 0x1d: // Overlay Extended Control
1675 case 0x22: // Graphics Data Latches Readback (R)
1676 case 0x25: // Part Status
1677 case 0x27: // Part ID (R)
1678 return s->vga.cr[s->vga.cr_index];
1679 case 0x26: // Attribute Controller Index Readback (R)
1680 return s->vga.ar_index & 0x3f;
1681 break;
1682 default:
1683 #ifdef DEBUG_CIRRUS
1684 printf("cirrus: inport cr_index %02x\n", reg_index);
1685 #endif
1686 return 0xff;
1687 }
1688 }
1689
1690 static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value)
1691 {
1692 switch (s->vga.cr_index) {
1693 case 0x00: // Standard VGA
1694 case 0x01: // Standard VGA
1695 case 0x02: // Standard VGA
1696 case 0x03: // Standard VGA
1697 case 0x04: // Standard VGA
1698 case 0x05: // Standard VGA
1699 case 0x06: // Standard VGA
1700 case 0x07: // Standard VGA
1701 case 0x08: // Standard VGA
1702 case 0x09: // Standard VGA
1703 case 0x0a: // Standard VGA
1704 case 0x0b: // Standard VGA
1705 case 0x0c: // Standard VGA
1706 case 0x0d: // Standard VGA
1707 case 0x0e: // Standard VGA
1708 case 0x0f: // Standard VGA
1709 case 0x10: // Standard VGA
1710 case 0x11: // Standard VGA
1711 case 0x12: // Standard VGA
1712 case 0x13: // Standard VGA
1713 case 0x14: // Standard VGA
1714 case 0x15: // Standard VGA
1715 case 0x16: // Standard VGA
1716 case 0x17: // Standard VGA
1717 case 0x18: // Standard VGA
1718 /* handle CR0-7 protection */
1719 if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
1720 /* can always write bit 4 of CR7 */
1721 if (s->vga.cr_index == 7)
1722 s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10);
1723 return;
1724 }
1725 s->vga.cr[s->vga.cr_index] = reg_value;
1726 switch(s->vga.cr_index) {
1727 case 0x00:
1728 case 0x04:
1729 case 0x05:
1730 case 0x06:
1731 case 0x07:
1732 case 0x11:
1733 case 0x17:
1734 s->vga.update_retrace_info(&s->vga);
1735 break;
1736 }
1737 break;
1738 case 0x19: // Interlace End
1739 case 0x1a: // Miscellaneous Control
1740 case 0x1b: // Extended Display Control
1741 case 0x1c: // Sync Adjust and Genlock
1742 case 0x1d: // Overlay Extended Control
1743 s->vga.cr[s->vga.cr_index] = reg_value;
1744 #ifdef DEBUG_CIRRUS
1745 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1746 s->vga.cr_index, reg_value);
1747 #endif
1748 break;
1749 case 0x22: // Graphics Data Latches Readback (R)
1750 case 0x24: // Attribute Controller Toggle Readback (R)
1751 case 0x26: // Attribute Controller Index Readback (R)
1752 case 0x27: // Part ID (R)
1753 break;
1754 case 0x25: // Part Status
1755 default:
1756 #ifdef DEBUG_CIRRUS
1757 printf("cirrus: outport cr_index %02x, cr_value %02x\n",
1758 s->vga.cr_index, reg_value);
1759 #endif
1760 break;
1761 }
1762 }
1763
1764 /***************************************
1765 *
1766 * memory-mapped I/O (bitblt)
1767 *
1768 ***************************************/
1769
1770 static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1771 {
1772 int value = 0xff;
1773
1774 switch (address) {
1775 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1776 value = cirrus_vga_read_gr(s, 0x00);
1777 break;
1778 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1779 value = cirrus_vga_read_gr(s, 0x10);
1780 break;
1781 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1782 value = cirrus_vga_read_gr(s, 0x12);
1783 break;
1784 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1785 value = cirrus_vga_read_gr(s, 0x14);
1786 break;
1787 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1788 value = cirrus_vga_read_gr(s, 0x01);
1789 break;
1790 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1791 value = cirrus_vga_read_gr(s, 0x11);
1792 break;
1793 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1794 value = cirrus_vga_read_gr(s, 0x13);
1795 break;
1796 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1797 value = cirrus_vga_read_gr(s, 0x15);
1798 break;
1799 case (CIRRUS_MMIO_BLTWIDTH + 0):
1800 value = cirrus_vga_read_gr(s, 0x20);
1801 break;
1802 case (CIRRUS_MMIO_BLTWIDTH + 1):
1803 value = cirrus_vga_read_gr(s, 0x21);
1804 break;
1805 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1806 value = cirrus_vga_read_gr(s, 0x22);
1807 break;
1808 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1809 value = cirrus_vga_read_gr(s, 0x23);
1810 break;
1811 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1812 value = cirrus_vga_read_gr(s, 0x24);
1813 break;
1814 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1815 value = cirrus_vga_read_gr(s, 0x25);
1816 break;
1817 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1818 value = cirrus_vga_read_gr(s, 0x26);
1819 break;
1820 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1821 value = cirrus_vga_read_gr(s, 0x27);
1822 break;
1823 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1824 value = cirrus_vga_read_gr(s, 0x28);
1825 break;
1826 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1827 value = cirrus_vga_read_gr(s, 0x29);
1828 break;
1829 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1830 value = cirrus_vga_read_gr(s, 0x2a);
1831 break;
1832 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1833 value = cirrus_vga_read_gr(s, 0x2c);
1834 break;
1835 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1836 value = cirrus_vga_read_gr(s, 0x2d);
1837 break;
1838 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1839 value = cirrus_vga_read_gr(s, 0x2e);
1840 break;
1841 case CIRRUS_MMIO_BLTWRITEMASK:
1842 value = cirrus_vga_read_gr(s, 0x2f);
1843 break;
1844 case CIRRUS_MMIO_BLTMODE:
1845 value = cirrus_vga_read_gr(s, 0x30);
1846 break;
1847 case CIRRUS_MMIO_BLTROP:
1848 value = cirrus_vga_read_gr(s, 0x32);
1849 break;
1850 case CIRRUS_MMIO_BLTMODEEXT:
1851 value = cirrus_vga_read_gr(s, 0x33);
1852 break;
1853 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1854 value = cirrus_vga_read_gr(s, 0x34);
1855 break;
1856 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1857 value = cirrus_vga_read_gr(s, 0x35);
1858 break;
1859 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1860 value = cirrus_vga_read_gr(s, 0x38);
1861 break;
1862 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1863 value = cirrus_vga_read_gr(s, 0x39);
1864 break;
1865 case CIRRUS_MMIO_BLTSTATUS:
1866 value = cirrus_vga_read_gr(s, 0x31);
1867 break;
1868 default:
1869 #ifdef DEBUG_CIRRUS
1870 printf("cirrus: mmio read - address 0x%04x\n", address);
1871 #endif
1872 break;
1873 }
1874
1875 trace_vga_cirrus_write_blt(address, value);
1876 return (uint8_t) value;
1877 }
1878
1879 static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1880 uint8_t value)
1881 {
1882 trace_vga_cirrus_write_blt(address, value);
1883 switch (address) {
1884 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1885 cirrus_vga_write_gr(s, 0x00, value);
1886 break;
1887 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1888 cirrus_vga_write_gr(s, 0x10, value);
1889 break;
1890 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1891 cirrus_vga_write_gr(s, 0x12, value);
1892 break;
1893 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1894 cirrus_vga_write_gr(s, 0x14, value);
1895 break;
1896 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1897 cirrus_vga_write_gr(s, 0x01, value);
1898 break;
1899 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1900 cirrus_vga_write_gr(s, 0x11, value);
1901 break;
1902 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1903 cirrus_vga_write_gr(s, 0x13, value);
1904 break;
1905 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1906 cirrus_vga_write_gr(s, 0x15, value);
1907 break;
1908 case (CIRRUS_MMIO_BLTWIDTH + 0):
1909 cirrus_vga_write_gr(s, 0x20, value);
1910 break;
1911 case (CIRRUS_MMIO_BLTWIDTH + 1):
1912 cirrus_vga_write_gr(s, 0x21, value);
1913 break;
1914 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1915 cirrus_vga_write_gr(s, 0x22, value);
1916 break;
1917 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1918 cirrus_vga_write_gr(s, 0x23, value);
1919 break;
1920 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1921 cirrus_vga_write_gr(s, 0x24, value);
1922 break;
1923 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1924 cirrus_vga_write_gr(s, 0x25, value);
1925 break;
1926 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1927 cirrus_vga_write_gr(s, 0x26, value);
1928 break;
1929 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1930 cirrus_vga_write_gr(s, 0x27, value);
1931 break;
1932 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1933 cirrus_vga_write_gr(s, 0x28, value);
1934 break;
1935 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1936 cirrus_vga_write_gr(s, 0x29, value);
1937 break;
1938 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1939 cirrus_vga_write_gr(s, 0x2a, value);
1940 break;
1941 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1942 /* ignored */
1943 break;
1944 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1945 cirrus_vga_write_gr(s, 0x2c, value);
1946 break;
1947 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1948 cirrus_vga_write_gr(s, 0x2d, value);
1949 break;
1950 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1951 cirrus_vga_write_gr(s, 0x2e, value);
1952 break;
1953 case CIRRUS_MMIO_BLTWRITEMASK:
1954 cirrus_vga_write_gr(s, 0x2f, value);
1955 break;
1956 case CIRRUS_MMIO_BLTMODE:
1957 cirrus_vga_write_gr(s, 0x30, value);
1958 break;
1959 case CIRRUS_MMIO_BLTROP:
1960 cirrus_vga_write_gr(s, 0x32, value);
1961 break;
1962 case CIRRUS_MMIO_BLTMODEEXT:
1963 cirrus_vga_write_gr(s, 0x33, value);
1964 break;
1965 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1966 cirrus_vga_write_gr(s, 0x34, value);
1967 break;
1968 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1969 cirrus_vga_write_gr(s, 0x35, value);
1970 break;
1971 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1972 cirrus_vga_write_gr(s, 0x38, value);
1973 break;
1974 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1975 cirrus_vga_write_gr(s, 0x39, value);
1976 break;
1977 case CIRRUS_MMIO_BLTSTATUS:
1978 cirrus_vga_write_gr(s, 0x31, value);
1979 break;
1980 default:
1981 #ifdef DEBUG_CIRRUS
1982 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1983 address, value);
1984 #endif
1985 break;
1986 }
1987 }
1988
1989 /***************************************
1990 *
1991 * write mode 4/5
1992 *
1993 ***************************************/
1994
1995 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1996 unsigned mode,
1997 unsigned offset,
1998 uint32_t mem_value)
1999 {
2000 int x;
2001 unsigned val = mem_value;
2002 uint8_t *dst;
2003
2004 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
2005 for (x = 0; x < 8; x++) {
2006 if (val & 0x80) {
2007 *dst = s->cirrus_shadow_gr1;
2008 } else if (mode == 5) {
2009 *dst = s->cirrus_shadow_gr0;
2010 }
2011 val <<= 1;
2012 dst++;
2013 }
2014 memory_region_set_dirty(&s->vga.vram, offset, 8);
2015 }
2016
2017 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
2018 unsigned mode,
2019 unsigned offset,
2020 uint32_t mem_value)
2021 {
2022 int x;
2023 unsigned val = mem_value;
2024 uint8_t *dst;
2025
2026 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
2027 for (x = 0; x < 8; x++) {
2028 if (val & 0x80) {
2029 *dst = s->cirrus_shadow_gr1;
2030 *(dst + 1) = s->vga.gr[0x11];
2031 } else if (mode == 5) {
2032 *dst = s->cirrus_shadow_gr0;
2033 *(dst + 1) = s->vga.gr[0x10];
2034 }
2035 val <<= 1;
2036 dst += 2;
2037 }
2038 memory_region_set_dirty(&s->vga.vram, offset, 16);
2039 }
2040
2041 /***************************************
2042 *
2043 * memory access between 0xa0000-0xbffff
2044 *
2045 ***************************************/
2046
2047 static uint64_t cirrus_vga_mem_read(void *opaque,
2048 hwaddr addr,
2049 uint32_t size)
2050 {
2051 CirrusVGAState *s = opaque;
2052 unsigned bank_index;
2053 unsigned bank_offset;
2054 uint32_t val;
2055
2056 if ((s->vga.sr[0x07] & 0x01) == 0) {
2057 return vga_mem_readb(&s->vga, addr);
2058 }
2059
2060 if (addr < 0x10000) {
2061 /* XXX handle bitblt */
2062 /* video memory */
2063 bank_index = addr >> 15;
2064 bank_offset = addr & 0x7fff;
2065 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2066 bank_offset += s->cirrus_bank_base[bank_index];
2067 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2068 bank_offset <<= 4;
2069 } else if (s->vga.gr[0x0B] & 0x02) {
2070 bank_offset <<= 3;
2071 }
2072 bank_offset &= s->cirrus_addr_mask;
2073 val = *(s->vga.vram_ptr + bank_offset);
2074 } else
2075 val = 0xff;
2076 } else if (addr >= 0x18000 && addr < 0x18100) {
2077 /* memory-mapped I/O */
2078 val = 0xff;
2079 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
2080 val = cirrus_mmio_blt_read(s, addr & 0xff);
2081 }
2082 } else {
2083 val = 0xff;
2084 #ifdef DEBUG_CIRRUS
2085 printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr);
2086 #endif
2087 }
2088 return val;
2089 }
2090
2091 static void cirrus_vga_mem_write(void *opaque,
2092 hwaddr addr,
2093 uint64_t mem_value,
2094 uint32_t size)
2095 {
2096 CirrusVGAState *s = opaque;
2097 unsigned bank_index;
2098 unsigned bank_offset;
2099 unsigned mode;
2100
2101 if ((s->vga.sr[0x07] & 0x01) == 0) {
2102 vga_mem_writeb(&s->vga, addr, mem_value);
2103 return;
2104 }
2105
2106 if (addr < 0x10000) {
2107 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2108 /* bitblt */
2109 *s->cirrus_srcptr++ = (uint8_t) mem_value;
2110 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2111 cirrus_bitblt_cputovideo_next(s);
2112 }
2113 } else {
2114 /* video memory */
2115 bank_index = addr >> 15;
2116 bank_offset = addr & 0x7fff;
2117 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2118 bank_offset += s->cirrus_bank_base[bank_index];
2119 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2120 bank_offset <<= 4;
2121 } else if (s->vga.gr[0x0B] & 0x02) {
2122 bank_offset <<= 3;
2123 }
2124 bank_offset &= s->cirrus_addr_mask;
2125 mode = s->vga.gr[0x05] & 0x7;
2126 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2127 *(s->vga.vram_ptr + bank_offset) = mem_value;
2128 memory_region_set_dirty(&s->vga.vram, bank_offset,
2129 sizeof(mem_value));
2130 } else {
2131 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2132 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2133 bank_offset,
2134 mem_value);
2135 } else {
2136 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2137 bank_offset,
2138 mem_value);
2139 }
2140 }
2141 }
2142 }
2143 } else if (addr >= 0x18000 && addr < 0x18100) {
2144 /* memory-mapped I/O */
2145 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
2146 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2147 }
2148 } else {
2149 #ifdef DEBUG_CIRRUS
2150 printf("cirrus: mem_writeb " TARGET_FMT_plx " value 0x%02" PRIu64 "\n", addr,
2151 mem_value);
2152 #endif
2153 }
2154 }
2155
2156 static const MemoryRegionOps cirrus_vga_mem_ops = {
2157 .read = cirrus_vga_mem_read,
2158 .write = cirrus_vga_mem_write,
2159 .endianness = DEVICE_LITTLE_ENDIAN,
2160 .impl = {
2161 .min_access_size = 1,
2162 .max_access_size = 1,
2163 },
2164 };
2165
2166 /***************************************
2167 *
2168 * hardware cursor
2169 *
2170 ***************************************/
2171
2172 static inline void invalidate_cursor1(CirrusVGAState *s)
2173 {
2174 if (s->last_hw_cursor_size) {
2175 vga_invalidate_scanlines(&s->vga,
2176 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2177 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2178 }
2179 }
2180
2181 static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2182 {
2183 const uint8_t *src;
2184 uint32_t content;
2185 int y, y_min, y_max;
2186
2187 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2188 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2189 src += (s->vga.sr[0x13] & 0x3c) * 256;
2190 y_min = 64;
2191 y_max = -1;
2192 for(y = 0; y < 64; y++) {
2193 content = ((uint32_t *)src)[0] |
2194 ((uint32_t *)src)[1] |
2195 ((uint32_t *)src)[2] |
2196 ((uint32_t *)src)[3];
2197 if (content) {
2198 if (y < y_min)
2199 y_min = y;
2200 if (y > y_max)
2201 y_max = y;
2202 }
2203 src += 16;
2204 }
2205 } else {
2206 src += (s->vga.sr[0x13] & 0x3f) * 256;
2207 y_min = 32;
2208 y_max = -1;
2209 for(y = 0; y < 32; y++) {
2210 content = ((uint32_t *)src)[0] |
2211 ((uint32_t *)(src + 128))[0];
2212 if (content) {
2213 if (y < y_min)
2214 y_min = y;
2215 if (y > y_max)
2216 y_max = y;
2217 }
2218 src += 4;
2219 }
2220 }
2221 if (y_min > y_max) {
2222 s->last_hw_cursor_y_start = 0;
2223 s->last_hw_cursor_y_end = 0;
2224 } else {
2225 s->last_hw_cursor_y_start = y_min;
2226 s->last_hw_cursor_y_end = y_max + 1;
2227 }
2228 }
2229
2230 /* NOTE: we do not currently handle the cursor bitmap change, so we
2231 update the cursor only if it moves. */
2232 static void cirrus_cursor_invalidate(VGACommonState *s1)
2233 {
2234 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2235 int size;
2236
2237 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
2238 size = 0;
2239 } else {
2240 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
2241 size = 64;
2242 else
2243 size = 32;
2244 }
2245 /* invalidate last cursor and new cursor if any change */
2246 if (s->last_hw_cursor_size != size ||
2247 s->last_hw_cursor_x != s->vga.hw_cursor_x ||
2248 s->last_hw_cursor_y != s->vga.hw_cursor_y) {
2249
2250 invalidate_cursor1(s);
2251
2252 s->last_hw_cursor_size = size;
2253 s->last_hw_cursor_x = s->vga.hw_cursor_x;
2254 s->last_hw_cursor_y = s->vga.hw_cursor_y;
2255 /* compute the real cursor min and max y */
2256 cirrus_cursor_compute_yrange(s);
2257 invalidate_cursor1(s);
2258 }
2259 }
2260
2261 static void vga_draw_cursor_line(uint8_t *d1,
2262 const uint8_t *src1,
2263 int poffset, int w,
2264 unsigned int color0,
2265 unsigned int color1,
2266 unsigned int color_xor)
2267 {
2268 const uint8_t *plane0, *plane1;
2269 int x, b0, b1;
2270 uint8_t *d;
2271
2272 d = d1;
2273 plane0 = src1;
2274 plane1 = src1 + poffset;
2275 for (x = 0; x < w; x++) {
2276 b0 = (plane0[x >> 3] >> (7 - (x & 7))) & 1;
2277 b1 = (plane1[x >> 3] >> (7 - (x & 7))) & 1;
2278 switch (b0 | (b1 << 1)) {
2279 case 0:
2280 break;
2281 case 1:
2282 ((uint32_t *)d)[0] ^= color_xor;
2283 break;
2284 case 2:
2285 ((uint32_t *)d)[0] = color0;
2286 break;
2287 case 3:
2288 ((uint32_t *)d)[0] = color1;
2289 break;
2290 }
2291 d += 4;
2292 }
2293 }
2294
2295 static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
2296 {
2297 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2298 int w, h, x1, x2, poffset;
2299 unsigned int color0, color1;
2300 const uint8_t *palette, *src;
2301 uint32_t content;
2302
2303 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
2304 return;
2305 /* fast test to see if the cursor intersects with the scan line */
2306 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2307 h = 64;
2308 } else {
2309 h = 32;
2310 }
2311 if (scr_y < s->vga.hw_cursor_y ||
2312 scr_y >= (s->vga.hw_cursor_y + h)) {
2313 return;
2314 }
2315
2316 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2317 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2318 src += (s->vga.sr[0x13] & 0x3c) * 256;
2319 src += (scr_y - s->vga.hw_cursor_y) * 16;
2320 poffset = 8;
2321 content = ((uint32_t *)src)[0] |
2322 ((uint32_t *)src)[1] |
2323 ((uint32_t *)src)[2] |
2324 ((uint32_t *)src)[3];
2325 } else {
2326 src += (s->vga.sr[0x13] & 0x3f) * 256;
2327 src += (scr_y - s->vga.hw_cursor_y) * 4;
2328
2329
2330 poffset = 128;
2331 content = ((uint32_t *)src)[0] |
2332 ((uint32_t *)(src + 128))[0];
2333 }
2334 /* if nothing to draw, no need to continue */
2335 if (!content)
2336 return;
2337 w = h;
2338
2339 x1 = s->vga.hw_cursor_x;
2340 if (x1 >= s->vga.last_scr_width)
2341 return;
2342 x2 = s->vga.hw_cursor_x + w;
2343 if (x2 > s->vga.last_scr_width)
2344 x2 = s->vga.last_scr_width;
2345 w = x2 - x1;
2346 palette = s->cirrus_hidden_palette;
2347 color0 = rgb_to_pixel32(c6_to_8(palette[0x0 * 3]),
2348 c6_to_8(palette[0x0 * 3 + 1]),
2349 c6_to_8(palette[0x0 * 3 + 2]));
2350 color1 = rgb_to_pixel32(c6_to_8(palette[0xf * 3]),
2351 c6_to_8(palette[0xf * 3 + 1]),
2352 c6_to_8(palette[0xf * 3 + 2]));
2353 d1 += x1 * 4;
2354 vga_draw_cursor_line(d1, src, poffset, w, color0, color1, 0xffffff);
2355 }
2356
2357 /***************************************
2358 *
2359 * LFB memory access
2360 *
2361 ***************************************/
2362
2363 static uint64_t cirrus_linear_read(void *opaque, hwaddr addr,
2364 unsigned size)
2365 {
2366 CirrusVGAState *s = opaque;
2367 uint32_t ret;
2368
2369 addr &= s->cirrus_addr_mask;
2370
2371 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2372 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2373 /* memory-mapped I/O */
2374 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2375 } else if (0) {
2376 /* XXX handle bitblt */
2377 ret = 0xff;
2378 } else {
2379 /* video memory */
2380 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2381 addr <<= 4;
2382 } else if (s->vga.gr[0x0B] & 0x02) {
2383 addr <<= 3;
2384 }
2385 addr &= s->cirrus_addr_mask;
2386 ret = *(s->vga.vram_ptr + addr);
2387 }
2388
2389 return ret;
2390 }
2391
2392 static void cirrus_linear_write(void *opaque, hwaddr addr,
2393 uint64_t val, unsigned size)
2394 {
2395 CirrusVGAState *s = opaque;
2396 unsigned mode;
2397
2398 addr &= s->cirrus_addr_mask;
2399
2400 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2401 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2402 /* memory-mapped I/O */
2403 cirrus_mmio_blt_write(s, addr & 0xff, val);
2404 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2405 /* bitblt */
2406 *s->cirrus_srcptr++ = (uint8_t) val;
2407 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2408 cirrus_bitblt_cputovideo_next(s);
2409 }
2410 } else {
2411 /* video memory */
2412 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2413 addr <<= 4;
2414 } else if (s->vga.gr[0x0B] & 0x02) {
2415 addr <<= 3;
2416 }
2417 addr &= s->cirrus_addr_mask;
2418
2419 mode = s->vga.gr[0x05] & 0x7;
2420 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2421 *(s->vga.vram_ptr + addr) = (uint8_t) val;
2422 memory_region_set_dirty(&s->vga.vram, addr, 1);
2423 } else {
2424 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2425 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2426 } else {
2427 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2428 }
2429 }
2430 }
2431 }
2432
2433 /***************************************
2434 *
2435 * system to screen memory access
2436 *
2437 ***************************************/
2438
2439
2440 static uint64_t cirrus_linear_bitblt_read(void *opaque,
2441 hwaddr addr,
2442 unsigned size)
2443 {
2444 CirrusVGAState *s = opaque;
2445 uint32_t ret;
2446
2447 /* XXX handle bitblt */
2448 (void)s;
2449 ret = 0xff;
2450 return ret;
2451 }
2452
2453 static void cirrus_linear_bitblt_write(void *opaque,
2454 hwaddr addr,
2455 uint64_t val,
2456 unsigned size)
2457 {
2458 CirrusVGAState *s = opaque;
2459
2460 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2461 /* bitblt */
2462 *s->cirrus_srcptr++ = (uint8_t) val;
2463 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2464 cirrus_bitblt_cputovideo_next(s);
2465 }
2466 }
2467 }
2468
2469 static const MemoryRegionOps cirrus_linear_bitblt_io_ops = {
2470 .read = cirrus_linear_bitblt_read,
2471 .write = cirrus_linear_bitblt_write,
2472 .endianness = DEVICE_LITTLE_ENDIAN,
2473 .impl = {
2474 .min_access_size = 1,
2475 .max_access_size = 1,
2476 },
2477 };
2478
2479 static void map_linear_vram_bank(CirrusVGAState *s, unsigned bank)
2480 {
2481 MemoryRegion *mr = &s->cirrus_bank[bank];
2482 bool enabled = !(s->cirrus_srcptr != s->cirrus_srcptr_end)
2483 && !((s->vga.sr[0x07] & 0x01) == 0)
2484 && !((s->vga.gr[0x0B] & 0x14) == 0x14)
2485 && !(s->vga.gr[0x0B] & 0x02);
2486
2487 memory_region_set_enabled(mr, enabled);
2488 memory_region_set_alias_offset(mr, s->cirrus_bank_base[bank]);
2489 }
2490
2491 static void map_linear_vram(CirrusVGAState *s)
2492 {
2493 if (s->bustype == CIRRUS_BUSTYPE_PCI && !s->linear_vram) {
2494 s->linear_vram = true;
2495 memory_region_add_subregion_overlap(&s->pci_bar, 0, &s->vga.vram, 1);
2496 }
2497 map_linear_vram_bank(s, 0);
2498 map_linear_vram_bank(s, 1);
2499 }
2500
2501 static void unmap_linear_vram(CirrusVGAState *s)
2502 {
2503 if (s->bustype == CIRRUS_BUSTYPE_PCI && s->linear_vram) {
2504 s->linear_vram = false;
2505 memory_region_del_subregion(&s->pci_bar, &s->vga.vram);
2506 }
2507 memory_region_set_enabled(&s->cirrus_bank[0], false);
2508 memory_region_set_enabled(&s->cirrus_bank[1], false);
2509 }
2510
2511 /* Compute the memory access functions */
2512 static void cirrus_update_memory_access(CirrusVGAState *s)
2513 {
2514 unsigned mode;
2515
2516 memory_region_transaction_begin();
2517 if ((s->vga.sr[0x17] & 0x44) == 0x44) {
2518 goto generic_io;
2519 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2520 goto generic_io;
2521 } else {
2522 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2523 goto generic_io;
2524 } else if (s->vga.gr[0x0B] & 0x02) {
2525 goto generic_io;
2526 }
2527
2528 mode = s->vga.gr[0x05] & 0x7;
2529 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2530 map_linear_vram(s);
2531 } else {
2532 generic_io:
2533 unmap_linear_vram(s);
2534 }
2535 }
2536 memory_region_transaction_commit();
2537 }
2538
2539
2540 /* I/O ports */
2541
2542 static uint64_t cirrus_vga_ioport_read(void *opaque, hwaddr addr,
2543 unsigned size)
2544 {
2545 CirrusVGAState *c = opaque;
2546 VGACommonState *s = &c->vga;
2547 int val, index;
2548
2549 addr += 0x3b0;
2550
2551 if (vga_ioport_invalid(s, addr)) {
2552 val = 0xff;
2553 } else {
2554 switch (addr) {
2555 case 0x3c0:
2556 if (s->ar_flip_flop == 0) {
2557 val = s->ar_index;
2558 } else {
2559 val = 0;
2560 }
2561 break;
2562 case 0x3c1:
2563 index = s->ar_index & 0x1f;
2564 if (index < 21)
2565 val = s->ar[index];
2566 else
2567 val = 0;
2568 break;
2569 case 0x3c2:
2570 val = s->st00;
2571 break;
2572 case 0x3c4:
2573 val = s->sr_index;
2574 break;
2575 case 0x3c5:
2576 val = cirrus_vga_read_sr(c);
2577 break;
2578 #ifdef DEBUG_VGA_REG
2579 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2580 #endif
2581 break;
2582 case 0x3c6:
2583 val = cirrus_read_hidden_dac(c);
2584 break;
2585 case 0x3c7:
2586 val = s->dac_state;
2587 break;
2588 case 0x3c8:
2589 val = s->dac_write_index;
2590 c->cirrus_hidden_dac_lockindex = 0;
2591 break;
2592 case 0x3c9:
2593 val = cirrus_vga_read_palette(c);
2594 break;
2595 case 0x3ca:
2596 val = s->fcr;
2597 break;
2598 case 0x3cc:
2599 val = s->msr;
2600 break;
2601 case 0x3ce:
2602 val = s->gr_index;
2603 break;
2604 case 0x3cf:
2605 val = cirrus_vga_read_gr(c, s->gr_index);
2606 #ifdef DEBUG_VGA_REG
2607 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2608 #endif
2609 break;
2610 case 0x3b4:
2611 case 0x3d4:
2612 val = s->cr_index;
2613 break;
2614 case 0x3b5:
2615 case 0x3d5:
2616 val = cirrus_vga_read_cr(c, s->cr_index);
2617 #ifdef DEBUG_VGA_REG
2618 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2619 #endif
2620 break;
2621 case 0x3ba:
2622 case 0x3da:
2623 /* just toggle to fool polling */
2624 val = s->st01 = s->retrace(s);
2625 s->ar_flip_flop = 0;
2626 break;
2627 default:
2628 val = 0x00;
2629 break;
2630 }
2631 }
2632 trace_vga_cirrus_read_io(addr, val);
2633 return val;
2634 }
2635
2636 static void cirrus_vga_ioport_write(void *opaque, hwaddr addr, uint64_t val,
2637 unsigned size)
2638 {
2639 CirrusVGAState *c = opaque;
2640 VGACommonState *s = &c->vga;
2641 int index;
2642
2643 addr += 0x3b0;
2644
2645 /* check port range access depending on color/monochrome mode */
2646 if (vga_ioport_invalid(s, addr)) {
2647 return;
2648 }
2649 trace_vga_cirrus_write_io(addr, val);
2650
2651 switch (addr) {
2652 case 0x3c0:
2653 if (s->ar_flip_flop == 0) {
2654 val &= 0x3f;
2655 s->ar_index = val;
2656 } else {
2657 index = s->ar_index & 0x1f;
2658 switch (index) {
2659 case 0x00 ... 0x0f:
2660 s->ar[index] = val & 0x3f;
2661 break;
2662 case 0x10:
2663 s->ar[index] = val & ~0x10;
2664 break;
2665 case 0x11:
2666 s->ar[index] = val;
2667 break;
2668 case 0x12:
2669 s->ar[index] = val & ~0xc0;
2670 break;
2671 case 0x13:
2672 s->ar[index] = val & ~0xf0;
2673 break;
2674 case 0x14:
2675 s->ar[index] = val & ~0xf0;
2676 break;
2677 default:
2678 break;
2679 }
2680 }
2681 s->ar_flip_flop ^= 1;
2682 break;
2683 case 0x3c2:
2684 s->msr = val & ~0x10;
2685 s->update_retrace_info(s);
2686 break;
2687 case 0x3c4:
2688 s->sr_index = val;
2689 break;
2690 case 0x3c5:
2691 #ifdef DEBUG_VGA_REG
2692 printf("vga: write SR%x = 0x%02" PRIu64 "\n", s->sr_index, val);
2693 #endif
2694 cirrus_vga_write_sr(c, val);
2695 break;
2696 case 0x3c6:
2697 cirrus_write_hidden_dac(c, val);
2698 break;
2699 case 0x3c7:
2700 s->dac_read_index = val;
2701 s->dac_sub_index = 0;
2702 s->dac_state = 3;
2703 break;
2704 case 0x3c8:
2705 s->dac_write_index = val;
2706 s->dac_sub_index = 0;
2707 s->dac_state = 0;
2708 break;
2709 case 0x3c9:
2710 cirrus_vga_write_palette(c, val);
2711 break;
2712 case 0x3ce:
2713 s->gr_index = val;
2714 break;
2715 case 0x3cf:
2716 #ifdef DEBUG_VGA_REG
2717 printf("vga: write GR%x = 0x%02" PRIu64 "\n", s->gr_index, val);
2718 #endif
2719 cirrus_vga_write_gr(c, s->gr_index, val);
2720 break;
2721 case 0x3b4:
2722 case 0x3d4:
2723 s->cr_index = val;
2724 break;
2725 case 0x3b5:
2726 case 0x3d5:
2727 #ifdef DEBUG_VGA_REG
2728 printf("vga: write CR%x = 0x%02"PRIu64"\n", s->cr_index, val);
2729 #endif
2730 cirrus_vga_write_cr(c, val);
2731 break;
2732 case 0x3ba:
2733 case 0x3da:
2734 s->fcr = val & 0x10;
2735 break;
2736 }
2737 }
2738
2739 /***************************************
2740 *
2741 * memory-mapped I/O access
2742 *
2743 ***************************************/
2744
2745 static uint64_t cirrus_mmio_read(void *opaque, hwaddr addr,
2746 unsigned size)
2747 {
2748 CirrusVGAState *s = opaque;
2749
2750 if (addr >= 0x100) {
2751 return cirrus_mmio_blt_read(s, addr - 0x100);
2752 } else {
2753 return cirrus_vga_ioport_read(s, addr + 0x10, size);
2754 }
2755 }
2756
2757 static void cirrus_mmio_write(void *opaque, hwaddr addr,
2758 uint64_t val, unsigned size)
2759 {
2760 CirrusVGAState *s = opaque;
2761
2762 if (addr >= 0x100) {
2763 cirrus_mmio_blt_write(s, addr - 0x100, val);
2764 } else {
2765 cirrus_vga_ioport_write(s, addr + 0x10, val, size);
2766 }
2767 }
2768
2769 static const MemoryRegionOps cirrus_mmio_io_ops = {
2770 .read = cirrus_mmio_read,
2771 .write = cirrus_mmio_write,
2772 .endianness = DEVICE_LITTLE_ENDIAN,
2773 .impl = {
2774 .min_access_size = 1,
2775 .max_access_size = 1,
2776 },
2777 };
2778
2779 /* load/save state */
2780
2781 static int cirrus_post_load(void *opaque, int version_id)
2782 {
2783 CirrusVGAState *s = opaque;
2784
2785 s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
2786 s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
2787
2788 cirrus_update_memory_access(s);
2789 /* force refresh */
2790 s->vga.graphic_mode = -1;
2791 cirrus_update_bank_ptr(s, 0);
2792 cirrus_update_bank_ptr(s, 1);
2793 return 0;
2794 }
2795
2796 static const VMStateDescription vmstate_cirrus_vga = {
2797 .name = "cirrus_vga",
2798 .version_id = 2,
2799 .minimum_version_id = 1,
2800 .post_load = cirrus_post_load,
2801 .fields = (VMStateField[]) {
2802 VMSTATE_UINT32(vga.latch, CirrusVGAState),
2803 VMSTATE_UINT8(vga.sr_index, CirrusVGAState),
2804 VMSTATE_BUFFER(vga.sr, CirrusVGAState),
2805 VMSTATE_UINT8(vga.gr_index, CirrusVGAState),
2806 VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState),
2807 VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState),
2808 VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2),
2809 VMSTATE_UINT8(vga.ar_index, CirrusVGAState),
2810 VMSTATE_BUFFER(vga.ar, CirrusVGAState),
2811 VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState),
2812 VMSTATE_UINT8(vga.cr_index, CirrusVGAState),
2813 VMSTATE_BUFFER(vga.cr, CirrusVGAState),
2814 VMSTATE_UINT8(vga.msr, CirrusVGAState),
2815 VMSTATE_UINT8(vga.fcr, CirrusVGAState),
2816 VMSTATE_UINT8(vga.st00, CirrusVGAState),
2817 VMSTATE_UINT8(vga.st01, CirrusVGAState),
2818 VMSTATE_UINT8(vga.dac_state, CirrusVGAState),
2819 VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState),
2820 VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState),
2821 VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState),
2822 VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState),
2823 VMSTATE_BUFFER(vga.palette, CirrusVGAState),
2824 VMSTATE_INT32(vga.bank_offset, CirrusVGAState),
2825 VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState),
2826 VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState),
2827 VMSTATE_UINT32(vga.hw_cursor_x, CirrusVGAState),
2828 VMSTATE_UINT32(vga.hw_cursor_y, CirrusVGAState),
2829 /* XXX: we do not save the bitblt state - we assume we do not save
2830 the state when the blitter is active */
2831 VMSTATE_END_OF_LIST()
2832 }
2833 };
2834
2835 static const VMStateDescription vmstate_pci_cirrus_vga = {
2836 .name = "cirrus_vga",
2837 .version_id = 2,
2838 .minimum_version_id = 2,
2839 .fields = (VMStateField[]) {
2840 VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState),
2841 VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
2842 vmstate_cirrus_vga, CirrusVGAState),
2843 VMSTATE_END_OF_LIST()
2844 }
2845 };
2846
2847 /***************************************
2848 *
2849 * initialize
2850 *
2851 ***************************************/
2852
2853 static void cirrus_reset(void *opaque)
2854 {
2855 CirrusVGAState *s = opaque;
2856
2857 vga_common_reset(&s->vga);
2858 unmap_linear_vram(s);
2859 s->vga.sr[0x06] = 0x0f;
2860 if (s->device_id == CIRRUS_ID_CLGD5446) {
2861 /* 4MB 64 bit memory config, always PCI */
2862 s->vga.sr[0x1F] = 0x2d; // MemClock
2863 s->vga.gr[0x18] = 0x0f; // fastest memory configuration
2864 s->vga.sr[0x0f] = 0x98;
2865 s->vga.sr[0x17] = 0x20;
2866 s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
2867 } else {
2868 s->vga.sr[0x1F] = 0x22; // MemClock
2869 s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
2870 s->vga.sr[0x17] = s->bustype;
2871 s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
2872 }
2873 s->vga.cr[0x27] = s->device_id;
2874
2875 s->cirrus_hidden_dac_lockindex = 5;
2876 s->cirrus_hidden_dac_data = 0;
2877 }
2878
2879 static const MemoryRegionOps cirrus_linear_io_ops = {
2880 .read = cirrus_linear_read,
2881 .write = cirrus_linear_write,
2882 .endianness = DEVICE_LITTLE_ENDIAN,
2883 .impl = {
2884 .min_access_size = 1,
2885 .max_access_size = 1,
2886 },
2887 };
2888
2889 static const MemoryRegionOps cirrus_vga_io_ops = {
2890 .read = cirrus_vga_ioport_read,
2891 .write = cirrus_vga_ioport_write,
2892 .endianness = DEVICE_LITTLE_ENDIAN,
2893 .impl = {
2894 .min_access_size = 1,
2895 .max_access_size = 1,
2896 },
2897 };
2898
2899 static void cirrus_init_common(CirrusVGAState *s, Object *owner,
2900 int device_id, int is_pci,
2901 MemoryRegion *system_memory,
2902 MemoryRegion *system_io)
2903 {
2904 int i;
2905 static int inited;
2906
2907 if (!inited) {
2908 inited = 1;
2909 for(i = 0;i < 256; i++)
2910 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
2911 rop_to_index[CIRRUS_ROP_0] = 0;
2912 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
2913 rop_to_index[CIRRUS_ROP_NOP] = 2;
2914 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
2915 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
2916 rop_to_index[CIRRUS_ROP_SRC] = 5;
2917 rop_to_index[CIRRUS_ROP_1] = 6;
2918 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
2919 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
2920 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
2921 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
2922 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
2923 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
2924 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
2925 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
2926 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
2927 s->device_id = device_id;
2928 if (is_pci)
2929 s->bustype = CIRRUS_BUSTYPE_PCI;
2930 else
2931 s->bustype = CIRRUS_BUSTYPE_ISA;
2932 }
2933
2934 /* Register ioport 0x3b0 - 0x3df */
2935 memory_region_init_io(&s->cirrus_vga_io, owner, &cirrus_vga_io_ops, s,
2936 "cirrus-io", 0x30);
2937 memory_region_set_flush_coalesced(&s->cirrus_vga_io);
2938 memory_region_add_subregion(system_io, 0x3b0, &s->cirrus_vga_io);
2939
2940 memory_region_init(&s->low_mem_container, owner,
2941 "cirrus-lowmem-container",
2942 0x20000);
2943
2944 memory_region_init_io(&s->low_mem, owner, &cirrus_vga_mem_ops, s,
2945 "cirrus-low-memory", 0x20000);
2946 memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem);
2947 for (i = 0; i < 2; ++i) {
2948 static const char *names[] = { "vga.bank0", "vga.bank1" };
2949 MemoryRegion *bank = &s->cirrus_bank[i];
2950 memory_region_init_alias(bank, owner, names[i], &s->vga.vram,
2951 0, 0x8000);
2952 memory_region_set_enabled(bank, false);
2953 memory_region_add_subregion_overlap(&s->low_mem_container, i * 0x8000,
2954 bank, 1);
2955 }
2956 memory_region_add_subregion_overlap(system_memory,
2957 0x000a0000,
2958 &s->low_mem_container,
2959 1);
2960 memory_region_set_coalescing(&s->low_mem);
2961
2962 /* I/O handler for LFB */
2963 memory_region_init_io(&s->cirrus_linear_io, owner, &cirrus_linear_io_ops, s,
2964 "cirrus-linear-io", s->vga.vram_size_mb
2965 * 1024 * 1024);
2966 memory_region_set_flush_coalesced(&s->cirrus_linear_io);
2967
2968 /* I/O handler for LFB */
2969 memory_region_init_io(&s->cirrus_linear_bitblt_io, owner,
2970 &cirrus_linear_bitblt_io_ops,
2971 s,
2972 "cirrus-bitblt-mmio",
2973 0x400000);
2974 memory_region_set_flush_coalesced(&s->cirrus_linear_bitblt_io);
2975
2976 /* I/O handler for memory-mapped I/O */
2977 memory_region_init_io(&s->cirrus_mmio_io, owner, &cirrus_mmio_io_ops, s,
2978 "cirrus-mmio", CIRRUS_PNPMMIO_SIZE);
2979 memory_region_set_flush_coalesced(&s->cirrus_mmio_io);
2980
2981 s->real_vram_size =
2982 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
2983
2984 /* XXX: s->vga.vram_size must be a power of two */
2985 s->cirrus_addr_mask = s->real_vram_size - 1;
2986 s->linear_mmio_mask = s->real_vram_size - 256;
2987
2988 s->vga.get_bpp = cirrus_get_bpp;
2989 s->vga.get_offsets = cirrus_get_offsets;
2990 s->vga.get_resolution = cirrus_get_resolution;
2991 s->vga.cursor_invalidate = cirrus_cursor_invalidate;
2992 s->vga.cursor_draw_line = cirrus_cursor_draw_line;
2993
2994 qemu_register_reset(cirrus_reset, s);
2995 }
2996
2997 /***************************************
2998 *
2999 * ISA bus support
3000 *
3001 ***************************************/
3002
3003 static void isa_cirrus_vga_realizefn(DeviceState *dev, Error **errp)
3004 {
3005 ISADevice *isadev = ISA_DEVICE(dev);
3006 ISACirrusVGAState *d = ISA_CIRRUS_VGA(dev);
3007 VGACommonState *s = &d->cirrus_vga.vga;
3008
3009 /* follow real hardware, cirrus card emulated has 4 MB video memory.
3010 Also accept 8 MB/16 MB for backward compatibility. */
3011 if (s->vram_size_mb != 4 && s->vram_size_mb != 8 &&
3012 s->vram_size_mb != 16) {
3013 error_setg(errp, "Invalid cirrus_vga ram size '%u'",
3014 s->vram_size_mb);
3015 return;
3016 }
3017 vga_common_init(s, OBJECT(dev), true);
3018 cirrus_init_common(&d->cirrus_vga, OBJECT(dev), CIRRUS_ID_CLGD5430, 0,
3019 isa_address_space(isadev),
3020 isa_address_space_io(isadev));
3021 s->con = graphic_console_init(dev, 0, s->hw_ops, s);
3022 rom_add_vga(VGABIOS_CIRRUS_FILENAME);
3023 /* XXX ISA-LFB support */
3024 /* FIXME not qdev yet */
3025 }
3026
3027 static Property isa_cirrus_vga_properties[] = {
3028 DEFINE_PROP_UINT32("vgamem_mb", struct ISACirrusVGAState,
3029 cirrus_vga.vga.vram_size_mb, 4),
3030 DEFINE_PROP_BOOL("blitter", struct ISACirrusVGAState,
3031 cirrus_vga.enable_blitter, true),
3032 DEFINE_PROP_END_OF_LIST(),
3033 };
3034
3035 static void isa_cirrus_vga_class_init(ObjectClass *klass, void *data)
3036 {
3037 DeviceClass *dc = DEVICE_CLASS(klass);
3038
3039 dc->vmsd = &vmstate_cirrus_vga;
3040 dc->realize = isa_cirrus_vga_realizefn;
3041 dc->props = isa_cirrus_vga_properties;
3042 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
3043 }
3044
3045 static const TypeInfo isa_cirrus_vga_info = {
3046 .name = TYPE_ISA_CIRRUS_VGA,
3047 .parent = TYPE_ISA_DEVICE,
3048 .instance_size = sizeof(ISACirrusVGAState),
3049 .class_init = isa_cirrus_vga_class_init,
3050 };
3051
3052 /***************************************
3053 *
3054 * PCI bus support
3055 *
3056 ***************************************/
3057
3058 static void pci_cirrus_vga_realize(PCIDevice *dev, Error **errp)
3059 {
3060 PCICirrusVGAState *d = PCI_CIRRUS_VGA(dev);
3061 CirrusVGAState *s = &d->cirrus_vga;
3062 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
3063 int16_t device_id = pc->device_id;
3064
3065 /* follow real hardware, cirrus card emulated has 4 MB video memory.
3066 Also accept 8 MB/16 MB for backward compatibility. */
3067 if (s->vga.vram_size_mb != 4 && s->vga.vram_size_mb != 8 &&
3068 s->vga.vram_size_mb != 16) {
3069 error_setg(errp, "Invalid cirrus_vga ram size '%u'",
3070 s->vga.vram_size_mb);
3071 return;
3072 }
3073 /* setup VGA */
3074 vga_common_init(&s->vga, OBJECT(dev), true);
3075 cirrus_init_common(s, OBJECT(dev), device_id, 1, pci_address_space(dev),
3076 pci_address_space_io(dev));
3077 s->vga.con = graphic_console_init(DEVICE(dev), 0, s->vga.hw_ops, &s->vga);
3078
3079 /* setup PCI */
3080
3081 memory_region_init(&s->pci_bar, OBJECT(dev), "cirrus-pci-bar0", 0x2000000);
3082
3083 /* XXX: add byte swapping apertures */
3084 memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io);
3085 memory_region_add_subregion(&s->pci_bar, 0x1000000,
3086 &s->cirrus_linear_bitblt_io);
3087
3088 /* setup memory space */
3089 /* memory #0 LFB */
3090 /* memory #1 memory-mapped I/O */
3091 /* XXX: s->vga.vram_size must be a power of two */
3092 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->pci_bar);
3093 if (device_id == CIRRUS_ID_CLGD5446) {
3094 pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io);
3095 }
3096 }
3097
3098 static Property pci_vga_cirrus_properties[] = {
3099 DEFINE_PROP_UINT32("vgamem_mb", struct PCICirrusVGAState,
3100 cirrus_vga.vga.vram_size_mb, 4),
3101 DEFINE_PROP_BOOL("blitter", struct PCICirrusVGAState,
3102 cirrus_vga.enable_blitter, true),
3103 DEFINE_PROP_END_OF_LIST(),
3104 };
3105
3106 static void cirrus_vga_class_init(ObjectClass *klass, void *data)
3107 {
3108 DeviceClass *dc = DEVICE_CLASS(klass);
3109 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3110
3111 k->realize = pci_cirrus_vga_realize;
3112 k->romfile = VGABIOS_CIRRUS_FILENAME;
3113 k->vendor_id = PCI_VENDOR_ID_CIRRUS;
3114 k->device_id = CIRRUS_ID_CLGD5446;
3115 k->class_id = PCI_CLASS_DISPLAY_VGA;
3116 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
3117 dc->desc = "Cirrus CLGD 54xx VGA";
3118 dc->vmsd = &vmstate_pci_cirrus_vga;
3119 dc->props = pci_vga_cirrus_properties;
3120 dc->hotpluggable = false;
3121 }
3122
3123 static const TypeInfo cirrus_vga_info = {
3124 .name = TYPE_PCI_CIRRUS_VGA,
3125 .parent = TYPE_PCI_DEVICE,
3126 .instance_size = sizeof(PCICirrusVGAState),
3127 .class_init = cirrus_vga_class_init,
3128 };
3129
3130 static void cirrus_vga_register_types(void)
3131 {
3132 type_register_static(&isa_cirrus_vga_info);
3133 type_register_static(&cirrus_vga_info);
3134 }
3135
3136 type_init(cirrus_vga_register_types)