Merge remote-tracking branch 'remotes/ericb/tags/pull-bitmaps-2020-09-21' into staging
[qemu.git] / hw / display / pl110.c
1 /*
2 * Arm PrimeCell PL110 Color LCD Controller
3 *
4 * Copyright (c) 2005-2009 CodeSourcery.
5 * Written by Paul Brook
6 *
7 * This code is licensed under the GNU LGPL
8 */
9
10 #include "qemu/osdep.h"
11 #include "hw/irq.h"
12 #include "hw/sysbus.h"
13 #include "migration/vmstate.h"
14 #include "ui/console.h"
15 #include "framebuffer.h"
16 #include "ui/pixel_ops.h"
17 #include "qemu/timer.h"
18 #include "qemu/log.h"
19 #include "qemu/module.h"
20 #include "qom/object.h"
21
22 #define PL110_CR_EN 0x001
23 #define PL110_CR_BGR 0x100
24 #define PL110_CR_BEBO 0x200
25 #define PL110_CR_BEPO 0x400
26 #define PL110_CR_PWR 0x800
27 #define PL110_IE_NB 0x004
28 #define PL110_IE_VC 0x008
29
30 enum pl110_bppmode
31 {
32 BPP_1,
33 BPP_2,
34 BPP_4,
35 BPP_8,
36 BPP_16,
37 BPP_32,
38 BPP_16_565, /* PL111 only */
39 BPP_12 /* PL111 only */
40 };
41
42
43 /* The Versatile/PB uses a slightly modified PL110 controller. */
44 enum pl110_version
45 {
46 VERSION_PL110,
47 VERSION_PL110_VERSATILE,
48 VERSION_PL111
49 };
50
51 #define TYPE_PL110 "pl110"
52 OBJECT_DECLARE_SIMPLE_TYPE(PL110State, PL110)
53
54 struct PL110State {
55 SysBusDevice parent_obj;
56
57 MemoryRegion iomem;
58 MemoryRegionSection fbsection;
59 QemuConsole *con;
60 QEMUTimer *vblank_timer;
61
62 int version;
63 uint32_t timing[4];
64 uint32_t cr;
65 uint32_t upbase;
66 uint32_t lpbase;
67 uint32_t int_status;
68 uint32_t int_mask;
69 int cols;
70 int rows;
71 enum pl110_bppmode bpp;
72 int invalidate;
73 uint32_t mux_ctrl;
74 uint32_t palette[256];
75 uint32_t raw_palette[128];
76 qemu_irq irq;
77 };
78
79 static int vmstate_pl110_post_load(void *opaque, int version_id);
80
81 static const VMStateDescription vmstate_pl110 = {
82 .name = "pl110",
83 .version_id = 2,
84 .minimum_version_id = 1,
85 .post_load = vmstate_pl110_post_load,
86 .fields = (VMStateField[]) {
87 VMSTATE_INT32(version, PL110State),
88 VMSTATE_UINT32_ARRAY(timing, PL110State, 4),
89 VMSTATE_UINT32(cr, PL110State),
90 VMSTATE_UINT32(upbase, PL110State),
91 VMSTATE_UINT32(lpbase, PL110State),
92 VMSTATE_UINT32(int_status, PL110State),
93 VMSTATE_UINT32(int_mask, PL110State),
94 VMSTATE_INT32(cols, PL110State),
95 VMSTATE_INT32(rows, PL110State),
96 VMSTATE_UINT32(bpp, PL110State),
97 VMSTATE_INT32(invalidate, PL110State),
98 VMSTATE_UINT32_ARRAY(palette, PL110State, 256),
99 VMSTATE_UINT32_ARRAY(raw_palette, PL110State, 128),
100 VMSTATE_UINT32_V(mux_ctrl, PL110State, 2),
101 VMSTATE_END_OF_LIST()
102 }
103 };
104
105 static const unsigned char pl110_id[] =
106 { 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
107
108 static const unsigned char pl111_id[] = {
109 0x11, 0x11, 0x24, 0x00, 0x0d, 0xf0, 0x05, 0xb1
110 };
111
112
113 /* Indexed by pl110_version */
114 static const unsigned char *idregs[] = {
115 pl110_id,
116 /* The ARM documentation (DDI0224C) says the CLCDC on the Versatile board
117 * has a different ID (0x93, 0x10, 0x04, 0x00, ...). However the hardware
118 * itself has the same ID values as a stock PL110, and guests (in
119 * particular Linux) rely on this. We emulate what the hardware does,
120 * rather than what the docs claim it ought to do.
121 */
122 pl110_id,
123 pl111_id
124 };
125
126 #define BITS 8
127 #include "pl110_template.h"
128 #define BITS 15
129 #include "pl110_template.h"
130 #define BITS 16
131 #include "pl110_template.h"
132 #define BITS 24
133 #include "pl110_template.h"
134 #define BITS 32
135 #include "pl110_template.h"
136
137 static int pl110_enabled(PL110State *s)
138 {
139 return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
140 }
141
142 static void pl110_update_display(void *opaque)
143 {
144 PL110State *s = (PL110State *)opaque;
145 SysBusDevice *sbd;
146 DisplaySurface *surface = qemu_console_surface(s->con);
147 drawfn* fntable;
148 drawfn fn;
149 int dest_width;
150 int src_width;
151 int bpp_offset;
152 int first;
153 int last;
154
155 if (!pl110_enabled(s)) {
156 return;
157 }
158
159 sbd = SYS_BUS_DEVICE(s);
160
161 switch (surface_bits_per_pixel(surface)) {
162 case 0:
163 return;
164 case 8:
165 fntable = pl110_draw_fn_8;
166 dest_width = 1;
167 break;
168 case 15:
169 fntable = pl110_draw_fn_15;
170 dest_width = 2;
171 break;
172 case 16:
173 fntable = pl110_draw_fn_16;
174 dest_width = 2;
175 break;
176 case 24:
177 fntable = pl110_draw_fn_24;
178 dest_width = 3;
179 break;
180 case 32:
181 fntable = pl110_draw_fn_32;
182 dest_width = 4;
183 break;
184 default:
185 fprintf(stderr, "pl110: Bad color depth\n");
186 exit(1);
187 }
188 if (s->cr & PL110_CR_BGR)
189 bpp_offset = 0;
190 else
191 bpp_offset = 24;
192
193 if ((s->version != VERSION_PL111) && (s->bpp == BPP_16)) {
194 /* The PL110's native 16 bit mode is 5551; however
195 * most boards with a PL110 implement an external
196 * mux which allows bits to be reshuffled to give
197 * 565 format. The mux is typically controlled by
198 * an external system register.
199 * This is controlled by a GPIO input pin
200 * so boards can wire it up to their register.
201 *
202 * The PL111 straightforwardly implements both
203 * 5551 and 565 under control of the bpp field
204 * in the LCDControl register.
205 */
206 switch (s->mux_ctrl) {
207 case 3: /* 565 BGR */
208 bpp_offset = (BPP_16_565 - BPP_16);
209 break;
210 case 1: /* 5551 */
211 break;
212 case 0: /* 888; also if we have loaded vmstate from an old version */
213 case 2: /* 565 RGB */
214 default:
215 /* treat as 565 but honour BGR bit */
216 bpp_offset += (BPP_16_565 - BPP_16);
217 break;
218 }
219 }
220
221 if (s->cr & PL110_CR_BEBO)
222 fn = fntable[s->bpp + 8 + bpp_offset];
223 else if (s->cr & PL110_CR_BEPO)
224 fn = fntable[s->bpp + 16 + bpp_offset];
225 else
226 fn = fntable[s->bpp + bpp_offset];
227
228 src_width = s->cols;
229 switch (s->bpp) {
230 case BPP_1:
231 src_width >>= 3;
232 break;
233 case BPP_2:
234 src_width >>= 2;
235 break;
236 case BPP_4:
237 src_width >>= 1;
238 break;
239 case BPP_8:
240 break;
241 case BPP_16:
242 case BPP_16_565:
243 case BPP_12:
244 src_width <<= 1;
245 break;
246 case BPP_32:
247 src_width <<= 2;
248 break;
249 }
250 dest_width *= s->cols;
251 first = 0;
252 if (s->invalidate) {
253 framebuffer_update_memory_section(&s->fbsection,
254 sysbus_address_space(sbd),
255 s->upbase,
256 s->rows, src_width);
257 }
258
259 framebuffer_update_display(surface, &s->fbsection,
260 s->cols, s->rows,
261 src_width, dest_width, 0,
262 s->invalidate,
263 fn, s->palette,
264 &first, &last);
265
266 if (first >= 0) {
267 dpy_gfx_update(s->con, 0, first, s->cols, last - first + 1);
268 }
269 s->invalidate = 0;
270 }
271
272 static void pl110_invalidate_display(void * opaque)
273 {
274 PL110State *s = (PL110State *)opaque;
275 s->invalidate = 1;
276 if (pl110_enabled(s)) {
277 qemu_console_resize(s->con, s->cols, s->rows);
278 }
279 }
280
281 static void pl110_update_palette(PL110State *s, int n)
282 {
283 DisplaySurface *surface = qemu_console_surface(s->con);
284 int i;
285 uint32_t raw;
286 unsigned int r, g, b;
287
288 raw = s->raw_palette[n];
289 n <<= 1;
290 for (i = 0; i < 2; i++) {
291 r = (raw & 0x1f) << 3;
292 raw >>= 5;
293 g = (raw & 0x1f) << 3;
294 raw >>= 5;
295 b = (raw & 0x1f) << 3;
296 /* The I bit is ignored. */
297 raw >>= 6;
298 switch (surface_bits_per_pixel(surface)) {
299 case 8:
300 s->palette[n] = rgb_to_pixel8(r, g, b);
301 break;
302 case 15:
303 s->palette[n] = rgb_to_pixel15(r, g, b);
304 break;
305 case 16:
306 s->palette[n] = rgb_to_pixel16(r, g, b);
307 break;
308 case 24:
309 case 32:
310 s->palette[n] = rgb_to_pixel32(r, g, b);
311 break;
312 }
313 n++;
314 }
315 }
316
317 static void pl110_resize(PL110State *s, int width, int height)
318 {
319 if (width != s->cols || height != s->rows) {
320 if (pl110_enabled(s)) {
321 qemu_console_resize(s->con, width, height);
322 }
323 }
324 s->cols = width;
325 s->rows = height;
326 }
327
328 /* Update interrupts. */
329 static void pl110_update(PL110State *s)
330 {
331 /* Raise IRQ if enabled and any status bit is 1 */
332 if (s->int_status & s->int_mask) {
333 qemu_irq_raise(s->irq);
334 } else {
335 qemu_irq_lower(s->irq);
336 }
337 }
338
339 static void pl110_vblank_interrupt(void *opaque)
340 {
341 PL110State *s = opaque;
342
343 /* Fire the vertical compare and next base IRQs and re-arm */
344 s->int_status |= (PL110_IE_NB | PL110_IE_VC);
345 timer_mod(s->vblank_timer,
346 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
347 NANOSECONDS_PER_SECOND / 60);
348 pl110_update(s);
349 }
350
351 static uint64_t pl110_read(void *opaque, hwaddr offset,
352 unsigned size)
353 {
354 PL110State *s = (PL110State *)opaque;
355
356 if (offset >= 0xfe0 && offset < 0x1000) {
357 return idregs[s->version][(offset - 0xfe0) >> 2];
358 }
359 if (offset >= 0x200 && offset < 0x400) {
360 return s->raw_palette[(offset - 0x200) >> 2];
361 }
362 switch (offset >> 2) {
363 case 0: /* LCDTiming0 */
364 return s->timing[0];
365 case 1: /* LCDTiming1 */
366 return s->timing[1];
367 case 2: /* LCDTiming2 */
368 return s->timing[2];
369 case 3: /* LCDTiming3 */
370 return s->timing[3];
371 case 4: /* LCDUPBASE */
372 return s->upbase;
373 case 5: /* LCDLPBASE */
374 return s->lpbase;
375 case 6: /* LCDIMSC */
376 if (s->version != VERSION_PL110) {
377 return s->cr;
378 }
379 return s->int_mask;
380 case 7: /* LCDControl */
381 if (s->version != VERSION_PL110) {
382 return s->int_mask;
383 }
384 return s->cr;
385 case 8: /* LCDRIS */
386 return s->int_status;
387 case 9: /* LCDMIS */
388 return s->int_status & s->int_mask;
389 case 11: /* LCDUPCURR */
390 /* TODO: Implement vertical refresh. */
391 return s->upbase;
392 case 12: /* LCDLPCURR */
393 return s->lpbase;
394 default:
395 qemu_log_mask(LOG_GUEST_ERROR,
396 "pl110_read: Bad offset %x\n", (int)offset);
397 return 0;
398 }
399 }
400
401 static void pl110_write(void *opaque, hwaddr offset,
402 uint64_t val, unsigned size)
403 {
404 PL110State *s = (PL110State *)opaque;
405 int n;
406
407 /* For simplicity invalidate the display whenever a control register
408 is written to. */
409 s->invalidate = 1;
410 if (offset >= 0x200 && offset < 0x400) {
411 /* Palette. */
412 n = (offset - 0x200) >> 2;
413 s->raw_palette[(offset - 0x200) >> 2] = val;
414 pl110_update_palette(s, n);
415 return;
416 }
417 switch (offset >> 2) {
418 case 0: /* LCDTiming0 */
419 s->timing[0] = val;
420 n = ((val & 0xfc) + 4) * 4;
421 pl110_resize(s, n, s->rows);
422 break;
423 case 1: /* LCDTiming1 */
424 s->timing[1] = val;
425 n = (val & 0x3ff) + 1;
426 pl110_resize(s, s->cols, n);
427 break;
428 case 2: /* LCDTiming2 */
429 s->timing[2] = val;
430 break;
431 case 3: /* LCDTiming3 */
432 s->timing[3] = val;
433 break;
434 case 4: /* LCDUPBASE */
435 s->upbase = val;
436 break;
437 case 5: /* LCDLPBASE */
438 s->lpbase = val;
439 break;
440 case 6: /* LCDIMSC */
441 if (s->version != VERSION_PL110) {
442 goto control;
443 }
444 imsc:
445 s->int_mask = val;
446 pl110_update(s);
447 break;
448 case 7: /* LCDControl */
449 if (s->version != VERSION_PL110) {
450 goto imsc;
451 }
452 control:
453 s->cr = val;
454 s->bpp = (val >> 1) & 7;
455 if (pl110_enabled(s)) {
456 qemu_console_resize(s->con, s->cols, s->rows);
457 timer_mod(s->vblank_timer,
458 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
459 NANOSECONDS_PER_SECOND / 60);
460 } else {
461 timer_del(s->vblank_timer);
462 }
463 break;
464 case 10: /* LCDICR */
465 s->int_status &= ~val;
466 pl110_update(s);
467 break;
468 default:
469 qemu_log_mask(LOG_GUEST_ERROR,
470 "pl110_write: Bad offset %x\n", (int)offset);
471 }
472 }
473
474 static const MemoryRegionOps pl110_ops = {
475 .read = pl110_read,
476 .write = pl110_write,
477 .endianness = DEVICE_NATIVE_ENDIAN,
478 };
479
480 static void pl110_mux_ctrl_set(void *opaque, int line, int level)
481 {
482 PL110State *s = (PL110State *)opaque;
483 s->mux_ctrl = level;
484 }
485
486 static int vmstate_pl110_post_load(void *opaque, int version_id)
487 {
488 PL110State *s = opaque;
489 /* Make sure we redraw, and at the right size */
490 pl110_invalidate_display(s);
491 return 0;
492 }
493
494 static const GraphicHwOps pl110_gfx_ops = {
495 .invalidate = pl110_invalidate_display,
496 .gfx_update = pl110_update_display,
497 };
498
499 static void pl110_realize(DeviceState *dev, Error **errp)
500 {
501 PL110State *s = PL110(dev);
502 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
503
504 memory_region_init_io(&s->iomem, OBJECT(s), &pl110_ops, s, "pl110", 0x1000);
505 sysbus_init_mmio(sbd, &s->iomem);
506 sysbus_init_irq(sbd, &s->irq);
507 s->vblank_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
508 pl110_vblank_interrupt, s);
509 qdev_init_gpio_in(dev, pl110_mux_ctrl_set, 1);
510 s->con = graphic_console_init(dev, 0, &pl110_gfx_ops, s);
511 }
512
513 static void pl110_init(Object *obj)
514 {
515 PL110State *s = PL110(obj);
516
517 s->version = VERSION_PL110;
518 }
519
520 static void pl110_versatile_init(Object *obj)
521 {
522 PL110State *s = PL110(obj);
523
524 s->version = VERSION_PL110_VERSATILE;
525 }
526
527 static void pl111_init(Object *obj)
528 {
529 PL110State *s = PL110(obj);
530
531 s->version = VERSION_PL111;
532 }
533
534 static void pl110_class_init(ObjectClass *klass, void *data)
535 {
536 DeviceClass *dc = DEVICE_CLASS(klass);
537
538 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
539 dc->vmsd = &vmstate_pl110;
540 dc->realize = pl110_realize;
541 }
542
543 static const TypeInfo pl110_info = {
544 .name = TYPE_PL110,
545 .parent = TYPE_SYS_BUS_DEVICE,
546 .instance_size = sizeof(PL110State),
547 .instance_init = pl110_init,
548 .class_init = pl110_class_init,
549 };
550
551 static const TypeInfo pl110_versatile_info = {
552 .name = "pl110_versatile",
553 .parent = TYPE_PL110,
554 .instance_init = pl110_versatile_init,
555 };
556
557 static const TypeInfo pl111_info = {
558 .name = "pl111",
559 .parent = TYPE_PL110,
560 .instance_init = pl111_init,
561 };
562
563 static void pl110_register_types(void)
564 {
565 type_register_static(&pl110_info);
566 type_register_static(&pl110_versatile_info);
567 type_register_static(&pl111_info);
568 }
569
570 type_init(pl110_register_types)