qxl: allow to specify head limit to qxl driver
[qemu.git] / hw / display / qxl.c
1 /*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include <zlib.h>
22 #include <stdint.h>
23
24 #include "qemu-common.h"
25 #include "qemu/timer.h"
26 #include "qemu/queue.h"
27 #include "qemu/atomic.h"
28 #include "sysemu/sysemu.h"
29 #include "trace.h"
30
31 #include "qxl.h"
32
33 /*
34 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as
35 * such can be changed by the guest, so to avoid a guest trigerrable
36 * abort we just qxl_set_guest_bug and set the return to NULL. Still
37 * it may happen as a result of emulator bug as well.
38 */
39 #undef SPICE_RING_PROD_ITEM
40 #define SPICE_RING_PROD_ITEM(qxl, r, ret) { \
41 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
42 if (prod >= ARRAY_SIZE((r)->items)) { \
43 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \
44 "%u >= %zu", prod, ARRAY_SIZE((r)->items)); \
45 ret = NULL; \
46 } else { \
47 ret = &(r)->items[prod].el; \
48 } \
49 }
50
51 #undef SPICE_RING_CONS_ITEM
52 #define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
53 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
54 if (cons >= ARRAY_SIZE((r)->items)) { \
55 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
56 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \
57 ret = NULL; \
58 } else { \
59 ret = &(r)->items[cons].el; \
60 } \
61 }
62
63 #undef ALIGN
64 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
65
66 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
67
68 #define QXL_MODE(_x, _y, _b, _o) \
69 { .x_res = _x, \
70 .y_res = _y, \
71 .bits = _b, \
72 .stride = (_x) * (_b) / 8, \
73 .x_mili = PIXEL_SIZE * (_x), \
74 .y_mili = PIXEL_SIZE * (_y), \
75 .orientation = _o, \
76 }
77
78 #define QXL_MODE_16_32(x_res, y_res, orientation) \
79 QXL_MODE(x_res, y_res, 16, orientation), \
80 QXL_MODE(x_res, y_res, 32, orientation)
81
82 #define QXL_MODE_EX(x_res, y_res) \
83 QXL_MODE_16_32(x_res, y_res, 0), \
84 QXL_MODE_16_32(x_res, y_res, 1)
85
86 static QXLMode qxl_modes[] = {
87 QXL_MODE_EX(640, 480),
88 QXL_MODE_EX(800, 480),
89 QXL_MODE_EX(800, 600),
90 QXL_MODE_EX(832, 624),
91 QXL_MODE_EX(960, 640),
92 QXL_MODE_EX(1024, 600),
93 QXL_MODE_EX(1024, 768),
94 QXL_MODE_EX(1152, 864),
95 QXL_MODE_EX(1152, 870),
96 QXL_MODE_EX(1280, 720),
97 QXL_MODE_EX(1280, 760),
98 QXL_MODE_EX(1280, 768),
99 QXL_MODE_EX(1280, 800),
100 QXL_MODE_EX(1280, 960),
101 QXL_MODE_EX(1280, 1024),
102 QXL_MODE_EX(1360, 768),
103 QXL_MODE_EX(1366, 768),
104 QXL_MODE_EX(1400, 1050),
105 QXL_MODE_EX(1440, 900),
106 QXL_MODE_EX(1600, 900),
107 QXL_MODE_EX(1600, 1200),
108 QXL_MODE_EX(1680, 1050),
109 QXL_MODE_EX(1920, 1080),
110 /* these modes need more than 8 MB video memory */
111 QXL_MODE_EX(1920, 1200),
112 QXL_MODE_EX(1920, 1440),
113 QXL_MODE_EX(2000, 2000),
114 QXL_MODE_EX(2048, 1536),
115 QXL_MODE_EX(2048, 2048),
116 QXL_MODE_EX(2560, 1440),
117 QXL_MODE_EX(2560, 1600),
118 /* these modes need more than 16 MB video memory */
119 QXL_MODE_EX(2560, 2048),
120 QXL_MODE_EX(2800, 2100),
121 QXL_MODE_EX(3200, 2400),
122 /* these modes need more than 32 MB video memory */
123 QXL_MODE_EX(3840, 2160), /* 4k mainstream */
124 QXL_MODE_EX(4096, 2160), /* 4k */
125 /* these modes need more than 64 MB video memory */
126 QXL_MODE_EX(7680, 4320), /* 8k mainstream */
127 /* these modes need more than 128 MB video memory */
128 QXL_MODE_EX(8192, 4320), /* 8k */
129 };
130
131 static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
132 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
133 static void qxl_reset_memslots(PCIQXLDevice *d);
134 static void qxl_reset_surfaces(PCIQXLDevice *d);
135 static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
136
137 static void qxl_hw_update(void *opaque);
138
139 void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
140 {
141 trace_qxl_set_guest_bug(qxl->id);
142 qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
143 qxl->guest_bug = 1;
144 if (qxl->guestdebug) {
145 va_list ap;
146 va_start(ap, msg);
147 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
148 vfprintf(stderr, msg, ap);
149 fprintf(stderr, "\n");
150 va_end(ap);
151 }
152 }
153
154 static void qxl_clear_guest_bug(PCIQXLDevice *qxl)
155 {
156 qxl->guest_bug = 0;
157 }
158
159 void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
160 struct QXLRect *area, struct QXLRect *dirty_rects,
161 uint32_t num_dirty_rects,
162 uint32_t clear_dirty_region,
163 qxl_async_io async, struct QXLCookie *cookie)
164 {
165 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right,
166 area->top, area->bottom);
167 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects,
168 clear_dirty_region);
169 if (async == QXL_SYNC) {
170 spice_qxl_update_area(&qxl->ssd.qxl, surface_id, area,
171 dirty_rects, num_dirty_rects, clear_dirty_region);
172 } else {
173 assert(cookie != NULL);
174 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
175 clear_dirty_region, (uintptr_t)cookie);
176 }
177 }
178
179 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
180 uint32_t id)
181 {
182 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id);
183 qemu_mutex_lock(&qxl->track_lock);
184 qxl->guest_surfaces.cmds[id] = 0;
185 qxl->guest_surfaces.count--;
186 qemu_mutex_unlock(&qxl->track_lock);
187 }
188
189 static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
190 qxl_async_io async)
191 {
192 QXLCookie *cookie;
193
194 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async);
195 if (async) {
196 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
197 QXL_IO_DESTROY_SURFACE_ASYNC);
198 cookie->u.surface_id = id;
199 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie);
200 } else {
201 spice_qxl_destroy_surface_wait(&qxl->ssd.qxl, id);
202 qxl_spice_destroy_surface_wait_complete(qxl, id);
203 }
204 }
205
206 static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
207 {
208 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count,
209 qxl->num_free_res);
210 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl,
211 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
212 QXL_IO_FLUSH_SURFACES_ASYNC));
213 }
214
215 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
216 uint32_t count)
217 {
218 trace_qxl_spice_loadvm_commands(qxl->id, ext, count);
219 spice_qxl_loadvm_commands(&qxl->ssd.qxl, ext, count);
220 }
221
222 void qxl_spice_oom(PCIQXLDevice *qxl)
223 {
224 trace_qxl_spice_oom(qxl->id);
225 spice_qxl_oom(&qxl->ssd.qxl);
226 }
227
228 void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
229 {
230 trace_qxl_spice_reset_memslots(qxl->id);
231 spice_qxl_reset_memslots(&qxl->ssd.qxl);
232 }
233
234 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
235 {
236 trace_qxl_spice_destroy_surfaces_complete(qxl->id);
237 qemu_mutex_lock(&qxl->track_lock);
238 memset(qxl->guest_surfaces.cmds, 0,
239 sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces);
240 qxl->guest_surfaces.count = 0;
241 qemu_mutex_unlock(&qxl->track_lock);
242 }
243
244 static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
245 {
246 trace_qxl_spice_destroy_surfaces(qxl->id, async);
247 if (async) {
248 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl,
249 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
250 QXL_IO_DESTROY_ALL_SURFACES_ASYNC));
251 } else {
252 spice_qxl_destroy_surfaces(&qxl->ssd.qxl);
253 qxl_spice_destroy_surfaces_complete(qxl);
254 }
255 }
256
257 static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay)
258 {
259 trace_qxl_spice_monitors_config(qxl->id);
260 if (replay) {
261 /*
262 * don't use QXL_COOKIE_TYPE_IO:
263 * - we are not running yet (post_load), we will assert
264 * in send_events
265 * - this is not a guest io, but a reply, so async_io isn't set.
266 */
267 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
268 qxl->guest_monitors_config,
269 MEMSLOT_GROUP_GUEST,
270 (uintptr_t)qxl_cookie_new(
271 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG,
272 0));
273 } else {
274 #if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
275 if (qxl->max_outputs) {
276 spice_qxl_set_monitors_config_limit(&qxl->ssd.qxl,
277 qxl->max_outputs);
278 }
279 #endif
280 qxl->guest_monitors_config = qxl->ram->monitors_config;
281 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
282 qxl->ram->monitors_config,
283 MEMSLOT_GROUP_GUEST,
284 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
285 QXL_IO_MONITORS_CONFIG_ASYNC));
286 }
287 }
288
289 void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
290 {
291 trace_qxl_spice_reset_image_cache(qxl->id);
292 spice_qxl_reset_image_cache(&qxl->ssd.qxl);
293 }
294
295 void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
296 {
297 trace_qxl_spice_reset_cursor(qxl->id);
298 spice_qxl_reset_cursor(&qxl->ssd.qxl);
299 qemu_mutex_lock(&qxl->track_lock);
300 qxl->guest_cursor = 0;
301 qemu_mutex_unlock(&qxl->track_lock);
302 if (qxl->ssd.cursor) {
303 cursor_put(qxl->ssd.cursor);
304 }
305 qxl->ssd.cursor = cursor_builtin_hidden();
306 }
307
308 static ram_addr_t qxl_rom_size(void)
309 {
310 uint32_t required_rom_size = sizeof(QXLRom) + sizeof(QXLModes) +
311 sizeof(qxl_modes);
312 uint32_t rom_size = 8192; /* two pages */
313
314 QEMU_BUILD_BUG_ON(required_rom_size > rom_size);
315 return rom_size;
316 }
317
318 static void init_qxl_rom(PCIQXLDevice *d)
319 {
320 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
321 QXLModes *modes = (QXLModes *)(rom + 1);
322 uint32_t ram_header_size;
323 uint32_t surface0_area_size;
324 uint32_t num_pages;
325 uint32_t fb;
326 int i, n;
327
328 memset(rom, 0, d->rom_size);
329
330 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
331 rom->id = cpu_to_le32(d->id);
332 rom->log_level = cpu_to_le32(d->guestdebug);
333 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
334
335 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
336 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
337 rom->slots_start = 1;
338 rom->slots_end = NUM_MEMSLOTS - 1;
339 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces);
340
341 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) {
342 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
343 if (fb > d->vgamem_size) {
344 continue;
345 }
346 modes->modes[n].id = cpu_to_le32(i);
347 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res);
348 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res);
349 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits);
350 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride);
351 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
352 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
353 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation);
354 n++;
355 }
356 modes->n_modes = cpu_to_le32(n);
357
358 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
359 surface0_area_size = ALIGN(d->vgamem_size, 4096);
360 num_pages = d->vga.vram_size;
361 num_pages -= ram_header_size;
362 num_pages -= surface0_area_size;
363 num_pages = num_pages / QXL_PAGE_SIZE;
364
365 assert(ram_header_size + surface0_area_size <= d->vga.vram_size);
366
367 rom->draw_area_offset = cpu_to_le32(0);
368 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
369 rom->pages_offset = cpu_to_le32(surface0_area_size);
370 rom->num_pages = cpu_to_le32(num_pages);
371 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
372
373 d->shadow_rom = *rom;
374 d->rom = rom;
375 d->modes = modes;
376 }
377
378 static void init_qxl_ram(PCIQXLDevice *d)
379 {
380 uint8_t *buf;
381 uint64_t *item;
382
383 buf = d->vga.vram_ptr;
384 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
385 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
386 d->ram->int_pending = cpu_to_le32(0);
387 d->ram->int_mask = cpu_to_le32(0);
388 d->ram->update_surface = 0;
389 d->ram->monitors_config = 0;
390 SPICE_RING_INIT(&d->ram->cmd_ring);
391 SPICE_RING_INIT(&d->ram->cursor_ring);
392 SPICE_RING_INIT(&d->ram->release_ring);
393 SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item);
394 assert(item);
395 *item = 0;
396 qxl_ring_set_dirty(d);
397 }
398
399 /* can be called from spice server thread context */
400 static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
401 {
402 memory_region_set_dirty(mr, addr, end - addr);
403 }
404
405 static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
406 {
407 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
408 }
409
410 /* called from spice server thread context only */
411 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
412 {
413 void *base = qxl->vga.vram_ptr;
414 intptr_t offset;
415
416 offset = ptr - base;
417 assert(offset < qxl->vga.vram_size);
418 qxl_set_dirty(&qxl->vga.vram, offset, offset + 3);
419 }
420
421 /* can be called from spice server thread context */
422 static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
423 {
424 ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
425 ram_addr_t end = qxl->vga.vram_size;
426 qxl_set_dirty(&qxl->vga.vram, addr, end);
427 }
428
429 /*
430 * keep track of some command state, for savevm/loadvm.
431 * called from spice server thread context only
432 */
433 static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
434 {
435 switch (le32_to_cpu(ext->cmd.type)) {
436 case QXL_CMD_SURFACE:
437 {
438 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
439
440 if (!cmd) {
441 return 1;
442 }
443 uint32_t id = le32_to_cpu(cmd->surface_id);
444
445 if (id >= qxl->ssd.num_surfaces) {
446 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id,
447 qxl->ssd.num_surfaces);
448 return 1;
449 }
450 if (cmd->type == QXL_SURFACE_CMD_CREATE &&
451 (cmd->u.surface_create.stride & 0x03) != 0) {
452 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n",
453 cmd->u.surface_create.stride);
454 return 1;
455 }
456 qemu_mutex_lock(&qxl->track_lock);
457 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
458 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
459 qxl->guest_surfaces.count++;
460 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
461 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
462 }
463 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
464 qxl->guest_surfaces.cmds[id] = 0;
465 qxl->guest_surfaces.count--;
466 }
467 qemu_mutex_unlock(&qxl->track_lock);
468 break;
469 }
470 case QXL_CMD_CURSOR:
471 {
472 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
473
474 if (!cmd) {
475 return 1;
476 }
477 if (cmd->type == QXL_CURSOR_SET) {
478 qemu_mutex_lock(&qxl->track_lock);
479 qxl->guest_cursor = ext->cmd.data;
480 qemu_mutex_unlock(&qxl->track_lock);
481 }
482 break;
483 }
484 }
485 return 0;
486 }
487
488 /* spice display interface callbacks */
489
490 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
491 {
492 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
493
494 trace_qxl_interface_attach_worker(qxl->id);
495 qxl->ssd.worker = qxl_worker;
496 }
497
498 static void interface_set_compression_level(QXLInstance *sin, int level)
499 {
500 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
501
502 trace_qxl_interface_set_compression_level(qxl->id, level);
503 qxl->shadow_rom.compression_level = cpu_to_le32(level);
504 qxl->rom->compression_level = cpu_to_le32(level);
505 qxl_rom_set_dirty(qxl);
506 }
507
508 static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
509 {
510 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
511
512 if (!qemu_spice_display_is_running(&qxl->ssd)) {
513 return;
514 }
515
516 trace_qxl_interface_set_mm_time(qxl->id, mm_time);
517 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
518 qxl->rom->mm_clock = cpu_to_le32(mm_time);
519 qxl_rom_set_dirty(qxl);
520 }
521
522 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
523 {
524 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
525
526 trace_qxl_interface_get_init_info(qxl->id);
527 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
528 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
529 info->num_memslots = NUM_MEMSLOTS;
530 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
531 info->internal_groupslot_id = 0;
532 info->qxl_ram_size =
533 le32_to_cpu(qxl->shadow_rom.num_pages) << QXL_PAGE_BITS;
534 info->n_surfaces = qxl->ssd.num_surfaces;
535 }
536
537 static const char *qxl_mode_to_string(int mode)
538 {
539 switch (mode) {
540 case QXL_MODE_COMPAT:
541 return "compat";
542 case QXL_MODE_NATIVE:
543 return "native";
544 case QXL_MODE_UNDEFINED:
545 return "undefined";
546 case QXL_MODE_VGA:
547 return "vga";
548 }
549 return "INVALID";
550 }
551
552 static const char *io_port_to_string(uint32_t io_port)
553 {
554 if (io_port >= QXL_IO_RANGE_SIZE) {
555 return "out of range";
556 }
557 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
558 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
559 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
560 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
561 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
562 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
563 [QXL_IO_RESET] = "QXL_IO_RESET",
564 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
565 [QXL_IO_LOG] = "QXL_IO_LOG",
566 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
567 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
568 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
569 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
570 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
571 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
572 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
573 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
574 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
575 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
576 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
577 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
578 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
579 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
580 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
581 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
582 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
583 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC",
584 };
585 return io_port_to_string[io_port];
586 }
587
588 /* called from spice server thread context only */
589 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
590 {
591 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
592 SimpleSpiceUpdate *update;
593 QXLCommandRing *ring;
594 QXLCommand *cmd;
595 int notify, ret;
596
597 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode));
598
599 switch (qxl->mode) {
600 case QXL_MODE_VGA:
601 ret = false;
602 qemu_mutex_lock(&qxl->ssd.lock);
603 update = QTAILQ_FIRST(&qxl->ssd.updates);
604 if (update != NULL) {
605 QTAILQ_REMOVE(&qxl->ssd.updates, update, next);
606 *ext = update->ext;
607 ret = true;
608 }
609 qemu_mutex_unlock(&qxl->ssd.lock);
610 if (ret) {
611 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
612 qxl_log_command(qxl, "vga", ext);
613 }
614 return ret;
615 case QXL_MODE_COMPAT:
616 case QXL_MODE_NATIVE:
617 case QXL_MODE_UNDEFINED:
618 ring = &qxl->ram->cmd_ring;
619 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) {
620 return false;
621 }
622 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
623 if (!cmd) {
624 return false;
625 }
626 ext->cmd = *cmd;
627 ext->group_id = MEMSLOT_GROUP_GUEST;
628 ext->flags = qxl->cmdflags;
629 SPICE_RING_POP(ring, notify);
630 qxl_ring_set_dirty(qxl);
631 if (notify) {
632 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
633 }
634 qxl->guest_primary.commands++;
635 qxl_track_command(qxl, ext);
636 qxl_log_command(qxl, "cmd", ext);
637 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
638 return true;
639 default:
640 return false;
641 }
642 }
643
644 /* called from spice server thread context only */
645 static int interface_req_cmd_notification(QXLInstance *sin)
646 {
647 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
648 int wait = 1;
649
650 trace_qxl_ring_command_req_notification(qxl->id);
651 switch (qxl->mode) {
652 case QXL_MODE_COMPAT:
653 case QXL_MODE_NATIVE:
654 case QXL_MODE_UNDEFINED:
655 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
656 qxl_ring_set_dirty(qxl);
657 break;
658 default:
659 /* nothing */
660 break;
661 }
662 return wait;
663 }
664
665 /* called from spice server thread context only */
666 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
667 {
668 QXLReleaseRing *ring = &d->ram->release_ring;
669 uint64_t *item;
670 int notify;
671
672 #define QXL_FREE_BUNCH_SIZE 32
673
674 if (ring->prod - ring->cons + 1 == ring->num_items) {
675 /* ring full -- can't push */
676 return;
677 }
678 if (!flush && d->oom_running) {
679 /* collect everything from oom handler before pushing */
680 return;
681 }
682 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
683 /* collect a bit more before pushing */
684 return;
685 }
686
687 SPICE_RING_PUSH(ring, notify);
688 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode),
689 d->guest_surfaces.count, d->num_free_res,
690 d->last_release, notify ? "yes" : "no");
691 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons,
692 ring->num_items, ring->prod, ring->cons);
693 if (notify) {
694 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
695 }
696 SPICE_RING_PROD_ITEM(d, ring, item);
697 if (!item) {
698 return;
699 }
700 *item = 0;
701 d->num_free_res = 0;
702 d->last_release = NULL;
703 qxl_ring_set_dirty(d);
704 }
705
706 /* called from spice server thread context only */
707 static void interface_release_resource(QXLInstance *sin,
708 QXLReleaseInfoExt ext)
709 {
710 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
711 QXLReleaseRing *ring;
712 uint64_t *item, id;
713
714 if (ext.group_id == MEMSLOT_GROUP_HOST) {
715 /* host group -> vga mode update request */
716 QXLCommandExt *cmdext = (void *)(intptr_t)(ext.info->id);
717 SimpleSpiceUpdate *update;
718 g_assert(cmdext->cmd.type == QXL_CMD_DRAW);
719 update = container_of(cmdext, SimpleSpiceUpdate, ext);
720 qemu_spice_destroy_update(&qxl->ssd, update);
721 return;
722 }
723
724 /*
725 * ext->info points into guest-visible memory
726 * pci bar 0, $command.release_info
727 */
728 ring = &qxl->ram->release_ring;
729 SPICE_RING_PROD_ITEM(qxl, ring, item);
730 if (!item) {
731 return;
732 }
733 if (*item == 0) {
734 /* stick head into the ring */
735 id = ext.info->id;
736 ext.info->next = 0;
737 qxl_ram_set_dirty(qxl, &ext.info->next);
738 *item = id;
739 qxl_ring_set_dirty(qxl);
740 } else {
741 /* append item to the list */
742 qxl->last_release->next = ext.info->id;
743 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
744 ext.info->next = 0;
745 qxl_ram_set_dirty(qxl, &ext.info->next);
746 }
747 qxl->last_release = ext.info;
748 qxl->num_free_res++;
749 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res);
750 qxl_push_free_res(qxl, 0);
751 }
752
753 /* called from spice server thread context only */
754 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
755 {
756 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
757 QXLCursorRing *ring;
758 QXLCommand *cmd;
759 int notify;
760
761 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode));
762
763 switch (qxl->mode) {
764 case QXL_MODE_COMPAT:
765 case QXL_MODE_NATIVE:
766 case QXL_MODE_UNDEFINED:
767 ring = &qxl->ram->cursor_ring;
768 if (SPICE_RING_IS_EMPTY(ring)) {
769 return false;
770 }
771 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
772 if (!cmd) {
773 return false;
774 }
775 ext->cmd = *cmd;
776 ext->group_id = MEMSLOT_GROUP_GUEST;
777 ext->flags = qxl->cmdflags;
778 SPICE_RING_POP(ring, notify);
779 qxl_ring_set_dirty(qxl);
780 if (notify) {
781 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
782 }
783 qxl->guest_primary.commands++;
784 qxl_track_command(qxl, ext);
785 qxl_log_command(qxl, "csr", ext);
786 if (qxl->id == 0) {
787 qxl_render_cursor(qxl, ext);
788 }
789 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode));
790 return true;
791 default:
792 return false;
793 }
794 }
795
796 /* called from spice server thread context only */
797 static int interface_req_cursor_notification(QXLInstance *sin)
798 {
799 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
800 int wait = 1;
801
802 trace_qxl_ring_cursor_req_notification(qxl->id);
803 switch (qxl->mode) {
804 case QXL_MODE_COMPAT:
805 case QXL_MODE_NATIVE:
806 case QXL_MODE_UNDEFINED:
807 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
808 qxl_ring_set_dirty(qxl);
809 break;
810 default:
811 /* nothing */
812 break;
813 }
814 return wait;
815 }
816
817 /* called from spice server thread context */
818 static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
819 {
820 /*
821 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
822 * use by xf86-video-qxl and is defined out in the qxl windows driver.
823 * Probably was at some earlier version that is prior to git start (2009),
824 * and is still guest trigerrable.
825 */
826 fprintf(stderr, "%s: deprecated\n", __func__);
827 }
828
829 /* called from spice server thread context only */
830 static int interface_flush_resources(QXLInstance *sin)
831 {
832 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
833 int ret;
834
835 ret = qxl->num_free_res;
836 if (ret) {
837 qxl_push_free_res(qxl, 1);
838 }
839 return ret;
840 }
841
842 static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
843
844 /* called from spice server thread context only */
845 static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie)
846 {
847 uint32_t current_async;
848
849 qemu_mutex_lock(&qxl->async_lock);
850 current_async = qxl->current_async;
851 qxl->current_async = QXL_UNDEFINED_IO;
852 qemu_mutex_unlock(&qxl->async_lock);
853
854 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie);
855 if (!cookie) {
856 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
857 return;
858 }
859 if (cookie && current_async != cookie->io) {
860 fprintf(stderr,
861 "qxl: %s: error: current_async = %d != %"
862 PRId64 " = cookie->io\n", __func__, current_async, cookie->io);
863 }
864 switch (current_async) {
865 case QXL_IO_MEMSLOT_ADD_ASYNC:
866 case QXL_IO_DESTROY_PRIMARY_ASYNC:
867 case QXL_IO_UPDATE_AREA_ASYNC:
868 case QXL_IO_FLUSH_SURFACES_ASYNC:
869 case QXL_IO_MONITORS_CONFIG_ASYNC:
870 break;
871 case QXL_IO_CREATE_PRIMARY_ASYNC:
872 qxl_create_guest_primary_complete(qxl);
873 break;
874 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
875 qxl_spice_destroy_surfaces_complete(qxl);
876 break;
877 case QXL_IO_DESTROY_SURFACE_ASYNC:
878 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id);
879 break;
880 default:
881 fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__,
882 current_async);
883 }
884 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
885 }
886
887 /* called from spice server thread context only */
888 static void interface_update_area_complete(QXLInstance *sin,
889 uint32_t surface_id,
890 QXLRect *dirty, uint32_t num_updated_rects)
891 {
892 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
893 int i;
894 int qxl_i;
895
896 qemu_mutex_lock(&qxl->ssd.lock);
897 if (surface_id != 0 || !qxl->render_update_cookie_num) {
898 qemu_mutex_unlock(&qxl->ssd.lock);
899 return;
900 }
901 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left,
902 dirty->right, dirty->top, dirty->bottom);
903 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects);
904 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) {
905 /*
906 * overflow - treat this as a full update. Not expected to be common.
907 */
908 trace_qxl_interface_update_area_complete_overflow(qxl->id,
909 QXL_NUM_DIRTY_RECTS);
910 qxl->guest_primary.resized = 1;
911 }
912 if (qxl->guest_primary.resized) {
913 /*
914 * Don't bother copying or scheduling the bh since we will flip
915 * the whole area anyway on completion of the update_area async call
916 */
917 qemu_mutex_unlock(&qxl->ssd.lock);
918 return;
919 }
920 qxl_i = qxl->num_dirty_rects;
921 for (i = 0; i < num_updated_rects; i++) {
922 qxl->dirty[qxl_i++] = dirty[i];
923 }
924 qxl->num_dirty_rects += num_updated_rects;
925 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id,
926 qxl->num_dirty_rects);
927 qemu_bh_schedule(qxl->update_area_bh);
928 qemu_mutex_unlock(&qxl->ssd.lock);
929 }
930
931 /* called from spice server thread context only */
932 static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token)
933 {
934 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
935 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token;
936
937 switch (cookie->type) {
938 case QXL_COOKIE_TYPE_IO:
939 interface_async_complete_io(qxl, cookie);
940 g_free(cookie);
941 break;
942 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
943 qxl_render_update_area_done(qxl, cookie);
944 break;
945 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG:
946 break;
947 default:
948 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
949 __func__, cookie->type);
950 g_free(cookie);
951 }
952 }
953
954 /* called from spice server thread context only */
955 static void interface_set_client_capabilities(QXLInstance *sin,
956 uint8_t client_present,
957 uint8_t caps[58])
958 {
959 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
960
961 if (qxl->revision < 4) {
962 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id,
963 qxl->revision);
964 return;
965 }
966
967 if (runstate_check(RUN_STATE_INMIGRATE) ||
968 runstate_check(RUN_STATE_POSTMIGRATE)) {
969 return;
970 }
971
972 qxl->shadow_rom.client_present = client_present;
973 memcpy(qxl->shadow_rom.client_capabilities, caps,
974 sizeof(qxl->shadow_rom.client_capabilities));
975 qxl->rom->client_present = client_present;
976 memcpy(qxl->rom->client_capabilities, caps,
977 sizeof(qxl->rom->client_capabilities));
978 qxl_rom_set_dirty(qxl);
979
980 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT);
981 }
982
983 static uint32_t qxl_crc32(const uint8_t *p, unsigned len)
984 {
985 /*
986 * zlib xors the seed with 0xffffffff, and xors the result
987 * again with 0xffffffff; Both are not done with linux's crc32,
988 * which we want to be compatible with, so undo that.
989 */
990 return crc32(0xffffffff, p, len) ^ 0xffffffff;
991 }
992
993 /* called from main context only */
994 static int interface_client_monitors_config(QXLInstance *sin,
995 VDAgentMonitorsConfig *monitors_config)
996 {
997 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
998 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar);
999 int i;
1000 unsigned max_outputs = ARRAY_SIZE(rom->client_monitors_config.heads);
1001
1002 if (qxl->revision < 4) {
1003 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id,
1004 qxl->revision);
1005 return 0;
1006 }
1007 /*
1008 * Older windows drivers set int_mask to 0 when their ISR is called,
1009 * then later set it to ~0. So it doesn't relate to the actual interrupts
1010 * handled. However, they are old, so clearly they don't support this
1011 * interrupt
1012 */
1013 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 ||
1014 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) {
1015 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id,
1016 qxl->ram->int_mask,
1017 monitors_config);
1018 return 0;
1019 }
1020 if (!monitors_config) {
1021 return 1;
1022 }
1023
1024 #if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
1025 /* limit number of outputs based on setting limit */
1026 if (qxl->max_outputs && qxl->max_outputs <= max_outputs) {
1027 max_outputs = qxl->max_outputs;
1028 }
1029 #endif
1030
1031 memset(&rom->client_monitors_config, 0,
1032 sizeof(rom->client_monitors_config));
1033 rom->client_monitors_config.count = monitors_config->num_of_monitors;
1034 /* monitors_config->flags ignored */
1035 if (rom->client_monitors_config.count >= max_outputs) {
1036 trace_qxl_client_monitors_config_capped(qxl->id,
1037 monitors_config->num_of_monitors,
1038 max_outputs);
1039 rom->client_monitors_config.count = max_outputs;
1040 }
1041 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1042 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1043 QXLURect *rect = &rom->client_monitors_config.heads[i];
1044 /* monitor->depth ignored */
1045 rect->left = monitor->x;
1046 rect->top = monitor->y;
1047 rect->right = monitor->x + monitor->width;
1048 rect->bottom = monitor->y + monitor->height;
1049 }
1050 rom->client_monitors_config_crc = qxl_crc32(
1051 (const uint8_t *)&rom->client_monitors_config,
1052 sizeof(rom->client_monitors_config));
1053 trace_qxl_client_monitors_config_crc(qxl->id,
1054 sizeof(rom->client_monitors_config),
1055 rom->client_monitors_config_crc);
1056
1057 trace_qxl_interrupt_client_monitors_config(qxl->id,
1058 rom->client_monitors_config.count,
1059 rom->client_monitors_config.heads);
1060 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG);
1061 return 1;
1062 }
1063
1064 static const QXLInterface qxl_interface = {
1065 .base.type = SPICE_INTERFACE_QXL,
1066 .base.description = "qxl gpu",
1067 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
1068 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
1069
1070 .attache_worker = interface_attach_worker,
1071 .set_compression_level = interface_set_compression_level,
1072 .set_mm_time = interface_set_mm_time,
1073 .get_init_info = interface_get_init_info,
1074
1075 /* the callbacks below are called from spice server thread context */
1076 .get_command = interface_get_command,
1077 .req_cmd_notification = interface_req_cmd_notification,
1078 .release_resource = interface_release_resource,
1079 .get_cursor_command = interface_get_cursor_command,
1080 .req_cursor_notification = interface_req_cursor_notification,
1081 .notify_update = interface_notify_update,
1082 .flush_resources = interface_flush_resources,
1083 .async_complete = interface_async_complete,
1084 .update_area_complete = interface_update_area_complete,
1085 .set_client_capabilities = interface_set_client_capabilities,
1086 .client_monitors_config = interface_client_monitors_config,
1087 };
1088
1089 static const GraphicHwOps qxl_ops = {
1090 .gfx_update = qxl_hw_update,
1091 };
1092
1093 static void qxl_enter_vga_mode(PCIQXLDevice *d)
1094 {
1095 if (d->mode == QXL_MODE_VGA) {
1096 return;
1097 }
1098 trace_qxl_enter_vga_mode(d->id);
1099 #if SPICE_SERVER_VERSION >= 0x000c03 /* release 0.12.3 */
1100 spice_qxl_driver_unload(&d->ssd.qxl);
1101 #endif
1102 graphic_console_set_hwops(d->ssd.dcl.con, d->vga.hw_ops, &d->vga);
1103 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_DEFAULT);
1104 qemu_spice_create_host_primary(&d->ssd);
1105 d->mode = QXL_MODE_VGA;
1106 vga_dirty_log_start(&d->vga);
1107 graphic_hw_update(d->vga.con);
1108 }
1109
1110 static void qxl_exit_vga_mode(PCIQXLDevice *d)
1111 {
1112 if (d->mode != QXL_MODE_VGA) {
1113 return;
1114 }
1115 trace_qxl_exit_vga_mode(d->id);
1116 graphic_console_set_hwops(d->ssd.dcl.con, &qxl_ops, d);
1117 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_IDLE);
1118 vga_dirty_log_stop(&d->vga);
1119 qxl_destroy_primary(d, QXL_SYNC);
1120 }
1121
1122 static void qxl_update_irq(PCIQXLDevice *d)
1123 {
1124 uint32_t pending = le32_to_cpu(d->ram->int_pending);
1125 uint32_t mask = le32_to_cpu(d->ram->int_mask);
1126 int level = !!(pending & mask);
1127 pci_set_irq(&d->pci, level);
1128 qxl_ring_set_dirty(d);
1129 }
1130
1131 static void qxl_check_state(PCIQXLDevice *d)
1132 {
1133 QXLRam *ram = d->ram;
1134 int spice_display_running = qemu_spice_display_is_running(&d->ssd);
1135
1136 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
1137 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
1138 }
1139
1140 static void qxl_reset_state(PCIQXLDevice *d)
1141 {
1142 QXLRom *rom = d->rom;
1143
1144 qxl_check_state(d);
1145 d->shadow_rom.update_id = cpu_to_le32(0);
1146 *rom = d->shadow_rom;
1147 qxl_rom_set_dirty(d);
1148 init_qxl_ram(d);
1149 d->num_free_res = 0;
1150 d->last_release = NULL;
1151 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
1152 qxl_update_irq(d);
1153 }
1154
1155 static void qxl_soft_reset(PCIQXLDevice *d)
1156 {
1157 trace_qxl_soft_reset(d->id);
1158 qxl_check_state(d);
1159 qxl_clear_guest_bug(d);
1160 d->current_async = QXL_UNDEFINED_IO;
1161
1162 if (d->id == 0) {
1163 qxl_enter_vga_mode(d);
1164 } else {
1165 d->mode = QXL_MODE_UNDEFINED;
1166 }
1167 }
1168
1169 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
1170 {
1171 bool startstop = qemu_spice_display_is_running(&d->ssd);
1172
1173 trace_qxl_hard_reset(d->id, loadvm);
1174
1175 if (startstop) {
1176 qemu_spice_display_stop();
1177 }
1178
1179 qxl_spice_reset_cursor(d);
1180 qxl_spice_reset_image_cache(d);
1181 qxl_reset_surfaces(d);
1182 qxl_reset_memslots(d);
1183
1184 /* pre loadvm reset must not touch QXLRam. This lives in
1185 * device memory, is migrated together with RAM and thus
1186 * already loaded at this point */
1187 if (!loadvm) {
1188 qxl_reset_state(d);
1189 }
1190 qemu_spice_create_host_memslot(&d->ssd);
1191 qxl_soft_reset(d);
1192
1193 if (startstop) {
1194 qemu_spice_display_start();
1195 }
1196 }
1197
1198 static void qxl_reset_handler(DeviceState *dev)
1199 {
1200 PCIQXLDevice *d = PCI_QXL(PCI_DEVICE(dev));
1201
1202 qxl_hard_reset(d, 0);
1203 }
1204
1205 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1206 {
1207 VGACommonState *vga = opaque;
1208 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
1209
1210 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val);
1211 if (qxl->mode != QXL_MODE_VGA) {
1212 qxl_destroy_primary(qxl, QXL_SYNC);
1213 qxl_soft_reset(qxl);
1214 }
1215 vga_ioport_write(opaque, addr, val);
1216 }
1217
1218 static const MemoryRegionPortio qxl_vga_portio_list[] = {
1219 { 0x04, 2, 1, .read = vga_ioport_read,
1220 .write = qxl_vga_ioport_write }, /* 3b4 */
1221 { 0x0a, 1, 1, .read = vga_ioport_read,
1222 .write = qxl_vga_ioport_write }, /* 3ba */
1223 { 0x10, 16, 1, .read = vga_ioport_read,
1224 .write = qxl_vga_ioport_write }, /* 3c0 */
1225 { 0x24, 2, 1, .read = vga_ioport_read,
1226 .write = qxl_vga_ioport_write }, /* 3d4 */
1227 { 0x2a, 1, 1, .read = vga_ioport_read,
1228 .write = qxl_vga_ioport_write }, /* 3da */
1229 PORTIO_END_OF_LIST(),
1230 };
1231
1232 static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
1233 qxl_async_io async)
1234 {
1235 static const int regions[] = {
1236 QXL_RAM_RANGE_INDEX,
1237 QXL_VRAM_RANGE_INDEX,
1238 QXL_VRAM64_RANGE_INDEX,
1239 };
1240 uint64_t guest_start;
1241 uint64_t guest_end;
1242 int pci_region;
1243 pcibus_t pci_start;
1244 pcibus_t pci_end;
1245 intptr_t virt_start;
1246 QXLDevMemSlot memslot;
1247 int i;
1248
1249 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
1250 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
1251
1252 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end);
1253
1254 if (slot_id >= NUM_MEMSLOTS) {
1255 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__,
1256 slot_id, NUM_MEMSLOTS);
1257 return 1;
1258 }
1259 if (guest_start > guest_end) {
1260 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64
1261 " > 0x%" PRIx64, __func__, guest_start, guest_end);
1262 return 1;
1263 }
1264
1265 for (i = 0; i < ARRAY_SIZE(regions); i++) {
1266 pci_region = regions[i];
1267 pci_start = d->pci.io_regions[pci_region].addr;
1268 pci_end = pci_start + d->pci.io_regions[pci_region].size;
1269 /* mapped? */
1270 if (pci_start == -1) {
1271 continue;
1272 }
1273 /* start address in range ? */
1274 if (guest_start < pci_start || guest_start > pci_end) {
1275 continue;
1276 }
1277 /* end address in range ? */
1278 if (guest_end > pci_end) {
1279 continue;
1280 }
1281 /* passed */
1282 break;
1283 }
1284 if (i == ARRAY_SIZE(regions)) {
1285 qxl_set_guest_bug(d, "%s: finished loop without match", __func__);
1286 return 1;
1287 }
1288
1289 switch (pci_region) {
1290 case QXL_RAM_RANGE_INDEX:
1291 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram);
1292 break;
1293 case QXL_VRAM_RANGE_INDEX:
1294 case 4 /* vram 64bit */:
1295 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar);
1296 break;
1297 default:
1298 /* should not happen */
1299 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region);
1300 return 1;
1301 }
1302
1303 memslot.slot_id = slot_id;
1304 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
1305 memslot.virt_start = virt_start + (guest_start - pci_start);
1306 memslot.virt_end = virt_start + (guest_end - pci_start);
1307 memslot.addr_delta = memslot.virt_start - delta;
1308 memslot.generation = d->rom->slot_generation = 0;
1309 qxl_rom_set_dirty(d);
1310
1311 qemu_spice_add_memslot(&d->ssd, &memslot, async);
1312 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
1313 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
1314 d->guest_slots[slot_id].delta = delta;
1315 d->guest_slots[slot_id].active = 1;
1316 return 0;
1317 }
1318
1319 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
1320 {
1321 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
1322 d->guest_slots[slot_id].active = 0;
1323 }
1324
1325 static void qxl_reset_memslots(PCIQXLDevice *d)
1326 {
1327 qxl_spice_reset_memslots(d);
1328 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1329 }
1330
1331 static void qxl_reset_surfaces(PCIQXLDevice *d)
1332 {
1333 trace_qxl_reset_surfaces(d->id);
1334 d->mode = QXL_MODE_UNDEFINED;
1335 qxl_spice_destroy_surfaces(d, QXL_SYNC);
1336 }
1337
1338 /* can be also called from spice server thread context */
1339 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
1340 {
1341 uint64_t phys = le64_to_cpu(pqxl);
1342 uint32_t slot = (phys >> (64 - 8)) & 0xff;
1343 uint64_t offset = phys & 0xffffffffffff;
1344
1345 switch (group_id) {
1346 case MEMSLOT_GROUP_HOST:
1347 return (void *)(intptr_t)offset;
1348 case MEMSLOT_GROUP_GUEST:
1349 if (slot >= NUM_MEMSLOTS) {
1350 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot,
1351 NUM_MEMSLOTS);
1352 return NULL;
1353 }
1354 if (!qxl->guest_slots[slot].active) {
1355 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot);
1356 return NULL;
1357 }
1358 if (offset < qxl->guest_slots[slot].delta) {
1359 qxl_set_guest_bug(qxl,
1360 "slot %d offset %"PRIu64" < delta %"PRIu64"\n",
1361 slot, offset, qxl->guest_slots[slot].delta);
1362 return NULL;
1363 }
1364 offset -= qxl->guest_slots[slot].delta;
1365 if (offset > qxl->guest_slots[slot].size) {
1366 qxl_set_guest_bug(qxl,
1367 "slot %d offset %"PRIu64" > size %"PRIu64"\n",
1368 slot, offset, qxl->guest_slots[slot].size);
1369 return NULL;
1370 }
1371 return qxl->guest_slots[slot].ptr + offset;
1372 }
1373 return NULL;
1374 }
1375
1376 static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1377 {
1378 /* for local rendering */
1379 qxl_render_resize(qxl);
1380 }
1381
1382 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1383 qxl_async_io async)
1384 {
1385 QXLDevSurfaceCreate surface;
1386 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
1387 uint32_t requested_height = le32_to_cpu(sc->height);
1388 int requested_stride = le32_to_cpu(sc->stride);
1389
1390 if (requested_stride == INT32_MIN ||
1391 abs(requested_stride) * (uint64_t)requested_height
1392 > qxl->vgamem_size) {
1393 qxl_set_guest_bug(qxl, "%s: requested primary larger than framebuffer"
1394 " stride %d x height %" PRIu32 " > %" PRIu32,
1395 __func__, requested_stride, requested_height,
1396 qxl->vgamem_size);
1397 return;
1398 }
1399
1400 if (qxl->mode == QXL_MODE_NATIVE) {
1401 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE",
1402 __func__);
1403 }
1404 qxl_exit_vga_mode(qxl);
1405
1406 surface.format = le32_to_cpu(sc->format);
1407 surface.height = le32_to_cpu(sc->height);
1408 surface.mem = le64_to_cpu(sc->mem);
1409 surface.position = le32_to_cpu(sc->position);
1410 surface.stride = le32_to_cpu(sc->stride);
1411 surface.width = le32_to_cpu(sc->width);
1412 surface.type = le32_to_cpu(sc->type);
1413 surface.flags = le32_to_cpu(sc->flags);
1414 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem,
1415 sc->format, sc->position);
1416 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type,
1417 sc->flags);
1418
1419 if ((surface.stride & 0x3) != 0) {
1420 qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0",
1421 surface.stride);
1422 return;
1423 }
1424
1425 surface.mouse_mode = true;
1426 surface.group_id = MEMSLOT_GROUP_GUEST;
1427 if (loadvm) {
1428 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1429 }
1430
1431 qxl->mode = QXL_MODE_NATIVE;
1432 qxl->cmdflags = 0;
1433 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
1434
1435 if (async == QXL_SYNC) {
1436 qxl_create_guest_primary_complete(qxl);
1437 }
1438 }
1439
1440 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1441 * done (in QXL_SYNC case), 0 otherwise. */
1442 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
1443 {
1444 if (d->mode == QXL_MODE_UNDEFINED) {
1445 return 0;
1446 }
1447 trace_qxl_destroy_primary(d->id);
1448 d->mode = QXL_MODE_UNDEFINED;
1449 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
1450 qxl_spice_reset_cursor(d);
1451 return 1;
1452 }
1453
1454 static void qxl_set_mode(PCIQXLDevice *d, unsigned int modenr, int loadvm)
1455 {
1456 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1457 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1458 QXLMode *mode = d->modes->modes + modenr;
1459 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1460 QXLMemSlot slot = {
1461 .mem_start = start,
1462 .mem_end = end
1463 };
1464
1465 if (modenr >= d->modes->n_modes) {
1466 qxl_set_guest_bug(d, "mode number out of range");
1467 return;
1468 }
1469
1470 QXLSurfaceCreate surface = {
1471 .width = mode->x_res,
1472 .height = mode->y_res,
1473 .stride = -mode->x_res * 4,
1474 .format = SPICE_SURFACE_FMT_32_xRGB,
1475 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1476 .mouse_mode = true,
1477 .mem = devmem + d->shadow_rom.draw_area_offset,
1478 };
1479
1480 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits,
1481 devmem);
1482 if (!loadvm) {
1483 qxl_hard_reset(d, 0);
1484 }
1485
1486 d->guest_slots[0].slot = slot;
1487 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0);
1488
1489 d->guest_primary.surface = surface;
1490 qxl_create_guest_primary(d, 0, QXL_SYNC);
1491
1492 d->mode = QXL_MODE_COMPAT;
1493 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
1494 if (mode->bits == 16) {
1495 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1496 }
1497 d->shadow_rom.mode = cpu_to_le32(modenr);
1498 d->rom->mode = cpu_to_le32(modenr);
1499 qxl_rom_set_dirty(d);
1500 }
1501
1502 static void ioport_write(void *opaque, hwaddr addr,
1503 uint64_t val, unsigned size)
1504 {
1505 PCIQXLDevice *d = opaque;
1506 uint32_t io_port = addr;
1507 qxl_async_io async = QXL_SYNC;
1508 uint32_t orig_io_port = io_port;
1509
1510 if (d->guest_bug && io_port != QXL_IO_RESET) {
1511 return;
1512 }
1513
1514 if (d->revision <= QXL_REVISION_STABLE_V10 &&
1515 io_port > QXL_IO_FLUSH_RELEASE) {
1516 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n",
1517 io_port, d->revision);
1518 return;
1519 }
1520
1521 switch (io_port) {
1522 case QXL_IO_RESET:
1523 case QXL_IO_SET_MODE:
1524 case QXL_IO_MEMSLOT_ADD:
1525 case QXL_IO_MEMSLOT_DEL:
1526 case QXL_IO_CREATE_PRIMARY:
1527 case QXL_IO_UPDATE_IRQ:
1528 case QXL_IO_LOG:
1529 case QXL_IO_MEMSLOT_ADD_ASYNC:
1530 case QXL_IO_CREATE_PRIMARY_ASYNC:
1531 break;
1532 default:
1533 if (d->mode != QXL_MODE_VGA) {
1534 break;
1535 }
1536 trace_qxl_io_unexpected_vga_mode(d->id,
1537 addr, val, io_port_to_string(io_port));
1538 /* be nice to buggy guest drivers */
1539 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
1540 io_port < QXL_IO_RANGE_SIZE) {
1541 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1542 }
1543 return;
1544 }
1545
1546 /* we change the io_port to avoid ifdeffery in the main switch */
1547 orig_io_port = io_port;
1548 switch (io_port) {
1549 case QXL_IO_UPDATE_AREA_ASYNC:
1550 io_port = QXL_IO_UPDATE_AREA;
1551 goto async_common;
1552 case QXL_IO_MEMSLOT_ADD_ASYNC:
1553 io_port = QXL_IO_MEMSLOT_ADD;
1554 goto async_common;
1555 case QXL_IO_CREATE_PRIMARY_ASYNC:
1556 io_port = QXL_IO_CREATE_PRIMARY;
1557 goto async_common;
1558 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1559 io_port = QXL_IO_DESTROY_PRIMARY;
1560 goto async_common;
1561 case QXL_IO_DESTROY_SURFACE_ASYNC:
1562 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1563 goto async_common;
1564 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1565 io_port = QXL_IO_DESTROY_ALL_SURFACES;
1566 goto async_common;
1567 case QXL_IO_FLUSH_SURFACES_ASYNC:
1568 case QXL_IO_MONITORS_CONFIG_ASYNC:
1569 async_common:
1570 async = QXL_ASYNC;
1571 qemu_mutex_lock(&d->async_lock);
1572 if (d->current_async != QXL_UNDEFINED_IO) {
1573 qxl_set_guest_bug(d, "%d async started before last (%d) complete",
1574 io_port, d->current_async);
1575 qemu_mutex_unlock(&d->async_lock);
1576 return;
1577 }
1578 d->current_async = orig_io_port;
1579 qemu_mutex_unlock(&d->async_lock);
1580 break;
1581 default:
1582 break;
1583 }
1584 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode),
1585 addr, io_port_to_string(addr),
1586 val, size, async);
1587
1588 switch (io_port) {
1589 case QXL_IO_UPDATE_AREA:
1590 {
1591 QXLCookie *cookie = NULL;
1592 QXLRect update = d->ram->update_area;
1593
1594 if (d->ram->update_surface > d->ssd.num_surfaces) {
1595 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1596 d->ram->update_surface);
1597 break;
1598 }
1599 if (update.left >= update.right || update.top >= update.bottom ||
1600 update.left < 0 || update.top < 0) {
1601 qxl_set_guest_bug(d,
1602 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1603 update.left, update.top, update.right, update.bottom);
1604 if (update.left == update.right || update.top == update.bottom) {
1605 /* old drivers may provide empty area, keep going */
1606 qxl_clear_guest_bug(d);
1607 goto cancel_async;
1608 }
1609 break;
1610 }
1611 if (async == QXL_ASYNC) {
1612 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
1613 QXL_IO_UPDATE_AREA_ASYNC);
1614 cookie->u.area = update;
1615 }
1616 qxl_spice_update_area(d, d->ram->update_surface,
1617 cookie ? &cookie->u.area : &update,
1618 NULL, 0, 0, async, cookie);
1619 break;
1620 }
1621 case QXL_IO_NOTIFY_CMD:
1622 qemu_spice_wakeup(&d->ssd);
1623 break;
1624 case QXL_IO_NOTIFY_CURSOR:
1625 qemu_spice_wakeup(&d->ssd);
1626 break;
1627 case QXL_IO_UPDATE_IRQ:
1628 qxl_update_irq(d);
1629 break;
1630 case QXL_IO_NOTIFY_OOM:
1631 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1632 break;
1633 }
1634 d->oom_running = 1;
1635 qxl_spice_oom(d);
1636 d->oom_running = 0;
1637 break;
1638 case QXL_IO_SET_MODE:
1639 qxl_set_mode(d, val, 0);
1640 break;
1641 case QXL_IO_LOG:
1642 trace_qxl_io_log(d->id, d->ram->log_buf);
1643 if (d->guestdebug) {
1644 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
1645 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), d->ram->log_buf);
1646 }
1647 break;
1648 case QXL_IO_RESET:
1649 qxl_hard_reset(d, 0);
1650 break;
1651 case QXL_IO_MEMSLOT_ADD:
1652 if (val >= NUM_MEMSLOTS) {
1653 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
1654 break;
1655 }
1656 if (d->guest_slots[val].active) {
1657 qxl_set_guest_bug(d,
1658 "QXL_IO_MEMSLOT_ADD: memory slot already active");
1659 break;
1660 }
1661 d->guest_slots[val].slot = d->ram->mem_slot;
1662 qxl_add_memslot(d, val, 0, async);
1663 break;
1664 case QXL_IO_MEMSLOT_DEL:
1665 if (val >= NUM_MEMSLOTS) {
1666 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
1667 break;
1668 }
1669 qxl_del_memslot(d, val);
1670 break;
1671 case QXL_IO_CREATE_PRIMARY:
1672 if (val != 0) {
1673 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1674 async);
1675 goto cancel_async;
1676 }
1677 d->guest_primary.surface = d->ram->create_surface;
1678 qxl_create_guest_primary(d, 0, async);
1679 break;
1680 case QXL_IO_DESTROY_PRIMARY:
1681 if (val != 0) {
1682 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1683 async);
1684 goto cancel_async;
1685 }
1686 if (!qxl_destroy_primary(d, async)) {
1687 trace_qxl_io_destroy_primary_ignored(d->id,
1688 qxl_mode_to_string(d->mode));
1689 goto cancel_async;
1690 }
1691 break;
1692 case QXL_IO_DESTROY_SURFACE_WAIT:
1693 if (val >= d->ssd.num_surfaces) {
1694 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
1695 "%" PRIu64 " >= NUM_SURFACES", async, val);
1696 goto cancel_async;
1697 }
1698 qxl_spice_destroy_surface_wait(d, val, async);
1699 break;
1700 case QXL_IO_FLUSH_RELEASE: {
1701 QXLReleaseRing *ring = &d->ram->release_ring;
1702 if (ring->prod - ring->cons + 1 == ring->num_items) {
1703 fprintf(stderr,
1704 "ERROR: no flush, full release ring [p%d,%dc]\n",
1705 ring->prod, ring->cons);
1706 }
1707 qxl_push_free_res(d, 1 /* flush */);
1708 break;
1709 }
1710 case QXL_IO_FLUSH_SURFACES_ASYNC:
1711 qxl_spice_flush_surfaces_async(d);
1712 break;
1713 case QXL_IO_DESTROY_ALL_SURFACES:
1714 d->mode = QXL_MODE_UNDEFINED;
1715 qxl_spice_destroy_surfaces(d, async);
1716 break;
1717 case QXL_IO_MONITORS_CONFIG_ASYNC:
1718 qxl_spice_monitors_config_async(d, 0);
1719 break;
1720 default:
1721 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port);
1722 }
1723 return;
1724 cancel_async:
1725 if (async) {
1726 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1727 qemu_mutex_lock(&d->async_lock);
1728 d->current_async = QXL_UNDEFINED_IO;
1729 qemu_mutex_unlock(&d->async_lock);
1730 }
1731 }
1732
1733 static uint64_t ioport_read(void *opaque, hwaddr addr,
1734 unsigned size)
1735 {
1736 PCIQXLDevice *qxl = opaque;
1737
1738 trace_qxl_io_read_unexpected(qxl->id);
1739 return 0xff;
1740 }
1741
1742 static const MemoryRegionOps qxl_io_ops = {
1743 .read = ioport_read,
1744 .write = ioport_write,
1745 .valid = {
1746 .min_access_size = 1,
1747 .max_access_size = 1,
1748 },
1749 };
1750
1751 static void qxl_update_irq_bh(void *opaque)
1752 {
1753 PCIQXLDevice *d = opaque;
1754 qxl_update_irq(d);
1755 }
1756
1757 static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1758 {
1759 uint32_t old_pending;
1760 uint32_t le_events = cpu_to_le32(events);
1761
1762 trace_qxl_send_events(d->id, events);
1763 if (!qemu_spice_display_is_running(&d->ssd)) {
1764 /* spice-server tracks guest running state and should not do this */
1765 fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n",
1766 __func__);
1767 trace_qxl_send_events_vm_stopped(d->id, events);
1768 return;
1769 }
1770 old_pending = atomic_fetch_or(&d->ram->int_pending, le_events);
1771 if ((old_pending & le_events) == le_events) {
1772 return;
1773 }
1774 qemu_bh_schedule(d->update_irq);
1775 }
1776
1777 /* graphics console */
1778
1779 static void qxl_hw_update(void *opaque)
1780 {
1781 PCIQXLDevice *qxl = opaque;
1782
1783 qxl_render_update(qxl);
1784 }
1785
1786 static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
1787 {
1788 uintptr_t vram_start;
1789 int i;
1790
1791 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
1792 return;
1793 }
1794
1795 /* dirty the primary surface */
1796 qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset,
1797 qxl->shadow_rom.surface0_area_size);
1798
1799 vram_start = (uintptr_t)memory_region_get_ram_ptr(&qxl->vram_bar);
1800
1801 /* dirty the off-screen surfaces */
1802 for (i = 0; i < qxl->ssd.num_surfaces; i++) {
1803 QXLSurfaceCmd *cmd;
1804 intptr_t surface_offset;
1805 int surface_size;
1806
1807 if (qxl->guest_surfaces.cmds[i] == 0) {
1808 continue;
1809 }
1810
1811 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1812 MEMSLOT_GROUP_GUEST);
1813 assert(cmd);
1814 assert(cmd->type == QXL_SURFACE_CMD_CREATE);
1815 surface_offset = (intptr_t)qxl_phys2virt(qxl,
1816 cmd->u.surface_create.data,
1817 MEMSLOT_GROUP_GUEST);
1818 assert(surface_offset);
1819 surface_offset -= vram_start;
1820 surface_size = cmd->u.surface_create.height *
1821 abs(cmd->u.surface_create.stride);
1822 trace_qxl_surfaces_dirty(qxl->id, i, (int)surface_offset, surface_size);
1823 qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size);
1824 }
1825 }
1826
1827 static void qxl_vm_change_state_handler(void *opaque, int running,
1828 RunState state)
1829 {
1830 PCIQXLDevice *qxl = opaque;
1831
1832 if (running) {
1833 /*
1834 * if qxl_send_events was called from spice server context before
1835 * migration ended, qxl_update_irq for these events might not have been
1836 * called
1837 */
1838 qxl_update_irq(qxl);
1839 } else {
1840 /* make sure surfaces are saved before migration */
1841 qxl_dirty_surfaces(qxl);
1842 }
1843 }
1844
1845 /* display change listener */
1846
1847 static void display_update(DisplayChangeListener *dcl,
1848 int x, int y, int w, int h)
1849 {
1850 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1851
1852 if (qxl->mode == QXL_MODE_VGA) {
1853 qemu_spice_display_update(&qxl->ssd, x, y, w, h);
1854 }
1855 }
1856
1857 static void display_switch(DisplayChangeListener *dcl,
1858 struct DisplaySurface *surface)
1859 {
1860 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1861
1862 qxl->ssd.ds = surface;
1863 if (qxl->mode == QXL_MODE_VGA) {
1864 qemu_spice_display_switch(&qxl->ssd, surface);
1865 }
1866 }
1867
1868 static void display_refresh(DisplayChangeListener *dcl)
1869 {
1870 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1871
1872 if (qxl->mode == QXL_MODE_VGA) {
1873 qemu_spice_display_refresh(&qxl->ssd);
1874 }
1875 }
1876
1877 static DisplayChangeListenerOps display_listener_ops = {
1878 .dpy_name = "spice/qxl",
1879 .dpy_gfx_update = display_update,
1880 .dpy_gfx_switch = display_switch,
1881 .dpy_refresh = display_refresh,
1882 };
1883
1884 static void qxl_init_ramsize(PCIQXLDevice *qxl)
1885 {
1886 /* vga mode framebuffer / primary surface (bar 0, first part) */
1887 if (qxl->vgamem_size_mb < 8) {
1888 qxl->vgamem_size_mb = 8;
1889 }
1890 /* XXX: we round vgamem_size_mb up to a nearest power of two and it must be
1891 * less than vga_common_init()'s maximum on qxl->vga.vram_size (512 now).
1892 */
1893 if (qxl->vgamem_size_mb > 256) {
1894 qxl->vgamem_size_mb = 256;
1895 }
1896 qxl->vgamem_size = qxl->vgamem_size_mb * 1024 * 1024;
1897
1898 /* vga ram (bar 0, total) */
1899 if (qxl->ram_size_mb != -1) {
1900 qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024;
1901 }
1902 if (qxl->vga.vram_size < qxl->vgamem_size * 2) {
1903 qxl->vga.vram_size = qxl->vgamem_size * 2;
1904 }
1905
1906 /* vram32 (surfaces, 32bit, bar 1) */
1907 if (qxl->vram32_size_mb != -1) {
1908 qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024;
1909 }
1910 if (qxl->vram32_size < 4096) {
1911 qxl->vram32_size = 4096;
1912 }
1913
1914 /* vram (surfaces, 64bit, bar 4+5) */
1915 if (qxl->vram_size_mb != -1) {
1916 qxl->vram_size = qxl->vram_size_mb * 1024 * 1024;
1917 }
1918 if (qxl->vram_size < qxl->vram32_size) {
1919 qxl->vram_size = qxl->vram32_size;
1920 }
1921
1922 if (qxl->revision == 1) {
1923 qxl->vram32_size = 4096;
1924 qxl->vram_size = 4096;
1925 }
1926 qxl->vgamem_size = pow2ceil(qxl->vgamem_size);
1927 qxl->vga.vram_size = pow2ceil(qxl->vga.vram_size);
1928 qxl->vram32_size = pow2ceil(qxl->vram32_size);
1929 qxl->vram_size = pow2ceil(qxl->vram_size);
1930 }
1931
1932 static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp)
1933 {
1934 uint8_t* config = qxl->pci.config;
1935 uint32_t pci_device_rev;
1936 uint32_t io_size;
1937
1938 qxl->mode = QXL_MODE_UNDEFINED;
1939 qxl->generation = 1;
1940 qxl->num_memslots = NUM_MEMSLOTS;
1941 qemu_mutex_init(&qxl->track_lock);
1942 qemu_mutex_init(&qxl->async_lock);
1943 qxl->current_async = QXL_UNDEFINED_IO;
1944 qxl->guest_bug = 0;
1945
1946 switch (qxl->revision) {
1947 case 1: /* spice 0.4 -- qxl-1 */
1948 pci_device_rev = QXL_REVISION_STABLE_V04;
1949 io_size = 8;
1950 break;
1951 case 2: /* spice 0.6 -- qxl-2 */
1952 pci_device_rev = QXL_REVISION_STABLE_V06;
1953 io_size = 16;
1954 break;
1955 case 3: /* qxl-3 */
1956 pci_device_rev = QXL_REVISION_STABLE_V10;
1957 io_size = 32; /* PCI region size must be pow2 */
1958 break;
1959 case 4: /* qxl-4 */
1960 pci_device_rev = QXL_REVISION_STABLE_V12;
1961 io_size = pow2ceil(QXL_IO_RANGE_SIZE);
1962 break;
1963 default:
1964 error_setg(errp, "Invalid revision %d for qxl device (max %d)",
1965 qxl->revision, QXL_DEFAULT_REVISION);
1966 return;
1967 }
1968
1969 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
1970 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
1971
1972 qxl->rom_size = qxl_rom_size();
1973 memory_region_init_ram(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom",
1974 qxl->rom_size, &error_abort);
1975 vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev);
1976 init_qxl_rom(qxl);
1977 init_qxl_ram(qxl);
1978
1979 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces);
1980 memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram",
1981 qxl->vram_size, &error_abort);
1982 vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev);
1983 memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), "qxl.vram32",
1984 &qxl->vram_bar, 0, qxl->vram32_size);
1985
1986 memory_region_init_io(&qxl->io_bar, OBJECT(qxl), &qxl_io_ops, qxl,
1987 "qxl-ioports", io_size);
1988 if (qxl->id == 0) {
1989 vga_dirty_log_start(&qxl->vga);
1990 }
1991 memory_region_set_flush_coalesced(&qxl->io_bar);
1992
1993
1994 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
1995 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
1996
1997 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
1998 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
1999
2000 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
2001 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
2002
2003 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
2004 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar);
2005
2006 if (qxl->vram32_size < qxl->vram_size) {
2007 /*
2008 * Make the 64bit vram bar show up only in case it is
2009 * configured to be larger than the 32bit vram bar.
2010 */
2011 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX,
2012 PCI_BASE_ADDRESS_SPACE_MEMORY |
2013 PCI_BASE_ADDRESS_MEM_TYPE_64 |
2014 PCI_BASE_ADDRESS_MEM_PREFETCH,
2015 &qxl->vram_bar);
2016 }
2017
2018 /* print pci bar details */
2019 dprint(qxl, 1, "ram/%s: %d MB [region 0]\n",
2020 qxl->id == 0 ? "pri" : "sec",
2021 qxl->vga.vram_size / (1024*1024));
2022 dprint(qxl, 1, "vram/32: %d MB [region 1]\n",
2023 qxl->vram32_size / (1024*1024));
2024 dprint(qxl, 1, "vram/64: %d MB %s\n",
2025 qxl->vram_size / (1024*1024),
2026 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
2027
2028 qxl->ssd.qxl.base.sif = &qxl_interface.base;
2029 if (qemu_spice_add_display_interface(&qxl->ssd.qxl, qxl->vga.con) != 0) {
2030 error_setg(errp, "qxl interface %d.%d not supported by spice-server",
2031 SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR);
2032 return;
2033 }
2034 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
2035
2036 qxl->update_irq = qemu_bh_new(qxl_update_irq_bh, qxl);
2037 qxl_reset_state(qxl);
2038
2039 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl);
2040 qxl->ssd.cursor_bh = qemu_bh_new(qemu_spice_cursor_refresh_bh, &qxl->ssd);
2041 }
2042
2043 static void qxl_realize_primary(PCIDevice *dev, Error **errp)
2044 {
2045 PCIQXLDevice *qxl = PCI_QXL(dev);
2046 VGACommonState *vga = &qxl->vga;
2047 Error *local_err = NULL;
2048
2049 qxl->id = 0;
2050 qxl_init_ramsize(qxl);
2051 vga->vbe_size = qxl->vgamem_size;
2052 vga->vram_size_mb = qxl->vga.vram_size >> 20;
2053 vga_common_init(vga, OBJECT(dev), true);
2054 vga_init(vga, OBJECT(dev),
2055 pci_address_space(dev), pci_address_space_io(dev), false);
2056 portio_list_init(&qxl->vga_port_list, OBJECT(dev), qxl_vga_portio_list,
2057 vga, "vga");
2058 portio_list_set_flush_coalesced(&qxl->vga_port_list);
2059 portio_list_add(&qxl->vga_port_list, pci_address_space_io(dev), 0x3b0);
2060
2061 vga->con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
2062 qemu_spice_display_init_common(&qxl->ssd);
2063
2064 qxl_realize_common(qxl, &local_err);
2065 if (local_err) {
2066 error_propagate(errp, local_err);
2067 return;
2068 }
2069
2070 qxl->ssd.dcl.ops = &display_listener_ops;
2071 qxl->ssd.dcl.con = vga->con;
2072 register_displaychangelistener(&qxl->ssd.dcl);
2073 }
2074
2075 static void qxl_realize_secondary(PCIDevice *dev, Error **errp)
2076 {
2077 static int device_id = 1;
2078 PCIQXLDevice *qxl = PCI_QXL(dev);
2079
2080 qxl->id = device_id++;
2081 qxl_init_ramsize(qxl);
2082 memory_region_init_ram(&qxl->vga.vram, OBJECT(dev), "qxl.vgavram",
2083 qxl->vga.vram_size, &error_abort);
2084 vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev);
2085 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
2086 qxl->vga.con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
2087
2088 qxl_realize_common(qxl, errp);
2089 }
2090
2091 static void qxl_pre_save(void *opaque)
2092 {
2093 PCIQXLDevice* d = opaque;
2094 uint8_t *ram_start = d->vga.vram_ptr;
2095
2096 trace_qxl_pre_save(d->id);
2097 if (d->last_release == NULL) {
2098 d->last_release_offset = 0;
2099 } else {
2100 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
2101 }
2102 assert(d->last_release_offset < d->vga.vram_size);
2103 }
2104
2105 static int qxl_pre_load(void *opaque)
2106 {
2107 PCIQXLDevice* d = opaque;
2108
2109 trace_qxl_pre_load(d->id);
2110 qxl_hard_reset(d, 1);
2111 qxl_exit_vga_mode(d);
2112 return 0;
2113 }
2114
2115 static void qxl_create_memslots(PCIQXLDevice *d)
2116 {
2117 int i;
2118
2119 for (i = 0; i < NUM_MEMSLOTS; i++) {
2120 if (!d->guest_slots[i].active) {
2121 continue;
2122 }
2123 qxl_add_memslot(d, i, 0, QXL_SYNC);
2124 }
2125 }
2126
2127 static int qxl_post_load(void *opaque, int version)
2128 {
2129 PCIQXLDevice* d = opaque;
2130 uint8_t *ram_start = d->vga.vram_ptr;
2131 QXLCommandExt *cmds;
2132 int in, out, newmode;
2133
2134 assert(d->last_release_offset < d->vga.vram_size);
2135 if (d->last_release_offset == 0) {
2136 d->last_release = NULL;
2137 } else {
2138 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
2139 }
2140
2141 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
2142
2143 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode));
2144 newmode = d->mode;
2145 d->mode = QXL_MODE_UNDEFINED;
2146
2147 switch (newmode) {
2148 case QXL_MODE_UNDEFINED:
2149 qxl_create_memslots(d);
2150 break;
2151 case QXL_MODE_VGA:
2152 qxl_create_memslots(d);
2153 qxl_enter_vga_mode(d);
2154 break;
2155 case QXL_MODE_NATIVE:
2156 qxl_create_memslots(d);
2157 qxl_create_guest_primary(d, 1, QXL_SYNC);
2158
2159 /* replay surface-create and cursor-set commands */
2160 cmds = g_malloc0(sizeof(QXLCommandExt) * (d->ssd.num_surfaces + 1));
2161 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) {
2162 if (d->guest_surfaces.cmds[in] == 0) {
2163 continue;
2164 }
2165 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
2166 cmds[out].cmd.type = QXL_CMD_SURFACE;
2167 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2168 out++;
2169 }
2170 if (d->guest_cursor) {
2171 cmds[out].cmd.data = d->guest_cursor;
2172 cmds[out].cmd.type = QXL_CMD_CURSOR;
2173 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2174 out++;
2175 }
2176 qxl_spice_loadvm_commands(d, cmds, out);
2177 g_free(cmds);
2178 if (d->guest_monitors_config) {
2179 qxl_spice_monitors_config_async(d, 1);
2180 }
2181 break;
2182 case QXL_MODE_COMPAT:
2183 /* note: no need to call qxl_create_memslots, qxl_set_mode
2184 * creates the mem slot. */
2185 qxl_set_mode(d, d->shadow_rom.mode, 1);
2186 break;
2187 }
2188 return 0;
2189 }
2190
2191 #define QXL_SAVE_VERSION 21
2192
2193 static bool qxl_monitors_config_needed(void *opaque)
2194 {
2195 PCIQXLDevice *qxl = opaque;
2196
2197 return qxl->guest_monitors_config != 0;
2198 }
2199
2200
2201 static VMStateDescription qxl_memslot = {
2202 .name = "qxl-memslot",
2203 .version_id = QXL_SAVE_VERSION,
2204 .minimum_version_id = QXL_SAVE_VERSION,
2205 .fields = (VMStateField[]) {
2206 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
2207 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
2208 VMSTATE_UINT32(active, struct guest_slots),
2209 VMSTATE_END_OF_LIST()
2210 }
2211 };
2212
2213 static VMStateDescription qxl_surface = {
2214 .name = "qxl-surface",
2215 .version_id = QXL_SAVE_VERSION,
2216 .minimum_version_id = QXL_SAVE_VERSION,
2217 .fields = (VMStateField[]) {
2218 VMSTATE_UINT32(width, QXLSurfaceCreate),
2219 VMSTATE_UINT32(height, QXLSurfaceCreate),
2220 VMSTATE_INT32(stride, QXLSurfaceCreate),
2221 VMSTATE_UINT32(format, QXLSurfaceCreate),
2222 VMSTATE_UINT32(position, QXLSurfaceCreate),
2223 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
2224 VMSTATE_UINT32(flags, QXLSurfaceCreate),
2225 VMSTATE_UINT32(type, QXLSurfaceCreate),
2226 VMSTATE_UINT64(mem, QXLSurfaceCreate),
2227 VMSTATE_END_OF_LIST()
2228 }
2229 };
2230
2231 static VMStateDescription qxl_vmstate_monitors_config = {
2232 .name = "qxl/monitors-config",
2233 .version_id = 1,
2234 .minimum_version_id = 1,
2235 .needed = qxl_monitors_config_needed,
2236 .fields = (VMStateField[]) {
2237 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice),
2238 VMSTATE_END_OF_LIST()
2239 },
2240 };
2241
2242 static VMStateDescription qxl_vmstate = {
2243 .name = "qxl",
2244 .version_id = QXL_SAVE_VERSION,
2245 .minimum_version_id = QXL_SAVE_VERSION,
2246 .pre_save = qxl_pre_save,
2247 .pre_load = qxl_pre_load,
2248 .post_load = qxl_post_load,
2249 .fields = (VMStateField[]) {
2250 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
2251 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
2252 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
2253 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
2254 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
2255 VMSTATE_UINT32(mode, PCIQXLDevice),
2256 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
2257 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice),
2258 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
2259 qxl_memslot, struct guest_slots),
2260 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
2261 qxl_surface, QXLSurfaceCreate),
2262 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice),
2263 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice,
2264 ssd.num_surfaces, 0,
2265 vmstate_info_uint64, uint64_t),
2266 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
2267 VMSTATE_END_OF_LIST()
2268 },
2269 .subsections = (const VMStateDescription*[]) {
2270 &qxl_vmstate_monitors_config,
2271 NULL
2272 }
2273 };
2274
2275 static Property qxl_properties[] = {
2276 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
2277 64 * 1024 * 1024),
2278 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram32_size,
2279 64 * 1024 * 1024),
2280 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
2281 QXL_DEFAULT_REVISION),
2282 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
2283 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
2284 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
2285 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1),
2286 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1),
2287 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1),
2288 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16),
2289 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024),
2290 #if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
2291 DEFINE_PROP_UINT16("max_outputs", PCIQXLDevice, max_outputs, 0),
2292 #endif
2293 DEFINE_PROP_END_OF_LIST(),
2294 };
2295
2296 static void qxl_pci_class_init(ObjectClass *klass, void *data)
2297 {
2298 DeviceClass *dc = DEVICE_CLASS(klass);
2299 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2300
2301 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2302 k->device_id = QXL_DEVICE_ID_STABLE;
2303 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
2304 dc->reset = qxl_reset_handler;
2305 dc->vmsd = &qxl_vmstate;
2306 dc->props = qxl_properties;
2307 }
2308
2309 static const TypeInfo qxl_pci_type_info = {
2310 .name = TYPE_PCI_QXL,
2311 .parent = TYPE_PCI_DEVICE,
2312 .instance_size = sizeof(PCIQXLDevice),
2313 .abstract = true,
2314 .class_init = qxl_pci_class_init,
2315 };
2316
2317 static void qxl_primary_class_init(ObjectClass *klass, void *data)
2318 {
2319 DeviceClass *dc = DEVICE_CLASS(klass);
2320 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2321
2322 k->realize = qxl_realize_primary;
2323 k->romfile = "vgabios-qxl.bin";
2324 k->class_id = PCI_CLASS_DISPLAY_VGA;
2325 dc->desc = "Spice QXL GPU (primary, vga compatible)";
2326 dc->hotpluggable = false;
2327 }
2328
2329 static const TypeInfo qxl_primary_info = {
2330 .name = "qxl-vga",
2331 .parent = TYPE_PCI_QXL,
2332 .class_init = qxl_primary_class_init,
2333 };
2334
2335 static void qxl_secondary_class_init(ObjectClass *klass, void *data)
2336 {
2337 DeviceClass *dc = DEVICE_CLASS(klass);
2338 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2339
2340 k->realize = qxl_realize_secondary;
2341 k->class_id = PCI_CLASS_DISPLAY_OTHER;
2342 dc->desc = "Spice QXL GPU (secondary)";
2343 }
2344
2345 static const TypeInfo qxl_secondary_info = {
2346 .name = "qxl",
2347 .parent = TYPE_PCI_QXL,
2348 .class_init = qxl_secondary_class_init,
2349 };
2350
2351 static void qxl_register_types(void)
2352 {
2353 type_register_static(&qxl_pci_type_info);
2354 type_register_static(&qxl_primary_info);
2355 type_register_static(&qxl_secondary_info);
2356 }
2357
2358 type_init(qxl_register_types)