sm501: Add missing arbitration control register
[qemu.git] / hw / display / sm501.c
1 /*
2 * QEMU SM501 Device
3 *
4 * Copyright (c) 2008 Shin-ichiro KAWASAKI
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/cutils.h"
27 #include "qapi/error.h"
28 #include "qemu-common.h"
29 #include "cpu.h"
30 #include "hw/hw.h"
31 #include "hw/char/serial.h"
32 #include "ui/console.h"
33 #include "hw/devices.h"
34 #include "hw/sysbus.h"
35 #include "qemu/range.h"
36 #include "ui/pixel_ops.h"
37 #include "exec/address-spaces.h"
38
39 /*
40 * Status: 2010/05/07
41 * - Minimum implementation for Linux console : mmio regs and CRT layer.
42 * - 2D graphics acceleration partially supported : only fill rectangle.
43 *
44 * TODO:
45 * - Panel support
46 * - Touch panel support
47 * - USB support
48 * - UART support
49 * - More 2D graphics engine support
50 * - Performance tuning
51 */
52
53 /*#define DEBUG_SM501*/
54 /*#define DEBUG_BITBLT*/
55
56 #ifdef DEBUG_SM501
57 #define SM501_DPRINTF(fmt, ...) printf(fmt, ## __VA_ARGS__)
58 #else
59 #define SM501_DPRINTF(fmt, ...) do {} while (0)
60 #endif
61
62
63 #define MMIO_BASE_OFFSET 0x3e00000
64
65 /* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" */
66
67 /* System Configuration area */
68 /* System config base */
69 #define SM501_SYS_CONFIG (0x000000)
70
71 /* config 1 */
72 #define SM501_SYSTEM_CONTROL (0x000000)
73
74 #define SM501_SYSCTRL_PANEL_TRISTATE (1 << 0)
75 #define SM501_SYSCTRL_MEM_TRISTATE (1 << 1)
76 #define SM501_SYSCTRL_CRT_TRISTATE (1 << 2)
77
78 #define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3 << 4)
79 #define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0 << 4)
80 #define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1 << 4)
81 #define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2 << 4)
82 #define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3 << 4)
83
84 #define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1 << 6)
85 #define SM501_SYSCTRL_PCI_RETRY_DISABLE (1 << 7)
86 #define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1 << 11)
87 #define SM501_SYSCTRL_PCI_BURST_READ_EN (1 << 15)
88
89 /* miscellaneous control */
90
91 #define SM501_MISC_CONTROL (0x000004)
92
93 #define SM501_MISC_BUS_SH (0x0)
94 #define SM501_MISC_BUS_PCI (0x1)
95 #define SM501_MISC_BUS_XSCALE (0x2)
96 #define SM501_MISC_BUS_NEC (0x6)
97 #define SM501_MISC_BUS_MASK (0x7)
98
99 #define SM501_MISC_VR_62MB (1 << 3)
100 #define SM501_MISC_CDR_RESET (1 << 7)
101 #define SM501_MISC_USB_LB (1 << 8)
102 #define SM501_MISC_USB_SLAVE (1 << 9)
103 #define SM501_MISC_BL_1 (1 << 10)
104 #define SM501_MISC_MC (1 << 11)
105 #define SM501_MISC_DAC_POWER (1 << 12)
106 #define SM501_MISC_IRQ_INVERT (1 << 16)
107 #define SM501_MISC_SH (1 << 17)
108
109 #define SM501_MISC_HOLD_EMPTY (0 << 18)
110 #define SM501_MISC_HOLD_8 (1 << 18)
111 #define SM501_MISC_HOLD_16 (2 << 18)
112 #define SM501_MISC_HOLD_24 (3 << 18)
113 #define SM501_MISC_HOLD_32 (4 << 18)
114 #define SM501_MISC_HOLD_MASK (7 << 18)
115
116 #define SM501_MISC_FREQ_12 (1 << 24)
117 #define SM501_MISC_PNL_24BIT (1 << 25)
118 #define SM501_MISC_8051_LE (1 << 26)
119
120
121
122 #define SM501_GPIO31_0_CONTROL (0x000008)
123 #define SM501_GPIO63_32_CONTROL (0x00000C)
124 #define SM501_DRAM_CONTROL (0x000010)
125
126 /* command list */
127 #define SM501_ARBTRTN_CONTROL (0x000014)
128
129 /* command list */
130 #define SM501_COMMAND_LIST_STATUS (0x000024)
131
132 /* interrupt debug */
133 #define SM501_RAW_IRQ_STATUS (0x000028)
134 #define SM501_RAW_IRQ_CLEAR (0x000028)
135 #define SM501_IRQ_STATUS (0x00002C)
136 #define SM501_IRQ_MASK (0x000030)
137 #define SM501_DEBUG_CONTROL (0x000034)
138
139 /* power management */
140 #define SM501_POWERMODE_P2X_SRC (1 << 29)
141 #define SM501_POWERMODE_V2X_SRC (1 << 20)
142 #define SM501_POWERMODE_M_SRC (1 << 12)
143 #define SM501_POWERMODE_M1_SRC (1 << 4)
144
145 #define SM501_CURRENT_GATE (0x000038)
146 #define SM501_CURRENT_CLOCK (0x00003C)
147 #define SM501_POWER_MODE_0_GATE (0x000040)
148 #define SM501_POWER_MODE_0_CLOCK (0x000044)
149 #define SM501_POWER_MODE_1_GATE (0x000048)
150 #define SM501_POWER_MODE_1_CLOCK (0x00004C)
151 #define SM501_SLEEP_MODE_GATE (0x000050)
152 #define SM501_POWER_MODE_CONTROL (0x000054)
153
154 /* power gates for units within the 501 */
155 #define SM501_GATE_HOST (0)
156 #define SM501_GATE_MEMORY (1)
157 #define SM501_GATE_DISPLAY (2)
158 #define SM501_GATE_2D_ENGINE (3)
159 #define SM501_GATE_CSC (4)
160 #define SM501_GATE_ZVPORT (5)
161 #define SM501_GATE_GPIO (6)
162 #define SM501_GATE_UART0 (7)
163 #define SM501_GATE_UART1 (8)
164 #define SM501_GATE_SSP (10)
165 #define SM501_GATE_USB_HOST (11)
166 #define SM501_GATE_USB_GADGET (12)
167 #define SM501_GATE_UCONTROLLER (17)
168 #define SM501_GATE_AC97 (18)
169
170 /* panel clock */
171 #define SM501_CLOCK_P2XCLK (24)
172 /* crt clock */
173 #define SM501_CLOCK_V2XCLK (16)
174 /* main clock */
175 #define SM501_CLOCK_MCLK (8)
176 /* SDRAM controller clock */
177 #define SM501_CLOCK_M1XCLK (0)
178
179 /* config 2 */
180 #define SM501_PCI_MASTER_BASE (0x000058)
181 #define SM501_ENDIAN_CONTROL (0x00005C)
182 #define SM501_DEVICEID (0x000060)
183 /* 0x050100A0 */
184
185 #define SM501_DEVICEID_SM501 (0x05010000)
186 #define SM501_DEVICEID_IDMASK (0xffff0000)
187 #define SM501_DEVICEID_REVMASK (0x000000ff)
188
189 #define SM501_PLLCLOCK_COUNT (0x000064)
190 #define SM501_MISC_TIMING (0x000068)
191 #define SM501_CURRENT_SDRAM_CLOCK (0x00006C)
192
193 #define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074)
194
195 /* GPIO base */
196 #define SM501_GPIO (0x010000)
197 #define SM501_GPIO_DATA_LOW (0x00)
198 #define SM501_GPIO_DATA_HIGH (0x04)
199 #define SM501_GPIO_DDR_LOW (0x08)
200 #define SM501_GPIO_DDR_HIGH (0x0C)
201 #define SM501_GPIO_IRQ_SETUP (0x10)
202 #define SM501_GPIO_IRQ_STATUS (0x14)
203 #define SM501_GPIO_IRQ_RESET (0x14)
204
205 /* I2C controller base */
206 #define SM501_I2C (0x010040)
207 #define SM501_I2C_BYTE_COUNT (0x00)
208 #define SM501_I2C_CONTROL (0x01)
209 #define SM501_I2C_STATUS (0x02)
210 #define SM501_I2C_RESET (0x02)
211 #define SM501_I2C_SLAVE_ADDRESS (0x03)
212 #define SM501_I2C_DATA (0x04)
213
214 /* SSP base */
215 #define SM501_SSP (0x020000)
216
217 /* Uart 0 base */
218 #define SM501_UART0 (0x030000)
219
220 /* Uart 1 base */
221 #define SM501_UART1 (0x030020)
222
223 /* USB host port base */
224 #define SM501_USB_HOST (0x040000)
225
226 /* USB slave/gadget base */
227 #define SM501_USB_GADGET (0x060000)
228
229 /* USB slave/gadget data port base */
230 #define SM501_USB_GADGET_DATA (0x070000)
231
232 /* Display controller/video engine base */
233 #define SM501_DC (0x080000)
234
235 /* common defines for the SM501 address registers */
236 #define SM501_ADDR_FLIP (1 << 31)
237 #define SM501_ADDR_EXT (1 << 27)
238 #define SM501_ADDR_CS1 (1 << 26)
239 #define SM501_ADDR_MASK (0x3f << 26)
240
241 #define SM501_FIFO_MASK (0x3 << 16)
242 #define SM501_FIFO_1 (0x0 << 16)
243 #define SM501_FIFO_3 (0x1 << 16)
244 #define SM501_FIFO_7 (0x2 << 16)
245 #define SM501_FIFO_11 (0x3 << 16)
246
247 /* common registers for panel and the crt */
248 #define SM501_OFF_DC_H_TOT (0x000)
249 #define SM501_OFF_DC_V_TOT (0x008)
250 #define SM501_OFF_DC_H_SYNC (0x004)
251 #define SM501_OFF_DC_V_SYNC (0x00C)
252
253 #define SM501_DC_PANEL_CONTROL (0x000)
254
255 #define SM501_DC_PANEL_CONTROL_FPEN (1 << 27)
256 #define SM501_DC_PANEL_CONTROL_BIAS (1 << 26)
257 #define SM501_DC_PANEL_CONTROL_DATA (1 << 25)
258 #define SM501_DC_PANEL_CONTROL_VDD (1 << 24)
259 #define SM501_DC_PANEL_CONTROL_DP (1 << 23)
260
261 #define SM501_DC_PANEL_CONTROL_TFT_888 (0 << 21)
262 #define SM501_DC_PANEL_CONTROL_TFT_333 (1 << 21)
263 #define SM501_DC_PANEL_CONTROL_TFT_444 (2 << 21)
264
265 #define SM501_DC_PANEL_CONTROL_DE (1 << 20)
266
267 #define SM501_DC_PANEL_CONTROL_LCD_TFT (0 << 18)
268 #define SM501_DC_PANEL_CONTROL_LCD_STN8 (1 << 18)
269 #define SM501_DC_PANEL_CONTROL_LCD_STN12 (2 << 18)
270
271 #define SM501_DC_PANEL_CONTROL_CP (1 << 14)
272 #define SM501_DC_PANEL_CONTROL_VSP (1 << 13)
273 #define SM501_DC_PANEL_CONTROL_HSP (1 << 12)
274 #define SM501_DC_PANEL_CONTROL_CK (1 << 9)
275 #define SM501_DC_PANEL_CONTROL_TE (1 << 8)
276 #define SM501_DC_PANEL_CONTROL_VPD (1 << 7)
277 #define SM501_DC_PANEL_CONTROL_VP (1 << 6)
278 #define SM501_DC_PANEL_CONTROL_HPD (1 << 5)
279 #define SM501_DC_PANEL_CONTROL_HP (1 << 4)
280 #define SM501_DC_PANEL_CONTROL_GAMMA (1 << 3)
281 #define SM501_DC_PANEL_CONTROL_EN (1 << 2)
282
283 #define SM501_DC_PANEL_CONTROL_8BPP (0 << 0)
284 #define SM501_DC_PANEL_CONTROL_16BPP (1 << 0)
285 #define SM501_DC_PANEL_CONTROL_32BPP (2 << 0)
286
287
288 #define SM501_DC_PANEL_PANNING_CONTROL (0x004)
289 #define SM501_DC_PANEL_COLOR_KEY (0x008)
290 #define SM501_DC_PANEL_FB_ADDR (0x00C)
291 #define SM501_DC_PANEL_FB_OFFSET (0x010)
292 #define SM501_DC_PANEL_FB_WIDTH (0x014)
293 #define SM501_DC_PANEL_FB_HEIGHT (0x018)
294 #define SM501_DC_PANEL_TL_LOC (0x01C)
295 #define SM501_DC_PANEL_BR_LOC (0x020)
296 #define SM501_DC_PANEL_H_TOT (0x024)
297 #define SM501_DC_PANEL_H_SYNC (0x028)
298 #define SM501_DC_PANEL_V_TOT (0x02C)
299 #define SM501_DC_PANEL_V_SYNC (0x030)
300 #define SM501_DC_PANEL_CUR_LINE (0x034)
301
302 #define SM501_DC_VIDEO_CONTROL (0x040)
303 #define SM501_DC_VIDEO_FB0_ADDR (0x044)
304 #define SM501_DC_VIDEO_FB_WIDTH (0x048)
305 #define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C)
306 #define SM501_DC_VIDEO_TL_LOC (0x050)
307 #define SM501_DC_VIDEO_BR_LOC (0x054)
308 #define SM501_DC_VIDEO_SCALE (0x058)
309 #define SM501_DC_VIDEO_INIT_SCALE (0x05C)
310 #define SM501_DC_VIDEO_YUV_CONSTANTS (0x060)
311 #define SM501_DC_VIDEO_FB1_ADDR (0x064)
312 #define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068)
313
314 #define SM501_DC_VIDEO_ALPHA_CONTROL (0x080)
315 #define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084)
316 #define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088)
317 #define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C)
318 #define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090)
319 #define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094)
320 #define SM501_DC_VIDEO_ALPHA_SCALE (0x098)
321 #define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C)
322 #define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0)
323 #define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4)
324
325 #define SM501_DC_PANEL_HWC_BASE (0x0F0)
326 #define SM501_DC_PANEL_HWC_ADDR (0x0F0)
327 #define SM501_DC_PANEL_HWC_LOC (0x0F4)
328 #define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8)
329 #define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC)
330
331 #define SM501_HWC_EN (1 << 31)
332
333 #define SM501_OFF_HWC_ADDR (0x00)
334 #define SM501_OFF_HWC_LOC (0x04)
335 #define SM501_OFF_HWC_COLOR_1_2 (0x08)
336 #define SM501_OFF_HWC_COLOR_3 (0x0C)
337
338 #define SM501_DC_ALPHA_CONTROL (0x100)
339 #define SM501_DC_ALPHA_FB_ADDR (0x104)
340 #define SM501_DC_ALPHA_FB_OFFSET (0x108)
341 #define SM501_DC_ALPHA_TL_LOC (0x10C)
342 #define SM501_DC_ALPHA_BR_LOC (0x110)
343 #define SM501_DC_ALPHA_CHROMA_KEY (0x114)
344 #define SM501_DC_ALPHA_COLOR_LOOKUP (0x118)
345
346 #define SM501_DC_CRT_CONTROL (0x200)
347
348 #define SM501_DC_CRT_CONTROL_TVP (1 << 15)
349 #define SM501_DC_CRT_CONTROL_CP (1 << 14)
350 #define SM501_DC_CRT_CONTROL_VSP (1 << 13)
351 #define SM501_DC_CRT_CONTROL_HSP (1 << 12)
352 #define SM501_DC_CRT_CONTROL_VS (1 << 11)
353 #define SM501_DC_CRT_CONTROL_BLANK (1 << 10)
354 #define SM501_DC_CRT_CONTROL_SEL (1 << 9)
355 #define SM501_DC_CRT_CONTROL_TE (1 << 8)
356 #define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4)
357 #define SM501_DC_CRT_CONTROL_GAMMA (1 << 3)
358 #define SM501_DC_CRT_CONTROL_ENABLE (1 << 2)
359
360 #define SM501_DC_CRT_CONTROL_8BPP (0 << 0)
361 #define SM501_DC_CRT_CONTROL_16BPP (1 << 0)
362 #define SM501_DC_CRT_CONTROL_32BPP (2 << 0)
363
364 #define SM501_DC_CRT_FB_ADDR (0x204)
365 #define SM501_DC_CRT_FB_OFFSET (0x208)
366 #define SM501_DC_CRT_H_TOT (0x20C)
367 #define SM501_DC_CRT_H_SYNC (0x210)
368 #define SM501_DC_CRT_V_TOT (0x214)
369 #define SM501_DC_CRT_V_SYNC (0x218)
370 #define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C)
371 #define SM501_DC_CRT_CUR_LINE (0x220)
372 #define SM501_DC_CRT_MONITOR_DETECT (0x224)
373
374 #define SM501_DC_CRT_HWC_BASE (0x230)
375 #define SM501_DC_CRT_HWC_ADDR (0x230)
376 #define SM501_DC_CRT_HWC_LOC (0x234)
377 #define SM501_DC_CRT_HWC_COLOR_1_2 (0x238)
378 #define SM501_DC_CRT_HWC_COLOR_3 (0x23C)
379
380 #define SM501_DC_PANEL_PALETTE (0x400)
381
382 #define SM501_DC_VIDEO_PALETTE (0x800)
383
384 #define SM501_DC_CRT_PALETTE (0xC00)
385
386 /* Zoom Video port base */
387 #define SM501_ZVPORT (0x090000)
388
389 /* AC97/I2S base */
390 #define SM501_AC97 (0x0A0000)
391
392 /* 8051 micro controller base */
393 #define SM501_UCONTROLLER (0x0B0000)
394
395 /* 8051 micro controller SRAM base */
396 #define SM501_UCONTROLLER_SRAM (0x0C0000)
397
398 /* DMA base */
399 #define SM501_DMA (0x0D0000)
400
401 /* 2d engine base */
402 #define SM501_2D_ENGINE (0x100000)
403 #define SM501_2D_SOURCE (0x00)
404 #define SM501_2D_DESTINATION (0x04)
405 #define SM501_2D_DIMENSION (0x08)
406 #define SM501_2D_CONTROL (0x0C)
407 #define SM501_2D_PITCH (0x10)
408 #define SM501_2D_FOREGROUND (0x14)
409 #define SM501_2D_BACKGROUND (0x18)
410 #define SM501_2D_STRETCH (0x1C)
411 #define SM501_2D_COLOR_COMPARE (0x20)
412 #define SM501_2D_COLOR_COMPARE_MASK (0x24)
413 #define SM501_2D_MASK (0x28)
414 #define SM501_2D_CLIP_TL (0x2C)
415 #define SM501_2D_CLIP_BR (0x30)
416 #define SM501_2D_MONO_PATTERN_LOW (0x34)
417 #define SM501_2D_MONO_PATTERN_HIGH (0x38)
418 #define SM501_2D_WINDOW_WIDTH (0x3C)
419 #define SM501_2D_SOURCE_BASE (0x40)
420 #define SM501_2D_DESTINATION_BASE (0x44)
421 #define SM501_2D_ALPHA (0x48)
422 #define SM501_2D_WRAP (0x4C)
423 #define SM501_2D_STATUS (0x50)
424
425 #define SM501_CSC_Y_SOURCE_BASE (0xC8)
426 #define SM501_CSC_CONSTANTS (0xCC)
427 #define SM501_CSC_Y_SOURCE_X (0xD0)
428 #define SM501_CSC_Y_SOURCE_Y (0xD4)
429 #define SM501_CSC_U_SOURCE_BASE (0xD8)
430 #define SM501_CSC_V_SOURCE_BASE (0xDC)
431 #define SM501_CSC_SOURCE_DIMENSION (0xE0)
432 #define SM501_CSC_SOURCE_PITCH (0xE4)
433 #define SM501_CSC_DESTINATION (0xE8)
434 #define SM501_CSC_DESTINATION_DIMENSION (0xEC)
435 #define SM501_CSC_DESTINATION_PITCH (0xF0)
436 #define SM501_CSC_SCALE_FACTOR (0xF4)
437 #define SM501_CSC_DESTINATION_BASE (0xF8)
438 #define SM501_CSC_CONTROL (0xFC)
439
440 /* 2d engine data port base */
441 #define SM501_2D_ENGINE_DATA (0x110000)
442
443 /* end of register definitions */
444
445 #define SM501_HWC_WIDTH (64)
446 #define SM501_HWC_HEIGHT (64)
447
448 /* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */
449 static const uint32_t sm501_mem_local_size[] = {
450 [0] = 4 * M_BYTE,
451 [1] = 8 * M_BYTE,
452 [2] = 16 * M_BYTE,
453 [3] = 32 * M_BYTE,
454 [4] = 64 * M_BYTE,
455 [5] = 2 * M_BYTE,
456 };
457 #define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index]
458
459 typedef struct SM501State {
460 /* graphic console status */
461 QemuConsole *con;
462
463 /* status & internal resources */
464 hwaddr base;
465 uint32_t local_mem_size_index;
466 uint8_t *local_mem;
467 MemoryRegion local_mem_region;
468 uint32_t last_width;
469 uint32_t last_height;
470
471 /* mmio registers */
472 uint32_t system_control;
473 uint32_t misc_control;
474 uint32_t gpio_31_0_control;
475 uint32_t gpio_63_32_control;
476 uint32_t dram_control;
477 uint32_t arbitration_control;
478 uint32_t irq_mask;
479 uint32_t misc_timing;
480 uint32_t power_mode_control;
481
482 uint32_t uart0_ier;
483 uint32_t uart0_lcr;
484 uint32_t uart0_mcr;
485 uint32_t uart0_scr;
486
487 uint8_t dc_palette[0x400 * 3];
488
489 uint32_t dc_panel_control;
490 uint32_t dc_panel_panning_control;
491 uint32_t dc_panel_fb_addr;
492 uint32_t dc_panel_fb_offset;
493 uint32_t dc_panel_fb_width;
494 uint32_t dc_panel_fb_height;
495 uint32_t dc_panel_tl_location;
496 uint32_t dc_panel_br_location;
497 uint32_t dc_panel_h_total;
498 uint32_t dc_panel_h_sync;
499 uint32_t dc_panel_v_total;
500 uint32_t dc_panel_v_sync;
501
502 uint32_t dc_panel_hwc_addr;
503 uint32_t dc_panel_hwc_location;
504 uint32_t dc_panel_hwc_color_1_2;
505 uint32_t dc_panel_hwc_color_3;
506
507 uint32_t dc_crt_control;
508 uint32_t dc_crt_fb_addr;
509 uint32_t dc_crt_fb_offset;
510 uint32_t dc_crt_h_total;
511 uint32_t dc_crt_h_sync;
512 uint32_t dc_crt_v_total;
513 uint32_t dc_crt_v_sync;
514
515 uint32_t dc_crt_hwc_addr;
516 uint32_t dc_crt_hwc_location;
517 uint32_t dc_crt_hwc_color_1_2;
518 uint32_t dc_crt_hwc_color_3;
519
520 uint32_t twoD_source;
521 uint32_t twoD_destination;
522 uint32_t twoD_dimension;
523 uint32_t twoD_control;
524 uint32_t twoD_pitch;
525 uint32_t twoD_foreground;
526 uint32_t twoD_stretch;
527 uint32_t twoD_color_compare_mask;
528 uint32_t twoD_mask;
529 uint32_t twoD_window_width;
530 uint32_t twoD_source_base;
531 uint32_t twoD_destination_base;
532
533 } SM501State;
534
535 static uint32_t get_local_mem_size_index(uint32_t size)
536 {
537 uint32_t norm_size = 0;
538 int i, index = 0;
539
540 for (i = 0; i < ARRAY_SIZE(sm501_mem_local_size); i++) {
541 uint32_t new_size = sm501_mem_local_size[i];
542 if (new_size >= size) {
543 if (norm_size == 0 || norm_size > new_size) {
544 norm_size = new_size;
545 index = i;
546 }
547 }
548 }
549
550 return index;
551 }
552
553 /**
554 * Check the availability of hardware cursor.
555 * @param crt 0 for PANEL, 1 for CRT.
556 */
557 static inline int is_hwc_enabled(SM501State *state, int crt)
558 {
559 uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr;
560 return addr & SM501_HWC_EN;
561 }
562
563 /**
564 * Get the address which holds cursor pattern data.
565 * @param crt 0 for PANEL, 1 for CRT.
566 */
567 static inline uint32_t get_hwc_address(SM501State *state, int crt)
568 {
569 uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr;
570 return (addr & 0x03FFFFF0)/* >> 4*/;
571 }
572
573 /**
574 * Get the cursor position in y coordinate.
575 * @param crt 0 for PANEL, 1 for CRT.
576 */
577 static inline uint32_t get_hwc_y(SM501State *state, int crt)
578 {
579 uint32_t location = crt ? state->dc_crt_hwc_location
580 : state->dc_panel_hwc_location;
581 return (location & 0x07FF0000) >> 16;
582 }
583
584 /**
585 * Get the cursor position in x coordinate.
586 * @param crt 0 for PANEL, 1 for CRT.
587 */
588 static inline uint32_t get_hwc_x(SM501State *state, int crt)
589 {
590 uint32_t location = crt ? state->dc_crt_hwc_location
591 : state->dc_panel_hwc_location;
592 return location & 0x000007FF;
593 }
594
595 /**
596 * Get the cursor position in x coordinate.
597 * @param crt 0 for PANEL, 1 for CRT.
598 * @param index 0, 1, 2 or 3 which specifies color of corsor dot.
599 */
600 static inline uint16_t get_hwc_color(SM501State *state, int crt, int index)
601 {
602 uint32_t color_reg = 0;
603 uint16_t color_565 = 0;
604
605 if (index == 0) {
606 return 0;
607 }
608
609 switch (index) {
610 case 1:
611 case 2:
612 color_reg = crt ? state->dc_crt_hwc_color_1_2
613 : state->dc_panel_hwc_color_1_2;
614 break;
615 case 3:
616 color_reg = crt ? state->dc_crt_hwc_color_3
617 : state->dc_panel_hwc_color_3;
618 break;
619 default:
620 printf("invalid hw cursor color.\n");
621 abort();
622 }
623
624 switch (index) {
625 case 1:
626 case 3:
627 color_565 = (uint16_t)(color_reg & 0xFFFF);
628 break;
629 case 2:
630 color_565 = (uint16_t)((color_reg >> 16) & 0xFFFF);
631 break;
632 }
633 return color_565;
634 }
635
636 static int within_hwc_y_range(SM501State *state, int y, int crt)
637 {
638 int hwc_y = get_hwc_y(state, crt);
639 return (hwc_y <= y && y < hwc_y + SM501_HWC_HEIGHT);
640 }
641
642 static void sm501_2d_operation(SM501State *s)
643 {
644 /* obtain operation parameters */
645 int operation = (s->twoD_control >> 16) & 0x1f;
646 int rtl = s->twoD_control & 0x8000000;
647 int src_x = (s->twoD_source >> 16) & 0x01FFF;
648 int src_y = s->twoD_source & 0xFFFF;
649 int dst_x = (s->twoD_destination >> 16) & 0x01FFF;
650 int dst_y = s->twoD_destination & 0xFFFF;
651 int operation_width = (s->twoD_dimension >> 16) & 0x1FFF;
652 int operation_height = s->twoD_dimension & 0xFFFF;
653 uint32_t color = s->twoD_foreground;
654 int format_flags = (s->twoD_stretch >> 20) & 0x3;
655 int addressing = (s->twoD_stretch >> 16) & 0xF;
656
657 /* get frame buffer info */
658 uint8_t *src = s->local_mem + (s->twoD_source_base & 0x03FFFFFF);
659 uint8_t *dst = s->local_mem + (s->twoD_destination_base & 0x03FFFFFF);
660 int src_width = (s->dc_crt_h_total & 0x00000FFF) + 1;
661 int dst_width = (s->dc_crt_h_total & 0x00000FFF) + 1;
662
663 if (addressing != 0x0) {
664 printf("%s: only XY addressing is supported.\n", __func__);
665 abort();
666 }
667
668 if ((s->twoD_source_base & 0x08000000) ||
669 (s->twoD_destination_base & 0x08000000)) {
670 printf("%s: only local memory is supported.\n", __func__);
671 abort();
672 }
673
674 switch (operation) {
675 case 0x00: /* copy area */
676 #define COPY_AREA(_bpp, _pixel_type, rtl) { \
677 int y, x, index_d, index_s; \
678 for (y = 0; y < operation_height; y++) { \
679 for (x = 0; x < operation_width; x++) { \
680 if (rtl) { \
681 index_s = ((src_y - y) * src_width + src_x - x) * _bpp; \
682 index_d = ((dst_y - y) * dst_width + dst_x - x) * _bpp; \
683 } else { \
684 index_s = ((src_y + y) * src_width + src_x + x) * _bpp; \
685 index_d = ((dst_y + y) * dst_width + dst_x + x) * _bpp; \
686 } \
687 *(_pixel_type *)&dst[index_d] = *(_pixel_type *)&src[index_s];\
688 } \
689 } \
690 }
691 switch (format_flags) {
692 case 0:
693 COPY_AREA(1, uint8_t, rtl);
694 break;
695 case 1:
696 COPY_AREA(2, uint16_t, rtl);
697 break;
698 case 2:
699 COPY_AREA(4, uint32_t, rtl);
700 break;
701 }
702 break;
703
704 case 0x01: /* fill rectangle */
705 #define FILL_RECT(_bpp, _pixel_type) { \
706 int y, x; \
707 for (y = 0; y < operation_height; y++) { \
708 for (x = 0; x < operation_width; x++) { \
709 int index = ((dst_y + y) * dst_width + dst_x + x) * _bpp; \
710 *(_pixel_type *)&dst[index] = (_pixel_type)color; \
711 } \
712 } \
713 }
714
715 switch (format_flags) {
716 case 0:
717 FILL_RECT(1, uint8_t);
718 break;
719 case 1:
720 FILL_RECT(2, uint16_t);
721 break;
722 case 2:
723 FILL_RECT(4, uint32_t);
724 break;
725 }
726 break;
727
728 default:
729 printf("non-implemented SM501 2D operation. %d\n", operation);
730 abort();
731 break;
732 }
733 }
734
735 static uint64_t sm501_system_config_read(void *opaque, hwaddr addr,
736 unsigned size)
737 {
738 SM501State *s = (SM501State *)opaque;
739 uint32_t ret = 0;
740 SM501_DPRINTF("sm501 system config regs : read addr=%x\n", (int)addr);
741
742 switch (addr) {
743 case SM501_SYSTEM_CONTROL:
744 ret = s->system_control;
745 break;
746 case SM501_MISC_CONTROL:
747 ret = s->misc_control;
748 break;
749 case SM501_GPIO31_0_CONTROL:
750 ret = s->gpio_31_0_control;
751 break;
752 case SM501_GPIO63_32_CONTROL:
753 ret = s->gpio_63_32_control;
754 break;
755 case SM501_DEVICEID:
756 ret = 0x050100A0;
757 break;
758 case SM501_DRAM_CONTROL:
759 ret = (s->dram_control & 0x07F107C0) | s->local_mem_size_index << 13;
760 break;
761 case SM501_ARBTRTN_CONTROL:
762 ret = s->arbitration_control;
763 break;
764 case SM501_IRQ_MASK:
765 ret = s->irq_mask;
766 break;
767 case SM501_MISC_TIMING:
768 /* TODO : simulate gate control */
769 ret = s->misc_timing;
770 break;
771 case SM501_CURRENT_GATE:
772 /* TODO : simulate gate control */
773 ret = 0x00021807;
774 break;
775 case SM501_CURRENT_CLOCK:
776 ret = 0x2A1A0A09;
777 break;
778 case SM501_POWER_MODE_CONTROL:
779 ret = s->power_mode_control;
780 break;
781
782 default:
783 printf("sm501 system config : not implemented register read."
784 " addr=%x\n", (int)addr);
785 abort();
786 }
787
788 return ret;
789 }
790
791 static void sm501_system_config_write(void *opaque, hwaddr addr,
792 uint64_t value, unsigned size)
793 {
794 SM501State *s = (SM501State *)opaque;
795 SM501_DPRINTF("sm501 system config regs : write addr=%x, val=%x\n",
796 (uint32_t)addr, (uint32_t)value);
797
798 switch (addr) {
799 case SM501_SYSTEM_CONTROL:
800 s->system_control = value & 0xE300B8F7;
801 break;
802 case SM501_MISC_CONTROL:
803 s->misc_control = value & 0xFF7FFF20;
804 break;
805 case SM501_GPIO31_0_CONTROL:
806 s->gpio_31_0_control = value;
807 break;
808 case SM501_GPIO63_32_CONTROL:
809 s->gpio_63_32_control = value;
810 break;
811 case SM501_DRAM_CONTROL:
812 s->local_mem_size_index = (value >> 13) & 0x7;
813 /* TODO : check validity of size change */
814 s->dram_control |= value & 0x7FFFFFC3;
815 break;
816 case SM501_ARBTRTN_CONTROL:
817 s->arbitration_control = value & 0x37777777;
818 break;
819 case SM501_IRQ_MASK:
820 s->irq_mask = value;
821 break;
822 case SM501_MISC_TIMING:
823 s->misc_timing = value & 0xF31F1FFF;
824 break;
825 case SM501_POWER_MODE_0_GATE:
826 case SM501_POWER_MODE_1_GATE:
827 case SM501_POWER_MODE_0_CLOCK:
828 case SM501_POWER_MODE_1_CLOCK:
829 /* TODO : simulate gate & clock control */
830 break;
831 case SM501_POWER_MODE_CONTROL:
832 s->power_mode_control = value & 0x00000003;
833 break;
834
835 default:
836 printf("sm501 system config : not implemented register write."
837 " addr=%x, val=%x\n", (int)addr, (uint32_t)value);
838 abort();
839 }
840 }
841
842 static const MemoryRegionOps sm501_system_config_ops = {
843 .read = sm501_system_config_read,
844 .write = sm501_system_config_write,
845 .valid = {
846 .min_access_size = 4,
847 .max_access_size = 4,
848 },
849 .endianness = DEVICE_NATIVE_ENDIAN,
850 };
851
852 static uint32_t sm501_palette_read(void *opaque, hwaddr addr)
853 {
854 SM501State *s = (SM501State *)opaque;
855 SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr);
856
857 /* TODO : consider BYTE/WORD access */
858 /* TODO : consider endian */
859
860 assert(range_covers_byte(0, 0x400 * 3, addr));
861 return *(uint32_t *)&s->dc_palette[addr];
862 }
863
864 static void sm501_palette_write(void *opaque, hwaddr addr,
865 uint32_t value)
866 {
867 SM501State *s = (SM501State *)opaque;
868 SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n",
869 (int)addr, value);
870
871 /* TODO : consider BYTE/WORD access */
872 /* TODO : consider endian */
873
874 assert(range_covers_byte(0, 0x400 * 3, addr));
875 *(uint32_t *)&s->dc_palette[addr] = value;
876 }
877
878 static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr,
879 unsigned size)
880 {
881 SM501State *s = (SM501State *)opaque;
882 uint32_t ret = 0;
883 SM501_DPRINTF("sm501 disp ctrl regs : read addr=%x\n", (int)addr);
884
885 switch (addr) {
886
887 case SM501_DC_PANEL_CONTROL:
888 ret = s->dc_panel_control;
889 break;
890 case SM501_DC_PANEL_PANNING_CONTROL:
891 ret = s->dc_panel_panning_control;
892 break;
893 case SM501_DC_PANEL_FB_ADDR:
894 ret = s->dc_panel_fb_addr;
895 break;
896 case SM501_DC_PANEL_FB_OFFSET:
897 ret = s->dc_panel_fb_offset;
898 break;
899 case SM501_DC_PANEL_FB_WIDTH:
900 ret = s->dc_panel_fb_width;
901 break;
902 case SM501_DC_PANEL_FB_HEIGHT:
903 ret = s->dc_panel_fb_height;
904 break;
905 case SM501_DC_PANEL_TL_LOC:
906 ret = s->dc_panel_tl_location;
907 break;
908 case SM501_DC_PANEL_BR_LOC:
909 ret = s->dc_panel_br_location;
910 break;
911
912 case SM501_DC_PANEL_H_TOT:
913 ret = s->dc_panel_h_total;
914 break;
915 case SM501_DC_PANEL_H_SYNC:
916 ret = s->dc_panel_h_sync;
917 break;
918 case SM501_DC_PANEL_V_TOT:
919 ret = s->dc_panel_v_total;
920 break;
921 case SM501_DC_PANEL_V_SYNC:
922 ret = s->dc_panel_v_sync;
923 break;
924
925 case SM501_DC_CRT_CONTROL:
926 ret = s->dc_crt_control;
927 break;
928 case SM501_DC_CRT_FB_ADDR:
929 ret = s->dc_crt_fb_addr;
930 break;
931 case SM501_DC_CRT_FB_OFFSET:
932 ret = s->dc_crt_fb_offset;
933 break;
934 case SM501_DC_CRT_H_TOT:
935 ret = s->dc_crt_h_total;
936 break;
937 case SM501_DC_CRT_H_SYNC:
938 ret = s->dc_crt_h_sync;
939 break;
940 case SM501_DC_CRT_V_TOT:
941 ret = s->dc_crt_v_total;
942 break;
943 case SM501_DC_CRT_V_SYNC:
944 ret = s->dc_crt_v_sync;
945 break;
946
947 case SM501_DC_CRT_HWC_ADDR:
948 ret = s->dc_crt_hwc_addr;
949 break;
950 case SM501_DC_CRT_HWC_LOC:
951 ret = s->dc_crt_hwc_location;
952 break;
953 case SM501_DC_CRT_HWC_COLOR_1_2:
954 ret = s->dc_crt_hwc_color_1_2;
955 break;
956 case SM501_DC_CRT_HWC_COLOR_3:
957 ret = s->dc_crt_hwc_color_3;
958 break;
959
960 case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4:
961 ret = sm501_palette_read(opaque, addr - SM501_DC_PANEL_PALETTE);
962 break;
963
964 default:
965 printf("sm501 disp ctrl : not implemented register read."
966 " addr=%x\n", (int)addr);
967 abort();
968 }
969
970 return ret;
971 }
972
973 static void sm501_disp_ctrl_write(void *opaque, hwaddr addr,
974 uint64_t value, unsigned size)
975 {
976 SM501State *s = (SM501State *)opaque;
977 SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, val=%x\n",
978 (unsigned)addr, (unsigned)value);
979
980 switch (addr) {
981 case SM501_DC_PANEL_CONTROL:
982 s->dc_panel_control = value & 0x0FFF73FF;
983 break;
984 case SM501_DC_PANEL_PANNING_CONTROL:
985 s->dc_panel_panning_control = value & 0xFF3FFF3F;
986 break;
987 case SM501_DC_PANEL_FB_ADDR:
988 s->dc_panel_fb_addr = value & 0x8FFFFFF0;
989 break;
990 case SM501_DC_PANEL_FB_OFFSET:
991 s->dc_panel_fb_offset = value & 0x3FF03FF0;
992 break;
993 case SM501_DC_PANEL_FB_WIDTH:
994 s->dc_panel_fb_width = value & 0x0FFF0FFF;
995 break;
996 case SM501_DC_PANEL_FB_HEIGHT:
997 s->dc_panel_fb_height = value & 0x0FFF0FFF;
998 break;
999 case SM501_DC_PANEL_TL_LOC:
1000 s->dc_panel_tl_location = value & 0x07FF07FF;
1001 break;
1002 case SM501_DC_PANEL_BR_LOC:
1003 s->dc_panel_br_location = value & 0x07FF07FF;
1004 break;
1005
1006 case SM501_DC_PANEL_H_TOT:
1007 s->dc_panel_h_total = value & 0x0FFF0FFF;
1008 break;
1009 case SM501_DC_PANEL_H_SYNC:
1010 s->dc_panel_h_sync = value & 0x00FF0FFF;
1011 break;
1012 case SM501_DC_PANEL_V_TOT:
1013 s->dc_panel_v_total = value & 0x0FFF0FFF;
1014 break;
1015 case SM501_DC_PANEL_V_SYNC:
1016 s->dc_panel_v_sync = value & 0x003F0FFF;
1017 break;
1018
1019 case SM501_DC_PANEL_HWC_ADDR:
1020 s->dc_panel_hwc_addr = value & 0x8FFFFFF0;
1021 break;
1022 case SM501_DC_PANEL_HWC_LOC:
1023 s->dc_panel_hwc_location = value & 0x0FFF0FFF;
1024 break;
1025 case SM501_DC_PANEL_HWC_COLOR_1_2:
1026 s->dc_panel_hwc_color_1_2 = value;
1027 break;
1028 case SM501_DC_PANEL_HWC_COLOR_3:
1029 s->dc_panel_hwc_color_3 = value & 0x0000FFFF;
1030 break;
1031
1032 case SM501_DC_CRT_CONTROL:
1033 s->dc_crt_control = value & 0x0003FFFF;
1034 break;
1035 case SM501_DC_CRT_FB_ADDR:
1036 s->dc_crt_fb_addr = value & 0x8FFFFFF0;
1037 break;
1038 case SM501_DC_CRT_FB_OFFSET:
1039 s->dc_crt_fb_offset = value & 0x3FF03FF0;
1040 break;
1041 case SM501_DC_CRT_H_TOT:
1042 s->dc_crt_h_total = value & 0x0FFF0FFF;
1043 break;
1044 case SM501_DC_CRT_H_SYNC:
1045 s->dc_crt_h_sync = value & 0x00FF0FFF;
1046 break;
1047 case SM501_DC_CRT_V_TOT:
1048 s->dc_crt_v_total = value & 0x0FFF0FFF;
1049 break;
1050 case SM501_DC_CRT_V_SYNC:
1051 s->dc_crt_v_sync = value & 0x003F0FFF;
1052 break;
1053
1054 case SM501_DC_CRT_HWC_ADDR:
1055 s->dc_crt_hwc_addr = value & 0x8FFFFFF0;
1056 break;
1057 case SM501_DC_CRT_HWC_LOC:
1058 s->dc_crt_hwc_location = value & 0x0FFF0FFF;
1059 break;
1060 case SM501_DC_CRT_HWC_COLOR_1_2:
1061 s->dc_crt_hwc_color_1_2 = value;
1062 break;
1063 case SM501_DC_CRT_HWC_COLOR_3:
1064 s->dc_crt_hwc_color_3 = value & 0x0000FFFF;
1065 break;
1066
1067 case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4:
1068 sm501_palette_write(opaque, addr - SM501_DC_PANEL_PALETTE, value);
1069 break;
1070
1071 default:
1072 printf("sm501 disp ctrl : not implemented register write."
1073 " addr=%x, val=%x\n", (int)addr, (unsigned)value);
1074 abort();
1075 }
1076 }
1077
1078 static const MemoryRegionOps sm501_disp_ctrl_ops = {
1079 .read = sm501_disp_ctrl_read,
1080 .write = sm501_disp_ctrl_write,
1081 .valid = {
1082 .min_access_size = 4,
1083 .max_access_size = 4,
1084 },
1085 .endianness = DEVICE_NATIVE_ENDIAN,
1086 };
1087
1088 static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr,
1089 unsigned size)
1090 {
1091 SM501State *s = (SM501State *)opaque;
1092 uint32_t ret = 0;
1093 SM501_DPRINTF("sm501 2d engine regs : read addr=%x\n", (int)addr);
1094
1095 switch (addr) {
1096 case SM501_2D_SOURCE_BASE:
1097 ret = s->twoD_source_base;
1098 break;
1099 default:
1100 printf("sm501 disp ctrl : not implemented register read."
1101 " addr=%x\n", (int)addr);
1102 abort();
1103 }
1104
1105 return ret;
1106 }
1107
1108 static void sm501_2d_engine_write(void *opaque, hwaddr addr,
1109 uint64_t value, unsigned size)
1110 {
1111 SM501State *s = (SM501State *)opaque;
1112 SM501_DPRINTF("sm501 2d engine regs : write addr=%x, val=%x\n",
1113 (unsigned)addr, (unsigned)value);
1114
1115 switch (addr) {
1116 case SM501_2D_SOURCE:
1117 s->twoD_source = value;
1118 break;
1119 case SM501_2D_DESTINATION:
1120 s->twoD_destination = value;
1121 break;
1122 case SM501_2D_DIMENSION:
1123 s->twoD_dimension = value;
1124 break;
1125 case SM501_2D_CONTROL:
1126 s->twoD_control = value;
1127
1128 /* do 2d operation if start flag is set. */
1129 if (value & 0x80000000) {
1130 sm501_2d_operation(s);
1131 s->twoD_control &= ~0x80000000; /* start flag down */
1132 }
1133
1134 break;
1135 case SM501_2D_PITCH:
1136 s->twoD_pitch = value;
1137 break;
1138 case SM501_2D_FOREGROUND:
1139 s->twoD_foreground = value;
1140 break;
1141 case SM501_2D_STRETCH:
1142 s->twoD_stretch = value;
1143 break;
1144 case SM501_2D_COLOR_COMPARE_MASK:
1145 s->twoD_color_compare_mask = value;
1146 break;
1147 case SM501_2D_MASK:
1148 s->twoD_mask = value;
1149 break;
1150 case SM501_2D_WINDOW_WIDTH:
1151 s->twoD_window_width = value;
1152 break;
1153 case SM501_2D_SOURCE_BASE:
1154 s->twoD_source_base = value;
1155 break;
1156 case SM501_2D_DESTINATION_BASE:
1157 s->twoD_destination_base = value;
1158 break;
1159 default:
1160 printf("sm501 2d engine : not implemented register write."
1161 " addr=%x, val=%x\n", (int)addr, (unsigned)value);
1162 abort();
1163 }
1164 }
1165
1166 static const MemoryRegionOps sm501_2d_engine_ops = {
1167 .read = sm501_2d_engine_read,
1168 .write = sm501_2d_engine_write,
1169 .valid = {
1170 .min_access_size = 4,
1171 .max_access_size = 4,
1172 },
1173 .endianness = DEVICE_NATIVE_ENDIAN,
1174 };
1175
1176 /* draw line functions for all console modes */
1177
1178 typedef void draw_line_func(uint8_t *d, const uint8_t *s,
1179 int width, const uint32_t *pal);
1180
1181 typedef void draw_hwc_line_func(SM501State *s, int crt, uint8_t *palette,
1182 int c_y, uint8_t *d, int width);
1183
1184 #define DEPTH 8
1185 #include "sm501_template.h"
1186
1187 #define DEPTH 15
1188 #include "sm501_template.h"
1189
1190 #define BGR_FORMAT
1191 #define DEPTH 15
1192 #include "sm501_template.h"
1193
1194 #define DEPTH 16
1195 #include "sm501_template.h"
1196
1197 #define BGR_FORMAT
1198 #define DEPTH 16
1199 #include "sm501_template.h"
1200
1201 #define DEPTH 32
1202 #include "sm501_template.h"
1203
1204 #define BGR_FORMAT
1205 #define DEPTH 32
1206 #include "sm501_template.h"
1207
1208 static draw_line_func *draw_line8_funcs[] = {
1209 draw_line8_8,
1210 draw_line8_15,
1211 draw_line8_16,
1212 draw_line8_32,
1213 draw_line8_32bgr,
1214 draw_line8_15bgr,
1215 draw_line8_16bgr,
1216 };
1217
1218 static draw_line_func *draw_line16_funcs[] = {
1219 draw_line16_8,
1220 draw_line16_15,
1221 draw_line16_16,
1222 draw_line16_32,
1223 draw_line16_32bgr,
1224 draw_line16_15bgr,
1225 draw_line16_16bgr,
1226 };
1227
1228 static draw_line_func *draw_line32_funcs[] = {
1229 draw_line32_8,
1230 draw_line32_15,
1231 draw_line32_16,
1232 draw_line32_32,
1233 draw_line32_32bgr,
1234 draw_line32_15bgr,
1235 draw_line32_16bgr,
1236 };
1237
1238 static draw_hwc_line_func *draw_hwc_line_funcs[] = {
1239 draw_hwc_line_8,
1240 draw_hwc_line_15,
1241 draw_hwc_line_16,
1242 draw_hwc_line_32,
1243 draw_hwc_line_32bgr,
1244 draw_hwc_line_15bgr,
1245 draw_hwc_line_16bgr,
1246 };
1247
1248 static inline int get_depth_index(DisplaySurface *surface)
1249 {
1250 switch (surface_bits_per_pixel(surface)) {
1251 default:
1252 case 8:
1253 return 0;
1254 case 15:
1255 return 1;
1256 case 16:
1257 return 2;
1258 case 32:
1259 if (is_surface_bgr(surface)) {
1260 return 4;
1261 } else {
1262 return 3;
1263 }
1264 }
1265 }
1266
1267 static void sm501_draw_crt(SM501State *s)
1268 {
1269 DisplaySurface *surface = qemu_console_surface(s->con);
1270 int y;
1271 int width = (s->dc_crt_h_total & 0x00000FFF) + 1;
1272 int height = (s->dc_crt_v_total & 0x00000FFF) + 1;
1273
1274 uint8_t *src = s->local_mem;
1275 int src_bpp = 0;
1276 int dst_bpp = surface_bytes_per_pixel(surface);
1277 uint32_t *palette = (uint32_t *)&s->dc_palette[SM501_DC_CRT_PALETTE -
1278 SM501_DC_PANEL_PALETTE];
1279 uint8_t hwc_palette[3 * 3];
1280 int ds_depth_index = get_depth_index(surface);
1281 draw_line_func *draw_line = NULL;
1282 draw_hwc_line_func *draw_hwc_line = NULL;
1283 int full_update = 0;
1284 int y_start = -1;
1285 ram_addr_t page_min = ~0l;
1286 ram_addr_t page_max = 0l;
1287 ram_addr_t offset = 0;
1288
1289 /* choose draw_line function */
1290 switch (s->dc_crt_control & 3) {
1291 case SM501_DC_CRT_CONTROL_8BPP:
1292 src_bpp = 1;
1293 draw_line = draw_line8_funcs[ds_depth_index];
1294 break;
1295 case SM501_DC_CRT_CONTROL_16BPP:
1296 src_bpp = 2;
1297 draw_line = draw_line16_funcs[ds_depth_index];
1298 break;
1299 case SM501_DC_CRT_CONTROL_32BPP:
1300 src_bpp = 4;
1301 draw_line = draw_line32_funcs[ds_depth_index];
1302 break;
1303 default:
1304 printf("sm501 draw crt : invalid DC_CRT_CONTROL=%x.\n",
1305 s->dc_crt_control);
1306 abort();
1307 break;
1308 }
1309
1310 /* set up to draw hardware cursor */
1311 if (is_hwc_enabled(s, 1)) {
1312 int i;
1313
1314 /* get cursor palette */
1315 for (i = 0; i < 3; i++) {
1316 uint16_t rgb565 = get_hwc_color(s, 1, i + 1);
1317 hwc_palette[i * 3 + 0] = (rgb565 & 0xf800) >> 8; /* red */
1318 hwc_palette[i * 3 + 1] = (rgb565 & 0x07e0) >> 3; /* green */
1319 hwc_palette[i * 3 + 2] = (rgb565 & 0x001f) << 3; /* blue */
1320 }
1321
1322 /* choose cursor draw line function */
1323 draw_hwc_line = draw_hwc_line_funcs[ds_depth_index];
1324 }
1325
1326 /* adjust console size */
1327 if (s->last_width != width || s->last_height != height) {
1328 qemu_console_resize(s->con, width, height);
1329 surface = qemu_console_surface(s->con);
1330 s->last_width = width;
1331 s->last_height = height;
1332 full_update = 1;
1333 }
1334
1335 /* draw each line according to conditions */
1336 memory_region_sync_dirty_bitmap(&s->local_mem_region);
1337 for (y = 0; y < height; y++) {
1338 int update_hwc = draw_hwc_line ? within_hwc_y_range(s, y, 1) : 0;
1339 int update = full_update || update_hwc;
1340 ram_addr_t page0 = offset;
1341 ram_addr_t page1 = offset + width * src_bpp - 1;
1342
1343 /* check dirty flags for each line */
1344 update = memory_region_get_dirty(&s->local_mem_region, page0,
1345 page1 - page0, DIRTY_MEMORY_VGA);
1346
1347 /* draw line and change status */
1348 if (update) {
1349 uint8_t *d = surface_data(surface);
1350 d += y * width * dst_bpp;
1351
1352 /* draw graphics layer */
1353 draw_line(d, src, width, palette);
1354
1355 /* draw hardware cursor */
1356 if (update_hwc) {
1357 draw_hwc_line(s, 1, hwc_palette, y - get_hwc_y(s, 1), d, width);
1358 }
1359
1360 if (y_start < 0) {
1361 y_start = y;
1362 }
1363 if (page0 < page_min) {
1364 page_min = page0;
1365 }
1366 if (page1 > page_max) {
1367 page_max = page1;
1368 }
1369 } else {
1370 if (y_start >= 0) {
1371 /* flush to display */
1372 dpy_gfx_update(s->con, 0, y_start, width, y - y_start);
1373 y_start = -1;
1374 }
1375 }
1376
1377 src += width * src_bpp;
1378 offset += width * src_bpp;
1379 }
1380
1381 /* complete flush to display */
1382 if (y_start >= 0) {
1383 dpy_gfx_update(s->con, 0, y_start, width, y - y_start);
1384 }
1385
1386 /* clear dirty flags */
1387 if (page_min != ~0l) {
1388 memory_region_reset_dirty(&s->local_mem_region,
1389 page_min, page_max + TARGET_PAGE_SIZE,
1390 DIRTY_MEMORY_VGA);
1391 }
1392 }
1393
1394 static void sm501_update_display(void *opaque)
1395 {
1396 SM501State *s = (SM501State *)opaque;
1397
1398 if (s->dc_crt_control & SM501_DC_CRT_CONTROL_ENABLE) {
1399 sm501_draw_crt(s);
1400 }
1401 }
1402
1403 static const GraphicHwOps sm501_ops = {
1404 .gfx_update = sm501_update_display,
1405 };
1406
1407 void sm501_init(MemoryRegion *address_space_mem, uint32_t base,
1408 uint32_t local_mem_bytes, qemu_irq irq, Chardev *chr)
1409 {
1410 SM501State *s;
1411 DeviceState *dev;
1412 MemoryRegion *sm501_system_config = g_new(MemoryRegion, 1);
1413 MemoryRegion *sm501_disp_ctrl = g_new(MemoryRegion, 1);
1414 MemoryRegion *sm501_2d_engine = g_new(MemoryRegion, 1);
1415
1416 /* allocate management data region */
1417 s = g_new0(SM501State, 1);
1418 s->base = base;
1419 s->local_mem_size_index = get_local_mem_size_index(local_mem_bytes);
1420 SM501_DPRINTF("local mem size=%x. index=%d\n", get_local_mem_size(s),
1421 s->local_mem_size_index);
1422 s->system_control = 0x00100000; /* 2D engine FIFO empty */
1423 /* Bits 17 (SH), 7 (CDR), 6:5 (Test), 2:0 (Bus) are all supposed
1424 * to be determined at reset by GPIO lines which set config bits.
1425 * We hardwire them:
1426 * SH = 0 : Hitachi Ready Polarity == Active Low
1427 * CDR = 0 : do not reset clock divider
1428 * TEST = 0 : Normal mode (not testing the silicon)
1429 * BUS = 0 : Hitachi SH3/SH4
1430 */
1431 s->misc_control = SM501_MISC_DAC_POWER;
1432 s->arbitration_control = 0x05146732;
1433 s->dc_panel_control = 0x00010000; /* FIFO level 3 */
1434 s->dc_crt_control = 0x00010000;
1435
1436 /* allocate local memory */
1437 memory_region_init_ram(&s->local_mem_region, NULL, "sm501.local",
1438 local_mem_bytes, &error_fatal);
1439 vmstate_register_ram_global(&s->local_mem_region);
1440 memory_region_set_log(&s->local_mem_region, true, DIRTY_MEMORY_VGA);
1441 s->local_mem = memory_region_get_ram_ptr(&s->local_mem_region);
1442 memory_region_add_subregion(address_space_mem, base, &s->local_mem_region);
1443
1444 /* map mmio */
1445 memory_region_init_io(sm501_system_config, NULL, &sm501_system_config_ops,
1446 s, "sm501-system-config", 0x6c);
1447 memory_region_add_subregion(address_space_mem, base + MMIO_BASE_OFFSET,
1448 sm501_system_config);
1449 memory_region_init_io(sm501_disp_ctrl, NULL, &sm501_disp_ctrl_ops, s,
1450 "sm501-disp-ctrl", 0x1000);
1451 memory_region_add_subregion(address_space_mem,
1452 base + MMIO_BASE_OFFSET + SM501_DC,
1453 sm501_disp_ctrl);
1454 memory_region_init_io(sm501_2d_engine, NULL, &sm501_2d_engine_ops, s,
1455 "sm501-2d-engine", 0x54);
1456 memory_region_add_subregion(address_space_mem,
1457 base + MMIO_BASE_OFFSET + SM501_2D_ENGINE,
1458 sm501_2d_engine);
1459
1460 /* bridge to usb host emulation module */
1461 dev = qdev_create(NULL, "sysbus-ohci");
1462 qdev_prop_set_uint32(dev, "num-ports", 2);
1463 qdev_prop_set_uint64(dev, "dma-offset", base);
1464 qdev_init_nofail(dev);
1465 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0,
1466 base + MMIO_BASE_OFFSET + SM501_USB_HOST);
1467 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
1468
1469 /* bridge to serial emulation module */
1470 if (chr) {
1471 serial_mm_init(address_space_mem,
1472 base + MMIO_BASE_OFFSET + SM501_UART0, 2,
1473 NULL, /* TODO : chain irq to IRL */
1474 115200, chr, DEVICE_NATIVE_ENDIAN);
1475 }
1476
1477 /* create qemu graphic console */
1478 s->con = graphic_console_init(DEVICE(dev), 0, &sm501_ops, s);
1479 }