hw/arm/bcm2836: Only provide "enabled-cpus" property to multicore SoCs
[qemu.git] / hw / display / sm501.c
1 /*
2 * QEMU SM501 Device
3 *
4 * Copyright (c) 2008 Shin-ichiro KAWASAKI
5 * Copyright (c) 2016-2020 BALATON Zoltan
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "qemu/osdep.h"
27 #include "qemu/units.h"
28 #include "qapi/error.h"
29 #include "qemu/log.h"
30 #include "qemu/module.h"
31 #include "hw/char/serial.h"
32 #include "ui/console.h"
33 #include "hw/sysbus.h"
34 #include "migration/vmstate.h"
35 #include "hw/pci/pci.h"
36 #include "hw/qdev-properties.h"
37 #include "hw/i2c/i2c.h"
38 #include "hw/display/i2c-ddc.h"
39 #include "qemu/range.h"
40 #include "ui/pixel_ops.h"
41 #include "qemu/bswap.h"
42 #include "trace.h"
43 #include "qom/object.h"
44
45 #define MMIO_BASE_OFFSET 0x3e00000
46 #define MMIO_SIZE 0x200000
47 #define DC_PALETTE_ENTRIES (0x400 * 3)
48
49 /* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" */
50
51 /* System Configuration area */
52 /* System config base */
53 #define SM501_SYS_CONFIG (0x000000)
54
55 /* config 1 */
56 #define SM501_SYSTEM_CONTROL (0x000000)
57
58 #define SM501_SYSCTRL_PANEL_TRISTATE (1 << 0)
59 #define SM501_SYSCTRL_MEM_TRISTATE (1 << 1)
60 #define SM501_SYSCTRL_CRT_TRISTATE (1 << 2)
61
62 #define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3 << 4)
63 #define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0 << 4)
64 #define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1 << 4)
65 #define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2 << 4)
66 #define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3 << 4)
67
68 #define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1 << 6)
69 #define SM501_SYSCTRL_PCI_RETRY_DISABLE (1 << 7)
70 #define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1 << 11)
71 #define SM501_SYSCTRL_PCI_BURST_READ_EN (1 << 15)
72
73 /* miscellaneous control */
74
75 #define SM501_MISC_CONTROL (0x000004)
76
77 #define SM501_MISC_BUS_SH (0x0)
78 #define SM501_MISC_BUS_PCI (0x1)
79 #define SM501_MISC_BUS_XSCALE (0x2)
80 #define SM501_MISC_BUS_NEC (0x6)
81 #define SM501_MISC_BUS_MASK (0x7)
82
83 #define SM501_MISC_VR_62MB (1 << 3)
84 #define SM501_MISC_CDR_RESET (1 << 7)
85 #define SM501_MISC_USB_LB (1 << 8)
86 #define SM501_MISC_USB_SLAVE (1 << 9)
87 #define SM501_MISC_BL_1 (1 << 10)
88 #define SM501_MISC_MC (1 << 11)
89 #define SM501_MISC_DAC_POWER (1 << 12)
90 #define SM501_MISC_IRQ_INVERT (1 << 16)
91 #define SM501_MISC_SH (1 << 17)
92
93 #define SM501_MISC_HOLD_EMPTY (0 << 18)
94 #define SM501_MISC_HOLD_8 (1 << 18)
95 #define SM501_MISC_HOLD_16 (2 << 18)
96 #define SM501_MISC_HOLD_24 (3 << 18)
97 #define SM501_MISC_HOLD_32 (4 << 18)
98 #define SM501_MISC_HOLD_MASK (7 << 18)
99
100 #define SM501_MISC_FREQ_12 (1 << 24)
101 #define SM501_MISC_PNL_24BIT (1 << 25)
102 #define SM501_MISC_8051_LE (1 << 26)
103
104
105
106 #define SM501_GPIO31_0_CONTROL (0x000008)
107 #define SM501_GPIO63_32_CONTROL (0x00000C)
108 #define SM501_DRAM_CONTROL (0x000010)
109
110 /* command list */
111 #define SM501_ARBTRTN_CONTROL (0x000014)
112
113 /* command list */
114 #define SM501_COMMAND_LIST_STATUS (0x000024)
115
116 /* interrupt debug */
117 #define SM501_RAW_IRQ_STATUS (0x000028)
118 #define SM501_RAW_IRQ_CLEAR (0x000028)
119 #define SM501_IRQ_STATUS (0x00002C)
120 #define SM501_IRQ_MASK (0x000030)
121 #define SM501_DEBUG_CONTROL (0x000034)
122
123 /* power management */
124 #define SM501_POWERMODE_P2X_SRC (1 << 29)
125 #define SM501_POWERMODE_V2X_SRC (1 << 20)
126 #define SM501_POWERMODE_M_SRC (1 << 12)
127 #define SM501_POWERMODE_M1_SRC (1 << 4)
128
129 #define SM501_CURRENT_GATE (0x000038)
130 #define SM501_CURRENT_CLOCK (0x00003C)
131 #define SM501_POWER_MODE_0_GATE (0x000040)
132 #define SM501_POWER_MODE_0_CLOCK (0x000044)
133 #define SM501_POWER_MODE_1_GATE (0x000048)
134 #define SM501_POWER_MODE_1_CLOCK (0x00004C)
135 #define SM501_SLEEP_MODE_GATE (0x000050)
136 #define SM501_POWER_MODE_CONTROL (0x000054)
137
138 /* power gates for units within the 501 */
139 #define SM501_GATE_HOST (0)
140 #define SM501_GATE_MEMORY (1)
141 #define SM501_GATE_DISPLAY (2)
142 #define SM501_GATE_2D_ENGINE (3)
143 #define SM501_GATE_CSC (4)
144 #define SM501_GATE_ZVPORT (5)
145 #define SM501_GATE_GPIO (6)
146 #define SM501_GATE_UART0 (7)
147 #define SM501_GATE_UART1 (8)
148 #define SM501_GATE_SSP (10)
149 #define SM501_GATE_USB_HOST (11)
150 #define SM501_GATE_USB_GADGET (12)
151 #define SM501_GATE_UCONTROLLER (17)
152 #define SM501_GATE_AC97 (18)
153
154 /* panel clock */
155 #define SM501_CLOCK_P2XCLK (24)
156 /* crt clock */
157 #define SM501_CLOCK_V2XCLK (16)
158 /* main clock */
159 #define SM501_CLOCK_MCLK (8)
160 /* SDRAM controller clock */
161 #define SM501_CLOCK_M1XCLK (0)
162
163 /* config 2 */
164 #define SM501_PCI_MASTER_BASE (0x000058)
165 #define SM501_ENDIAN_CONTROL (0x00005C)
166 #define SM501_DEVICEID (0x000060)
167 /* 0x050100A0 */
168
169 #define SM501_DEVICEID_SM501 (0x05010000)
170 #define SM501_DEVICEID_IDMASK (0xffff0000)
171 #define SM501_DEVICEID_REVMASK (0x000000ff)
172
173 #define SM501_PLLCLOCK_COUNT (0x000064)
174 #define SM501_MISC_TIMING (0x000068)
175 #define SM501_CURRENT_SDRAM_CLOCK (0x00006C)
176
177 #define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074)
178
179 /* GPIO base */
180 #define SM501_GPIO (0x010000)
181 #define SM501_GPIO_DATA_LOW (0x00)
182 #define SM501_GPIO_DATA_HIGH (0x04)
183 #define SM501_GPIO_DDR_LOW (0x08)
184 #define SM501_GPIO_DDR_HIGH (0x0C)
185 #define SM501_GPIO_IRQ_SETUP (0x10)
186 #define SM501_GPIO_IRQ_STATUS (0x14)
187 #define SM501_GPIO_IRQ_RESET (0x14)
188
189 /* I2C controller base */
190 #define SM501_I2C (0x010040)
191 #define SM501_I2C_BYTE_COUNT (0x00)
192 #define SM501_I2C_CONTROL (0x01)
193 #define SM501_I2C_STATUS (0x02)
194 #define SM501_I2C_RESET (0x02)
195 #define SM501_I2C_SLAVE_ADDRESS (0x03)
196 #define SM501_I2C_DATA (0x04)
197
198 #define SM501_I2C_CONTROL_START (1 << 2)
199 #define SM501_I2C_CONTROL_ENABLE (1 << 0)
200
201 #define SM501_I2C_STATUS_COMPLETE (1 << 3)
202 #define SM501_I2C_STATUS_ERROR (1 << 2)
203
204 #define SM501_I2C_RESET_ERROR (1 << 2)
205
206 /* SSP base */
207 #define SM501_SSP (0x020000)
208
209 /* Uart 0 base */
210 #define SM501_UART0 (0x030000)
211
212 /* Uart 1 base */
213 #define SM501_UART1 (0x030020)
214
215 /* USB host port base */
216 #define SM501_USB_HOST (0x040000)
217
218 /* USB slave/gadget base */
219 #define SM501_USB_GADGET (0x060000)
220
221 /* USB slave/gadget data port base */
222 #define SM501_USB_GADGET_DATA (0x070000)
223
224 /* Display controller/video engine base */
225 #define SM501_DC (0x080000)
226
227 /* common defines for the SM501 address registers */
228 #define SM501_ADDR_FLIP (1 << 31)
229 #define SM501_ADDR_EXT (1 << 27)
230 #define SM501_ADDR_CS1 (1 << 26)
231 #define SM501_ADDR_MASK (0x3f << 26)
232
233 #define SM501_FIFO_MASK (0x3 << 16)
234 #define SM501_FIFO_1 (0x0 << 16)
235 #define SM501_FIFO_3 (0x1 << 16)
236 #define SM501_FIFO_7 (0x2 << 16)
237 #define SM501_FIFO_11 (0x3 << 16)
238
239 /* common registers for panel and the crt */
240 #define SM501_OFF_DC_H_TOT (0x000)
241 #define SM501_OFF_DC_V_TOT (0x008)
242 #define SM501_OFF_DC_H_SYNC (0x004)
243 #define SM501_OFF_DC_V_SYNC (0x00C)
244
245 #define SM501_DC_PANEL_CONTROL (0x000)
246
247 #define SM501_DC_PANEL_CONTROL_FPEN (1 << 27)
248 #define SM501_DC_PANEL_CONTROL_BIAS (1 << 26)
249 #define SM501_DC_PANEL_CONTROL_DATA (1 << 25)
250 #define SM501_DC_PANEL_CONTROL_VDD (1 << 24)
251 #define SM501_DC_PANEL_CONTROL_DP (1 << 23)
252
253 #define SM501_DC_PANEL_CONTROL_TFT_888 (0 << 21)
254 #define SM501_DC_PANEL_CONTROL_TFT_333 (1 << 21)
255 #define SM501_DC_PANEL_CONTROL_TFT_444 (2 << 21)
256
257 #define SM501_DC_PANEL_CONTROL_DE (1 << 20)
258
259 #define SM501_DC_PANEL_CONTROL_LCD_TFT (0 << 18)
260 #define SM501_DC_PANEL_CONTROL_LCD_STN8 (1 << 18)
261 #define SM501_DC_PANEL_CONTROL_LCD_STN12 (2 << 18)
262
263 #define SM501_DC_PANEL_CONTROL_CP (1 << 14)
264 #define SM501_DC_PANEL_CONTROL_VSP (1 << 13)
265 #define SM501_DC_PANEL_CONTROL_HSP (1 << 12)
266 #define SM501_DC_PANEL_CONTROL_CK (1 << 9)
267 #define SM501_DC_PANEL_CONTROL_TE (1 << 8)
268 #define SM501_DC_PANEL_CONTROL_VPD (1 << 7)
269 #define SM501_DC_PANEL_CONTROL_VP (1 << 6)
270 #define SM501_DC_PANEL_CONTROL_HPD (1 << 5)
271 #define SM501_DC_PANEL_CONTROL_HP (1 << 4)
272 #define SM501_DC_PANEL_CONTROL_GAMMA (1 << 3)
273 #define SM501_DC_PANEL_CONTROL_EN (1 << 2)
274
275 #define SM501_DC_PANEL_CONTROL_8BPP (0 << 0)
276 #define SM501_DC_PANEL_CONTROL_16BPP (1 << 0)
277 #define SM501_DC_PANEL_CONTROL_32BPP (2 << 0)
278
279
280 #define SM501_DC_PANEL_PANNING_CONTROL (0x004)
281 #define SM501_DC_PANEL_COLOR_KEY (0x008)
282 #define SM501_DC_PANEL_FB_ADDR (0x00C)
283 #define SM501_DC_PANEL_FB_OFFSET (0x010)
284 #define SM501_DC_PANEL_FB_WIDTH (0x014)
285 #define SM501_DC_PANEL_FB_HEIGHT (0x018)
286 #define SM501_DC_PANEL_TL_LOC (0x01C)
287 #define SM501_DC_PANEL_BR_LOC (0x020)
288 #define SM501_DC_PANEL_H_TOT (0x024)
289 #define SM501_DC_PANEL_H_SYNC (0x028)
290 #define SM501_DC_PANEL_V_TOT (0x02C)
291 #define SM501_DC_PANEL_V_SYNC (0x030)
292 #define SM501_DC_PANEL_CUR_LINE (0x034)
293
294 #define SM501_DC_VIDEO_CONTROL (0x040)
295 #define SM501_DC_VIDEO_FB0_ADDR (0x044)
296 #define SM501_DC_VIDEO_FB_WIDTH (0x048)
297 #define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C)
298 #define SM501_DC_VIDEO_TL_LOC (0x050)
299 #define SM501_DC_VIDEO_BR_LOC (0x054)
300 #define SM501_DC_VIDEO_SCALE (0x058)
301 #define SM501_DC_VIDEO_INIT_SCALE (0x05C)
302 #define SM501_DC_VIDEO_YUV_CONSTANTS (0x060)
303 #define SM501_DC_VIDEO_FB1_ADDR (0x064)
304 #define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068)
305
306 #define SM501_DC_VIDEO_ALPHA_CONTROL (0x080)
307 #define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084)
308 #define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088)
309 #define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C)
310 #define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090)
311 #define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094)
312 #define SM501_DC_VIDEO_ALPHA_SCALE (0x098)
313 #define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C)
314 #define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0)
315 #define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4)
316
317 #define SM501_DC_PANEL_HWC_BASE (0x0F0)
318 #define SM501_DC_PANEL_HWC_ADDR (0x0F0)
319 #define SM501_DC_PANEL_HWC_LOC (0x0F4)
320 #define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8)
321 #define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC)
322
323 #define SM501_HWC_EN (1 << 31)
324
325 #define SM501_OFF_HWC_ADDR (0x00)
326 #define SM501_OFF_HWC_LOC (0x04)
327 #define SM501_OFF_HWC_COLOR_1_2 (0x08)
328 #define SM501_OFF_HWC_COLOR_3 (0x0C)
329
330 #define SM501_DC_ALPHA_CONTROL (0x100)
331 #define SM501_DC_ALPHA_FB_ADDR (0x104)
332 #define SM501_DC_ALPHA_FB_OFFSET (0x108)
333 #define SM501_DC_ALPHA_TL_LOC (0x10C)
334 #define SM501_DC_ALPHA_BR_LOC (0x110)
335 #define SM501_DC_ALPHA_CHROMA_KEY (0x114)
336 #define SM501_DC_ALPHA_COLOR_LOOKUP (0x118)
337
338 #define SM501_DC_CRT_CONTROL (0x200)
339
340 #define SM501_DC_CRT_CONTROL_TVP (1 << 15)
341 #define SM501_DC_CRT_CONTROL_CP (1 << 14)
342 #define SM501_DC_CRT_CONTROL_VSP (1 << 13)
343 #define SM501_DC_CRT_CONTROL_HSP (1 << 12)
344 #define SM501_DC_CRT_CONTROL_VS (1 << 11)
345 #define SM501_DC_CRT_CONTROL_BLANK (1 << 10)
346 #define SM501_DC_CRT_CONTROL_SEL (1 << 9)
347 #define SM501_DC_CRT_CONTROL_TE (1 << 8)
348 #define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4)
349 #define SM501_DC_CRT_CONTROL_GAMMA (1 << 3)
350 #define SM501_DC_CRT_CONTROL_ENABLE (1 << 2)
351
352 #define SM501_DC_CRT_CONTROL_8BPP (0 << 0)
353 #define SM501_DC_CRT_CONTROL_16BPP (1 << 0)
354 #define SM501_DC_CRT_CONTROL_32BPP (2 << 0)
355
356 #define SM501_DC_CRT_FB_ADDR (0x204)
357 #define SM501_DC_CRT_FB_OFFSET (0x208)
358 #define SM501_DC_CRT_H_TOT (0x20C)
359 #define SM501_DC_CRT_H_SYNC (0x210)
360 #define SM501_DC_CRT_V_TOT (0x214)
361 #define SM501_DC_CRT_V_SYNC (0x218)
362 #define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C)
363 #define SM501_DC_CRT_CUR_LINE (0x220)
364 #define SM501_DC_CRT_MONITOR_DETECT (0x224)
365
366 #define SM501_DC_CRT_HWC_BASE (0x230)
367 #define SM501_DC_CRT_HWC_ADDR (0x230)
368 #define SM501_DC_CRT_HWC_LOC (0x234)
369 #define SM501_DC_CRT_HWC_COLOR_1_2 (0x238)
370 #define SM501_DC_CRT_HWC_COLOR_3 (0x23C)
371
372 #define SM501_DC_PANEL_PALETTE (0x400)
373
374 #define SM501_DC_VIDEO_PALETTE (0x800)
375
376 #define SM501_DC_CRT_PALETTE (0xC00)
377
378 /* Zoom Video port base */
379 #define SM501_ZVPORT (0x090000)
380
381 /* AC97/I2S base */
382 #define SM501_AC97 (0x0A0000)
383
384 /* 8051 micro controller base */
385 #define SM501_UCONTROLLER (0x0B0000)
386
387 /* 8051 micro controller SRAM base */
388 #define SM501_UCONTROLLER_SRAM (0x0C0000)
389
390 /* DMA base */
391 #define SM501_DMA (0x0D0000)
392
393 /* 2d engine base */
394 #define SM501_2D_ENGINE (0x100000)
395 #define SM501_2D_SOURCE (0x00)
396 #define SM501_2D_DESTINATION (0x04)
397 #define SM501_2D_DIMENSION (0x08)
398 #define SM501_2D_CONTROL (0x0C)
399 #define SM501_2D_PITCH (0x10)
400 #define SM501_2D_FOREGROUND (0x14)
401 #define SM501_2D_BACKGROUND (0x18)
402 #define SM501_2D_STRETCH (0x1C)
403 #define SM501_2D_COLOR_COMPARE (0x20)
404 #define SM501_2D_COLOR_COMPARE_MASK (0x24)
405 #define SM501_2D_MASK (0x28)
406 #define SM501_2D_CLIP_TL (0x2C)
407 #define SM501_2D_CLIP_BR (0x30)
408 #define SM501_2D_MONO_PATTERN_LOW (0x34)
409 #define SM501_2D_MONO_PATTERN_HIGH (0x38)
410 #define SM501_2D_WINDOW_WIDTH (0x3C)
411 #define SM501_2D_SOURCE_BASE (0x40)
412 #define SM501_2D_DESTINATION_BASE (0x44)
413 #define SM501_2D_ALPHA (0x48)
414 #define SM501_2D_WRAP (0x4C)
415 #define SM501_2D_STATUS (0x50)
416
417 #define SM501_CSC_Y_SOURCE_BASE (0xC8)
418 #define SM501_CSC_CONSTANTS (0xCC)
419 #define SM501_CSC_Y_SOURCE_X (0xD0)
420 #define SM501_CSC_Y_SOURCE_Y (0xD4)
421 #define SM501_CSC_U_SOURCE_BASE (0xD8)
422 #define SM501_CSC_V_SOURCE_BASE (0xDC)
423 #define SM501_CSC_SOURCE_DIMENSION (0xE0)
424 #define SM501_CSC_SOURCE_PITCH (0xE4)
425 #define SM501_CSC_DESTINATION (0xE8)
426 #define SM501_CSC_DESTINATION_DIMENSION (0xEC)
427 #define SM501_CSC_DESTINATION_PITCH (0xF0)
428 #define SM501_CSC_SCALE_FACTOR (0xF4)
429 #define SM501_CSC_DESTINATION_BASE (0xF8)
430 #define SM501_CSC_CONTROL (0xFC)
431
432 /* 2d engine data port base */
433 #define SM501_2D_ENGINE_DATA (0x110000)
434
435 /* end of register definitions */
436
437 #define SM501_HWC_WIDTH (64)
438 #define SM501_HWC_HEIGHT (64)
439
440 /* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */
441 static const uint32_t sm501_mem_local_size[] = {
442 [0] = 4 * MiB,
443 [1] = 8 * MiB,
444 [2] = 16 * MiB,
445 [3] = 32 * MiB,
446 [4] = 64 * MiB,
447 [5] = 2 * MiB,
448 };
449 #define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index]
450
451 typedef struct SM501State {
452 /* graphic console status */
453 QemuConsole *con;
454
455 /* status & internal resources */
456 uint32_t local_mem_size_index;
457 uint8_t *local_mem;
458 MemoryRegion local_mem_region;
459 MemoryRegion mmio_region;
460 MemoryRegion system_config_region;
461 MemoryRegion i2c_region;
462 MemoryRegion disp_ctrl_region;
463 MemoryRegion twoD_engine_region;
464 uint32_t last_width;
465 uint32_t last_height;
466 bool do_full_update; /* perform a full update next time */
467 I2CBus *i2c_bus;
468
469 /* mmio registers */
470 uint32_t system_control;
471 uint32_t misc_control;
472 uint32_t gpio_31_0_control;
473 uint32_t gpio_63_32_control;
474 uint32_t dram_control;
475 uint32_t arbitration_control;
476 uint32_t irq_mask;
477 uint32_t misc_timing;
478 uint32_t power_mode_control;
479
480 uint8_t i2c_byte_count;
481 uint8_t i2c_status;
482 uint8_t i2c_addr;
483 uint8_t i2c_data[16];
484
485 uint32_t uart0_ier;
486 uint32_t uart0_lcr;
487 uint32_t uart0_mcr;
488 uint32_t uart0_scr;
489
490 uint8_t dc_palette[DC_PALETTE_ENTRIES];
491
492 uint32_t dc_panel_control;
493 uint32_t dc_panel_panning_control;
494 uint32_t dc_panel_fb_addr;
495 uint32_t dc_panel_fb_offset;
496 uint32_t dc_panel_fb_width;
497 uint32_t dc_panel_fb_height;
498 uint32_t dc_panel_tl_location;
499 uint32_t dc_panel_br_location;
500 uint32_t dc_panel_h_total;
501 uint32_t dc_panel_h_sync;
502 uint32_t dc_panel_v_total;
503 uint32_t dc_panel_v_sync;
504
505 uint32_t dc_panel_hwc_addr;
506 uint32_t dc_panel_hwc_location;
507 uint32_t dc_panel_hwc_color_1_2;
508 uint32_t dc_panel_hwc_color_3;
509
510 uint32_t dc_video_control;
511
512 uint32_t dc_crt_control;
513 uint32_t dc_crt_fb_addr;
514 uint32_t dc_crt_fb_offset;
515 uint32_t dc_crt_h_total;
516 uint32_t dc_crt_h_sync;
517 uint32_t dc_crt_v_total;
518 uint32_t dc_crt_v_sync;
519
520 uint32_t dc_crt_hwc_addr;
521 uint32_t dc_crt_hwc_location;
522 uint32_t dc_crt_hwc_color_1_2;
523 uint32_t dc_crt_hwc_color_3;
524
525 uint32_t twoD_source;
526 uint32_t twoD_destination;
527 uint32_t twoD_dimension;
528 uint32_t twoD_control;
529 uint32_t twoD_pitch;
530 uint32_t twoD_foreground;
531 uint32_t twoD_background;
532 uint32_t twoD_stretch;
533 uint32_t twoD_color_compare;
534 uint32_t twoD_color_compare_mask;
535 uint32_t twoD_mask;
536 uint32_t twoD_clip_tl;
537 uint32_t twoD_clip_br;
538 uint32_t twoD_mono_pattern_low;
539 uint32_t twoD_mono_pattern_high;
540 uint32_t twoD_window_width;
541 uint32_t twoD_source_base;
542 uint32_t twoD_destination_base;
543 uint32_t twoD_alpha;
544 uint32_t twoD_wrap;
545 } SM501State;
546
547 static uint32_t get_local_mem_size_index(uint32_t size)
548 {
549 uint32_t norm_size = 0;
550 int i, index = 0;
551
552 for (i = 0; i < ARRAY_SIZE(sm501_mem_local_size); i++) {
553 uint32_t new_size = sm501_mem_local_size[i];
554 if (new_size >= size) {
555 if (norm_size == 0 || norm_size > new_size) {
556 norm_size = new_size;
557 index = i;
558 }
559 }
560 }
561
562 return index;
563 }
564
565 static ram_addr_t get_fb_addr(SM501State *s, int crt)
566 {
567 return (crt ? s->dc_crt_fb_addr : s->dc_panel_fb_addr) & 0x3FFFFF0;
568 }
569
570 static inline int get_width(SM501State *s, int crt)
571 {
572 int width = crt ? s->dc_crt_h_total : s->dc_panel_h_total;
573 return (width & 0x00000FFF) + 1;
574 }
575
576 static inline int get_height(SM501State *s, int crt)
577 {
578 int height = crt ? s->dc_crt_v_total : s->dc_panel_v_total;
579 return (height & 0x00000FFF) + 1;
580 }
581
582 static inline int get_bpp(SM501State *s, int crt)
583 {
584 int bpp = crt ? s->dc_crt_control : s->dc_panel_control;
585 return 1 << (bpp & 3);
586 }
587
588 /**
589 * Check the availability of hardware cursor.
590 * @param crt 0 for PANEL, 1 for CRT.
591 */
592 static inline int is_hwc_enabled(SM501State *state, int crt)
593 {
594 uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr;
595 return addr & SM501_HWC_EN;
596 }
597
598 /**
599 * Get the address which holds cursor pattern data.
600 * @param crt 0 for PANEL, 1 for CRT.
601 */
602 static inline uint8_t *get_hwc_address(SM501State *state, int crt)
603 {
604 uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr;
605 return state->local_mem + (addr & 0x03FFFFF0);
606 }
607
608 /**
609 * Get the cursor position in y coordinate.
610 * @param crt 0 for PANEL, 1 for CRT.
611 */
612 static inline uint32_t get_hwc_y(SM501State *state, int crt)
613 {
614 uint32_t location = crt ? state->dc_crt_hwc_location
615 : state->dc_panel_hwc_location;
616 return (location & 0x07FF0000) >> 16;
617 }
618
619 /**
620 * Get the cursor position in x coordinate.
621 * @param crt 0 for PANEL, 1 for CRT.
622 */
623 static inline uint32_t get_hwc_x(SM501State *state, int crt)
624 {
625 uint32_t location = crt ? state->dc_crt_hwc_location
626 : state->dc_panel_hwc_location;
627 return location & 0x000007FF;
628 }
629
630 /**
631 * Get the hardware cursor palette.
632 * @param crt 0 for PANEL, 1 for CRT.
633 * @param palette pointer to a [3 * 3] array to store color values in
634 */
635 static inline void get_hwc_palette(SM501State *state, int crt, uint8_t *palette)
636 {
637 int i;
638 uint32_t color_reg;
639 uint16_t rgb565;
640
641 for (i = 0; i < 3; i++) {
642 if (i + 1 == 3) {
643 color_reg = crt ? state->dc_crt_hwc_color_3
644 : state->dc_panel_hwc_color_3;
645 } else {
646 color_reg = crt ? state->dc_crt_hwc_color_1_2
647 : state->dc_panel_hwc_color_1_2;
648 }
649
650 if (i + 1 == 2) {
651 rgb565 = (color_reg >> 16) & 0xFFFF;
652 } else {
653 rgb565 = color_reg & 0xFFFF;
654 }
655 palette[i * 3 + 0] = ((rgb565 >> 11) * 527 + 23) >> 6; /* r */
656 palette[i * 3 + 1] = (((rgb565 >> 5) & 0x3f) * 259 + 33) >> 6; /* g */
657 palette[i * 3 + 2] = ((rgb565 & 0x1f) * 527 + 23) >> 6; /* b */
658 }
659 }
660
661 static inline void hwc_invalidate(SM501State *s, int crt)
662 {
663 int w = get_width(s, crt);
664 int h = get_height(s, crt);
665 int bpp = get_bpp(s, crt);
666 int start = get_hwc_y(s, crt);
667 int end = MIN(h, start + SM501_HWC_HEIGHT) + 1;
668
669 start *= w * bpp;
670 end *= w * bpp;
671
672 memory_region_set_dirty(&s->local_mem_region,
673 get_fb_addr(s, crt) + start, end - start);
674 }
675
676 static void sm501_2d_operation(SM501State *s)
677 {
678 int cmd = (s->twoD_control >> 16) & 0x1F;
679 int rtl = s->twoD_control & BIT(27);
680 int format = (s->twoD_stretch >> 20) & 3;
681 int bypp = 1 << format; /* bytes per pixel */
682 int rop_mode = (s->twoD_control >> 15) & 1; /* 1 for rop2, else rop3 */
683 /* 1 if rop2 source is the pattern, otherwise the source is the bitmap */
684 int rop2_source_is_pattern = (s->twoD_control >> 14) & 1;
685 int rop = s->twoD_control & 0xFF;
686 unsigned int dst_x = (s->twoD_destination >> 16) & 0x01FFF;
687 unsigned int dst_y = s->twoD_destination & 0xFFFF;
688 unsigned int width = (s->twoD_dimension >> 16) & 0x1FFF;
689 unsigned int height = s->twoD_dimension & 0xFFFF;
690 uint32_t dst_base = s->twoD_destination_base & 0x03FFFFFF;
691 unsigned int dst_pitch = (s->twoD_pitch >> 16) & 0x1FFF;
692 int crt = (s->dc_crt_control & SM501_DC_CRT_CONTROL_SEL) ? 1 : 0;
693 int fb_len = get_width(s, crt) * get_height(s, crt) * get_bpp(s, crt);
694 bool overlap = false;
695
696 if ((s->twoD_stretch >> 16) & 0xF) {
697 qemu_log_mask(LOG_UNIMP, "sm501: only XY addressing is supported.\n");
698 return;
699 }
700
701 if (s->twoD_source_base & BIT(27) || s->twoD_destination_base & BIT(27)) {
702 qemu_log_mask(LOG_UNIMP, "sm501: only local memory is supported.\n");
703 return;
704 }
705
706 if (!dst_pitch) {
707 qemu_log_mask(LOG_GUEST_ERROR, "sm501: Zero dest pitch.\n");
708 return;
709 }
710
711 if (!width || !height) {
712 qemu_log_mask(LOG_GUEST_ERROR, "sm501: Zero size 2D op.\n");
713 return;
714 }
715
716 if (rtl) {
717 dst_x -= width - 1;
718 dst_y -= height - 1;
719 }
720
721 if (dst_base >= get_local_mem_size(s) ||
722 dst_base + (dst_x + width + (dst_y + height) * dst_pitch) * bypp >=
723 get_local_mem_size(s)) {
724 qemu_log_mask(LOG_GUEST_ERROR, "sm501: 2D op dest is outside vram.\n");
725 return;
726 }
727
728 switch (cmd) {
729 case 0: /* BitBlt */
730 {
731 static uint32_t tmp_buf[16384];
732 unsigned int src_x = (s->twoD_source >> 16) & 0x01FFF;
733 unsigned int src_y = s->twoD_source & 0xFFFF;
734 uint32_t src_base = s->twoD_source_base & 0x03FFFFFF;
735 unsigned int src_pitch = s->twoD_pitch & 0x1FFF;
736
737 if (!src_pitch) {
738 qemu_log_mask(LOG_GUEST_ERROR, "sm501: Zero src pitch.\n");
739 return;
740 }
741
742 if (rtl) {
743 src_x -= width - 1;
744 src_y -= height - 1;
745 }
746
747 if (src_base >= get_local_mem_size(s) ||
748 src_base + (src_x + width + (src_y + height) * src_pitch) * bypp >=
749 get_local_mem_size(s)) {
750 qemu_log_mask(LOG_GUEST_ERROR,
751 "sm501: 2D op src is outside vram.\n");
752 return;
753 }
754
755 if ((rop_mode && rop == 0x5) || (!rop_mode && rop == 0x55)) {
756 /* Invert dest, is there a way to do this with pixman? */
757 unsigned int x, y, i;
758 uint8_t *d = s->local_mem + dst_base;
759
760 for (y = 0; y < height; y++) {
761 i = (dst_x + (dst_y + y) * dst_pitch) * bypp;
762 for (x = 0; x < width; x++, i += bypp) {
763 stn_he_p(&d[i], bypp, ~ldn_he_p(&d[i], bypp));
764 }
765 }
766 } else {
767 /* Do copy src for unimplemented ops, better than unpainted area */
768 if ((rop_mode && (rop != 0xc || rop2_source_is_pattern)) ||
769 (!rop_mode && rop != 0xcc)) {
770 qemu_log_mask(LOG_UNIMP,
771 "sm501: rop%d op %x%s not implemented\n",
772 (rop_mode ? 2 : 3), rop,
773 (rop2_source_is_pattern ?
774 " with pattern source" : ""));
775 }
776 /* Ignore no-op blits, some guests seem to do this */
777 if (src_base == dst_base && src_pitch == dst_pitch &&
778 src_x == dst_x && src_y == dst_y) {
779 break;
780 }
781 /* Some clients also do 1 pixel blits, avoid overhead for these */
782 if (width == 1 && height == 1) {
783 unsigned int si = (src_x + src_y * src_pitch) * bypp;
784 unsigned int di = (dst_x + dst_y * dst_pitch) * bypp;
785 stn_he_p(&s->local_mem[dst_base + di], bypp,
786 ldn_he_p(&s->local_mem[src_base + si], bypp));
787 break;
788 }
789 /* If reverse blit do simple check for overlaps */
790 if (rtl && src_base == dst_base && src_pitch == dst_pitch) {
791 overlap = (src_x < dst_x + width && src_x + width > dst_x &&
792 src_y < dst_y + height && src_y + height > dst_y);
793 } else if (rtl) {
794 unsigned int sb, se, db, de;
795 sb = src_base + (src_x + src_y * src_pitch) * bypp;
796 se = sb + (width + (height - 1) * src_pitch) * bypp;
797 db = dst_base + (dst_x + dst_y * dst_pitch) * bypp;
798 de = db + (width + (height - 1) * dst_pitch) * bypp;
799 overlap = (db < se && sb < de);
800 }
801 if (overlap) {
802 /* pixman can't do reverse blit: copy via temporary */
803 int tmp_stride = DIV_ROUND_UP(width * bypp, sizeof(uint32_t));
804 uint32_t *tmp = tmp_buf;
805
806 if (tmp_stride * sizeof(uint32_t) * height > sizeof(tmp_buf)) {
807 tmp = g_malloc(tmp_stride * sizeof(uint32_t) * height);
808 }
809 pixman_blt((uint32_t *)&s->local_mem[src_base], tmp,
810 src_pitch * bypp / sizeof(uint32_t),
811 tmp_stride, 8 * bypp, 8 * bypp,
812 src_x, src_y, 0, 0, width, height);
813 pixman_blt(tmp, (uint32_t *)&s->local_mem[dst_base],
814 tmp_stride,
815 dst_pitch * bypp / sizeof(uint32_t),
816 8 * bypp, 8 * bypp,
817 0, 0, dst_x, dst_y, width, height);
818 if (tmp != tmp_buf) {
819 g_free(tmp);
820 }
821 } else {
822 pixman_blt((uint32_t *)&s->local_mem[src_base],
823 (uint32_t *)&s->local_mem[dst_base],
824 src_pitch * bypp / sizeof(uint32_t),
825 dst_pitch * bypp / sizeof(uint32_t),
826 8 * bypp, 8 * bypp,
827 src_x, src_y, dst_x, dst_y, width, height);
828 }
829 }
830 break;
831 }
832 case 1: /* Rectangle Fill */
833 {
834 uint32_t color = s->twoD_foreground;
835
836 if (format == 2) {
837 color = cpu_to_le32(color);
838 } else if (format == 1) {
839 color = cpu_to_le16(color);
840 }
841
842 if (width == 1 && height == 1) {
843 unsigned int i = (dst_x + dst_y * dst_pitch) * bypp;
844 stn_he_p(&s->local_mem[dst_base + i], bypp, color);
845 } else {
846 pixman_fill((uint32_t *)&s->local_mem[dst_base],
847 dst_pitch * bypp / sizeof(uint32_t),
848 8 * bypp, dst_x, dst_y, width, height, color);
849 }
850 break;
851 }
852 default:
853 qemu_log_mask(LOG_UNIMP, "sm501: not implemented 2D operation: %d\n",
854 cmd);
855 return;
856 }
857
858 if (dst_base >= get_fb_addr(s, crt) &&
859 dst_base <= get_fb_addr(s, crt) + fb_len) {
860 int dst_len = MIN(fb_len, ((dst_y + height - 1) * dst_pitch +
861 dst_x + width) * bypp);
862 if (dst_len) {
863 memory_region_set_dirty(&s->local_mem_region, dst_base, dst_len);
864 }
865 }
866 }
867
868 static uint64_t sm501_system_config_read(void *opaque, hwaddr addr,
869 unsigned size)
870 {
871 SM501State *s = (SM501State *)opaque;
872 uint32_t ret = 0;
873
874 switch (addr) {
875 case SM501_SYSTEM_CONTROL:
876 ret = s->system_control;
877 break;
878 case SM501_MISC_CONTROL:
879 ret = s->misc_control;
880 break;
881 case SM501_GPIO31_0_CONTROL:
882 ret = s->gpio_31_0_control;
883 break;
884 case SM501_GPIO63_32_CONTROL:
885 ret = s->gpio_63_32_control;
886 break;
887 case SM501_DEVICEID:
888 ret = 0x050100A0;
889 break;
890 case SM501_DRAM_CONTROL:
891 ret = (s->dram_control & 0x07F107C0) | s->local_mem_size_index << 13;
892 break;
893 case SM501_ARBTRTN_CONTROL:
894 ret = s->arbitration_control;
895 break;
896 case SM501_COMMAND_LIST_STATUS:
897 ret = 0x00180002; /* FIFOs are empty, everything idle */
898 break;
899 case SM501_IRQ_MASK:
900 ret = s->irq_mask;
901 break;
902 case SM501_MISC_TIMING:
903 /* TODO : simulate gate control */
904 ret = s->misc_timing;
905 break;
906 case SM501_CURRENT_GATE:
907 /* TODO : simulate gate control */
908 ret = 0x00021807;
909 break;
910 case SM501_CURRENT_CLOCK:
911 ret = 0x2A1A0A09;
912 break;
913 case SM501_POWER_MODE_CONTROL:
914 ret = s->power_mode_control;
915 break;
916 case SM501_ENDIAN_CONTROL:
917 ret = 0; /* Only default little endian mode is supported */
918 break;
919
920 default:
921 qemu_log_mask(LOG_UNIMP, "sm501: not implemented system config"
922 "register read. addr=%" HWADDR_PRIx "\n", addr);
923 }
924 trace_sm501_system_config_read(addr, ret);
925 return ret;
926 }
927
928 static void sm501_system_config_write(void *opaque, hwaddr addr,
929 uint64_t value, unsigned size)
930 {
931 SM501State *s = (SM501State *)opaque;
932
933 trace_sm501_system_config_write((uint32_t)addr, (uint32_t)value);
934 switch (addr) {
935 case SM501_SYSTEM_CONTROL:
936 s->system_control &= 0x10DB0000;
937 s->system_control |= value & 0xEF00B8F7;
938 break;
939 case SM501_MISC_CONTROL:
940 s->misc_control &= 0xEF;
941 s->misc_control |= value & 0xFF7FFF10;
942 break;
943 case SM501_GPIO31_0_CONTROL:
944 s->gpio_31_0_control = value;
945 break;
946 case SM501_GPIO63_32_CONTROL:
947 s->gpio_63_32_control = value & 0xFF80FFFF;
948 break;
949 case SM501_DRAM_CONTROL:
950 s->local_mem_size_index = (value >> 13) & 0x7;
951 /* TODO : check validity of size change */
952 s->dram_control &= 0x80000000;
953 s->dram_control |= value & 0x7FFFFFC3;
954 break;
955 case SM501_ARBTRTN_CONTROL:
956 s->arbitration_control = value & 0x37777777;
957 break;
958 case SM501_IRQ_MASK:
959 s->irq_mask = value & 0xFFDF3F5F;
960 break;
961 case SM501_MISC_TIMING:
962 s->misc_timing = value & 0xF31F1FFF;
963 break;
964 case SM501_POWER_MODE_0_GATE:
965 case SM501_POWER_MODE_1_GATE:
966 case SM501_POWER_MODE_0_CLOCK:
967 case SM501_POWER_MODE_1_CLOCK:
968 /* TODO : simulate gate & clock control */
969 break;
970 case SM501_POWER_MODE_CONTROL:
971 s->power_mode_control = value & 0x00000003;
972 break;
973 case SM501_ENDIAN_CONTROL:
974 if (value & 0x00000001) {
975 qemu_log_mask(LOG_UNIMP, "sm501: system config big endian mode not"
976 " implemented.\n");
977 }
978 break;
979
980 default:
981 qemu_log_mask(LOG_UNIMP, "sm501: not implemented system config"
982 "register write. addr=%" HWADDR_PRIx
983 ", val=%" PRIx64 "\n", addr, value);
984 }
985 }
986
987 static const MemoryRegionOps sm501_system_config_ops = {
988 .read = sm501_system_config_read,
989 .write = sm501_system_config_write,
990 .valid = {
991 .min_access_size = 4,
992 .max_access_size = 4,
993 },
994 .endianness = DEVICE_LITTLE_ENDIAN,
995 };
996
997 static uint64_t sm501_i2c_read(void *opaque, hwaddr addr, unsigned size)
998 {
999 SM501State *s = (SM501State *)opaque;
1000 uint8_t ret = 0;
1001
1002 switch (addr) {
1003 case SM501_I2C_BYTE_COUNT:
1004 ret = s->i2c_byte_count;
1005 break;
1006 case SM501_I2C_STATUS:
1007 ret = s->i2c_status;
1008 break;
1009 case SM501_I2C_SLAVE_ADDRESS:
1010 ret = s->i2c_addr;
1011 break;
1012 case SM501_I2C_DATA ... SM501_I2C_DATA + 15:
1013 ret = s->i2c_data[addr - SM501_I2C_DATA];
1014 break;
1015 default:
1016 qemu_log_mask(LOG_UNIMP, "sm501 i2c : not implemented register read."
1017 " addr=0x%" HWADDR_PRIx "\n", addr);
1018 }
1019 trace_sm501_i2c_read((uint32_t)addr, ret);
1020 return ret;
1021 }
1022
1023 static void sm501_i2c_write(void *opaque, hwaddr addr, uint64_t value,
1024 unsigned size)
1025 {
1026 SM501State *s = (SM501State *)opaque;
1027
1028 trace_sm501_i2c_write((uint32_t)addr, (uint32_t)value);
1029 switch (addr) {
1030 case SM501_I2C_BYTE_COUNT:
1031 s->i2c_byte_count = value & 0xf;
1032 break;
1033 case SM501_I2C_CONTROL:
1034 if (value & SM501_I2C_CONTROL_ENABLE) {
1035 if (value & SM501_I2C_CONTROL_START) {
1036 int res = i2c_start_transfer(s->i2c_bus,
1037 s->i2c_addr >> 1,
1038 s->i2c_addr & 1);
1039 s->i2c_status |= (res ? SM501_I2C_STATUS_ERROR : 0);
1040 if (!res) {
1041 int i;
1042 for (i = 0; i <= s->i2c_byte_count; i++) {
1043 res = i2c_send_recv(s->i2c_bus, &s->i2c_data[i],
1044 !(s->i2c_addr & 1));
1045 if (res) {
1046 s->i2c_status |= SM501_I2C_STATUS_ERROR;
1047 return;
1048 }
1049 }
1050 if (i) {
1051 s->i2c_status = SM501_I2C_STATUS_COMPLETE;
1052 }
1053 }
1054 } else {
1055 i2c_end_transfer(s->i2c_bus);
1056 s->i2c_status &= ~SM501_I2C_STATUS_ERROR;
1057 }
1058 }
1059 break;
1060 case SM501_I2C_RESET:
1061 if ((value & SM501_I2C_RESET_ERROR) == 0) {
1062 s->i2c_status &= ~SM501_I2C_STATUS_ERROR;
1063 }
1064 break;
1065 case SM501_I2C_SLAVE_ADDRESS:
1066 s->i2c_addr = value & 0xff;
1067 break;
1068 case SM501_I2C_DATA ... SM501_I2C_DATA + 15:
1069 s->i2c_data[addr - SM501_I2C_DATA] = value & 0xff;
1070 break;
1071 default:
1072 qemu_log_mask(LOG_UNIMP, "sm501 i2c : not implemented register write. "
1073 "addr=0x%" HWADDR_PRIx " val=%" PRIx64 "\n", addr, value);
1074 }
1075 }
1076
1077 static const MemoryRegionOps sm501_i2c_ops = {
1078 .read = sm501_i2c_read,
1079 .write = sm501_i2c_write,
1080 .valid = {
1081 .min_access_size = 1,
1082 .max_access_size = 1,
1083 },
1084 .impl = {
1085 .min_access_size = 1,
1086 .max_access_size = 1,
1087 },
1088 .endianness = DEVICE_LITTLE_ENDIAN,
1089 };
1090
1091 static uint32_t sm501_palette_read(void *opaque, hwaddr addr)
1092 {
1093 SM501State *s = (SM501State *)opaque;
1094
1095 trace_sm501_palette_read((uint32_t)addr);
1096
1097 /* TODO : consider BYTE/WORD access */
1098 /* TODO : consider endian */
1099
1100 assert(range_covers_byte(0, 0x400 * 3, addr));
1101 return *(uint32_t *)&s->dc_palette[addr];
1102 }
1103
1104 static void sm501_palette_write(void *opaque, hwaddr addr,
1105 uint32_t value)
1106 {
1107 SM501State *s = (SM501State *)opaque;
1108
1109 trace_sm501_palette_write((uint32_t)addr, value);
1110
1111 /* TODO : consider BYTE/WORD access */
1112 /* TODO : consider endian */
1113
1114 assert(range_covers_byte(0, 0x400 * 3, addr));
1115 *(uint32_t *)&s->dc_palette[addr] = value;
1116 s->do_full_update = true;
1117 }
1118
1119 static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr,
1120 unsigned size)
1121 {
1122 SM501State *s = (SM501State *)opaque;
1123 uint32_t ret = 0;
1124
1125 switch (addr) {
1126
1127 case SM501_DC_PANEL_CONTROL:
1128 ret = s->dc_panel_control;
1129 break;
1130 case SM501_DC_PANEL_PANNING_CONTROL:
1131 ret = s->dc_panel_panning_control;
1132 break;
1133 case SM501_DC_PANEL_COLOR_KEY:
1134 /* Not implemented yet */
1135 break;
1136 case SM501_DC_PANEL_FB_ADDR:
1137 ret = s->dc_panel_fb_addr;
1138 break;
1139 case SM501_DC_PANEL_FB_OFFSET:
1140 ret = s->dc_panel_fb_offset;
1141 break;
1142 case SM501_DC_PANEL_FB_WIDTH:
1143 ret = s->dc_panel_fb_width;
1144 break;
1145 case SM501_DC_PANEL_FB_HEIGHT:
1146 ret = s->dc_panel_fb_height;
1147 break;
1148 case SM501_DC_PANEL_TL_LOC:
1149 ret = s->dc_panel_tl_location;
1150 break;
1151 case SM501_DC_PANEL_BR_LOC:
1152 ret = s->dc_panel_br_location;
1153 break;
1154
1155 case SM501_DC_PANEL_H_TOT:
1156 ret = s->dc_panel_h_total;
1157 break;
1158 case SM501_DC_PANEL_H_SYNC:
1159 ret = s->dc_panel_h_sync;
1160 break;
1161 case SM501_DC_PANEL_V_TOT:
1162 ret = s->dc_panel_v_total;
1163 break;
1164 case SM501_DC_PANEL_V_SYNC:
1165 ret = s->dc_panel_v_sync;
1166 break;
1167
1168 case SM501_DC_PANEL_HWC_ADDR:
1169 ret = s->dc_panel_hwc_addr;
1170 break;
1171 case SM501_DC_PANEL_HWC_LOC:
1172 ret = s->dc_panel_hwc_location;
1173 break;
1174 case SM501_DC_PANEL_HWC_COLOR_1_2:
1175 ret = s->dc_panel_hwc_color_1_2;
1176 break;
1177 case SM501_DC_PANEL_HWC_COLOR_3:
1178 ret = s->dc_panel_hwc_color_3;
1179 break;
1180
1181 case SM501_DC_VIDEO_CONTROL:
1182 ret = s->dc_video_control;
1183 break;
1184
1185 case SM501_DC_CRT_CONTROL:
1186 ret = s->dc_crt_control;
1187 break;
1188 case SM501_DC_CRT_FB_ADDR:
1189 ret = s->dc_crt_fb_addr;
1190 break;
1191 case SM501_DC_CRT_FB_OFFSET:
1192 ret = s->dc_crt_fb_offset;
1193 break;
1194 case SM501_DC_CRT_H_TOT:
1195 ret = s->dc_crt_h_total;
1196 break;
1197 case SM501_DC_CRT_H_SYNC:
1198 ret = s->dc_crt_h_sync;
1199 break;
1200 case SM501_DC_CRT_V_TOT:
1201 ret = s->dc_crt_v_total;
1202 break;
1203 case SM501_DC_CRT_V_SYNC:
1204 ret = s->dc_crt_v_sync;
1205 break;
1206
1207 case SM501_DC_CRT_HWC_ADDR:
1208 ret = s->dc_crt_hwc_addr;
1209 break;
1210 case SM501_DC_CRT_HWC_LOC:
1211 ret = s->dc_crt_hwc_location;
1212 break;
1213 case SM501_DC_CRT_HWC_COLOR_1_2:
1214 ret = s->dc_crt_hwc_color_1_2;
1215 break;
1216 case SM501_DC_CRT_HWC_COLOR_3:
1217 ret = s->dc_crt_hwc_color_3;
1218 break;
1219
1220 case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4:
1221 ret = sm501_palette_read(opaque, addr - SM501_DC_PANEL_PALETTE);
1222 break;
1223
1224 default:
1225 qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register "
1226 "read. addr=%" HWADDR_PRIx "\n", addr);
1227 }
1228 trace_sm501_disp_ctrl_read((uint32_t)addr, ret);
1229 return ret;
1230 }
1231
1232 static void sm501_disp_ctrl_write(void *opaque, hwaddr addr,
1233 uint64_t value, unsigned size)
1234 {
1235 SM501State *s = (SM501State *)opaque;
1236
1237 trace_sm501_disp_ctrl_write((uint32_t)addr, (uint32_t)value);
1238 switch (addr) {
1239 case SM501_DC_PANEL_CONTROL:
1240 s->dc_panel_control = value & 0x0FFF73FF;
1241 break;
1242 case SM501_DC_PANEL_PANNING_CONTROL:
1243 s->dc_panel_panning_control = value & 0xFF3FFF3F;
1244 break;
1245 case SM501_DC_PANEL_COLOR_KEY:
1246 /* Not implemented yet */
1247 break;
1248 case SM501_DC_PANEL_FB_ADDR:
1249 s->dc_panel_fb_addr = value & 0x8FFFFFF0;
1250 if (value & 0x8000000) {
1251 qemu_log_mask(LOG_UNIMP, "Panel external memory not supported\n");
1252 }
1253 s->do_full_update = true;
1254 break;
1255 case SM501_DC_PANEL_FB_OFFSET:
1256 s->dc_panel_fb_offset = value & 0x3FF03FF0;
1257 break;
1258 case SM501_DC_PANEL_FB_WIDTH:
1259 s->dc_panel_fb_width = value & 0x0FFF0FFF;
1260 break;
1261 case SM501_DC_PANEL_FB_HEIGHT:
1262 s->dc_panel_fb_height = value & 0x0FFF0FFF;
1263 break;
1264 case SM501_DC_PANEL_TL_LOC:
1265 s->dc_panel_tl_location = value & 0x07FF07FF;
1266 break;
1267 case SM501_DC_PANEL_BR_LOC:
1268 s->dc_panel_br_location = value & 0x07FF07FF;
1269 break;
1270
1271 case SM501_DC_PANEL_H_TOT:
1272 s->dc_panel_h_total = value & 0x0FFF0FFF;
1273 break;
1274 case SM501_DC_PANEL_H_SYNC:
1275 s->dc_panel_h_sync = value & 0x00FF0FFF;
1276 break;
1277 case SM501_DC_PANEL_V_TOT:
1278 s->dc_panel_v_total = value & 0x0FFF0FFF;
1279 break;
1280 case SM501_DC_PANEL_V_SYNC:
1281 s->dc_panel_v_sync = value & 0x003F0FFF;
1282 break;
1283
1284 case SM501_DC_PANEL_HWC_ADDR:
1285 value &= 0x8FFFFFF0;
1286 if (value != s->dc_panel_hwc_addr) {
1287 hwc_invalidate(s, 0);
1288 s->dc_panel_hwc_addr = value;
1289 }
1290 break;
1291 case SM501_DC_PANEL_HWC_LOC:
1292 value &= 0x0FFF0FFF;
1293 if (value != s->dc_panel_hwc_location) {
1294 hwc_invalidate(s, 0);
1295 s->dc_panel_hwc_location = value;
1296 }
1297 break;
1298 case SM501_DC_PANEL_HWC_COLOR_1_2:
1299 s->dc_panel_hwc_color_1_2 = value;
1300 break;
1301 case SM501_DC_PANEL_HWC_COLOR_3:
1302 s->dc_panel_hwc_color_3 = value & 0x0000FFFF;
1303 break;
1304
1305 case SM501_DC_VIDEO_CONTROL:
1306 s->dc_video_control = value & 0x00037FFF;
1307 break;
1308
1309 case SM501_DC_CRT_CONTROL:
1310 s->dc_crt_control = value & 0x0003FFFF;
1311 break;
1312 case SM501_DC_CRT_FB_ADDR:
1313 s->dc_crt_fb_addr = value & 0x8FFFFFF0;
1314 if (value & 0x8000000) {
1315 qemu_log_mask(LOG_UNIMP, "CRT external memory not supported\n");
1316 }
1317 s->do_full_update = true;
1318 break;
1319 case SM501_DC_CRT_FB_OFFSET:
1320 s->dc_crt_fb_offset = value & 0x3FF03FF0;
1321 break;
1322 case SM501_DC_CRT_H_TOT:
1323 s->dc_crt_h_total = value & 0x0FFF0FFF;
1324 break;
1325 case SM501_DC_CRT_H_SYNC:
1326 s->dc_crt_h_sync = value & 0x00FF0FFF;
1327 break;
1328 case SM501_DC_CRT_V_TOT:
1329 s->dc_crt_v_total = value & 0x0FFF0FFF;
1330 break;
1331 case SM501_DC_CRT_V_SYNC:
1332 s->dc_crt_v_sync = value & 0x003F0FFF;
1333 break;
1334
1335 case SM501_DC_CRT_HWC_ADDR:
1336 value &= 0x8FFFFFF0;
1337 if (value != s->dc_crt_hwc_addr) {
1338 hwc_invalidate(s, 1);
1339 s->dc_crt_hwc_addr = value;
1340 }
1341 break;
1342 case SM501_DC_CRT_HWC_LOC:
1343 value &= 0x0FFF0FFF;
1344 if (value != s->dc_crt_hwc_location) {
1345 hwc_invalidate(s, 1);
1346 s->dc_crt_hwc_location = value;
1347 }
1348 break;
1349 case SM501_DC_CRT_HWC_COLOR_1_2:
1350 s->dc_crt_hwc_color_1_2 = value;
1351 break;
1352 case SM501_DC_CRT_HWC_COLOR_3:
1353 s->dc_crt_hwc_color_3 = value & 0x0000FFFF;
1354 break;
1355
1356 case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4:
1357 sm501_palette_write(opaque, addr - SM501_DC_PANEL_PALETTE, value);
1358 break;
1359
1360 default:
1361 qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register "
1362 "write. addr=%" HWADDR_PRIx
1363 ", val=%" PRIx64 "\n", addr, value);
1364 }
1365 }
1366
1367 static const MemoryRegionOps sm501_disp_ctrl_ops = {
1368 .read = sm501_disp_ctrl_read,
1369 .write = sm501_disp_ctrl_write,
1370 .valid = {
1371 .min_access_size = 4,
1372 .max_access_size = 4,
1373 },
1374 .endianness = DEVICE_LITTLE_ENDIAN,
1375 };
1376
1377 static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr,
1378 unsigned size)
1379 {
1380 SM501State *s = (SM501State *)opaque;
1381 uint32_t ret = 0;
1382
1383 switch (addr) {
1384 case SM501_2D_SOURCE:
1385 ret = s->twoD_source;
1386 break;
1387 case SM501_2D_DESTINATION:
1388 ret = s->twoD_destination;
1389 break;
1390 case SM501_2D_DIMENSION:
1391 ret = s->twoD_dimension;
1392 break;
1393 case SM501_2D_CONTROL:
1394 ret = s->twoD_control;
1395 break;
1396 case SM501_2D_PITCH:
1397 ret = s->twoD_pitch;
1398 break;
1399 case SM501_2D_FOREGROUND:
1400 ret = s->twoD_foreground;
1401 break;
1402 case SM501_2D_BACKGROUND:
1403 ret = s->twoD_background;
1404 break;
1405 case SM501_2D_STRETCH:
1406 ret = s->twoD_stretch;
1407 break;
1408 case SM501_2D_COLOR_COMPARE:
1409 ret = s->twoD_color_compare;
1410 break;
1411 case SM501_2D_COLOR_COMPARE_MASK:
1412 ret = s->twoD_color_compare_mask;
1413 break;
1414 case SM501_2D_MASK:
1415 ret = s->twoD_mask;
1416 break;
1417 case SM501_2D_CLIP_TL:
1418 ret = s->twoD_clip_tl;
1419 break;
1420 case SM501_2D_CLIP_BR:
1421 ret = s->twoD_clip_br;
1422 break;
1423 case SM501_2D_MONO_PATTERN_LOW:
1424 ret = s->twoD_mono_pattern_low;
1425 break;
1426 case SM501_2D_MONO_PATTERN_HIGH:
1427 ret = s->twoD_mono_pattern_high;
1428 break;
1429 case SM501_2D_WINDOW_WIDTH:
1430 ret = s->twoD_window_width;
1431 break;
1432 case SM501_2D_SOURCE_BASE:
1433 ret = s->twoD_source_base;
1434 break;
1435 case SM501_2D_DESTINATION_BASE:
1436 ret = s->twoD_destination_base;
1437 break;
1438 case SM501_2D_ALPHA:
1439 ret = s->twoD_alpha;
1440 break;
1441 case SM501_2D_WRAP:
1442 ret = s->twoD_wrap;
1443 break;
1444 case SM501_2D_STATUS:
1445 ret = 0; /* Should return interrupt status */
1446 break;
1447 default:
1448 qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register "
1449 "read. addr=%" HWADDR_PRIx "\n", addr);
1450 }
1451 trace_sm501_2d_engine_read((uint32_t)addr, ret);
1452 return ret;
1453 }
1454
1455 static void sm501_2d_engine_write(void *opaque, hwaddr addr,
1456 uint64_t value, unsigned size)
1457 {
1458 SM501State *s = (SM501State *)opaque;
1459
1460 trace_sm501_2d_engine_write((uint32_t)addr, (uint32_t)value);
1461 switch (addr) {
1462 case SM501_2D_SOURCE:
1463 s->twoD_source = value;
1464 break;
1465 case SM501_2D_DESTINATION:
1466 s->twoD_destination = value;
1467 break;
1468 case SM501_2D_DIMENSION:
1469 s->twoD_dimension = value;
1470 break;
1471 case SM501_2D_CONTROL:
1472 s->twoD_control = value;
1473
1474 /* do 2d operation if start flag is set. */
1475 if (value & 0x80000000) {
1476 sm501_2d_operation(s);
1477 s->twoD_control &= ~0x80000000; /* start flag down */
1478 }
1479
1480 break;
1481 case SM501_2D_PITCH:
1482 s->twoD_pitch = value;
1483 break;
1484 case SM501_2D_FOREGROUND:
1485 s->twoD_foreground = value;
1486 break;
1487 case SM501_2D_BACKGROUND:
1488 s->twoD_background = value;
1489 break;
1490 case SM501_2D_STRETCH:
1491 if (((value >> 20) & 3) == 3) {
1492 value &= ~BIT(20);
1493 }
1494 s->twoD_stretch = value;
1495 break;
1496 case SM501_2D_COLOR_COMPARE:
1497 s->twoD_color_compare = value;
1498 break;
1499 case SM501_2D_COLOR_COMPARE_MASK:
1500 s->twoD_color_compare_mask = value;
1501 break;
1502 case SM501_2D_MASK:
1503 s->twoD_mask = value;
1504 break;
1505 case SM501_2D_CLIP_TL:
1506 s->twoD_clip_tl = value;
1507 break;
1508 case SM501_2D_CLIP_BR:
1509 s->twoD_clip_br = value;
1510 break;
1511 case SM501_2D_MONO_PATTERN_LOW:
1512 s->twoD_mono_pattern_low = value;
1513 break;
1514 case SM501_2D_MONO_PATTERN_HIGH:
1515 s->twoD_mono_pattern_high = value;
1516 break;
1517 case SM501_2D_WINDOW_WIDTH:
1518 s->twoD_window_width = value;
1519 break;
1520 case SM501_2D_SOURCE_BASE:
1521 s->twoD_source_base = value;
1522 break;
1523 case SM501_2D_DESTINATION_BASE:
1524 s->twoD_destination_base = value;
1525 break;
1526 case SM501_2D_ALPHA:
1527 s->twoD_alpha = value;
1528 break;
1529 case SM501_2D_WRAP:
1530 s->twoD_wrap = value;
1531 break;
1532 case SM501_2D_STATUS:
1533 /* ignored, writing 0 should clear interrupt status */
1534 break;
1535 default:
1536 qemu_log_mask(LOG_UNIMP, "sm501: not implemented 2d engine register "
1537 "write. addr=%" HWADDR_PRIx
1538 ", val=%" PRIx64 "\n", addr, value);
1539 }
1540 }
1541
1542 static const MemoryRegionOps sm501_2d_engine_ops = {
1543 .read = sm501_2d_engine_read,
1544 .write = sm501_2d_engine_write,
1545 .valid = {
1546 .min_access_size = 4,
1547 .max_access_size = 4,
1548 },
1549 .endianness = DEVICE_LITTLE_ENDIAN,
1550 };
1551
1552 /* draw line functions for all console modes */
1553
1554 typedef void draw_line_func(uint8_t *d, const uint8_t *s,
1555 int width, const uint32_t *pal);
1556
1557 typedef void draw_hwc_line_func(uint8_t *d, const uint8_t *s,
1558 int width, const uint8_t *palette,
1559 int c_x, int c_y);
1560
1561 #define DEPTH 8
1562 #include "sm501_template.h"
1563
1564 #define DEPTH 15
1565 #include "sm501_template.h"
1566
1567 #define BGR_FORMAT
1568 #define DEPTH 15
1569 #include "sm501_template.h"
1570
1571 #define DEPTH 16
1572 #include "sm501_template.h"
1573
1574 #define BGR_FORMAT
1575 #define DEPTH 16
1576 #include "sm501_template.h"
1577
1578 #define DEPTH 32
1579 #include "sm501_template.h"
1580
1581 #define BGR_FORMAT
1582 #define DEPTH 32
1583 #include "sm501_template.h"
1584
1585 static draw_line_func *draw_line8_funcs[] = {
1586 draw_line8_8,
1587 draw_line8_15,
1588 draw_line8_16,
1589 draw_line8_32,
1590 draw_line8_32bgr,
1591 draw_line8_15bgr,
1592 draw_line8_16bgr,
1593 };
1594
1595 static draw_line_func *draw_line16_funcs[] = {
1596 draw_line16_8,
1597 draw_line16_15,
1598 draw_line16_16,
1599 draw_line16_32,
1600 draw_line16_32bgr,
1601 draw_line16_15bgr,
1602 draw_line16_16bgr,
1603 };
1604
1605 static draw_line_func *draw_line32_funcs[] = {
1606 draw_line32_8,
1607 draw_line32_15,
1608 draw_line32_16,
1609 draw_line32_32,
1610 draw_line32_32bgr,
1611 draw_line32_15bgr,
1612 draw_line32_16bgr,
1613 };
1614
1615 static draw_hwc_line_func *draw_hwc_line_funcs[] = {
1616 draw_hwc_line_8,
1617 draw_hwc_line_15,
1618 draw_hwc_line_16,
1619 draw_hwc_line_32,
1620 draw_hwc_line_32bgr,
1621 draw_hwc_line_15bgr,
1622 draw_hwc_line_16bgr,
1623 };
1624
1625 static inline int get_depth_index(DisplaySurface *surface)
1626 {
1627 switch (surface_bits_per_pixel(surface)) {
1628 default:
1629 case 8:
1630 return 0;
1631 case 15:
1632 return 1;
1633 case 16:
1634 return 2;
1635 case 32:
1636 if (is_surface_bgr(surface)) {
1637 return 4;
1638 } else {
1639 return 3;
1640 }
1641 }
1642 }
1643
1644 static void sm501_update_display(void *opaque)
1645 {
1646 SM501State *s = (SM501State *)opaque;
1647 DisplaySurface *surface = qemu_console_surface(s->con);
1648 DirtyBitmapSnapshot *snap;
1649 int y, c_x = 0, c_y = 0;
1650 int crt = (s->dc_crt_control & SM501_DC_CRT_CONTROL_SEL) ? 1 : 0;
1651 int width = get_width(s, crt);
1652 int height = get_height(s, crt);
1653 int src_bpp = get_bpp(s, crt);
1654 int dst_bpp = surface_bytes_per_pixel(surface);
1655 int dst_depth_index = get_depth_index(surface);
1656 draw_line_func *draw_line = NULL;
1657 draw_hwc_line_func *draw_hwc_line = NULL;
1658 int full_update = 0;
1659 int y_start = -1;
1660 ram_addr_t offset;
1661 uint32_t *palette;
1662 uint8_t hwc_palette[3 * 3];
1663 uint8_t *hwc_src = NULL;
1664
1665 if (!((crt ? s->dc_crt_control : s->dc_panel_control)
1666 & SM501_DC_CRT_CONTROL_ENABLE)) {
1667 return;
1668 }
1669
1670 palette = (uint32_t *)(crt ? &s->dc_palette[SM501_DC_CRT_PALETTE -
1671 SM501_DC_PANEL_PALETTE]
1672 : &s->dc_palette[0]);
1673
1674 /* choose draw_line function */
1675 switch (src_bpp) {
1676 case 1:
1677 draw_line = draw_line8_funcs[dst_depth_index];
1678 break;
1679 case 2:
1680 draw_line = draw_line16_funcs[dst_depth_index];
1681 break;
1682 case 4:
1683 draw_line = draw_line32_funcs[dst_depth_index];
1684 break;
1685 default:
1686 qemu_log_mask(LOG_GUEST_ERROR, "sm501: update display"
1687 "invalid control register value.\n");
1688 return;
1689 }
1690
1691 /* set up to draw hardware cursor */
1692 if (is_hwc_enabled(s, crt)) {
1693 /* choose cursor draw line function */
1694 draw_hwc_line = draw_hwc_line_funcs[dst_depth_index];
1695 hwc_src = get_hwc_address(s, crt);
1696 c_x = get_hwc_x(s, crt);
1697 c_y = get_hwc_y(s, crt);
1698 get_hwc_palette(s, crt, hwc_palette);
1699 }
1700
1701 /* adjust console size */
1702 if (s->last_width != width || s->last_height != height) {
1703 qemu_console_resize(s->con, width, height);
1704 surface = qemu_console_surface(s->con);
1705 s->last_width = width;
1706 s->last_height = height;
1707 full_update = 1;
1708 }
1709
1710 /* someone else requested a full update */
1711 if (s->do_full_update) {
1712 s->do_full_update = false;
1713 full_update = 1;
1714 }
1715
1716 /* draw each line according to conditions */
1717 offset = get_fb_addr(s, crt);
1718 snap = memory_region_snapshot_and_clear_dirty(&s->local_mem_region,
1719 offset, width * height * src_bpp, DIRTY_MEMORY_VGA);
1720 for (y = 0; y < height; y++, offset += width * src_bpp) {
1721 int update, update_hwc;
1722
1723 /* check if hardware cursor is enabled and we're within its range */
1724 update_hwc = draw_hwc_line && c_y <= y && y < c_y + SM501_HWC_HEIGHT;
1725 update = full_update || update_hwc;
1726 /* check dirty flags for each line */
1727 update |= memory_region_snapshot_get_dirty(&s->local_mem_region, snap,
1728 offset, width * src_bpp);
1729
1730 /* draw line and change status */
1731 if (update) {
1732 uint8_t *d = surface_data(surface);
1733 d += y * width * dst_bpp;
1734
1735 /* draw graphics layer */
1736 draw_line(d, s->local_mem + offset, width, palette);
1737
1738 /* draw hardware cursor */
1739 if (update_hwc) {
1740 draw_hwc_line(d, hwc_src, width, hwc_palette, c_x, y - c_y);
1741 }
1742
1743 if (y_start < 0) {
1744 y_start = y;
1745 }
1746 } else {
1747 if (y_start >= 0) {
1748 /* flush to display */
1749 dpy_gfx_update(s->con, 0, y_start, width, y - y_start);
1750 y_start = -1;
1751 }
1752 }
1753 }
1754 g_free(snap);
1755
1756 /* complete flush to display */
1757 if (y_start >= 0) {
1758 dpy_gfx_update(s->con, 0, y_start, width, y - y_start);
1759 }
1760 }
1761
1762 static const GraphicHwOps sm501_ops = {
1763 .gfx_update = sm501_update_display,
1764 };
1765
1766 static void sm501_reset(SM501State *s)
1767 {
1768 s->system_control = 0x00100000; /* 2D engine FIFO empty */
1769 /* Bits 17 (SH), 7 (CDR), 6:5 (Test), 2:0 (Bus) are all supposed
1770 * to be determined at reset by GPIO lines which set config bits.
1771 * We hardwire them:
1772 * SH = 0 : Hitachi Ready Polarity == Active Low
1773 * CDR = 0 : do not reset clock divider
1774 * TEST = 0 : Normal mode (not testing the silicon)
1775 * BUS = 0 : Hitachi SH3/SH4
1776 */
1777 s->misc_control = SM501_MISC_DAC_POWER;
1778 s->gpio_31_0_control = 0;
1779 s->gpio_63_32_control = 0;
1780 s->dram_control = 0;
1781 s->arbitration_control = 0x05146732;
1782 s->irq_mask = 0;
1783 s->misc_timing = 0;
1784 s->power_mode_control = 0;
1785 s->i2c_byte_count = 0;
1786 s->i2c_status = 0;
1787 s->i2c_addr = 0;
1788 memset(s->i2c_data, 0, 16);
1789 s->dc_panel_control = 0x00010000; /* FIFO level 3 */
1790 s->dc_video_control = 0;
1791 s->dc_crt_control = 0x00010000;
1792 s->twoD_source = 0;
1793 s->twoD_destination = 0;
1794 s->twoD_dimension = 0;
1795 s->twoD_control = 0;
1796 s->twoD_pitch = 0;
1797 s->twoD_foreground = 0;
1798 s->twoD_background = 0;
1799 s->twoD_stretch = 0;
1800 s->twoD_color_compare = 0;
1801 s->twoD_color_compare_mask = 0;
1802 s->twoD_mask = 0;
1803 s->twoD_clip_tl = 0;
1804 s->twoD_clip_br = 0;
1805 s->twoD_mono_pattern_low = 0;
1806 s->twoD_mono_pattern_high = 0;
1807 s->twoD_window_width = 0;
1808 s->twoD_source_base = 0;
1809 s->twoD_destination_base = 0;
1810 s->twoD_alpha = 0;
1811 s->twoD_wrap = 0;
1812 }
1813
1814 static void sm501_init(SM501State *s, DeviceState *dev,
1815 uint32_t local_mem_bytes)
1816 {
1817 s->local_mem_size_index = get_local_mem_size_index(local_mem_bytes);
1818
1819 /* local memory */
1820 memory_region_init_ram(&s->local_mem_region, OBJECT(dev), "sm501.local",
1821 get_local_mem_size(s), &error_fatal);
1822 memory_region_set_log(&s->local_mem_region, true, DIRTY_MEMORY_VGA);
1823 s->local_mem = memory_region_get_ram_ptr(&s->local_mem_region);
1824
1825 /* i2c */
1826 s->i2c_bus = i2c_init_bus(dev, "sm501.i2c");
1827 /* ddc */
1828 I2CDDCState *ddc = I2CDDC(qdev_new(TYPE_I2CDDC));
1829 i2c_set_slave_address(I2C_SLAVE(ddc), 0x50);
1830 qdev_realize_and_unref(DEVICE(ddc), BUS(s->i2c_bus), &error_abort);
1831
1832 /* mmio */
1833 memory_region_init(&s->mmio_region, OBJECT(dev), "sm501.mmio", MMIO_SIZE);
1834 memory_region_init_io(&s->system_config_region, OBJECT(dev),
1835 &sm501_system_config_ops, s,
1836 "sm501-system-config", 0x6c);
1837 memory_region_add_subregion(&s->mmio_region, SM501_SYS_CONFIG,
1838 &s->system_config_region);
1839 memory_region_init_io(&s->i2c_region, OBJECT(dev), &sm501_i2c_ops, s,
1840 "sm501-i2c", 0x14);
1841 memory_region_add_subregion(&s->mmio_region, SM501_I2C, &s->i2c_region);
1842 memory_region_init_io(&s->disp_ctrl_region, OBJECT(dev),
1843 &sm501_disp_ctrl_ops, s,
1844 "sm501-disp-ctrl", 0x1000);
1845 memory_region_add_subregion(&s->mmio_region, SM501_DC,
1846 &s->disp_ctrl_region);
1847 memory_region_init_io(&s->twoD_engine_region, OBJECT(dev),
1848 &sm501_2d_engine_ops, s,
1849 "sm501-2d-engine", 0x54);
1850 memory_region_add_subregion(&s->mmio_region, SM501_2D_ENGINE,
1851 &s->twoD_engine_region);
1852
1853 /* create qemu graphic console */
1854 s->con = graphic_console_init(dev, 0, &sm501_ops, s);
1855 }
1856
1857 static const VMStateDescription vmstate_sm501_state = {
1858 .name = "sm501-state",
1859 .version_id = 1,
1860 .minimum_version_id = 1,
1861 .fields = (VMStateField[]) {
1862 VMSTATE_UINT32(local_mem_size_index, SM501State),
1863 VMSTATE_UINT32(system_control, SM501State),
1864 VMSTATE_UINT32(misc_control, SM501State),
1865 VMSTATE_UINT32(gpio_31_0_control, SM501State),
1866 VMSTATE_UINT32(gpio_63_32_control, SM501State),
1867 VMSTATE_UINT32(dram_control, SM501State),
1868 VMSTATE_UINT32(arbitration_control, SM501State),
1869 VMSTATE_UINT32(irq_mask, SM501State),
1870 VMSTATE_UINT32(misc_timing, SM501State),
1871 VMSTATE_UINT32(power_mode_control, SM501State),
1872 VMSTATE_UINT32(uart0_ier, SM501State),
1873 VMSTATE_UINT32(uart0_lcr, SM501State),
1874 VMSTATE_UINT32(uart0_mcr, SM501State),
1875 VMSTATE_UINT32(uart0_scr, SM501State),
1876 VMSTATE_UINT8_ARRAY(dc_palette, SM501State, DC_PALETTE_ENTRIES),
1877 VMSTATE_UINT32(dc_panel_control, SM501State),
1878 VMSTATE_UINT32(dc_panel_panning_control, SM501State),
1879 VMSTATE_UINT32(dc_panel_fb_addr, SM501State),
1880 VMSTATE_UINT32(dc_panel_fb_offset, SM501State),
1881 VMSTATE_UINT32(dc_panel_fb_width, SM501State),
1882 VMSTATE_UINT32(dc_panel_fb_height, SM501State),
1883 VMSTATE_UINT32(dc_panel_tl_location, SM501State),
1884 VMSTATE_UINT32(dc_panel_br_location, SM501State),
1885 VMSTATE_UINT32(dc_panel_h_total, SM501State),
1886 VMSTATE_UINT32(dc_panel_h_sync, SM501State),
1887 VMSTATE_UINT32(dc_panel_v_total, SM501State),
1888 VMSTATE_UINT32(dc_panel_v_sync, SM501State),
1889 VMSTATE_UINT32(dc_panel_hwc_addr, SM501State),
1890 VMSTATE_UINT32(dc_panel_hwc_location, SM501State),
1891 VMSTATE_UINT32(dc_panel_hwc_color_1_2, SM501State),
1892 VMSTATE_UINT32(dc_panel_hwc_color_3, SM501State),
1893 VMSTATE_UINT32(dc_video_control, SM501State),
1894 VMSTATE_UINT32(dc_crt_control, SM501State),
1895 VMSTATE_UINT32(dc_crt_fb_addr, SM501State),
1896 VMSTATE_UINT32(dc_crt_fb_offset, SM501State),
1897 VMSTATE_UINT32(dc_crt_h_total, SM501State),
1898 VMSTATE_UINT32(dc_crt_h_sync, SM501State),
1899 VMSTATE_UINT32(dc_crt_v_total, SM501State),
1900 VMSTATE_UINT32(dc_crt_v_sync, SM501State),
1901 VMSTATE_UINT32(dc_crt_hwc_addr, SM501State),
1902 VMSTATE_UINT32(dc_crt_hwc_location, SM501State),
1903 VMSTATE_UINT32(dc_crt_hwc_color_1_2, SM501State),
1904 VMSTATE_UINT32(dc_crt_hwc_color_3, SM501State),
1905 VMSTATE_UINT32(twoD_source, SM501State),
1906 VMSTATE_UINT32(twoD_destination, SM501State),
1907 VMSTATE_UINT32(twoD_dimension, SM501State),
1908 VMSTATE_UINT32(twoD_control, SM501State),
1909 VMSTATE_UINT32(twoD_pitch, SM501State),
1910 VMSTATE_UINT32(twoD_foreground, SM501State),
1911 VMSTATE_UINT32(twoD_background, SM501State),
1912 VMSTATE_UINT32(twoD_stretch, SM501State),
1913 VMSTATE_UINT32(twoD_color_compare, SM501State),
1914 VMSTATE_UINT32(twoD_color_compare_mask, SM501State),
1915 VMSTATE_UINT32(twoD_mask, SM501State),
1916 VMSTATE_UINT32(twoD_clip_tl, SM501State),
1917 VMSTATE_UINT32(twoD_clip_br, SM501State),
1918 VMSTATE_UINT32(twoD_mono_pattern_low, SM501State),
1919 VMSTATE_UINT32(twoD_mono_pattern_high, SM501State),
1920 VMSTATE_UINT32(twoD_window_width, SM501State),
1921 VMSTATE_UINT32(twoD_source_base, SM501State),
1922 VMSTATE_UINT32(twoD_destination_base, SM501State),
1923 VMSTATE_UINT32(twoD_alpha, SM501State),
1924 VMSTATE_UINT32(twoD_wrap, SM501State),
1925 /* Added in version 2 */
1926 VMSTATE_UINT8(i2c_byte_count, SM501State),
1927 VMSTATE_UINT8(i2c_status, SM501State),
1928 VMSTATE_UINT8(i2c_addr, SM501State),
1929 VMSTATE_UINT8_ARRAY(i2c_data, SM501State, 16),
1930 VMSTATE_END_OF_LIST()
1931 }
1932 };
1933
1934 #define TYPE_SYSBUS_SM501 "sysbus-sm501"
1935 OBJECT_DECLARE_SIMPLE_TYPE(SM501SysBusState, SYSBUS_SM501)
1936
1937 struct SM501SysBusState {
1938 /*< private >*/
1939 SysBusDevice parent_obj;
1940 /*< public >*/
1941 SM501State state;
1942 uint32_t vram_size;
1943 uint32_t base;
1944 SerialMM serial;
1945 };
1946
1947 static void sm501_realize_sysbus(DeviceState *dev, Error **errp)
1948 {
1949 SM501SysBusState *s = SYSBUS_SM501(dev);
1950 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1951 DeviceState *usb_dev;
1952 MemoryRegion *mr;
1953
1954 sm501_init(&s->state, dev, s->vram_size);
1955 if (get_local_mem_size(&s->state) != s->vram_size) {
1956 error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32,
1957 get_local_mem_size(&s->state));
1958 return;
1959 }
1960 sysbus_init_mmio(sbd, &s->state.local_mem_region);
1961 sysbus_init_mmio(sbd, &s->state.mmio_region);
1962
1963 /* bridge to usb host emulation module */
1964 usb_dev = qdev_new("sysbus-ohci");
1965 qdev_prop_set_uint32(usb_dev, "num-ports", 2);
1966 qdev_prop_set_uint64(usb_dev, "dma-offset", s->base);
1967 sysbus_realize_and_unref(SYS_BUS_DEVICE(usb_dev), &error_fatal);
1968 memory_region_add_subregion(&s->state.mmio_region, SM501_USB_HOST,
1969 sysbus_mmio_get_region(SYS_BUS_DEVICE(usb_dev), 0));
1970 sysbus_pass_irq(sbd, SYS_BUS_DEVICE(usb_dev));
1971
1972 /* bridge to serial emulation module */
1973 sysbus_realize(SYS_BUS_DEVICE(&s->serial), &error_fatal);
1974 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->serial), 0);
1975 memory_region_add_subregion(&s->state.mmio_region, SM501_UART0, mr);
1976 /* TODO : chain irq to IRL */
1977 }
1978
1979 static Property sm501_sysbus_properties[] = {
1980 DEFINE_PROP_UINT32("vram-size", SM501SysBusState, vram_size, 0),
1981 DEFINE_PROP_UINT32("base", SM501SysBusState, base, 0),
1982 DEFINE_PROP_END_OF_LIST(),
1983 };
1984
1985 static void sm501_reset_sysbus(DeviceState *dev)
1986 {
1987 SM501SysBusState *s = SYSBUS_SM501(dev);
1988 sm501_reset(&s->state);
1989 }
1990
1991 static const VMStateDescription vmstate_sm501_sysbus = {
1992 .name = TYPE_SYSBUS_SM501,
1993 .version_id = 2,
1994 .minimum_version_id = 2,
1995 .fields = (VMStateField[]) {
1996 VMSTATE_STRUCT(state, SM501SysBusState, 1,
1997 vmstate_sm501_state, SM501State),
1998 VMSTATE_END_OF_LIST()
1999 }
2000 };
2001
2002 static void sm501_sysbus_class_init(ObjectClass *klass, void *data)
2003 {
2004 DeviceClass *dc = DEVICE_CLASS(klass);
2005
2006 dc->realize = sm501_realize_sysbus;
2007 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
2008 dc->desc = "SM501 Multimedia Companion";
2009 device_class_set_props(dc, sm501_sysbus_properties);
2010 dc->reset = sm501_reset_sysbus;
2011 dc->vmsd = &vmstate_sm501_sysbus;
2012 }
2013
2014 static void sm501_sysbus_init(Object *o)
2015 {
2016 SM501SysBusState *sm501 = SYSBUS_SM501(o);
2017 SerialMM *smm = &sm501->serial;
2018
2019 object_initialize_child(o, "serial", smm, TYPE_SERIAL_MM);
2020 qdev_set_legacy_instance_id(DEVICE(smm), SM501_UART0, 2);
2021 qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
2022 qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
2023
2024 object_property_add_alias(o, "chardev",
2025 OBJECT(smm), "chardev");
2026 }
2027
2028 static const TypeInfo sm501_sysbus_info = {
2029 .name = TYPE_SYSBUS_SM501,
2030 .parent = TYPE_SYS_BUS_DEVICE,
2031 .instance_size = sizeof(SM501SysBusState),
2032 .class_init = sm501_sysbus_class_init,
2033 .instance_init = sm501_sysbus_init,
2034 };
2035
2036 #define TYPE_PCI_SM501 "sm501"
2037 OBJECT_DECLARE_SIMPLE_TYPE(SM501PCIState, PCI_SM501)
2038
2039 struct SM501PCIState {
2040 /*< private >*/
2041 PCIDevice parent_obj;
2042 /*< public >*/
2043 SM501State state;
2044 uint32_t vram_size;
2045 };
2046
2047 static void sm501_realize_pci(PCIDevice *dev, Error **errp)
2048 {
2049 SM501PCIState *s = PCI_SM501(dev);
2050
2051 sm501_init(&s->state, DEVICE(dev), s->vram_size);
2052 if (get_local_mem_size(&s->state) != s->vram_size) {
2053 error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32,
2054 get_local_mem_size(&s->state));
2055 return;
2056 }
2057 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
2058 &s->state.local_mem_region);
2059 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY,
2060 &s->state.mmio_region);
2061 }
2062
2063 static Property sm501_pci_properties[] = {
2064 DEFINE_PROP_UINT32("vram-size", SM501PCIState, vram_size, 64 * MiB),
2065 DEFINE_PROP_END_OF_LIST(),
2066 };
2067
2068 static void sm501_reset_pci(DeviceState *dev)
2069 {
2070 SM501PCIState *s = PCI_SM501(dev);
2071 sm501_reset(&s->state);
2072 /* Bits 2:0 of misc_control register is 001 for PCI */
2073 s->state.misc_control |= 1;
2074 }
2075
2076 static const VMStateDescription vmstate_sm501_pci = {
2077 .name = TYPE_PCI_SM501,
2078 .version_id = 2,
2079 .minimum_version_id = 2,
2080 .fields = (VMStateField[]) {
2081 VMSTATE_PCI_DEVICE(parent_obj, SM501PCIState),
2082 VMSTATE_STRUCT(state, SM501PCIState, 1,
2083 vmstate_sm501_state, SM501State),
2084 VMSTATE_END_OF_LIST()
2085 }
2086 };
2087
2088 static void sm501_pci_class_init(ObjectClass *klass, void *data)
2089 {
2090 DeviceClass *dc = DEVICE_CLASS(klass);
2091 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2092
2093 k->realize = sm501_realize_pci;
2094 k->vendor_id = PCI_VENDOR_ID_SILICON_MOTION;
2095 k->device_id = PCI_DEVICE_ID_SM501;
2096 k->class_id = PCI_CLASS_DISPLAY_OTHER;
2097 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
2098 dc->desc = "SM501 Display Controller";
2099 device_class_set_props(dc, sm501_pci_properties);
2100 dc->reset = sm501_reset_pci;
2101 dc->hotpluggable = false;
2102 dc->vmsd = &vmstate_sm501_pci;
2103 }
2104
2105 static const TypeInfo sm501_pci_info = {
2106 .name = TYPE_PCI_SM501,
2107 .parent = TYPE_PCI_DEVICE,
2108 .instance_size = sizeof(SM501PCIState),
2109 .class_init = sm501_pci_class_init,
2110 .interfaces = (InterfaceInfo[]) {
2111 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2112 { },
2113 },
2114 };
2115
2116 static void sm501_register_types(void)
2117 {
2118 type_register_static(&sm501_sysbus_info);
2119 type_register_static(&sm501_pci_info);
2120 }
2121
2122 type_init(sm501_register_types)