Merge remote-tracking branch 'remotes/elmarco/tags/slirp-pull-request' into staging
[qemu.git] / hw / display / sm501.c
1 /*
2 * QEMU SM501 Device
3 *
4 * Copyright (c) 2008 Shin-ichiro KAWASAKI
5 * Copyright (c) 2016 BALATON Zoltan
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "qemu/osdep.h"
27 #include "qemu/units.h"
28 #include "qapi/error.h"
29 #include "qemu/log.h"
30 #include "qemu/module.h"
31 #include "hw/char/serial.h"
32 #include "ui/console.h"
33 #include "hw/sysbus.h"
34 #include "migration/vmstate.h"
35 #include "hw/pci/pci.h"
36 #include "hw/qdev-properties.h"
37 #include "hw/i2c/i2c.h"
38 #include "hw/display/i2c-ddc.h"
39 #include "qemu/range.h"
40 #include "ui/pixel_ops.h"
41 #include "qemu/bswap.h"
42
43 /*
44 * Status: 2010/05/07
45 * - Minimum implementation for Linux console : mmio regs and CRT layer.
46 * - 2D graphics acceleration partially supported : only fill rectangle.
47 *
48 * Status: 2016/12/04
49 * - Misc fixes: endianness, hardware cursor
50 * - Panel support
51 *
52 * TODO:
53 * - Touch panel support
54 * - USB support
55 * - UART support
56 * - More 2D graphics engine support
57 * - Performance tuning
58 */
59
60 /*#define DEBUG_SM501*/
61 /*#define DEBUG_BITBLT*/
62
63 #ifdef DEBUG_SM501
64 #define SM501_DPRINTF(fmt, ...) printf(fmt, ## __VA_ARGS__)
65 #else
66 #define SM501_DPRINTF(fmt, ...) do {} while (0)
67 #endif
68
69 #define MMIO_BASE_OFFSET 0x3e00000
70 #define MMIO_SIZE 0x200000
71 #define DC_PALETTE_ENTRIES (0x400 * 3)
72
73 /* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" */
74
75 /* System Configuration area */
76 /* System config base */
77 #define SM501_SYS_CONFIG (0x000000)
78
79 /* config 1 */
80 #define SM501_SYSTEM_CONTROL (0x000000)
81
82 #define SM501_SYSCTRL_PANEL_TRISTATE (1 << 0)
83 #define SM501_SYSCTRL_MEM_TRISTATE (1 << 1)
84 #define SM501_SYSCTRL_CRT_TRISTATE (1 << 2)
85
86 #define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3 << 4)
87 #define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0 << 4)
88 #define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1 << 4)
89 #define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2 << 4)
90 #define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3 << 4)
91
92 #define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1 << 6)
93 #define SM501_SYSCTRL_PCI_RETRY_DISABLE (1 << 7)
94 #define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1 << 11)
95 #define SM501_SYSCTRL_PCI_BURST_READ_EN (1 << 15)
96
97 /* miscellaneous control */
98
99 #define SM501_MISC_CONTROL (0x000004)
100
101 #define SM501_MISC_BUS_SH (0x0)
102 #define SM501_MISC_BUS_PCI (0x1)
103 #define SM501_MISC_BUS_XSCALE (0x2)
104 #define SM501_MISC_BUS_NEC (0x6)
105 #define SM501_MISC_BUS_MASK (0x7)
106
107 #define SM501_MISC_VR_62MB (1 << 3)
108 #define SM501_MISC_CDR_RESET (1 << 7)
109 #define SM501_MISC_USB_LB (1 << 8)
110 #define SM501_MISC_USB_SLAVE (1 << 9)
111 #define SM501_MISC_BL_1 (1 << 10)
112 #define SM501_MISC_MC (1 << 11)
113 #define SM501_MISC_DAC_POWER (1 << 12)
114 #define SM501_MISC_IRQ_INVERT (1 << 16)
115 #define SM501_MISC_SH (1 << 17)
116
117 #define SM501_MISC_HOLD_EMPTY (0 << 18)
118 #define SM501_MISC_HOLD_8 (1 << 18)
119 #define SM501_MISC_HOLD_16 (2 << 18)
120 #define SM501_MISC_HOLD_24 (3 << 18)
121 #define SM501_MISC_HOLD_32 (4 << 18)
122 #define SM501_MISC_HOLD_MASK (7 << 18)
123
124 #define SM501_MISC_FREQ_12 (1 << 24)
125 #define SM501_MISC_PNL_24BIT (1 << 25)
126 #define SM501_MISC_8051_LE (1 << 26)
127
128
129
130 #define SM501_GPIO31_0_CONTROL (0x000008)
131 #define SM501_GPIO63_32_CONTROL (0x00000C)
132 #define SM501_DRAM_CONTROL (0x000010)
133
134 /* command list */
135 #define SM501_ARBTRTN_CONTROL (0x000014)
136
137 /* command list */
138 #define SM501_COMMAND_LIST_STATUS (0x000024)
139
140 /* interrupt debug */
141 #define SM501_RAW_IRQ_STATUS (0x000028)
142 #define SM501_RAW_IRQ_CLEAR (0x000028)
143 #define SM501_IRQ_STATUS (0x00002C)
144 #define SM501_IRQ_MASK (0x000030)
145 #define SM501_DEBUG_CONTROL (0x000034)
146
147 /* power management */
148 #define SM501_POWERMODE_P2X_SRC (1 << 29)
149 #define SM501_POWERMODE_V2X_SRC (1 << 20)
150 #define SM501_POWERMODE_M_SRC (1 << 12)
151 #define SM501_POWERMODE_M1_SRC (1 << 4)
152
153 #define SM501_CURRENT_GATE (0x000038)
154 #define SM501_CURRENT_CLOCK (0x00003C)
155 #define SM501_POWER_MODE_0_GATE (0x000040)
156 #define SM501_POWER_MODE_0_CLOCK (0x000044)
157 #define SM501_POWER_MODE_1_GATE (0x000048)
158 #define SM501_POWER_MODE_1_CLOCK (0x00004C)
159 #define SM501_SLEEP_MODE_GATE (0x000050)
160 #define SM501_POWER_MODE_CONTROL (0x000054)
161
162 /* power gates for units within the 501 */
163 #define SM501_GATE_HOST (0)
164 #define SM501_GATE_MEMORY (1)
165 #define SM501_GATE_DISPLAY (2)
166 #define SM501_GATE_2D_ENGINE (3)
167 #define SM501_GATE_CSC (4)
168 #define SM501_GATE_ZVPORT (5)
169 #define SM501_GATE_GPIO (6)
170 #define SM501_GATE_UART0 (7)
171 #define SM501_GATE_UART1 (8)
172 #define SM501_GATE_SSP (10)
173 #define SM501_GATE_USB_HOST (11)
174 #define SM501_GATE_USB_GADGET (12)
175 #define SM501_GATE_UCONTROLLER (17)
176 #define SM501_GATE_AC97 (18)
177
178 /* panel clock */
179 #define SM501_CLOCK_P2XCLK (24)
180 /* crt clock */
181 #define SM501_CLOCK_V2XCLK (16)
182 /* main clock */
183 #define SM501_CLOCK_MCLK (8)
184 /* SDRAM controller clock */
185 #define SM501_CLOCK_M1XCLK (0)
186
187 /* config 2 */
188 #define SM501_PCI_MASTER_BASE (0x000058)
189 #define SM501_ENDIAN_CONTROL (0x00005C)
190 #define SM501_DEVICEID (0x000060)
191 /* 0x050100A0 */
192
193 #define SM501_DEVICEID_SM501 (0x05010000)
194 #define SM501_DEVICEID_IDMASK (0xffff0000)
195 #define SM501_DEVICEID_REVMASK (0x000000ff)
196
197 #define SM501_PLLCLOCK_COUNT (0x000064)
198 #define SM501_MISC_TIMING (0x000068)
199 #define SM501_CURRENT_SDRAM_CLOCK (0x00006C)
200
201 #define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074)
202
203 /* GPIO base */
204 #define SM501_GPIO (0x010000)
205 #define SM501_GPIO_DATA_LOW (0x00)
206 #define SM501_GPIO_DATA_HIGH (0x04)
207 #define SM501_GPIO_DDR_LOW (0x08)
208 #define SM501_GPIO_DDR_HIGH (0x0C)
209 #define SM501_GPIO_IRQ_SETUP (0x10)
210 #define SM501_GPIO_IRQ_STATUS (0x14)
211 #define SM501_GPIO_IRQ_RESET (0x14)
212
213 /* I2C controller base */
214 #define SM501_I2C (0x010040)
215 #define SM501_I2C_BYTE_COUNT (0x00)
216 #define SM501_I2C_CONTROL (0x01)
217 #define SM501_I2C_STATUS (0x02)
218 #define SM501_I2C_RESET (0x02)
219 #define SM501_I2C_SLAVE_ADDRESS (0x03)
220 #define SM501_I2C_DATA (0x04)
221
222 #define SM501_I2C_CONTROL_START (1 << 2)
223 #define SM501_I2C_CONTROL_ENABLE (1 << 0)
224
225 #define SM501_I2C_STATUS_COMPLETE (1 << 3)
226 #define SM501_I2C_STATUS_ERROR (1 << 2)
227
228 #define SM501_I2C_RESET_ERROR (1 << 2)
229
230 /* SSP base */
231 #define SM501_SSP (0x020000)
232
233 /* Uart 0 base */
234 #define SM501_UART0 (0x030000)
235
236 /* Uart 1 base */
237 #define SM501_UART1 (0x030020)
238
239 /* USB host port base */
240 #define SM501_USB_HOST (0x040000)
241
242 /* USB slave/gadget base */
243 #define SM501_USB_GADGET (0x060000)
244
245 /* USB slave/gadget data port base */
246 #define SM501_USB_GADGET_DATA (0x070000)
247
248 /* Display controller/video engine base */
249 #define SM501_DC (0x080000)
250
251 /* common defines for the SM501 address registers */
252 #define SM501_ADDR_FLIP (1 << 31)
253 #define SM501_ADDR_EXT (1 << 27)
254 #define SM501_ADDR_CS1 (1 << 26)
255 #define SM501_ADDR_MASK (0x3f << 26)
256
257 #define SM501_FIFO_MASK (0x3 << 16)
258 #define SM501_FIFO_1 (0x0 << 16)
259 #define SM501_FIFO_3 (0x1 << 16)
260 #define SM501_FIFO_7 (0x2 << 16)
261 #define SM501_FIFO_11 (0x3 << 16)
262
263 /* common registers for panel and the crt */
264 #define SM501_OFF_DC_H_TOT (0x000)
265 #define SM501_OFF_DC_V_TOT (0x008)
266 #define SM501_OFF_DC_H_SYNC (0x004)
267 #define SM501_OFF_DC_V_SYNC (0x00C)
268
269 #define SM501_DC_PANEL_CONTROL (0x000)
270
271 #define SM501_DC_PANEL_CONTROL_FPEN (1 << 27)
272 #define SM501_DC_PANEL_CONTROL_BIAS (1 << 26)
273 #define SM501_DC_PANEL_CONTROL_DATA (1 << 25)
274 #define SM501_DC_PANEL_CONTROL_VDD (1 << 24)
275 #define SM501_DC_PANEL_CONTROL_DP (1 << 23)
276
277 #define SM501_DC_PANEL_CONTROL_TFT_888 (0 << 21)
278 #define SM501_DC_PANEL_CONTROL_TFT_333 (1 << 21)
279 #define SM501_DC_PANEL_CONTROL_TFT_444 (2 << 21)
280
281 #define SM501_DC_PANEL_CONTROL_DE (1 << 20)
282
283 #define SM501_DC_PANEL_CONTROL_LCD_TFT (0 << 18)
284 #define SM501_DC_PANEL_CONTROL_LCD_STN8 (1 << 18)
285 #define SM501_DC_PANEL_CONTROL_LCD_STN12 (2 << 18)
286
287 #define SM501_DC_PANEL_CONTROL_CP (1 << 14)
288 #define SM501_DC_PANEL_CONTROL_VSP (1 << 13)
289 #define SM501_DC_PANEL_CONTROL_HSP (1 << 12)
290 #define SM501_DC_PANEL_CONTROL_CK (1 << 9)
291 #define SM501_DC_PANEL_CONTROL_TE (1 << 8)
292 #define SM501_DC_PANEL_CONTROL_VPD (1 << 7)
293 #define SM501_DC_PANEL_CONTROL_VP (1 << 6)
294 #define SM501_DC_PANEL_CONTROL_HPD (1 << 5)
295 #define SM501_DC_PANEL_CONTROL_HP (1 << 4)
296 #define SM501_DC_PANEL_CONTROL_GAMMA (1 << 3)
297 #define SM501_DC_PANEL_CONTROL_EN (1 << 2)
298
299 #define SM501_DC_PANEL_CONTROL_8BPP (0 << 0)
300 #define SM501_DC_PANEL_CONTROL_16BPP (1 << 0)
301 #define SM501_DC_PANEL_CONTROL_32BPP (2 << 0)
302
303
304 #define SM501_DC_PANEL_PANNING_CONTROL (0x004)
305 #define SM501_DC_PANEL_COLOR_KEY (0x008)
306 #define SM501_DC_PANEL_FB_ADDR (0x00C)
307 #define SM501_DC_PANEL_FB_OFFSET (0x010)
308 #define SM501_DC_PANEL_FB_WIDTH (0x014)
309 #define SM501_DC_PANEL_FB_HEIGHT (0x018)
310 #define SM501_DC_PANEL_TL_LOC (0x01C)
311 #define SM501_DC_PANEL_BR_LOC (0x020)
312 #define SM501_DC_PANEL_H_TOT (0x024)
313 #define SM501_DC_PANEL_H_SYNC (0x028)
314 #define SM501_DC_PANEL_V_TOT (0x02C)
315 #define SM501_DC_PANEL_V_SYNC (0x030)
316 #define SM501_DC_PANEL_CUR_LINE (0x034)
317
318 #define SM501_DC_VIDEO_CONTROL (0x040)
319 #define SM501_DC_VIDEO_FB0_ADDR (0x044)
320 #define SM501_DC_VIDEO_FB_WIDTH (0x048)
321 #define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C)
322 #define SM501_DC_VIDEO_TL_LOC (0x050)
323 #define SM501_DC_VIDEO_BR_LOC (0x054)
324 #define SM501_DC_VIDEO_SCALE (0x058)
325 #define SM501_DC_VIDEO_INIT_SCALE (0x05C)
326 #define SM501_DC_VIDEO_YUV_CONSTANTS (0x060)
327 #define SM501_DC_VIDEO_FB1_ADDR (0x064)
328 #define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068)
329
330 #define SM501_DC_VIDEO_ALPHA_CONTROL (0x080)
331 #define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084)
332 #define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088)
333 #define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C)
334 #define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090)
335 #define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094)
336 #define SM501_DC_VIDEO_ALPHA_SCALE (0x098)
337 #define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C)
338 #define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0)
339 #define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4)
340
341 #define SM501_DC_PANEL_HWC_BASE (0x0F0)
342 #define SM501_DC_PANEL_HWC_ADDR (0x0F0)
343 #define SM501_DC_PANEL_HWC_LOC (0x0F4)
344 #define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8)
345 #define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC)
346
347 #define SM501_HWC_EN (1 << 31)
348
349 #define SM501_OFF_HWC_ADDR (0x00)
350 #define SM501_OFF_HWC_LOC (0x04)
351 #define SM501_OFF_HWC_COLOR_1_2 (0x08)
352 #define SM501_OFF_HWC_COLOR_3 (0x0C)
353
354 #define SM501_DC_ALPHA_CONTROL (0x100)
355 #define SM501_DC_ALPHA_FB_ADDR (0x104)
356 #define SM501_DC_ALPHA_FB_OFFSET (0x108)
357 #define SM501_DC_ALPHA_TL_LOC (0x10C)
358 #define SM501_DC_ALPHA_BR_LOC (0x110)
359 #define SM501_DC_ALPHA_CHROMA_KEY (0x114)
360 #define SM501_DC_ALPHA_COLOR_LOOKUP (0x118)
361
362 #define SM501_DC_CRT_CONTROL (0x200)
363
364 #define SM501_DC_CRT_CONTROL_TVP (1 << 15)
365 #define SM501_DC_CRT_CONTROL_CP (1 << 14)
366 #define SM501_DC_CRT_CONTROL_VSP (1 << 13)
367 #define SM501_DC_CRT_CONTROL_HSP (1 << 12)
368 #define SM501_DC_CRT_CONTROL_VS (1 << 11)
369 #define SM501_DC_CRT_CONTROL_BLANK (1 << 10)
370 #define SM501_DC_CRT_CONTROL_SEL (1 << 9)
371 #define SM501_DC_CRT_CONTROL_TE (1 << 8)
372 #define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4)
373 #define SM501_DC_CRT_CONTROL_GAMMA (1 << 3)
374 #define SM501_DC_CRT_CONTROL_ENABLE (1 << 2)
375
376 #define SM501_DC_CRT_CONTROL_8BPP (0 << 0)
377 #define SM501_DC_CRT_CONTROL_16BPP (1 << 0)
378 #define SM501_DC_CRT_CONTROL_32BPP (2 << 0)
379
380 #define SM501_DC_CRT_FB_ADDR (0x204)
381 #define SM501_DC_CRT_FB_OFFSET (0x208)
382 #define SM501_DC_CRT_H_TOT (0x20C)
383 #define SM501_DC_CRT_H_SYNC (0x210)
384 #define SM501_DC_CRT_V_TOT (0x214)
385 #define SM501_DC_CRT_V_SYNC (0x218)
386 #define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C)
387 #define SM501_DC_CRT_CUR_LINE (0x220)
388 #define SM501_DC_CRT_MONITOR_DETECT (0x224)
389
390 #define SM501_DC_CRT_HWC_BASE (0x230)
391 #define SM501_DC_CRT_HWC_ADDR (0x230)
392 #define SM501_DC_CRT_HWC_LOC (0x234)
393 #define SM501_DC_CRT_HWC_COLOR_1_2 (0x238)
394 #define SM501_DC_CRT_HWC_COLOR_3 (0x23C)
395
396 #define SM501_DC_PANEL_PALETTE (0x400)
397
398 #define SM501_DC_VIDEO_PALETTE (0x800)
399
400 #define SM501_DC_CRT_PALETTE (0xC00)
401
402 /* Zoom Video port base */
403 #define SM501_ZVPORT (0x090000)
404
405 /* AC97/I2S base */
406 #define SM501_AC97 (0x0A0000)
407
408 /* 8051 micro controller base */
409 #define SM501_UCONTROLLER (0x0B0000)
410
411 /* 8051 micro controller SRAM base */
412 #define SM501_UCONTROLLER_SRAM (0x0C0000)
413
414 /* DMA base */
415 #define SM501_DMA (0x0D0000)
416
417 /* 2d engine base */
418 #define SM501_2D_ENGINE (0x100000)
419 #define SM501_2D_SOURCE (0x00)
420 #define SM501_2D_DESTINATION (0x04)
421 #define SM501_2D_DIMENSION (0x08)
422 #define SM501_2D_CONTROL (0x0C)
423 #define SM501_2D_PITCH (0x10)
424 #define SM501_2D_FOREGROUND (0x14)
425 #define SM501_2D_BACKGROUND (0x18)
426 #define SM501_2D_STRETCH (0x1C)
427 #define SM501_2D_COLOR_COMPARE (0x20)
428 #define SM501_2D_COLOR_COMPARE_MASK (0x24)
429 #define SM501_2D_MASK (0x28)
430 #define SM501_2D_CLIP_TL (0x2C)
431 #define SM501_2D_CLIP_BR (0x30)
432 #define SM501_2D_MONO_PATTERN_LOW (0x34)
433 #define SM501_2D_MONO_PATTERN_HIGH (0x38)
434 #define SM501_2D_WINDOW_WIDTH (0x3C)
435 #define SM501_2D_SOURCE_BASE (0x40)
436 #define SM501_2D_DESTINATION_BASE (0x44)
437 #define SM501_2D_ALPHA (0x48)
438 #define SM501_2D_WRAP (0x4C)
439 #define SM501_2D_STATUS (0x50)
440
441 #define SM501_CSC_Y_SOURCE_BASE (0xC8)
442 #define SM501_CSC_CONSTANTS (0xCC)
443 #define SM501_CSC_Y_SOURCE_X (0xD0)
444 #define SM501_CSC_Y_SOURCE_Y (0xD4)
445 #define SM501_CSC_U_SOURCE_BASE (0xD8)
446 #define SM501_CSC_V_SOURCE_BASE (0xDC)
447 #define SM501_CSC_SOURCE_DIMENSION (0xE0)
448 #define SM501_CSC_SOURCE_PITCH (0xE4)
449 #define SM501_CSC_DESTINATION (0xE8)
450 #define SM501_CSC_DESTINATION_DIMENSION (0xEC)
451 #define SM501_CSC_DESTINATION_PITCH (0xF0)
452 #define SM501_CSC_SCALE_FACTOR (0xF4)
453 #define SM501_CSC_DESTINATION_BASE (0xF8)
454 #define SM501_CSC_CONTROL (0xFC)
455
456 /* 2d engine data port base */
457 #define SM501_2D_ENGINE_DATA (0x110000)
458
459 /* end of register definitions */
460
461 #define SM501_HWC_WIDTH (64)
462 #define SM501_HWC_HEIGHT (64)
463
464 /* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */
465 static const uint32_t sm501_mem_local_size[] = {
466 [0] = 4 * MiB,
467 [1] = 8 * MiB,
468 [2] = 16 * MiB,
469 [3] = 32 * MiB,
470 [4] = 64 * MiB,
471 [5] = 2 * MiB,
472 };
473 #define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index]
474
475 typedef struct SM501State {
476 /* graphic console status */
477 QemuConsole *con;
478
479 /* status & internal resources */
480 uint32_t local_mem_size_index;
481 uint8_t *local_mem;
482 MemoryRegion local_mem_region;
483 MemoryRegion mmio_region;
484 MemoryRegion system_config_region;
485 MemoryRegion i2c_region;
486 MemoryRegion disp_ctrl_region;
487 MemoryRegion twoD_engine_region;
488 uint32_t last_width;
489 uint32_t last_height;
490 bool do_full_update; /* perform a full update next time */
491 I2CBus *i2c_bus;
492
493 /* mmio registers */
494 uint32_t system_control;
495 uint32_t misc_control;
496 uint32_t gpio_31_0_control;
497 uint32_t gpio_63_32_control;
498 uint32_t dram_control;
499 uint32_t arbitration_control;
500 uint32_t irq_mask;
501 uint32_t misc_timing;
502 uint32_t power_mode_control;
503
504 uint8_t i2c_byte_count;
505 uint8_t i2c_status;
506 uint8_t i2c_addr;
507 uint8_t i2c_data[16];
508
509 uint32_t uart0_ier;
510 uint32_t uart0_lcr;
511 uint32_t uart0_mcr;
512 uint32_t uart0_scr;
513
514 uint8_t dc_palette[DC_PALETTE_ENTRIES];
515
516 uint32_t dc_panel_control;
517 uint32_t dc_panel_panning_control;
518 uint32_t dc_panel_fb_addr;
519 uint32_t dc_panel_fb_offset;
520 uint32_t dc_panel_fb_width;
521 uint32_t dc_panel_fb_height;
522 uint32_t dc_panel_tl_location;
523 uint32_t dc_panel_br_location;
524 uint32_t dc_panel_h_total;
525 uint32_t dc_panel_h_sync;
526 uint32_t dc_panel_v_total;
527 uint32_t dc_panel_v_sync;
528
529 uint32_t dc_panel_hwc_addr;
530 uint32_t dc_panel_hwc_location;
531 uint32_t dc_panel_hwc_color_1_2;
532 uint32_t dc_panel_hwc_color_3;
533
534 uint32_t dc_video_control;
535
536 uint32_t dc_crt_control;
537 uint32_t dc_crt_fb_addr;
538 uint32_t dc_crt_fb_offset;
539 uint32_t dc_crt_h_total;
540 uint32_t dc_crt_h_sync;
541 uint32_t dc_crt_v_total;
542 uint32_t dc_crt_v_sync;
543
544 uint32_t dc_crt_hwc_addr;
545 uint32_t dc_crt_hwc_location;
546 uint32_t dc_crt_hwc_color_1_2;
547 uint32_t dc_crt_hwc_color_3;
548
549 uint32_t twoD_source;
550 uint32_t twoD_destination;
551 uint32_t twoD_dimension;
552 uint32_t twoD_control;
553 uint32_t twoD_pitch;
554 uint32_t twoD_foreground;
555 uint32_t twoD_background;
556 uint32_t twoD_stretch;
557 uint32_t twoD_color_compare;
558 uint32_t twoD_color_compare_mask;
559 uint32_t twoD_mask;
560 uint32_t twoD_clip_tl;
561 uint32_t twoD_clip_br;
562 uint32_t twoD_mono_pattern_low;
563 uint32_t twoD_mono_pattern_high;
564 uint32_t twoD_window_width;
565 uint32_t twoD_source_base;
566 uint32_t twoD_destination_base;
567 uint32_t twoD_alpha;
568 uint32_t twoD_wrap;
569 } SM501State;
570
571 static uint32_t get_local_mem_size_index(uint32_t size)
572 {
573 uint32_t norm_size = 0;
574 int i, index = 0;
575
576 for (i = 0; i < ARRAY_SIZE(sm501_mem_local_size); i++) {
577 uint32_t new_size = sm501_mem_local_size[i];
578 if (new_size >= size) {
579 if (norm_size == 0 || norm_size > new_size) {
580 norm_size = new_size;
581 index = i;
582 }
583 }
584 }
585
586 return index;
587 }
588
589 static ram_addr_t get_fb_addr(SM501State *s, int crt)
590 {
591 return (crt ? s->dc_crt_fb_addr : s->dc_panel_fb_addr) & 0x3FFFFF0;
592 }
593
594 static inline int get_width(SM501State *s, int crt)
595 {
596 int width = crt ? s->dc_crt_h_total : s->dc_panel_h_total;
597 return (width & 0x00000FFF) + 1;
598 }
599
600 static inline int get_height(SM501State *s, int crt)
601 {
602 int height = crt ? s->dc_crt_v_total : s->dc_panel_v_total;
603 return (height & 0x00000FFF) + 1;
604 }
605
606 static inline int get_bpp(SM501State *s, int crt)
607 {
608 int bpp = crt ? s->dc_crt_control : s->dc_panel_control;
609 return 1 << (bpp & 3);
610 }
611
612 /**
613 * Check the availability of hardware cursor.
614 * @param crt 0 for PANEL, 1 for CRT.
615 */
616 static inline int is_hwc_enabled(SM501State *state, int crt)
617 {
618 uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr;
619 return addr & SM501_HWC_EN;
620 }
621
622 /**
623 * Get the address which holds cursor pattern data.
624 * @param crt 0 for PANEL, 1 for CRT.
625 */
626 static inline uint8_t *get_hwc_address(SM501State *state, int crt)
627 {
628 uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr;
629 return state->local_mem + (addr & 0x03FFFFF0);
630 }
631
632 /**
633 * Get the cursor position in y coordinate.
634 * @param crt 0 for PANEL, 1 for CRT.
635 */
636 static inline uint32_t get_hwc_y(SM501State *state, int crt)
637 {
638 uint32_t location = crt ? state->dc_crt_hwc_location
639 : state->dc_panel_hwc_location;
640 return (location & 0x07FF0000) >> 16;
641 }
642
643 /**
644 * Get the cursor position in x coordinate.
645 * @param crt 0 for PANEL, 1 for CRT.
646 */
647 static inline uint32_t get_hwc_x(SM501State *state, int crt)
648 {
649 uint32_t location = crt ? state->dc_crt_hwc_location
650 : state->dc_panel_hwc_location;
651 return location & 0x000007FF;
652 }
653
654 /**
655 * Get the hardware cursor palette.
656 * @param crt 0 for PANEL, 1 for CRT.
657 * @param palette pointer to a [3 * 3] array to store color values in
658 */
659 static inline void get_hwc_palette(SM501State *state, int crt, uint8_t *palette)
660 {
661 int i;
662 uint32_t color_reg;
663 uint16_t rgb565;
664
665 for (i = 0; i < 3; i++) {
666 if (i + 1 == 3) {
667 color_reg = crt ? state->dc_crt_hwc_color_3
668 : state->dc_panel_hwc_color_3;
669 } else {
670 color_reg = crt ? state->dc_crt_hwc_color_1_2
671 : state->dc_panel_hwc_color_1_2;
672 }
673
674 if (i + 1 == 2) {
675 rgb565 = (color_reg >> 16) & 0xFFFF;
676 } else {
677 rgb565 = color_reg & 0xFFFF;
678 }
679 palette[i * 3 + 0] = ((rgb565 >> 11) * 527 + 23) >> 6; /* r */
680 palette[i * 3 + 1] = (((rgb565 >> 5) & 0x3f) * 259 + 33) >> 6; /* g */
681 palette[i * 3 + 2] = ((rgb565 & 0x1f) * 527 + 23) >> 6; /* b */
682 }
683 }
684
685 static inline void hwc_invalidate(SM501State *s, int crt)
686 {
687 int w = get_width(s, crt);
688 int h = get_height(s, crt);
689 int bpp = get_bpp(s, crt);
690 int start = get_hwc_y(s, crt);
691 int end = MIN(h, start + SM501_HWC_HEIGHT) + 1;
692
693 start *= w * bpp;
694 end *= w * bpp;
695
696 memory_region_set_dirty(&s->local_mem_region,
697 get_fb_addr(s, crt) + start, end - start);
698 }
699
700 static void sm501_2d_operation(SM501State *s)
701 {
702 /* obtain operation parameters */
703 int operation = (s->twoD_control >> 16) & 0x1f;
704 int rtl = s->twoD_control & 0x8000000;
705 int src_x = (s->twoD_source >> 16) & 0x01FFF;
706 int src_y = s->twoD_source & 0xFFFF;
707 int dst_x = (s->twoD_destination >> 16) & 0x01FFF;
708 int dst_y = s->twoD_destination & 0xFFFF;
709 int operation_width = (s->twoD_dimension >> 16) & 0x1FFF;
710 int operation_height = s->twoD_dimension & 0xFFFF;
711 uint32_t color = s->twoD_foreground;
712 int format_flags = (s->twoD_stretch >> 20) & 0x3;
713 int addressing = (s->twoD_stretch >> 16) & 0xF;
714 int rop_mode = (s->twoD_control >> 15) & 0x1; /* 1 for rop2, else rop3 */
715 /* 1 if rop2 source is the pattern, otherwise the source is the bitmap */
716 int rop2_source_is_pattern = (s->twoD_control >> 14) & 0x1;
717 int rop = s->twoD_control & 0xFF;
718 uint32_t src_base = s->twoD_source_base & 0x03FFFFFF;
719 uint32_t dst_base = s->twoD_destination_base & 0x03FFFFFF;
720
721 /* get frame buffer info */
722 uint8_t *src = s->local_mem + src_base;
723 uint8_t *dst = s->local_mem + dst_base;
724 int src_width = s->twoD_pitch & 0x1FFF;
725 int dst_width = (s->twoD_pitch >> 16) & 0x1FFF;
726 int crt = (s->dc_crt_control & SM501_DC_CRT_CONTROL_SEL) ? 1 : 0;
727 int fb_len = get_width(s, crt) * get_height(s, crt) * get_bpp(s, crt);
728
729 if (addressing != 0x0) {
730 printf("%s: only XY addressing is supported.\n", __func__);
731 abort();
732 }
733
734 if (rop_mode == 0) {
735 if (rop != 0xcc) {
736 /* Anything other than plain copies are not supported */
737 qemu_log_mask(LOG_UNIMP, "sm501: rop3 mode with rop %x is not "
738 "supported.\n", rop);
739 }
740 } else {
741 if (rop2_source_is_pattern && rop != 0x5) {
742 /* For pattern source, we support only inverse dest */
743 qemu_log_mask(LOG_UNIMP, "sm501: rop2 source being the pattern and "
744 "rop %x is not supported.\n", rop);
745 } else {
746 if (rop != 0x5 && rop != 0xc) {
747 /* Anything other than plain copies or inverse dest is not
748 * supported */
749 qemu_log_mask(LOG_UNIMP, "sm501: rop mode %x is not "
750 "supported.\n", rop);
751 }
752 }
753 }
754
755 if ((s->twoD_source_base & 0x08000000) ||
756 (s->twoD_destination_base & 0x08000000)) {
757 printf("%s: only local memory is supported.\n", __func__);
758 abort();
759 }
760
761 switch (operation) {
762 case 0x00: /* copy area */
763 #define COPY_AREA(_bpp, _pixel_type, rtl) { \
764 int y, x, index_d, index_s; \
765 for (y = 0; y < operation_height; y++) { \
766 for (x = 0; x < operation_width; x++) { \
767 _pixel_type val; \
768 \
769 if (rtl) { \
770 index_s = ((src_y - y) * src_width + src_x - x) * _bpp; \
771 index_d = ((dst_y - y) * dst_width + dst_x - x) * _bpp; \
772 } else { \
773 index_s = ((src_y + y) * src_width + src_x + x) * _bpp; \
774 index_d = ((dst_y + y) * dst_width + dst_x + x) * _bpp; \
775 } \
776 if (rop_mode == 1 && rop == 5) { \
777 /* Invert dest */ \
778 val = ~*(_pixel_type *)&dst[index_d]; \
779 } else { \
780 val = *(_pixel_type *)&src[index_s]; \
781 } \
782 *(_pixel_type *)&dst[index_d] = val; \
783 } \
784 } \
785 }
786 switch (format_flags) {
787 case 0:
788 COPY_AREA(1, uint8_t, rtl);
789 break;
790 case 1:
791 COPY_AREA(2, uint16_t, rtl);
792 break;
793 case 2:
794 COPY_AREA(4, uint32_t, rtl);
795 break;
796 }
797 break;
798
799 case 0x01: /* fill rectangle */
800 #define FILL_RECT(_bpp, _pixel_type) { \
801 int y, x; \
802 for (y = 0; y < operation_height; y++) { \
803 for (x = 0; x < operation_width; x++) { \
804 int index = ((dst_y + y) * dst_width + dst_x + x) * _bpp; \
805 *(_pixel_type *)&dst[index] = (_pixel_type)color; \
806 } \
807 } \
808 }
809
810 switch (format_flags) {
811 case 0:
812 FILL_RECT(1, uint8_t);
813 break;
814 case 1:
815 color = cpu_to_le16(color);
816 FILL_RECT(2, uint16_t);
817 break;
818 case 2:
819 color = cpu_to_le32(color);
820 FILL_RECT(4, uint32_t);
821 break;
822 }
823 break;
824
825 default:
826 printf("non-implemented SM501 2D operation. %d\n", operation);
827 abort();
828 break;
829 }
830
831 if (dst_base >= get_fb_addr(s, crt) &&
832 dst_base <= get_fb_addr(s, crt) + fb_len) {
833 int dst_len = MIN(fb_len, ((dst_y + operation_height - 1) * dst_width +
834 dst_x + operation_width) * (1 << format_flags));
835 if (dst_len) {
836 memory_region_set_dirty(&s->local_mem_region, dst_base, dst_len);
837 }
838 }
839 }
840
841 static uint64_t sm501_system_config_read(void *opaque, hwaddr addr,
842 unsigned size)
843 {
844 SM501State *s = (SM501State *)opaque;
845 uint32_t ret = 0;
846 SM501_DPRINTF("sm501 system config regs : read addr=%x\n", (int)addr);
847
848 switch (addr) {
849 case SM501_SYSTEM_CONTROL:
850 ret = s->system_control;
851 break;
852 case SM501_MISC_CONTROL:
853 ret = s->misc_control;
854 break;
855 case SM501_GPIO31_0_CONTROL:
856 ret = s->gpio_31_0_control;
857 break;
858 case SM501_GPIO63_32_CONTROL:
859 ret = s->gpio_63_32_control;
860 break;
861 case SM501_DEVICEID:
862 ret = 0x050100A0;
863 break;
864 case SM501_DRAM_CONTROL:
865 ret = (s->dram_control & 0x07F107C0) | s->local_mem_size_index << 13;
866 break;
867 case SM501_ARBTRTN_CONTROL:
868 ret = s->arbitration_control;
869 break;
870 case SM501_COMMAND_LIST_STATUS:
871 ret = 0x00180002; /* FIFOs are empty, everything idle */
872 break;
873 case SM501_IRQ_MASK:
874 ret = s->irq_mask;
875 break;
876 case SM501_MISC_TIMING:
877 /* TODO : simulate gate control */
878 ret = s->misc_timing;
879 break;
880 case SM501_CURRENT_GATE:
881 /* TODO : simulate gate control */
882 ret = 0x00021807;
883 break;
884 case SM501_CURRENT_CLOCK:
885 ret = 0x2A1A0A09;
886 break;
887 case SM501_POWER_MODE_CONTROL:
888 ret = s->power_mode_control;
889 break;
890 case SM501_ENDIAN_CONTROL:
891 ret = 0; /* Only default little endian mode is supported */
892 break;
893
894 default:
895 printf("sm501 system config : not implemented register read."
896 " addr=%x\n", (int)addr);
897 abort();
898 }
899
900 return ret;
901 }
902
903 static void sm501_system_config_write(void *opaque, hwaddr addr,
904 uint64_t value, unsigned size)
905 {
906 SM501State *s = (SM501State *)opaque;
907 SM501_DPRINTF("sm501 system config regs : write addr=%x, val=%x\n",
908 (uint32_t)addr, (uint32_t)value);
909
910 switch (addr) {
911 case SM501_SYSTEM_CONTROL:
912 s->system_control &= 0x10DB0000;
913 s->system_control |= value & 0xEF00B8F7;
914 break;
915 case SM501_MISC_CONTROL:
916 s->misc_control &= 0xEF;
917 s->misc_control |= value & 0xFF7FFF10;
918 break;
919 case SM501_GPIO31_0_CONTROL:
920 s->gpio_31_0_control = value;
921 break;
922 case SM501_GPIO63_32_CONTROL:
923 s->gpio_63_32_control = value & 0xFF80FFFF;
924 break;
925 case SM501_DRAM_CONTROL:
926 s->local_mem_size_index = (value >> 13) & 0x7;
927 /* TODO : check validity of size change */
928 s->dram_control &= 0x80000000;
929 s->dram_control |= value & 0x7FFFFFC3;
930 break;
931 case SM501_ARBTRTN_CONTROL:
932 s->arbitration_control = value & 0x37777777;
933 break;
934 case SM501_IRQ_MASK:
935 s->irq_mask = value & 0xFFDF3F5F;
936 break;
937 case SM501_MISC_TIMING:
938 s->misc_timing = value & 0xF31F1FFF;
939 break;
940 case SM501_POWER_MODE_0_GATE:
941 case SM501_POWER_MODE_1_GATE:
942 case SM501_POWER_MODE_0_CLOCK:
943 case SM501_POWER_MODE_1_CLOCK:
944 /* TODO : simulate gate & clock control */
945 break;
946 case SM501_POWER_MODE_CONTROL:
947 s->power_mode_control = value & 0x00000003;
948 break;
949 case SM501_ENDIAN_CONTROL:
950 if (value & 0x00000001) {
951 printf("sm501 system config : big endian mode not implemented.\n");
952 abort();
953 }
954 break;
955
956 default:
957 printf("sm501 system config : not implemented register write."
958 " addr=%x, val=%x\n", (int)addr, (uint32_t)value);
959 abort();
960 }
961 }
962
963 static const MemoryRegionOps sm501_system_config_ops = {
964 .read = sm501_system_config_read,
965 .write = sm501_system_config_write,
966 .valid = {
967 .min_access_size = 4,
968 .max_access_size = 4,
969 },
970 .endianness = DEVICE_LITTLE_ENDIAN,
971 };
972
973 static uint64_t sm501_i2c_read(void *opaque, hwaddr addr, unsigned size)
974 {
975 SM501State *s = (SM501State *)opaque;
976 uint8_t ret = 0;
977
978 switch (addr) {
979 case SM501_I2C_BYTE_COUNT:
980 ret = s->i2c_byte_count;
981 break;
982 case SM501_I2C_STATUS:
983 ret = s->i2c_status;
984 break;
985 case SM501_I2C_SLAVE_ADDRESS:
986 ret = s->i2c_addr;
987 break;
988 case SM501_I2C_DATA ... SM501_I2C_DATA + 15:
989 ret = s->i2c_data[addr - SM501_I2C_DATA];
990 break;
991 default:
992 qemu_log_mask(LOG_UNIMP, "sm501 i2c : not implemented register read."
993 " addr=0x%" HWADDR_PRIx "\n", addr);
994 }
995
996 SM501_DPRINTF("sm501 i2c regs : read addr=%" HWADDR_PRIx " val=%x\n",
997 addr, ret);
998 return ret;
999 }
1000
1001 static void sm501_i2c_write(void *opaque, hwaddr addr, uint64_t value,
1002 unsigned size)
1003 {
1004 SM501State *s = (SM501State *)opaque;
1005 SM501_DPRINTF("sm501 i2c regs : write addr=%" HWADDR_PRIx
1006 " val=%" PRIx64 "\n", addr, value);
1007
1008 switch (addr) {
1009 case SM501_I2C_BYTE_COUNT:
1010 s->i2c_byte_count = value & 0xf;
1011 break;
1012 case SM501_I2C_CONTROL:
1013 if (value & SM501_I2C_CONTROL_ENABLE) {
1014 if (value & SM501_I2C_CONTROL_START) {
1015 int res = i2c_start_transfer(s->i2c_bus,
1016 s->i2c_addr >> 1,
1017 s->i2c_addr & 1);
1018 s->i2c_status |= (res ? SM501_I2C_STATUS_ERROR : 0);
1019 if (!res) {
1020 int i;
1021 SM501_DPRINTF("sm501 i2c : transferring %d bytes to 0x%x\n",
1022 s->i2c_byte_count + 1, s->i2c_addr >> 1);
1023 for (i = 0; i <= s->i2c_byte_count; i++) {
1024 res = i2c_send_recv(s->i2c_bus, &s->i2c_data[i],
1025 !(s->i2c_addr & 1));
1026 if (res) {
1027 SM501_DPRINTF("sm501 i2c : transfer failed"
1028 " i=%d, res=%d\n", i, res);
1029 s->i2c_status |= SM501_I2C_STATUS_ERROR;
1030 return;
1031 }
1032 }
1033 if (i) {
1034 SM501_DPRINTF("sm501 i2c : transferred %d bytes\n", i);
1035 s->i2c_status = SM501_I2C_STATUS_COMPLETE;
1036 }
1037 }
1038 } else {
1039 SM501_DPRINTF("sm501 i2c : end transfer\n");
1040 i2c_end_transfer(s->i2c_bus);
1041 s->i2c_status &= ~SM501_I2C_STATUS_ERROR;
1042 }
1043 }
1044 break;
1045 case SM501_I2C_RESET:
1046 if ((value & SM501_I2C_RESET_ERROR) == 0) {
1047 s->i2c_status &= ~SM501_I2C_STATUS_ERROR;
1048 }
1049 break;
1050 case SM501_I2C_SLAVE_ADDRESS:
1051 s->i2c_addr = value & 0xff;
1052 break;
1053 case SM501_I2C_DATA ... SM501_I2C_DATA + 15:
1054 s->i2c_data[addr - SM501_I2C_DATA] = value & 0xff;
1055 break;
1056 default:
1057 qemu_log_mask(LOG_UNIMP, "sm501 i2c : not implemented register write. "
1058 "addr=0x%" HWADDR_PRIx " val=%" PRIx64 "\n", addr, value);
1059 }
1060 }
1061
1062 static const MemoryRegionOps sm501_i2c_ops = {
1063 .read = sm501_i2c_read,
1064 .write = sm501_i2c_write,
1065 .valid = {
1066 .min_access_size = 1,
1067 .max_access_size = 1,
1068 },
1069 .impl = {
1070 .min_access_size = 1,
1071 .max_access_size = 1,
1072 },
1073 .endianness = DEVICE_LITTLE_ENDIAN,
1074 };
1075
1076 static uint32_t sm501_palette_read(void *opaque, hwaddr addr)
1077 {
1078 SM501State *s = (SM501State *)opaque;
1079 SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr);
1080
1081 /* TODO : consider BYTE/WORD access */
1082 /* TODO : consider endian */
1083
1084 assert(range_covers_byte(0, 0x400 * 3, addr));
1085 return *(uint32_t *)&s->dc_palette[addr];
1086 }
1087
1088 static void sm501_palette_write(void *opaque, hwaddr addr,
1089 uint32_t value)
1090 {
1091 SM501State *s = (SM501State *)opaque;
1092 SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n",
1093 (int)addr, value);
1094
1095 /* TODO : consider BYTE/WORD access */
1096 /* TODO : consider endian */
1097
1098 assert(range_covers_byte(0, 0x400 * 3, addr));
1099 *(uint32_t *)&s->dc_palette[addr] = value;
1100 s->do_full_update = true;
1101 }
1102
1103 static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr,
1104 unsigned size)
1105 {
1106 SM501State *s = (SM501State *)opaque;
1107 uint32_t ret = 0;
1108 SM501_DPRINTF("sm501 disp ctrl regs : read addr=%x\n", (int)addr);
1109
1110 switch (addr) {
1111
1112 case SM501_DC_PANEL_CONTROL:
1113 ret = s->dc_panel_control;
1114 break;
1115 case SM501_DC_PANEL_PANNING_CONTROL:
1116 ret = s->dc_panel_panning_control;
1117 break;
1118 case SM501_DC_PANEL_COLOR_KEY:
1119 /* Not implemented yet */
1120 break;
1121 case SM501_DC_PANEL_FB_ADDR:
1122 ret = s->dc_panel_fb_addr;
1123 break;
1124 case SM501_DC_PANEL_FB_OFFSET:
1125 ret = s->dc_panel_fb_offset;
1126 break;
1127 case SM501_DC_PANEL_FB_WIDTH:
1128 ret = s->dc_panel_fb_width;
1129 break;
1130 case SM501_DC_PANEL_FB_HEIGHT:
1131 ret = s->dc_panel_fb_height;
1132 break;
1133 case SM501_DC_PANEL_TL_LOC:
1134 ret = s->dc_panel_tl_location;
1135 break;
1136 case SM501_DC_PANEL_BR_LOC:
1137 ret = s->dc_panel_br_location;
1138 break;
1139
1140 case SM501_DC_PANEL_H_TOT:
1141 ret = s->dc_panel_h_total;
1142 break;
1143 case SM501_DC_PANEL_H_SYNC:
1144 ret = s->dc_panel_h_sync;
1145 break;
1146 case SM501_DC_PANEL_V_TOT:
1147 ret = s->dc_panel_v_total;
1148 break;
1149 case SM501_DC_PANEL_V_SYNC:
1150 ret = s->dc_panel_v_sync;
1151 break;
1152
1153 case SM501_DC_PANEL_HWC_ADDR:
1154 ret = s->dc_panel_hwc_addr;
1155 break;
1156 case SM501_DC_PANEL_HWC_LOC:
1157 ret = s->dc_panel_hwc_location;
1158 break;
1159 case SM501_DC_PANEL_HWC_COLOR_1_2:
1160 ret = s->dc_panel_hwc_color_1_2;
1161 break;
1162 case SM501_DC_PANEL_HWC_COLOR_3:
1163 ret = s->dc_panel_hwc_color_3;
1164 break;
1165
1166 case SM501_DC_VIDEO_CONTROL:
1167 ret = s->dc_video_control;
1168 break;
1169
1170 case SM501_DC_CRT_CONTROL:
1171 ret = s->dc_crt_control;
1172 break;
1173 case SM501_DC_CRT_FB_ADDR:
1174 ret = s->dc_crt_fb_addr;
1175 break;
1176 case SM501_DC_CRT_FB_OFFSET:
1177 ret = s->dc_crt_fb_offset;
1178 break;
1179 case SM501_DC_CRT_H_TOT:
1180 ret = s->dc_crt_h_total;
1181 break;
1182 case SM501_DC_CRT_H_SYNC:
1183 ret = s->dc_crt_h_sync;
1184 break;
1185 case SM501_DC_CRT_V_TOT:
1186 ret = s->dc_crt_v_total;
1187 break;
1188 case SM501_DC_CRT_V_SYNC:
1189 ret = s->dc_crt_v_sync;
1190 break;
1191
1192 case SM501_DC_CRT_HWC_ADDR:
1193 ret = s->dc_crt_hwc_addr;
1194 break;
1195 case SM501_DC_CRT_HWC_LOC:
1196 ret = s->dc_crt_hwc_location;
1197 break;
1198 case SM501_DC_CRT_HWC_COLOR_1_2:
1199 ret = s->dc_crt_hwc_color_1_2;
1200 break;
1201 case SM501_DC_CRT_HWC_COLOR_3:
1202 ret = s->dc_crt_hwc_color_3;
1203 break;
1204
1205 case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4:
1206 ret = sm501_palette_read(opaque, addr - SM501_DC_PANEL_PALETTE);
1207 break;
1208
1209 default:
1210 printf("sm501 disp ctrl : not implemented register read."
1211 " addr=%x\n", (int)addr);
1212 abort();
1213 }
1214
1215 return ret;
1216 }
1217
1218 static void sm501_disp_ctrl_write(void *opaque, hwaddr addr,
1219 uint64_t value, unsigned size)
1220 {
1221 SM501State *s = (SM501State *)opaque;
1222 SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, val=%x\n",
1223 (unsigned)addr, (unsigned)value);
1224
1225 switch (addr) {
1226 case SM501_DC_PANEL_CONTROL:
1227 s->dc_panel_control = value & 0x0FFF73FF;
1228 break;
1229 case SM501_DC_PANEL_PANNING_CONTROL:
1230 s->dc_panel_panning_control = value & 0xFF3FFF3F;
1231 break;
1232 case SM501_DC_PANEL_COLOR_KEY:
1233 /* Not implemented yet */
1234 break;
1235 case SM501_DC_PANEL_FB_ADDR:
1236 s->dc_panel_fb_addr = value & 0x8FFFFFF0;
1237 if (value & 0x8000000) {
1238 qemu_log_mask(LOG_UNIMP, "Panel external memory not supported\n");
1239 }
1240 s->do_full_update = true;
1241 break;
1242 case SM501_DC_PANEL_FB_OFFSET:
1243 s->dc_panel_fb_offset = value & 0x3FF03FF0;
1244 break;
1245 case SM501_DC_PANEL_FB_WIDTH:
1246 s->dc_panel_fb_width = value & 0x0FFF0FFF;
1247 break;
1248 case SM501_DC_PANEL_FB_HEIGHT:
1249 s->dc_panel_fb_height = value & 0x0FFF0FFF;
1250 break;
1251 case SM501_DC_PANEL_TL_LOC:
1252 s->dc_panel_tl_location = value & 0x07FF07FF;
1253 break;
1254 case SM501_DC_PANEL_BR_LOC:
1255 s->dc_panel_br_location = value & 0x07FF07FF;
1256 break;
1257
1258 case SM501_DC_PANEL_H_TOT:
1259 s->dc_panel_h_total = value & 0x0FFF0FFF;
1260 break;
1261 case SM501_DC_PANEL_H_SYNC:
1262 s->dc_panel_h_sync = value & 0x00FF0FFF;
1263 break;
1264 case SM501_DC_PANEL_V_TOT:
1265 s->dc_panel_v_total = value & 0x0FFF0FFF;
1266 break;
1267 case SM501_DC_PANEL_V_SYNC:
1268 s->dc_panel_v_sync = value & 0x003F0FFF;
1269 break;
1270
1271 case SM501_DC_PANEL_HWC_ADDR:
1272 value &= 0x8FFFFFF0;
1273 if (value != s->dc_panel_hwc_addr) {
1274 hwc_invalidate(s, 0);
1275 s->dc_panel_hwc_addr = value;
1276 }
1277 break;
1278 case SM501_DC_PANEL_HWC_LOC:
1279 value &= 0x0FFF0FFF;
1280 if (value != s->dc_panel_hwc_location) {
1281 hwc_invalidate(s, 0);
1282 s->dc_panel_hwc_location = value;
1283 }
1284 break;
1285 case SM501_DC_PANEL_HWC_COLOR_1_2:
1286 s->dc_panel_hwc_color_1_2 = value;
1287 break;
1288 case SM501_DC_PANEL_HWC_COLOR_3:
1289 s->dc_panel_hwc_color_3 = value & 0x0000FFFF;
1290 break;
1291
1292 case SM501_DC_VIDEO_CONTROL:
1293 s->dc_video_control = value & 0x00037FFF;
1294 break;
1295
1296 case SM501_DC_CRT_CONTROL:
1297 s->dc_crt_control = value & 0x0003FFFF;
1298 break;
1299 case SM501_DC_CRT_FB_ADDR:
1300 s->dc_crt_fb_addr = value & 0x8FFFFFF0;
1301 if (value & 0x8000000) {
1302 qemu_log_mask(LOG_UNIMP, "CRT external memory not supported\n");
1303 }
1304 s->do_full_update = true;
1305 break;
1306 case SM501_DC_CRT_FB_OFFSET:
1307 s->dc_crt_fb_offset = value & 0x3FF03FF0;
1308 break;
1309 case SM501_DC_CRT_H_TOT:
1310 s->dc_crt_h_total = value & 0x0FFF0FFF;
1311 break;
1312 case SM501_DC_CRT_H_SYNC:
1313 s->dc_crt_h_sync = value & 0x00FF0FFF;
1314 break;
1315 case SM501_DC_CRT_V_TOT:
1316 s->dc_crt_v_total = value & 0x0FFF0FFF;
1317 break;
1318 case SM501_DC_CRT_V_SYNC:
1319 s->dc_crt_v_sync = value & 0x003F0FFF;
1320 break;
1321
1322 case SM501_DC_CRT_HWC_ADDR:
1323 value &= 0x8FFFFFF0;
1324 if (value != s->dc_crt_hwc_addr) {
1325 hwc_invalidate(s, 1);
1326 s->dc_crt_hwc_addr = value;
1327 }
1328 break;
1329 case SM501_DC_CRT_HWC_LOC:
1330 value &= 0x0FFF0FFF;
1331 if (value != s->dc_crt_hwc_location) {
1332 hwc_invalidate(s, 1);
1333 s->dc_crt_hwc_location = value;
1334 }
1335 break;
1336 case SM501_DC_CRT_HWC_COLOR_1_2:
1337 s->dc_crt_hwc_color_1_2 = value;
1338 break;
1339 case SM501_DC_CRT_HWC_COLOR_3:
1340 s->dc_crt_hwc_color_3 = value & 0x0000FFFF;
1341 break;
1342
1343 case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4:
1344 sm501_palette_write(opaque, addr - SM501_DC_PANEL_PALETTE, value);
1345 break;
1346
1347 default:
1348 printf("sm501 disp ctrl : not implemented register write."
1349 " addr=%x, val=%x\n", (int)addr, (unsigned)value);
1350 abort();
1351 }
1352 }
1353
1354 static const MemoryRegionOps sm501_disp_ctrl_ops = {
1355 .read = sm501_disp_ctrl_read,
1356 .write = sm501_disp_ctrl_write,
1357 .valid = {
1358 .min_access_size = 4,
1359 .max_access_size = 4,
1360 },
1361 .endianness = DEVICE_LITTLE_ENDIAN,
1362 };
1363
1364 static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr,
1365 unsigned size)
1366 {
1367 SM501State *s = (SM501State *)opaque;
1368 uint32_t ret = 0;
1369 SM501_DPRINTF("sm501 2d engine regs : read addr=%x\n", (int)addr);
1370
1371 switch (addr) {
1372 case SM501_2D_SOURCE:
1373 ret = s->twoD_source;
1374 break;
1375 case SM501_2D_DESTINATION:
1376 ret = s->twoD_destination;
1377 break;
1378 case SM501_2D_DIMENSION:
1379 ret = s->twoD_dimension;
1380 break;
1381 case SM501_2D_CONTROL:
1382 ret = s->twoD_control;
1383 break;
1384 case SM501_2D_PITCH:
1385 ret = s->twoD_pitch;
1386 break;
1387 case SM501_2D_FOREGROUND:
1388 ret = s->twoD_foreground;
1389 break;
1390 case SM501_2D_BACKGROUND:
1391 ret = s->twoD_background;
1392 break;
1393 case SM501_2D_STRETCH:
1394 ret = s->twoD_stretch;
1395 break;
1396 case SM501_2D_COLOR_COMPARE:
1397 ret = s->twoD_color_compare;
1398 break;
1399 case SM501_2D_COLOR_COMPARE_MASK:
1400 ret = s->twoD_color_compare_mask;
1401 break;
1402 case SM501_2D_MASK:
1403 ret = s->twoD_mask;
1404 break;
1405 case SM501_2D_CLIP_TL:
1406 ret = s->twoD_clip_tl;
1407 break;
1408 case SM501_2D_CLIP_BR:
1409 ret = s->twoD_clip_br;
1410 break;
1411 case SM501_2D_MONO_PATTERN_LOW:
1412 ret = s->twoD_mono_pattern_low;
1413 break;
1414 case SM501_2D_MONO_PATTERN_HIGH:
1415 ret = s->twoD_mono_pattern_high;
1416 break;
1417 case SM501_2D_WINDOW_WIDTH:
1418 ret = s->twoD_window_width;
1419 break;
1420 case SM501_2D_SOURCE_BASE:
1421 ret = s->twoD_source_base;
1422 break;
1423 case SM501_2D_DESTINATION_BASE:
1424 ret = s->twoD_destination_base;
1425 break;
1426 case SM501_2D_ALPHA:
1427 ret = s->twoD_alpha;
1428 break;
1429 case SM501_2D_WRAP:
1430 ret = s->twoD_wrap;
1431 break;
1432 case SM501_2D_STATUS:
1433 ret = 0; /* Should return interrupt status */
1434 break;
1435 default:
1436 printf("sm501 disp ctrl : not implemented register read."
1437 " addr=%x\n", (int)addr);
1438 abort();
1439 }
1440
1441 return ret;
1442 }
1443
1444 static void sm501_2d_engine_write(void *opaque, hwaddr addr,
1445 uint64_t value, unsigned size)
1446 {
1447 SM501State *s = (SM501State *)opaque;
1448 SM501_DPRINTF("sm501 2d engine regs : write addr=%x, val=%x\n",
1449 (unsigned)addr, (unsigned)value);
1450
1451 switch (addr) {
1452 case SM501_2D_SOURCE:
1453 s->twoD_source = value;
1454 break;
1455 case SM501_2D_DESTINATION:
1456 s->twoD_destination = value;
1457 break;
1458 case SM501_2D_DIMENSION:
1459 s->twoD_dimension = value;
1460 break;
1461 case SM501_2D_CONTROL:
1462 s->twoD_control = value;
1463
1464 /* do 2d operation if start flag is set. */
1465 if (value & 0x80000000) {
1466 sm501_2d_operation(s);
1467 s->twoD_control &= ~0x80000000; /* start flag down */
1468 }
1469
1470 break;
1471 case SM501_2D_PITCH:
1472 s->twoD_pitch = value;
1473 break;
1474 case SM501_2D_FOREGROUND:
1475 s->twoD_foreground = value;
1476 break;
1477 case SM501_2D_BACKGROUND:
1478 s->twoD_background = value;
1479 break;
1480 case SM501_2D_STRETCH:
1481 s->twoD_stretch = value;
1482 break;
1483 case SM501_2D_COLOR_COMPARE:
1484 s->twoD_color_compare = value;
1485 break;
1486 case SM501_2D_COLOR_COMPARE_MASK:
1487 s->twoD_color_compare_mask = value;
1488 break;
1489 case SM501_2D_MASK:
1490 s->twoD_mask = value;
1491 break;
1492 case SM501_2D_CLIP_TL:
1493 s->twoD_clip_tl = value;
1494 break;
1495 case SM501_2D_CLIP_BR:
1496 s->twoD_clip_br = value;
1497 break;
1498 case SM501_2D_MONO_PATTERN_LOW:
1499 s->twoD_mono_pattern_low = value;
1500 break;
1501 case SM501_2D_MONO_PATTERN_HIGH:
1502 s->twoD_mono_pattern_high = value;
1503 break;
1504 case SM501_2D_WINDOW_WIDTH:
1505 s->twoD_window_width = value;
1506 break;
1507 case SM501_2D_SOURCE_BASE:
1508 s->twoD_source_base = value;
1509 break;
1510 case SM501_2D_DESTINATION_BASE:
1511 s->twoD_destination_base = value;
1512 break;
1513 case SM501_2D_ALPHA:
1514 s->twoD_alpha = value;
1515 break;
1516 case SM501_2D_WRAP:
1517 s->twoD_wrap = value;
1518 break;
1519 case SM501_2D_STATUS:
1520 /* ignored, writing 0 should clear interrupt status */
1521 break;
1522 default:
1523 printf("sm501 2d engine : not implemented register write."
1524 " addr=%x, val=%x\n", (int)addr, (unsigned)value);
1525 abort();
1526 }
1527 }
1528
1529 static const MemoryRegionOps sm501_2d_engine_ops = {
1530 .read = sm501_2d_engine_read,
1531 .write = sm501_2d_engine_write,
1532 .valid = {
1533 .min_access_size = 4,
1534 .max_access_size = 4,
1535 },
1536 .endianness = DEVICE_LITTLE_ENDIAN,
1537 };
1538
1539 /* draw line functions for all console modes */
1540
1541 typedef void draw_line_func(uint8_t *d, const uint8_t *s,
1542 int width, const uint32_t *pal);
1543
1544 typedef void draw_hwc_line_func(uint8_t *d, const uint8_t *s,
1545 int width, const uint8_t *palette,
1546 int c_x, int c_y);
1547
1548 #define DEPTH 8
1549 #include "sm501_template.h"
1550
1551 #define DEPTH 15
1552 #include "sm501_template.h"
1553
1554 #define BGR_FORMAT
1555 #define DEPTH 15
1556 #include "sm501_template.h"
1557
1558 #define DEPTH 16
1559 #include "sm501_template.h"
1560
1561 #define BGR_FORMAT
1562 #define DEPTH 16
1563 #include "sm501_template.h"
1564
1565 #define DEPTH 32
1566 #include "sm501_template.h"
1567
1568 #define BGR_FORMAT
1569 #define DEPTH 32
1570 #include "sm501_template.h"
1571
1572 static draw_line_func *draw_line8_funcs[] = {
1573 draw_line8_8,
1574 draw_line8_15,
1575 draw_line8_16,
1576 draw_line8_32,
1577 draw_line8_32bgr,
1578 draw_line8_15bgr,
1579 draw_line8_16bgr,
1580 };
1581
1582 static draw_line_func *draw_line16_funcs[] = {
1583 draw_line16_8,
1584 draw_line16_15,
1585 draw_line16_16,
1586 draw_line16_32,
1587 draw_line16_32bgr,
1588 draw_line16_15bgr,
1589 draw_line16_16bgr,
1590 };
1591
1592 static draw_line_func *draw_line32_funcs[] = {
1593 draw_line32_8,
1594 draw_line32_15,
1595 draw_line32_16,
1596 draw_line32_32,
1597 draw_line32_32bgr,
1598 draw_line32_15bgr,
1599 draw_line32_16bgr,
1600 };
1601
1602 static draw_hwc_line_func *draw_hwc_line_funcs[] = {
1603 draw_hwc_line_8,
1604 draw_hwc_line_15,
1605 draw_hwc_line_16,
1606 draw_hwc_line_32,
1607 draw_hwc_line_32bgr,
1608 draw_hwc_line_15bgr,
1609 draw_hwc_line_16bgr,
1610 };
1611
1612 static inline int get_depth_index(DisplaySurface *surface)
1613 {
1614 switch (surface_bits_per_pixel(surface)) {
1615 default:
1616 case 8:
1617 return 0;
1618 case 15:
1619 return 1;
1620 case 16:
1621 return 2;
1622 case 32:
1623 if (is_surface_bgr(surface)) {
1624 return 4;
1625 } else {
1626 return 3;
1627 }
1628 }
1629 }
1630
1631 static void sm501_update_display(void *opaque)
1632 {
1633 SM501State *s = (SM501State *)opaque;
1634 DisplaySurface *surface = qemu_console_surface(s->con);
1635 DirtyBitmapSnapshot *snap;
1636 int y, c_x = 0, c_y = 0;
1637 int crt = (s->dc_crt_control & SM501_DC_CRT_CONTROL_SEL) ? 1 : 0;
1638 int width = get_width(s, crt);
1639 int height = get_height(s, crt);
1640 int src_bpp = get_bpp(s, crt);
1641 int dst_bpp = surface_bytes_per_pixel(surface);
1642 int dst_depth_index = get_depth_index(surface);
1643 draw_line_func *draw_line = NULL;
1644 draw_hwc_line_func *draw_hwc_line = NULL;
1645 int full_update = 0;
1646 int y_start = -1;
1647 ram_addr_t offset;
1648 uint32_t *palette;
1649 uint8_t hwc_palette[3 * 3];
1650 uint8_t *hwc_src = NULL;
1651
1652 if (!((crt ? s->dc_crt_control : s->dc_panel_control)
1653 & SM501_DC_CRT_CONTROL_ENABLE)) {
1654 return;
1655 }
1656
1657 palette = (uint32_t *)(crt ? &s->dc_palette[SM501_DC_CRT_PALETTE -
1658 SM501_DC_PANEL_PALETTE]
1659 : &s->dc_palette[0]);
1660
1661 /* choose draw_line function */
1662 switch (src_bpp) {
1663 case 1:
1664 draw_line = draw_line8_funcs[dst_depth_index];
1665 break;
1666 case 2:
1667 draw_line = draw_line16_funcs[dst_depth_index];
1668 break;
1669 case 4:
1670 draw_line = draw_line32_funcs[dst_depth_index];
1671 break;
1672 default:
1673 printf("sm501 update display : invalid control register value.\n");
1674 abort();
1675 break;
1676 }
1677
1678 /* set up to draw hardware cursor */
1679 if (is_hwc_enabled(s, crt)) {
1680 /* choose cursor draw line function */
1681 draw_hwc_line = draw_hwc_line_funcs[dst_depth_index];
1682 hwc_src = get_hwc_address(s, crt);
1683 c_x = get_hwc_x(s, crt);
1684 c_y = get_hwc_y(s, crt);
1685 get_hwc_palette(s, crt, hwc_palette);
1686 }
1687
1688 /* adjust console size */
1689 if (s->last_width != width || s->last_height != height) {
1690 qemu_console_resize(s->con, width, height);
1691 surface = qemu_console_surface(s->con);
1692 s->last_width = width;
1693 s->last_height = height;
1694 full_update = 1;
1695 }
1696
1697 /* someone else requested a full update */
1698 if (s->do_full_update) {
1699 s->do_full_update = false;
1700 full_update = 1;
1701 }
1702
1703 /* draw each line according to conditions */
1704 offset = get_fb_addr(s, crt);
1705 snap = memory_region_snapshot_and_clear_dirty(&s->local_mem_region,
1706 offset, width * height * src_bpp, DIRTY_MEMORY_VGA);
1707 for (y = 0; y < height; y++, offset += width * src_bpp) {
1708 int update, update_hwc;
1709
1710 /* check if hardware cursor is enabled and we're within its range */
1711 update_hwc = draw_hwc_line && c_y <= y && y < c_y + SM501_HWC_HEIGHT;
1712 update = full_update || update_hwc;
1713 /* check dirty flags for each line */
1714 update |= memory_region_snapshot_get_dirty(&s->local_mem_region, snap,
1715 offset, width * src_bpp);
1716
1717 /* draw line and change status */
1718 if (update) {
1719 uint8_t *d = surface_data(surface);
1720 d += y * width * dst_bpp;
1721
1722 /* draw graphics layer */
1723 draw_line(d, s->local_mem + offset, width, palette);
1724
1725 /* draw hardware cursor */
1726 if (update_hwc) {
1727 draw_hwc_line(d, hwc_src, width, hwc_palette, c_x, y - c_y);
1728 }
1729
1730 if (y_start < 0) {
1731 y_start = y;
1732 }
1733 } else {
1734 if (y_start >= 0) {
1735 /* flush to display */
1736 dpy_gfx_update(s->con, 0, y_start, width, y - y_start);
1737 y_start = -1;
1738 }
1739 }
1740 }
1741 g_free(snap);
1742
1743 /* complete flush to display */
1744 if (y_start >= 0) {
1745 dpy_gfx_update(s->con, 0, y_start, width, y - y_start);
1746 }
1747 }
1748
1749 static const GraphicHwOps sm501_ops = {
1750 .gfx_update = sm501_update_display,
1751 };
1752
1753 static void sm501_reset(SM501State *s)
1754 {
1755 s->system_control = 0x00100000; /* 2D engine FIFO empty */
1756 /* Bits 17 (SH), 7 (CDR), 6:5 (Test), 2:0 (Bus) are all supposed
1757 * to be determined at reset by GPIO lines which set config bits.
1758 * We hardwire them:
1759 * SH = 0 : Hitachi Ready Polarity == Active Low
1760 * CDR = 0 : do not reset clock divider
1761 * TEST = 0 : Normal mode (not testing the silicon)
1762 * BUS = 0 : Hitachi SH3/SH4
1763 */
1764 s->misc_control = SM501_MISC_DAC_POWER;
1765 s->gpio_31_0_control = 0;
1766 s->gpio_63_32_control = 0;
1767 s->dram_control = 0;
1768 s->arbitration_control = 0x05146732;
1769 s->irq_mask = 0;
1770 s->misc_timing = 0;
1771 s->power_mode_control = 0;
1772 s->i2c_byte_count = 0;
1773 s->i2c_status = 0;
1774 s->i2c_addr = 0;
1775 memset(s->i2c_data, 0, 16);
1776 s->dc_panel_control = 0x00010000; /* FIFO level 3 */
1777 s->dc_video_control = 0;
1778 s->dc_crt_control = 0x00010000;
1779 s->twoD_source = 0;
1780 s->twoD_destination = 0;
1781 s->twoD_dimension = 0;
1782 s->twoD_control = 0;
1783 s->twoD_pitch = 0;
1784 s->twoD_foreground = 0;
1785 s->twoD_background = 0;
1786 s->twoD_stretch = 0;
1787 s->twoD_color_compare = 0;
1788 s->twoD_color_compare_mask = 0;
1789 s->twoD_mask = 0;
1790 s->twoD_clip_tl = 0;
1791 s->twoD_clip_br = 0;
1792 s->twoD_mono_pattern_low = 0;
1793 s->twoD_mono_pattern_high = 0;
1794 s->twoD_window_width = 0;
1795 s->twoD_source_base = 0;
1796 s->twoD_destination_base = 0;
1797 s->twoD_alpha = 0;
1798 s->twoD_wrap = 0;
1799 }
1800
1801 static void sm501_init(SM501State *s, DeviceState *dev,
1802 uint32_t local_mem_bytes)
1803 {
1804 s->local_mem_size_index = get_local_mem_size_index(local_mem_bytes);
1805 SM501_DPRINTF("sm501 local mem size=%x. index=%d\n", get_local_mem_size(s),
1806 s->local_mem_size_index);
1807
1808 /* local memory */
1809 memory_region_init_ram(&s->local_mem_region, OBJECT(dev), "sm501.local",
1810 get_local_mem_size(s), &error_fatal);
1811 memory_region_set_log(&s->local_mem_region, true, DIRTY_MEMORY_VGA);
1812 s->local_mem = memory_region_get_ram_ptr(&s->local_mem_region);
1813
1814 /* i2c */
1815 s->i2c_bus = i2c_init_bus(dev, "sm501.i2c");
1816 /* ddc */
1817 I2CDDCState *ddc = I2CDDC(qdev_create(BUS(s->i2c_bus), TYPE_I2CDDC));
1818 i2c_set_slave_address(I2C_SLAVE(ddc), 0x50);
1819
1820 /* mmio */
1821 memory_region_init(&s->mmio_region, OBJECT(dev), "sm501.mmio", MMIO_SIZE);
1822 memory_region_init_io(&s->system_config_region, OBJECT(dev),
1823 &sm501_system_config_ops, s,
1824 "sm501-system-config", 0x6c);
1825 memory_region_add_subregion(&s->mmio_region, SM501_SYS_CONFIG,
1826 &s->system_config_region);
1827 memory_region_init_io(&s->i2c_region, OBJECT(dev), &sm501_i2c_ops, s,
1828 "sm501-i2c", 0x14);
1829 memory_region_add_subregion(&s->mmio_region, SM501_I2C, &s->i2c_region);
1830 memory_region_init_io(&s->disp_ctrl_region, OBJECT(dev),
1831 &sm501_disp_ctrl_ops, s,
1832 "sm501-disp-ctrl", 0x1000);
1833 memory_region_add_subregion(&s->mmio_region, SM501_DC,
1834 &s->disp_ctrl_region);
1835 memory_region_init_io(&s->twoD_engine_region, OBJECT(dev),
1836 &sm501_2d_engine_ops, s,
1837 "sm501-2d-engine", 0x54);
1838 memory_region_add_subregion(&s->mmio_region, SM501_2D_ENGINE,
1839 &s->twoD_engine_region);
1840
1841 /* create qemu graphic console */
1842 s->con = graphic_console_init(DEVICE(dev), 0, &sm501_ops, s);
1843 }
1844
1845 static const VMStateDescription vmstate_sm501_state = {
1846 .name = "sm501-state",
1847 .version_id = 1,
1848 .minimum_version_id = 1,
1849 .fields = (VMStateField[]) {
1850 VMSTATE_UINT32(local_mem_size_index, SM501State),
1851 VMSTATE_UINT32(system_control, SM501State),
1852 VMSTATE_UINT32(misc_control, SM501State),
1853 VMSTATE_UINT32(gpio_31_0_control, SM501State),
1854 VMSTATE_UINT32(gpio_63_32_control, SM501State),
1855 VMSTATE_UINT32(dram_control, SM501State),
1856 VMSTATE_UINT32(arbitration_control, SM501State),
1857 VMSTATE_UINT32(irq_mask, SM501State),
1858 VMSTATE_UINT32(misc_timing, SM501State),
1859 VMSTATE_UINT32(power_mode_control, SM501State),
1860 VMSTATE_UINT32(uart0_ier, SM501State),
1861 VMSTATE_UINT32(uart0_lcr, SM501State),
1862 VMSTATE_UINT32(uart0_mcr, SM501State),
1863 VMSTATE_UINT32(uart0_scr, SM501State),
1864 VMSTATE_UINT8_ARRAY(dc_palette, SM501State, DC_PALETTE_ENTRIES),
1865 VMSTATE_UINT32(dc_panel_control, SM501State),
1866 VMSTATE_UINT32(dc_panel_panning_control, SM501State),
1867 VMSTATE_UINT32(dc_panel_fb_addr, SM501State),
1868 VMSTATE_UINT32(dc_panel_fb_offset, SM501State),
1869 VMSTATE_UINT32(dc_panel_fb_width, SM501State),
1870 VMSTATE_UINT32(dc_panel_fb_height, SM501State),
1871 VMSTATE_UINT32(dc_panel_tl_location, SM501State),
1872 VMSTATE_UINT32(dc_panel_br_location, SM501State),
1873 VMSTATE_UINT32(dc_panel_h_total, SM501State),
1874 VMSTATE_UINT32(dc_panel_h_sync, SM501State),
1875 VMSTATE_UINT32(dc_panel_v_total, SM501State),
1876 VMSTATE_UINT32(dc_panel_v_sync, SM501State),
1877 VMSTATE_UINT32(dc_panel_hwc_addr, SM501State),
1878 VMSTATE_UINT32(dc_panel_hwc_location, SM501State),
1879 VMSTATE_UINT32(dc_panel_hwc_color_1_2, SM501State),
1880 VMSTATE_UINT32(dc_panel_hwc_color_3, SM501State),
1881 VMSTATE_UINT32(dc_video_control, SM501State),
1882 VMSTATE_UINT32(dc_crt_control, SM501State),
1883 VMSTATE_UINT32(dc_crt_fb_addr, SM501State),
1884 VMSTATE_UINT32(dc_crt_fb_offset, SM501State),
1885 VMSTATE_UINT32(dc_crt_h_total, SM501State),
1886 VMSTATE_UINT32(dc_crt_h_sync, SM501State),
1887 VMSTATE_UINT32(dc_crt_v_total, SM501State),
1888 VMSTATE_UINT32(dc_crt_v_sync, SM501State),
1889 VMSTATE_UINT32(dc_crt_hwc_addr, SM501State),
1890 VMSTATE_UINT32(dc_crt_hwc_location, SM501State),
1891 VMSTATE_UINT32(dc_crt_hwc_color_1_2, SM501State),
1892 VMSTATE_UINT32(dc_crt_hwc_color_3, SM501State),
1893 VMSTATE_UINT32(twoD_source, SM501State),
1894 VMSTATE_UINT32(twoD_destination, SM501State),
1895 VMSTATE_UINT32(twoD_dimension, SM501State),
1896 VMSTATE_UINT32(twoD_control, SM501State),
1897 VMSTATE_UINT32(twoD_pitch, SM501State),
1898 VMSTATE_UINT32(twoD_foreground, SM501State),
1899 VMSTATE_UINT32(twoD_background, SM501State),
1900 VMSTATE_UINT32(twoD_stretch, SM501State),
1901 VMSTATE_UINT32(twoD_color_compare, SM501State),
1902 VMSTATE_UINT32(twoD_color_compare_mask, SM501State),
1903 VMSTATE_UINT32(twoD_mask, SM501State),
1904 VMSTATE_UINT32(twoD_clip_tl, SM501State),
1905 VMSTATE_UINT32(twoD_clip_br, SM501State),
1906 VMSTATE_UINT32(twoD_mono_pattern_low, SM501State),
1907 VMSTATE_UINT32(twoD_mono_pattern_high, SM501State),
1908 VMSTATE_UINT32(twoD_window_width, SM501State),
1909 VMSTATE_UINT32(twoD_source_base, SM501State),
1910 VMSTATE_UINT32(twoD_destination_base, SM501State),
1911 VMSTATE_UINT32(twoD_alpha, SM501State),
1912 VMSTATE_UINT32(twoD_wrap, SM501State),
1913 /* Added in version 2 */
1914 VMSTATE_UINT8(i2c_byte_count, SM501State),
1915 VMSTATE_UINT8(i2c_status, SM501State),
1916 VMSTATE_UINT8(i2c_addr, SM501State),
1917 VMSTATE_UINT8_ARRAY(i2c_data, SM501State, 16),
1918 VMSTATE_END_OF_LIST()
1919 }
1920 };
1921
1922 #define TYPE_SYSBUS_SM501 "sysbus-sm501"
1923 #define SYSBUS_SM501(obj) \
1924 OBJECT_CHECK(SM501SysBusState, (obj), TYPE_SYSBUS_SM501)
1925
1926 typedef struct {
1927 /*< private >*/
1928 SysBusDevice parent_obj;
1929 /*< public >*/
1930 SM501State state;
1931 uint32_t vram_size;
1932 uint32_t base;
1933 SerialMM serial;
1934 } SM501SysBusState;
1935
1936 static void sm501_realize_sysbus(DeviceState *dev, Error **errp)
1937 {
1938 SM501SysBusState *s = SYSBUS_SM501(dev);
1939 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1940 DeviceState *usb_dev;
1941 MemoryRegion *mr;
1942
1943 sm501_init(&s->state, dev, s->vram_size);
1944 if (get_local_mem_size(&s->state) != s->vram_size) {
1945 error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32,
1946 get_local_mem_size(&s->state));
1947 return;
1948 }
1949 sysbus_init_mmio(sbd, &s->state.local_mem_region);
1950 sysbus_init_mmio(sbd, &s->state.mmio_region);
1951
1952 /* bridge to usb host emulation module */
1953 usb_dev = qdev_create(NULL, "sysbus-ohci");
1954 qdev_prop_set_uint32(usb_dev, "num-ports", 2);
1955 qdev_prop_set_uint64(usb_dev, "dma-offset", s->base);
1956 qdev_init_nofail(usb_dev);
1957 memory_region_add_subregion(&s->state.mmio_region, SM501_USB_HOST,
1958 sysbus_mmio_get_region(SYS_BUS_DEVICE(usb_dev), 0));
1959 sysbus_pass_irq(sbd, SYS_BUS_DEVICE(usb_dev));
1960
1961 /* bridge to serial emulation module */
1962 qdev_init_nofail(DEVICE(&s->serial));
1963 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->serial), 0);
1964 memory_region_add_subregion(&s->state.mmio_region, SM501_UART0, mr);
1965 /* TODO : chain irq to IRL */
1966 }
1967
1968 static Property sm501_sysbus_properties[] = {
1969 DEFINE_PROP_UINT32("vram-size", SM501SysBusState, vram_size, 0),
1970 DEFINE_PROP_UINT32("base", SM501SysBusState, base, 0),
1971 DEFINE_PROP_END_OF_LIST(),
1972 };
1973
1974 static void sm501_reset_sysbus(DeviceState *dev)
1975 {
1976 SM501SysBusState *s = SYSBUS_SM501(dev);
1977 sm501_reset(&s->state);
1978 }
1979
1980 static const VMStateDescription vmstate_sm501_sysbus = {
1981 .name = TYPE_SYSBUS_SM501,
1982 .version_id = 2,
1983 .minimum_version_id = 2,
1984 .fields = (VMStateField[]) {
1985 VMSTATE_STRUCT(state, SM501SysBusState, 1,
1986 vmstate_sm501_state, SM501State),
1987 VMSTATE_END_OF_LIST()
1988 }
1989 };
1990
1991 static void sm501_sysbus_class_init(ObjectClass *klass, void *data)
1992 {
1993 DeviceClass *dc = DEVICE_CLASS(klass);
1994
1995 dc->realize = sm501_realize_sysbus;
1996 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
1997 dc->desc = "SM501 Multimedia Companion";
1998 device_class_set_props(dc, sm501_sysbus_properties);
1999 dc->reset = sm501_reset_sysbus;
2000 dc->vmsd = &vmstate_sm501_sysbus;
2001 }
2002
2003 static void sm501_sysbus_init(Object *o)
2004 {
2005 SM501SysBusState *sm501 = SYSBUS_SM501(o);
2006 SerialMM *smm = &sm501->serial;
2007
2008 sysbus_init_child_obj(o, "serial", smm, sizeof(SerialMM), TYPE_SERIAL_MM);
2009 qdev_set_legacy_instance_id(DEVICE(smm), SM501_UART0, 2);
2010 qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
2011 qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
2012
2013 object_property_add_alias(o, "chardev",
2014 OBJECT(smm), "chardev", &error_abort);
2015 }
2016
2017 static const TypeInfo sm501_sysbus_info = {
2018 .name = TYPE_SYSBUS_SM501,
2019 .parent = TYPE_SYS_BUS_DEVICE,
2020 .instance_size = sizeof(SM501SysBusState),
2021 .class_init = sm501_sysbus_class_init,
2022 .instance_init = sm501_sysbus_init,
2023 };
2024
2025 #define TYPE_PCI_SM501 "sm501"
2026 #define PCI_SM501(obj) OBJECT_CHECK(SM501PCIState, (obj), TYPE_PCI_SM501)
2027
2028 typedef struct {
2029 /*< private >*/
2030 PCIDevice parent_obj;
2031 /*< public >*/
2032 SM501State state;
2033 uint32_t vram_size;
2034 } SM501PCIState;
2035
2036 static void sm501_realize_pci(PCIDevice *dev, Error **errp)
2037 {
2038 SM501PCIState *s = PCI_SM501(dev);
2039
2040 sm501_init(&s->state, DEVICE(dev), s->vram_size);
2041 if (get_local_mem_size(&s->state) != s->vram_size) {
2042 error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32,
2043 get_local_mem_size(&s->state));
2044 return;
2045 }
2046 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
2047 &s->state.local_mem_region);
2048 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY,
2049 &s->state.mmio_region);
2050 }
2051
2052 static Property sm501_pci_properties[] = {
2053 DEFINE_PROP_UINT32("vram-size", SM501PCIState, vram_size, 64 * MiB),
2054 DEFINE_PROP_END_OF_LIST(),
2055 };
2056
2057 static void sm501_reset_pci(DeviceState *dev)
2058 {
2059 SM501PCIState *s = PCI_SM501(dev);
2060 sm501_reset(&s->state);
2061 /* Bits 2:0 of misc_control register is 001 for PCI */
2062 s->state.misc_control |= 1;
2063 }
2064
2065 static const VMStateDescription vmstate_sm501_pci = {
2066 .name = TYPE_PCI_SM501,
2067 .version_id = 2,
2068 .minimum_version_id = 2,
2069 .fields = (VMStateField[]) {
2070 VMSTATE_PCI_DEVICE(parent_obj, SM501PCIState),
2071 VMSTATE_STRUCT(state, SM501PCIState, 1,
2072 vmstate_sm501_state, SM501State),
2073 VMSTATE_END_OF_LIST()
2074 }
2075 };
2076
2077 static void sm501_pci_class_init(ObjectClass *klass, void *data)
2078 {
2079 DeviceClass *dc = DEVICE_CLASS(klass);
2080 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2081
2082 k->realize = sm501_realize_pci;
2083 k->vendor_id = PCI_VENDOR_ID_SILICON_MOTION;
2084 k->device_id = PCI_DEVICE_ID_SM501;
2085 k->class_id = PCI_CLASS_DISPLAY_OTHER;
2086 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
2087 dc->desc = "SM501 Display Controller";
2088 device_class_set_props(dc, sm501_pci_properties);
2089 dc->reset = sm501_reset_pci;
2090 dc->hotpluggable = false;
2091 dc->vmsd = &vmstate_sm501_pci;
2092 }
2093
2094 static const TypeInfo sm501_pci_info = {
2095 .name = TYPE_PCI_SM501,
2096 .parent = TYPE_PCI_DEVICE,
2097 .instance_size = sizeof(SM501PCIState),
2098 .class_init = sm501_pci_class_init,
2099 .interfaces = (InterfaceInfo[]) {
2100 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2101 { },
2102 },
2103 };
2104
2105 static void sm501_register_types(void)
2106 {
2107 type_register_static(&sm501_sysbus_info);
2108 type_register_static(&sm501_pci_info);
2109 }
2110
2111 type_init(sm501_register_types)