virtio-gpu: check max_outputs only
[qemu.git] / hw / display / virtio-gpu-3d.c
1 /*
2 * Virtio GPU Device
3 *
4 * Copyright Red Hat, Inc. 2013-2014
5 *
6 * Authors:
7 * Dave Airlie <airlied@redhat.com>
8 * Gerd Hoffmann <kraxel@redhat.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 */
13
14 #include "qemu/osdep.h"
15 #include "qemu-common.h"
16 #include "qemu/iov.h"
17 #include "trace.h"
18 #include "hw/virtio/virtio.h"
19 #include "hw/virtio/virtio-gpu.h"
20 #include "qapi/error.h"
21
22 #ifdef CONFIG_VIRGL
23
24 #include "virglrenderer.h"
25
26 static struct virgl_renderer_callbacks virtio_gpu_3d_cbs;
27
28 static void virgl_cmd_create_resource_2d(VirtIOGPU *g,
29 struct virtio_gpu_ctrl_command *cmd)
30 {
31 struct virtio_gpu_resource_create_2d c2d;
32 struct virgl_renderer_resource_create_args args;
33
34 VIRTIO_GPU_FILL_CMD(c2d);
35 trace_virtio_gpu_cmd_res_create_2d(c2d.resource_id, c2d.format,
36 c2d.width, c2d.height);
37
38 args.handle = c2d.resource_id;
39 args.target = 2;
40 args.format = c2d.format;
41 args.bind = (1 << 1);
42 args.width = c2d.width;
43 args.height = c2d.height;
44 args.depth = 1;
45 args.array_size = 1;
46 args.last_level = 0;
47 args.nr_samples = 0;
48 args.flags = VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP;
49 virgl_renderer_resource_create(&args, NULL, 0);
50 }
51
52 static void virgl_cmd_create_resource_3d(VirtIOGPU *g,
53 struct virtio_gpu_ctrl_command *cmd)
54 {
55 struct virtio_gpu_resource_create_3d c3d;
56 struct virgl_renderer_resource_create_args args;
57
58 VIRTIO_GPU_FILL_CMD(c3d);
59 trace_virtio_gpu_cmd_res_create_3d(c3d.resource_id, c3d.format,
60 c3d.width, c3d.height, c3d.depth);
61
62 args.handle = c3d.resource_id;
63 args.target = c3d.target;
64 args.format = c3d.format;
65 args.bind = c3d.bind;
66 args.width = c3d.width;
67 args.height = c3d.height;
68 args.depth = c3d.depth;
69 args.array_size = c3d.array_size;
70 args.last_level = c3d.last_level;
71 args.nr_samples = c3d.nr_samples;
72 args.flags = c3d.flags;
73 virgl_renderer_resource_create(&args, NULL, 0);
74 }
75
76 static void virgl_cmd_resource_unref(VirtIOGPU *g,
77 struct virtio_gpu_ctrl_command *cmd)
78 {
79 struct virtio_gpu_resource_unref unref;
80
81 VIRTIO_GPU_FILL_CMD(unref);
82 trace_virtio_gpu_cmd_res_unref(unref.resource_id);
83
84 virgl_renderer_resource_unref(unref.resource_id);
85 }
86
87 static void virgl_cmd_context_create(VirtIOGPU *g,
88 struct virtio_gpu_ctrl_command *cmd)
89 {
90 struct virtio_gpu_ctx_create cc;
91
92 VIRTIO_GPU_FILL_CMD(cc);
93 trace_virtio_gpu_cmd_ctx_create(cc.hdr.ctx_id,
94 cc.debug_name);
95
96 virgl_renderer_context_create(cc.hdr.ctx_id, cc.nlen,
97 cc.debug_name);
98 }
99
100 static void virgl_cmd_context_destroy(VirtIOGPU *g,
101 struct virtio_gpu_ctrl_command *cmd)
102 {
103 struct virtio_gpu_ctx_destroy cd;
104
105 VIRTIO_GPU_FILL_CMD(cd);
106 trace_virtio_gpu_cmd_ctx_destroy(cd.hdr.ctx_id);
107
108 virgl_renderer_context_destroy(cd.hdr.ctx_id);
109 }
110
111 static void virtio_gpu_rect_update(VirtIOGPU *g, int idx, int x, int y,
112 int width, int height)
113 {
114 if (!g->scanout[idx].con) {
115 return;
116 }
117
118 dpy_gl_update(g->scanout[idx].con, x, y, width, height);
119 }
120
121 static void virgl_cmd_resource_flush(VirtIOGPU *g,
122 struct virtio_gpu_ctrl_command *cmd)
123 {
124 struct virtio_gpu_resource_flush rf;
125 int i;
126
127 VIRTIO_GPU_FILL_CMD(rf);
128 trace_virtio_gpu_cmd_res_flush(rf.resource_id,
129 rf.r.width, rf.r.height, rf.r.x, rf.r.y);
130
131 for (i = 0; i < g->conf.max_outputs; i++) {
132 if (g->scanout[i].resource_id != rf.resource_id) {
133 continue;
134 }
135 virtio_gpu_rect_update(g, i, rf.r.x, rf.r.y, rf.r.width, rf.r.height);
136 }
137 }
138
139 static void virgl_cmd_set_scanout(VirtIOGPU *g,
140 struct virtio_gpu_ctrl_command *cmd)
141 {
142 struct virtio_gpu_set_scanout ss;
143 struct virgl_renderer_resource_info info;
144 int ret;
145
146 VIRTIO_GPU_FILL_CMD(ss);
147 trace_virtio_gpu_cmd_set_scanout(ss.scanout_id, ss.resource_id,
148 ss.r.width, ss.r.height, ss.r.x, ss.r.y);
149
150 if (ss.scanout_id >= g->conf.max_outputs) {
151 qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal scanout id specified %d",
152 __func__, ss.scanout_id);
153 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID;
154 return;
155 }
156 g->enable = 1;
157
158 memset(&info, 0, sizeof(info));
159
160 if (ss.resource_id && ss.r.width && ss.r.height) {
161 ret = virgl_renderer_resource_get_info(ss.resource_id, &info);
162 if (ret == -1) {
163 qemu_log_mask(LOG_GUEST_ERROR,
164 "%s: illegal resource specified %d\n",
165 __func__, ss.resource_id);
166 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
167 return;
168 }
169 qemu_console_resize(g->scanout[ss.scanout_id].con,
170 ss.r.width, ss.r.height);
171 virgl_renderer_force_ctx_0();
172 dpy_gl_scanout(g->scanout[ss.scanout_id].con, info.tex_id,
173 info.flags & 1 /* FIXME: Y_0_TOP */,
174 ss.r.x, ss.r.y, ss.r.width, ss.r.height);
175 } else {
176 if (ss.scanout_id != 0) {
177 dpy_gfx_replace_surface(g->scanout[ss.scanout_id].con, NULL);
178 }
179 dpy_gl_scanout(g->scanout[ss.scanout_id].con, 0, false,
180 0, 0, 0, 0);
181 }
182 g->scanout[ss.scanout_id].resource_id = ss.resource_id;
183 }
184
185 static void virgl_cmd_submit_3d(VirtIOGPU *g,
186 struct virtio_gpu_ctrl_command *cmd)
187 {
188 struct virtio_gpu_cmd_submit cs;
189 void *buf;
190 size_t s;
191
192 VIRTIO_GPU_FILL_CMD(cs);
193 trace_virtio_gpu_cmd_ctx_submit(cs.hdr.ctx_id, cs.size);
194
195 buf = g_malloc(cs.size);
196 s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num,
197 sizeof(cs), buf, cs.size);
198 if (s != cs.size) {
199 qemu_log_mask(LOG_GUEST_ERROR, "%s: size mismatch (%zd/%d)",
200 __func__, s, cs.size);
201 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER;
202 goto out;
203 }
204
205 if (virtio_gpu_stats_enabled(g->conf)) {
206 g->stats.req_3d++;
207 g->stats.bytes_3d += cs.size;
208 }
209
210 virgl_renderer_submit_cmd(buf, cs.hdr.ctx_id, cs.size / 4);
211
212 out:
213 g_free(buf);
214 }
215
216 static void virgl_cmd_transfer_to_host_2d(VirtIOGPU *g,
217 struct virtio_gpu_ctrl_command *cmd)
218 {
219 struct virtio_gpu_transfer_to_host_2d t2d;
220 struct virtio_gpu_box box;
221
222 VIRTIO_GPU_FILL_CMD(t2d);
223 trace_virtio_gpu_cmd_res_xfer_toh_2d(t2d.resource_id);
224
225 box.x = t2d.r.x;
226 box.y = t2d.r.y;
227 box.z = 0;
228 box.w = t2d.r.width;
229 box.h = t2d.r.height;
230 box.d = 1;
231
232 virgl_renderer_transfer_write_iov(t2d.resource_id,
233 0,
234 0,
235 0,
236 0,
237 (struct virgl_box *)&box,
238 t2d.offset, NULL, 0);
239 }
240
241 static void virgl_cmd_transfer_to_host_3d(VirtIOGPU *g,
242 struct virtio_gpu_ctrl_command *cmd)
243 {
244 struct virtio_gpu_transfer_host_3d t3d;
245
246 VIRTIO_GPU_FILL_CMD(t3d);
247 trace_virtio_gpu_cmd_res_xfer_toh_3d(t3d.resource_id);
248
249 virgl_renderer_transfer_write_iov(t3d.resource_id,
250 t3d.hdr.ctx_id,
251 t3d.level,
252 t3d.stride,
253 t3d.layer_stride,
254 (struct virgl_box *)&t3d.box,
255 t3d.offset, NULL, 0);
256 }
257
258 static void
259 virgl_cmd_transfer_from_host_3d(VirtIOGPU *g,
260 struct virtio_gpu_ctrl_command *cmd)
261 {
262 struct virtio_gpu_transfer_host_3d tf3d;
263
264 VIRTIO_GPU_FILL_CMD(tf3d);
265 trace_virtio_gpu_cmd_res_xfer_fromh_3d(tf3d.resource_id);
266
267 virgl_renderer_transfer_read_iov(tf3d.resource_id,
268 tf3d.hdr.ctx_id,
269 tf3d.level,
270 tf3d.stride,
271 tf3d.layer_stride,
272 (struct virgl_box *)&tf3d.box,
273 tf3d.offset, NULL, 0);
274 }
275
276
277 static void virgl_resource_attach_backing(VirtIOGPU *g,
278 struct virtio_gpu_ctrl_command *cmd)
279 {
280 struct virtio_gpu_resource_attach_backing att_rb;
281 struct iovec *res_iovs;
282 int ret;
283
284 VIRTIO_GPU_FILL_CMD(att_rb);
285 trace_virtio_gpu_cmd_res_back_attach(att_rb.resource_id);
286
287 ret = virtio_gpu_create_mapping_iov(&att_rb, cmd, &res_iovs);
288 if (ret != 0) {
289 cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
290 return;
291 }
292
293 virgl_renderer_resource_attach_iov(att_rb.resource_id,
294 res_iovs, att_rb.nr_entries);
295 }
296
297 static void virgl_resource_detach_backing(VirtIOGPU *g,
298 struct virtio_gpu_ctrl_command *cmd)
299 {
300 struct virtio_gpu_resource_detach_backing detach_rb;
301 struct iovec *res_iovs = NULL;
302 int num_iovs = 0;
303
304 VIRTIO_GPU_FILL_CMD(detach_rb);
305 trace_virtio_gpu_cmd_res_back_detach(detach_rb.resource_id);
306
307 virgl_renderer_resource_detach_iov(detach_rb.resource_id,
308 &res_iovs,
309 &num_iovs);
310 if (res_iovs == NULL || num_iovs == 0) {
311 return;
312 }
313 virtio_gpu_cleanup_mapping_iov(res_iovs, num_iovs);
314 }
315
316
317 static void virgl_cmd_ctx_attach_resource(VirtIOGPU *g,
318 struct virtio_gpu_ctrl_command *cmd)
319 {
320 struct virtio_gpu_ctx_resource att_res;
321
322 VIRTIO_GPU_FILL_CMD(att_res);
323 trace_virtio_gpu_cmd_ctx_res_attach(att_res.hdr.ctx_id,
324 att_res.resource_id);
325
326 virgl_renderer_ctx_attach_resource(att_res.hdr.ctx_id, att_res.resource_id);
327 }
328
329 static void virgl_cmd_ctx_detach_resource(VirtIOGPU *g,
330 struct virtio_gpu_ctrl_command *cmd)
331 {
332 struct virtio_gpu_ctx_resource det_res;
333
334 VIRTIO_GPU_FILL_CMD(det_res);
335 trace_virtio_gpu_cmd_ctx_res_detach(det_res.hdr.ctx_id,
336 det_res.resource_id);
337
338 virgl_renderer_ctx_detach_resource(det_res.hdr.ctx_id, det_res.resource_id);
339 }
340
341 static void virgl_cmd_get_capset_info(VirtIOGPU *g,
342 struct virtio_gpu_ctrl_command *cmd)
343 {
344 struct virtio_gpu_get_capset_info info;
345 struct virtio_gpu_resp_capset_info resp;
346
347 VIRTIO_GPU_FILL_CMD(info);
348
349 if (info.capset_index == 0) {
350 resp.capset_id = VIRTIO_GPU_CAPSET_VIRGL;
351 virgl_renderer_get_cap_set(resp.capset_id,
352 &resp.capset_max_version,
353 &resp.capset_max_size);
354 } else {
355 resp.capset_max_version = 0;
356 resp.capset_max_size = 0;
357 }
358 resp.hdr.type = VIRTIO_GPU_RESP_OK_CAPSET_INFO;
359 virtio_gpu_ctrl_response(g, cmd, &resp.hdr, sizeof(resp));
360 }
361
362 static void virgl_cmd_get_capset(VirtIOGPU *g,
363 struct virtio_gpu_ctrl_command *cmd)
364 {
365 struct virtio_gpu_get_capset gc;
366 struct virtio_gpu_resp_capset *resp;
367 uint32_t max_ver, max_size;
368 VIRTIO_GPU_FILL_CMD(gc);
369
370 virgl_renderer_get_cap_set(gc.capset_id, &max_ver,
371 &max_size);
372 resp = g_malloc(sizeof(*resp) + max_size);
373
374 resp->hdr.type = VIRTIO_GPU_RESP_OK_CAPSET;
375 virgl_renderer_fill_caps(gc.capset_id,
376 gc.capset_version,
377 (void *)resp->capset_data);
378 virtio_gpu_ctrl_response(g, cmd, &resp->hdr, sizeof(*resp) + max_size);
379 g_free(resp);
380 }
381
382 void virtio_gpu_virgl_process_cmd(VirtIOGPU *g,
383 struct virtio_gpu_ctrl_command *cmd)
384 {
385 VIRTIO_GPU_FILL_CMD(cmd->cmd_hdr);
386
387 cmd->waiting = g->renderer_blocked;
388 if (cmd->waiting) {
389 return;
390 }
391
392 virgl_renderer_force_ctx_0();
393 switch (cmd->cmd_hdr.type) {
394 case VIRTIO_GPU_CMD_CTX_CREATE:
395 virgl_cmd_context_create(g, cmd);
396 break;
397 case VIRTIO_GPU_CMD_CTX_DESTROY:
398 virgl_cmd_context_destroy(g, cmd);
399 break;
400 case VIRTIO_GPU_CMD_RESOURCE_CREATE_2D:
401 virgl_cmd_create_resource_2d(g, cmd);
402 break;
403 case VIRTIO_GPU_CMD_RESOURCE_CREATE_3D:
404 virgl_cmd_create_resource_3d(g, cmd);
405 break;
406 case VIRTIO_GPU_CMD_SUBMIT_3D:
407 virgl_cmd_submit_3d(g, cmd);
408 break;
409 case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D:
410 virgl_cmd_transfer_to_host_2d(g, cmd);
411 break;
412 case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D:
413 virgl_cmd_transfer_to_host_3d(g, cmd);
414 break;
415 case VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D:
416 virgl_cmd_transfer_from_host_3d(g, cmd);
417 break;
418 case VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING:
419 virgl_resource_attach_backing(g, cmd);
420 break;
421 case VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING:
422 virgl_resource_detach_backing(g, cmd);
423 break;
424 case VIRTIO_GPU_CMD_SET_SCANOUT:
425 virgl_cmd_set_scanout(g, cmd);
426 break;
427 case VIRTIO_GPU_CMD_RESOURCE_FLUSH:
428 virgl_cmd_resource_flush(g, cmd);
429 break;
430 case VIRTIO_GPU_CMD_RESOURCE_UNREF:
431 virgl_cmd_resource_unref(g, cmd);
432 break;
433 case VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE:
434 /* TODO add security */
435 virgl_cmd_ctx_attach_resource(g, cmd);
436 break;
437 case VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE:
438 /* TODO add security */
439 virgl_cmd_ctx_detach_resource(g, cmd);
440 break;
441 case VIRTIO_GPU_CMD_GET_CAPSET_INFO:
442 virgl_cmd_get_capset_info(g, cmd);
443 break;
444 case VIRTIO_GPU_CMD_GET_CAPSET:
445 virgl_cmd_get_capset(g, cmd);
446 break;
447
448 case VIRTIO_GPU_CMD_GET_DISPLAY_INFO:
449 virtio_gpu_get_display_info(g, cmd);
450 break;
451 default:
452 cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
453 break;
454 }
455
456 if (cmd->finished) {
457 return;
458 }
459 if (cmd->error) {
460 fprintf(stderr, "%s: ctrl 0x%x, error 0x%x\n", __func__,
461 cmd->cmd_hdr.type, cmd->error);
462 virtio_gpu_ctrl_response_nodata(g, cmd, cmd->error);
463 return;
464 }
465 if (!(cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_FENCE)) {
466 virtio_gpu_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA);
467 return;
468 }
469
470 trace_virtio_gpu_fence_ctrl(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type);
471 virgl_renderer_create_fence(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type);
472 }
473
474 static void virgl_write_fence(void *opaque, uint32_t fence)
475 {
476 VirtIOGPU *g = opaque;
477 struct virtio_gpu_ctrl_command *cmd, *tmp;
478
479 QTAILQ_FOREACH_SAFE(cmd, &g->fenceq, next, tmp) {
480 /*
481 * the guest can end up emitting fences out of order
482 * so we should check all fenced cmds not just the first one.
483 */
484 if (cmd->cmd_hdr.fence_id > fence) {
485 continue;
486 }
487 trace_virtio_gpu_fence_resp(cmd->cmd_hdr.fence_id);
488 virtio_gpu_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA);
489 QTAILQ_REMOVE(&g->fenceq, cmd, next);
490 g_free(cmd);
491 g->inflight--;
492 if (virtio_gpu_stats_enabled(g->conf)) {
493 fprintf(stderr, "inflight: %3d (-)\r", g->inflight);
494 }
495 }
496 }
497
498 static virgl_renderer_gl_context
499 virgl_create_context(void *opaque, int scanout_idx,
500 struct virgl_renderer_gl_ctx_param *params)
501 {
502 VirtIOGPU *g = opaque;
503 QEMUGLContext ctx;
504 QEMUGLParams qparams;
505
506 qparams.major_ver = params->major_ver;
507 qparams.minor_ver = params->minor_ver;
508
509 ctx = dpy_gl_ctx_create(g->scanout[scanout_idx].con, &qparams);
510 return (virgl_renderer_gl_context)ctx;
511 }
512
513 static void virgl_destroy_context(void *opaque, virgl_renderer_gl_context ctx)
514 {
515 VirtIOGPU *g = opaque;
516 QEMUGLContext qctx = (QEMUGLContext)ctx;
517
518 dpy_gl_ctx_destroy(g->scanout[0].con, qctx);
519 }
520
521 static int virgl_make_context_current(void *opaque, int scanout_idx,
522 virgl_renderer_gl_context ctx)
523 {
524 VirtIOGPU *g = opaque;
525 QEMUGLContext qctx = (QEMUGLContext)ctx;
526
527 return dpy_gl_ctx_make_current(g->scanout[scanout_idx].con, qctx);
528 }
529
530 static struct virgl_renderer_callbacks virtio_gpu_3d_cbs = {
531 .version = 1,
532 .write_fence = virgl_write_fence,
533 .create_gl_context = virgl_create_context,
534 .destroy_gl_context = virgl_destroy_context,
535 .make_current = virgl_make_context_current,
536 };
537
538 static void virtio_gpu_print_stats(void *opaque)
539 {
540 VirtIOGPU *g = opaque;
541
542 if (g->stats.requests) {
543 fprintf(stderr, "stats: vq req %4d, %3d -- 3D %4d (%5d)\n",
544 g->stats.requests,
545 g->stats.max_inflight,
546 g->stats.req_3d,
547 g->stats.bytes_3d);
548 g->stats.requests = 0;
549 g->stats.max_inflight = 0;
550 g->stats.req_3d = 0;
551 g->stats.bytes_3d = 0;
552 } else {
553 fprintf(stderr, "stats: idle\r");
554 }
555 timer_mod(g->print_stats, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000);
556 }
557
558 static void virtio_gpu_fence_poll(void *opaque)
559 {
560 VirtIOGPU *g = opaque;
561
562 virgl_renderer_poll();
563 virtio_gpu_process_cmdq(g);
564 if (!QTAILQ_EMPTY(&g->cmdq) || !QTAILQ_EMPTY(&g->fenceq)) {
565 timer_mod(g->fence_poll, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 10);
566 }
567 }
568
569 void virtio_gpu_virgl_fence_poll(VirtIOGPU *g)
570 {
571 virtio_gpu_fence_poll(g);
572 }
573
574 void virtio_gpu_virgl_reset(VirtIOGPU *g)
575 {
576 int i;
577
578 /* virgl_renderer_reset() ??? */
579 for (i = 0; i < g->conf.max_outputs; i++) {
580 if (i != 0) {
581 dpy_gfx_replace_surface(g->scanout[i].con, NULL);
582 }
583 dpy_gl_scanout(g->scanout[i].con, 0, false, 0, 0, 0, 0);
584 }
585 }
586
587 int virtio_gpu_virgl_init(VirtIOGPU *g)
588 {
589 int ret;
590
591 ret = virgl_renderer_init(g, 0, &virtio_gpu_3d_cbs);
592 if (ret != 0) {
593 return ret;
594 }
595
596 g->fence_poll = timer_new_ms(QEMU_CLOCK_VIRTUAL,
597 virtio_gpu_fence_poll, g);
598
599 if (virtio_gpu_stats_enabled(g->conf)) {
600 g->print_stats = timer_new_ms(QEMU_CLOCK_VIRTUAL,
601 virtio_gpu_print_stats, g);
602 timer_mod(g->print_stats, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000);
603 }
604 return 0;
605 }
606
607 #endif /* CONFIG_VIRGL */