sm501: Add missing arbitration control register
[qemu.git] / hw / display / virtio-gpu-3d.c
1 /*
2 * Virtio GPU Device
3 *
4 * Copyright Red Hat, Inc. 2013-2014
5 *
6 * Authors:
7 * Dave Airlie <airlied@redhat.com>
8 * Gerd Hoffmann <kraxel@redhat.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 */
13
14 #include "qemu/osdep.h"
15 #include "qemu-common.h"
16 #include "qemu/iov.h"
17 #include "trace.h"
18 #include "hw/virtio/virtio.h"
19 #include "hw/virtio/virtio-gpu.h"
20 #include "qapi/error.h"
21
22 #ifdef CONFIG_VIRGL
23
24 #include <virglrenderer.h>
25
26 static struct virgl_renderer_callbacks virtio_gpu_3d_cbs;
27
28 static void virgl_cmd_create_resource_2d(VirtIOGPU *g,
29 struct virtio_gpu_ctrl_command *cmd)
30 {
31 struct virtio_gpu_resource_create_2d c2d;
32 struct virgl_renderer_resource_create_args args;
33
34 VIRTIO_GPU_FILL_CMD(c2d);
35 trace_virtio_gpu_cmd_res_create_2d(c2d.resource_id, c2d.format,
36 c2d.width, c2d.height);
37
38 args.handle = c2d.resource_id;
39 args.target = 2;
40 args.format = c2d.format;
41 args.bind = (1 << 1);
42 args.width = c2d.width;
43 args.height = c2d.height;
44 args.depth = 1;
45 args.array_size = 1;
46 args.last_level = 0;
47 args.nr_samples = 0;
48 args.flags = VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP;
49 virgl_renderer_resource_create(&args, NULL, 0);
50 }
51
52 static void virgl_cmd_create_resource_3d(VirtIOGPU *g,
53 struct virtio_gpu_ctrl_command *cmd)
54 {
55 struct virtio_gpu_resource_create_3d c3d;
56 struct virgl_renderer_resource_create_args args;
57
58 VIRTIO_GPU_FILL_CMD(c3d);
59 trace_virtio_gpu_cmd_res_create_3d(c3d.resource_id, c3d.format,
60 c3d.width, c3d.height, c3d.depth);
61
62 args.handle = c3d.resource_id;
63 args.target = c3d.target;
64 args.format = c3d.format;
65 args.bind = c3d.bind;
66 args.width = c3d.width;
67 args.height = c3d.height;
68 args.depth = c3d.depth;
69 args.array_size = c3d.array_size;
70 args.last_level = c3d.last_level;
71 args.nr_samples = c3d.nr_samples;
72 args.flags = c3d.flags;
73 virgl_renderer_resource_create(&args, NULL, 0);
74 }
75
76 static void virgl_cmd_resource_unref(VirtIOGPU *g,
77 struct virtio_gpu_ctrl_command *cmd)
78 {
79 struct virtio_gpu_resource_unref unref;
80 struct iovec *res_iovs = NULL;
81 int num_iovs = 0;
82
83 VIRTIO_GPU_FILL_CMD(unref);
84 trace_virtio_gpu_cmd_res_unref(unref.resource_id);
85
86 virgl_renderer_resource_detach_iov(unref.resource_id,
87 &res_iovs,
88 &num_iovs);
89 if (res_iovs != NULL && num_iovs != 0) {
90 virtio_gpu_cleanup_mapping_iov(res_iovs, num_iovs);
91 }
92 virgl_renderer_resource_unref(unref.resource_id);
93 }
94
95 static void virgl_cmd_context_create(VirtIOGPU *g,
96 struct virtio_gpu_ctrl_command *cmd)
97 {
98 struct virtio_gpu_ctx_create cc;
99
100 VIRTIO_GPU_FILL_CMD(cc);
101 trace_virtio_gpu_cmd_ctx_create(cc.hdr.ctx_id,
102 cc.debug_name);
103
104 virgl_renderer_context_create(cc.hdr.ctx_id, cc.nlen,
105 cc.debug_name);
106 }
107
108 static void virgl_cmd_context_destroy(VirtIOGPU *g,
109 struct virtio_gpu_ctrl_command *cmd)
110 {
111 struct virtio_gpu_ctx_destroy cd;
112
113 VIRTIO_GPU_FILL_CMD(cd);
114 trace_virtio_gpu_cmd_ctx_destroy(cd.hdr.ctx_id);
115
116 virgl_renderer_context_destroy(cd.hdr.ctx_id);
117 }
118
119 static void virtio_gpu_rect_update(VirtIOGPU *g, int idx, int x, int y,
120 int width, int height)
121 {
122 if (!g->scanout[idx].con) {
123 return;
124 }
125
126 dpy_gl_update(g->scanout[idx].con, x, y, width, height);
127 }
128
129 static void virgl_cmd_resource_flush(VirtIOGPU *g,
130 struct virtio_gpu_ctrl_command *cmd)
131 {
132 struct virtio_gpu_resource_flush rf;
133 int i;
134
135 VIRTIO_GPU_FILL_CMD(rf);
136 trace_virtio_gpu_cmd_res_flush(rf.resource_id,
137 rf.r.width, rf.r.height, rf.r.x, rf.r.y);
138
139 for (i = 0; i < g->conf.max_outputs; i++) {
140 if (g->scanout[i].resource_id != rf.resource_id) {
141 continue;
142 }
143 virtio_gpu_rect_update(g, i, rf.r.x, rf.r.y, rf.r.width, rf.r.height);
144 }
145 }
146
147 static void virgl_cmd_set_scanout(VirtIOGPU *g,
148 struct virtio_gpu_ctrl_command *cmd)
149 {
150 struct virtio_gpu_set_scanout ss;
151 struct virgl_renderer_resource_info info;
152 int ret;
153
154 VIRTIO_GPU_FILL_CMD(ss);
155 trace_virtio_gpu_cmd_set_scanout(ss.scanout_id, ss.resource_id,
156 ss.r.width, ss.r.height, ss.r.x, ss.r.y);
157
158 if (ss.scanout_id >= g->conf.max_outputs) {
159 qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal scanout id specified %d",
160 __func__, ss.scanout_id);
161 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID;
162 return;
163 }
164 g->enable = 1;
165
166 memset(&info, 0, sizeof(info));
167
168 if (ss.resource_id && ss.r.width && ss.r.height) {
169 ret = virgl_renderer_resource_get_info(ss.resource_id, &info);
170 if (ret == -1) {
171 qemu_log_mask(LOG_GUEST_ERROR,
172 "%s: illegal resource specified %d\n",
173 __func__, ss.resource_id);
174 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
175 return;
176 }
177 qemu_console_resize(g->scanout[ss.scanout_id].con,
178 ss.r.width, ss.r.height);
179 virgl_renderer_force_ctx_0();
180 dpy_gl_scanout_texture(g->scanout[ss.scanout_id].con, info.tex_id,
181 info.flags & 1 /* FIXME: Y_0_TOP */,
182 info.width, info.height,
183 ss.r.x, ss.r.y, ss.r.width, ss.r.height);
184 } else {
185 if (ss.scanout_id != 0) {
186 dpy_gfx_replace_surface(g->scanout[ss.scanout_id].con, NULL);
187 }
188 dpy_gl_scanout_disable(g->scanout[ss.scanout_id].con);
189 }
190 g->scanout[ss.scanout_id].resource_id = ss.resource_id;
191 }
192
193 static void virgl_cmd_submit_3d(VirtIOGPU *g,
194 struct virtio_gpu_ctrl_command *cmd)
195 {
196 struct virtio_gpu_cmd_submit cs;
197 void *buf;
198 size_t s;
199
200 VIRTIO_GPU_FILL_CMD(cs);
201 trace_virtio_gpu_cmd_ctx_submit(cs.hdr.ctx_id, cs.size);
202
203 buf = g_malloc(cs.size);
204 s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num,
205 sizeof(cs), buf, cs.size);
206 if (s != cs.size) {
207 qemu_log_mask(LOG_GUEST_ERROR, "%s: size mismatch (%zd/%d)",
208 __func__, s, cs.size);
209 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER;
210 goto out;
211 }
212
213 if (virtio_gpu_stats_enabled(g->conf)) {
214 g->stats.req_3d++;
215 g->stats.bytes_3d += cs.size;
216 }
217
218 virgl_renderer_submit_cmd(buf, cs.hdr.ctx_id, cs.size / 4);
219
220 out:
221 g_free(buf);
222 }
223
224 static void virgl_cmd_transfer_to_host_2d(VirtIOGPU *g,
225 struct virtio_gpu_ctrl_command *cmd)
226 {
227 struct virtio_gpu_transfer_to_host_2d t2d;
228 struct virtio_gpu_box box;
229
230 VIRTIO_GPU_FILL_CMD(t2d);
231 trace_virtio_gpu_cmd_res_xfer_toh_2d(t2d.resource_id);
232
233 box.x = t2d.r.x;
234 box.y = t2d.r.y;
235 box.z = 0;
236 box.w = t2d.r.width;
237 box.h = t2d.r.height;
238 box.d = 1;
239
240 virgl_renderer_transfer_write_iov(t2d.resource_id,
241 0,
242 0,
243 0,
244 0,
245 (struct virgl_box *)&box,
246 t2d.offset, NULL, 0);
247 }
248
249 static void virgl_cmd_transfer_to_host_3d(VirtIOGPU *g,
250 struct virtio_gpu_ctrl_command *cmd)
251 {
252 struct virtio_gpu_transfer_host_3d t3d;
253
254 VIRTIO_GPU_FILL_CMD(t3d);
255 trace_virtio_gpu_cmd_res_xfer_toh_3d(t3d.resource_id);
256
257 virgl_renderer_transfer_write_iov(t3d.resource_id,
258 t3d.hdr.ctx_id,
259 t3d.level,
260 t3d.stride,
261 t3d.layer_stride,
262 (struct virgl_box *)&t3d.box,
263 t3d.offset, NULL, 0);
264 }
265
266 static void
267 virgl_cmd_transfer_from_host_3d(VirtIOGPU *g,
268 struct virtio_gpu_ctrl_command *cmd)
269 {
270 struct virtio_gpu_transfer_host_3d tf3d;
271
272 VIRTIO_GPU_FILL_CMD(tf3d);
273 trace_virtio_gpu_cmd_res_xfer_fromh_3d(tf3d.resource_id);
274
275 virgl_renderer_transfer_read_iov(tf3d.resource_id,
276 tf3d.hdr.ctx_id,
277 tf3d.level,
278 tf3d.stride,
279 tf3d.layer_stride,
280 (struct virgl_box *)&tf3d.box,
281 tf3d.offset, NULL, 0);
282 }
283
284
285 static void virgl_resource_attach_backing(VirtIOGPU *g,
286 struct virtio_gpu_ctrl_command *cmd)
287 {
288 struct virtio_gpu_resource_attach_backing att_rb;
289 struct iovec *res_iovs;
290 int ret;
291
292 VIRTIO_GPU_FILL_CMD(att_rb);
293 trace_virtio_gpu_cmd_res_back_attach(att_rb.resource_id);
294
295 ret = virtio_gpu_create_mapping_iov(&att_rb, cmd, NULL, &res_iovs);
296 if (ret != 0) {
297 cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
298 return;
299 }
300
301 ret = virgl_renderer_resource_attach_iov(att_rb.resource_id,
302 res_iovs, att_rb.nr_entries);
303
304 if (ret != 0)
305 virtio_gpu_cleanup_mapping_iov(res_iovs, att_rb.nr_entries);
306 }
307
308 static void virgl_resource_detach_backing(VirtIOGPU *g,
309 struct virtio_gpu_ctrl_command *cmd)
310 {
311 struct virtio_gpu_resource_detach_backing detach_rb;
312 struct iovec *res_iovs = NULL;
313 int num_iovs = 0;
314
315 VIRTIO_GPU_FILL_CMD(detach_rb);
316 trace_virtio_gpu_cmd_res_back_detach(detach_rb.resource_id);
317
318 virgl_renderer_resource_detach_iov(detach_rb.resource_id,
319 &res_iovs,
320 &num_iovs);
321 if (res_iovs == NULL || num_iovs == 0) {
322 return;
323 }
324 virtio_gpu_cleanup_mapping_iov(res_iovs, num_iovs);
325 }
326
327
328 static void virgl_cmd_ctx_attach_resource(VirtIOGPU *g,
329 struct virtio_gpu_ctrl_command *cmd)
330 {
331 struct virtio_gpu_ctx_resource att_res;
332
333 VIRTIO_GPU_FILL_CMD(att_res);
334 trace_virtio_gpu_cmd_ctx_res_attach(att_res.hdr.ctx_id,
335 att_res.resource_id);
336
337 virgl_renderer_ctx_attach_resource(att_res.hdr.ctx_id, att_res.resource_id);
338 }
339
340 static void virgl_cmd_ctx_detach_resource(VirtIOGPU *g,
341 struct virtio_gpu_ctrl_command *cmd)
342 {
343 struct virtio_gpu_ctx_resource det_res;
344
345 VIRTIO_GPU_FILL_CMD(det_res);
346 trace_virtio_gpu_cmd_ctx_res_detach(det_res.hdr.ctx_id,
347 det_res.resource_id);
348
349 virgl_renderer_ctx_detach_resource(det_res.hdr.ctx_id, det_res.resource_id);
350 }
351
352 static void virgl_cmd_get_capset_info(VirtIOGPU *g,
353 struct virtio_gpu_ctrl_command *cmd)
354 {
355 struct virtio_gpu_get_capset_info info;
356 struct virtio_gpu_resp_capset_info resp;
357
358 VIRTIO_GPU_FILL_CMD(info);
359
360 memset(&resp, 0, sizeof(resp));
361 if (info.capset_index == 0) {
362 resp.capset_id = VIRTIO_GPU_CAPSET_VIRGL;
363 virgl_renderer_get_cap_set(resp.capset_id,
364 &resp.capset_max_version,
365 &resp.capset_max_size);
366 } else {
367 resp.capset_max_version = 0;
368 resp.capset_max_size = 0;
369 }
370 resp.hdr.type = VIRTIO_GPU_RESP_OK_CAPSET_INFO;
371 virtio_gpu_ctrl_response(g, cmd, &resp.hdr, sizeof(resp));
372 }
373
374 static void virgl_cmd_get_capset(VirtIOGPU *g,
375 struct virtio_gpu_ctrl_command *cmd)
376 {
377 struct virtio_gpu_get_capset gc;
378 struct virtio_gpu_resp_capset *resp;
379 uint32_t max_ver, max_size;
380 VIRTIO_GPU_FILL_CMD(gc);
381
382 virgl_renderer_get_cap_set(gc.capset_id, &max_ver,
383 &max_size);
384 if (!max_size) {
385 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER;
386 return;
387 }
388
389 resp = g_malloc0(sizeof(*resp) + max_size);
390 resp->hdr.type = VIRTIO_GPU_RESP_OK_CAPSET;
391 virgl_renderer_fill_caps(gc.capset_id,
392 gc.capset_version,
393 (void *)resp->capset_data);
394 virtio_gpu_ctrl_response(g, cmd, &resp->hdr, sizeof(*resp) + max_size);
395 g_free(resp);
396 }
397
398 void virtio_gpu_virgl_process_cmd(VirtIOGPU *g,
399 struct virtio_gpu_ctrl_command *cmd)
400 {
401 VIRTIO_GPU_FILL_CMD(cmd->cmd_hdr);
402
403 cmd->waiting = g->renderer_blocked;
404 if (cmd->waiting) {
405 return;
406 }
407
408 virgl_renderer_force_ctx_0();
409 switch (cmd->cmd_hdr.type) {
410 case VIRTIO_GPU_CMD_CTX_CREATE:
411 virgl_cmd_context_create(g, cmd);
412 break;
413 case VIRTIO_GPU_CMD_CTX_DESTROY:
414 virgl_cmd_context_destroy(g, cmd);
415 break;
416 case VIRTIO_GPU_CMD_RESOURCE_CREATE_2D:
417 virgl_cmd_create_resource_2d(g, cmd);
418 break;
419 case VIRTIO_GPU_CMD_RESOURCE_CREATE_3D:
420 virgl_cmd_create_resource_3d(g, cmd);
421 break;
422 case VIRTIO_GPU_CMD_SUBMIT_3D:
423 virgl_cmd_submit_3d(g, cmd);
424 break;
425 case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D:
426 virgl_cmd_transfer_to_host_2d(g, cmd);
427 break;
428 case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D:
429 virgl_cmd_transfer_to_host_3d(g, cmd);
430 break;
431 case VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D:
432 virgl_cmd_transfer_from_host_3d(g, cmd);
433 break;
434 case VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING:
435 virgl_resource_attach_backing(g, cmd);
436 break;
437 case VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING:
438 virgl_resource_detach_backing(g, cmd);
439 break;
440 case VIRTIO_GPU_CMD_SET_SCANOUT:
441 virgl_cmd_set_scanout(g, cmd);
442 break;
443 case VIRTIO_GPU_CMD_RESOURCE_FLUSH:
444 virgl_cmd_resource_flush(g, cmd);
445 break;
446 case VIRTIO_GPU_CMD_RESOURCE_UNREF:
447 virgl_cmd_resource_unref(g, cmd);
448 break;
449 case VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE:
450 /* TODO add security */
451 virgl_cmd_ctx_attach_resource(g, cmd);
452 break;
453 case VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE:
454 /* TODO add security */
455 virgl_cmd_ctx_detach_resource(g, cmd);
456 break;
457 case VIRTIO_GPU_CMD_GET_CAPSET_INFO:
458 virgl_cmd_get_capset_info(g, cmd);
459 break;
460 case VIRTIO_GPU_CMD_GET_CAPSET:
461 virgl_cmd_get_capset(g, cmd);
462 break;
463
464 case VIRTIO_GPU_CMD_GET_DISPLAY_INFO:
465 virtio_gpu_get_display_info(g, cmd);
466 break;
467 default:
468 cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
469 break;
470 }
471
472 if (cmd->finished) {
473 return;
474 }
475 if (cmd->error) {
476 fprintf(stderr, "%s: ctrl 0x%x, error 0x%x\n", __func__,
477 cmd->cmd_hdr.type, cmd->error);
478 virtio_gpu_ctrl_response_nodata(g, cmd, cmd->error);
479 return;
480 }
481 if (!(cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_FENCE)) {
482 virtio_gpu_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA);
483 return;
484 }
485
486 trace_virtio_gpu_fence_ctrl(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type);
487 virgl_renderer_create_fence(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type);
488 }
489
490 static void virgl_write_fence(void *opaque, uint32_t fence)
491 {
492 VirtIOGPU *g = opaque;
493 struct virtio_gpu_ctrl_command *cmd, *tmp;
494
495 QTAILQ_FOREACH_SAFE(cmd, &g->fenceq, next, tmp) {
496 /*
497 * the guest can end up emitting fences out of order
498 * so we should check all fenced cmds not just the first one.
499 */
500 if (cmd->cmd_hdr.fence_id > fence) {
501 continue;
502 }
503 trace_virtio_gpu_fence_resp(cmd->cmd_hdr.fence_id);
504 virtio_gpu_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA);
505 QTAILQ_REMOVE(&g->fenceq, cmd, next);
506 g_free(cmd);
507 g->inflight--;
508 if (virtio_gpu_stats_enabled(g->conf)) {
509 fprintf(stderr, "inflight: %3d (-)\r", g->inflight);
510 }
511 }
512 }
513
514 static virgl_renderer_gl_context
515 virgl_create_context(void *opaque, int scanout_idx,
516 struct virgl_renderer_gl_ctx_param *params)
517 {
518 VirtIOGPU *g = opaque;
519 QEMUGLContext ctx;
520 QEMUGLParams qparams;
521
522 qparams.major_ver = params->major_ver;
523 qparams.minor_ver = params->minor_ver;
524
525 ctx = dpy_gl_ctx_create(g->scanout[scanout_idx].con, &qparams);
526 return (virgl_renderer_gl_context)ctx;
527 }
528
529 static void virgl_destroy_context(void *opaque, virgl_renderer_gl_context ctx)
530 {
531 VirtIOGPU *g = opaque;
532 QEMUGLContext qctx = (QEMUGLContext)ctx;
533
534 dpy_gl_ctx_destroy(g->scanout[0].con, qctx);
535 }
536
537 static int virgl_make_context_current(void *opaque, int scanout_idx,
538 virgl_renderer_gl_context ctx)
539 {
540 VirtIOGPU *g = opaque;
541 QEMUGLContext qctx = (QEMUGLContext)ctx;
542
543 return dpy_gl_ctx_make_current(g->scanout[scanout_idx].con, qctx);
544 }
545
546 static struct virgl_renderer_callbacks virtio_gpu_3d_cbs = {
547 .version = 1,
548 .write_fence = virgl_write_fence,
549 .create_gl_context = virgl_create_context,
550 .destroy_gl_context = virgl_destroy_context,
551 .make_current = virgl_make_context_current,
552 };
553
554 static void virtio_gpu_print_stats(void *opaque)
555 {
556 VirtIOGPU *g = opaque;
557
558 if (g->stats.requests) {
559 fprintf(stderr, "stats: vq req %4d, %3d -- 3D %4d (%5d)\n",
560 g->stats.requests,
561 g->stats.max_inflight,
562 g->stats.req_3d,
563 g->stats.bytes_3d);
564 g->stats.requests = 0;
565 g->stats.max_inflight = 0;
566 g->stats.req_3d = 0;
567 g->stats.bytes_3d = 0;
568 } else {
569 fprintf(stderr, "stats: idle\r");
570 }
571 timer_mod(g->print_stats, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000);
572 }
573
574 static void virtio_gpu_fence_poll(void *opaque)
575 {
576 VirtIOGPU *g = opaque;
577
578 virgl_renderer_poll();
579 virtio_gpu_process_cmdq(g);
580 if (!QTAILQ_EMPTY(&g->cmdq) || !QTAILQ_EMPTY(&g->fenceq)) {
581 timer_mod(g->fence_poll, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 10);
582 }
583 }
584
585 void virtio_gpu_virgl_fence_poll(VirtIOGPU *g)
586 {
587 virtio_gpu_fence_poll(g);
588 }
589
590 void virtio_gpu_virgl_reset(VirtIOGPU *g)
591 {
592 int i;
593
594 /* virgl_renderer_reset() ??? */
595 for (i = 0; i < g->conf.max_outputs; i++) {
596 if (i != 0) {
597 dpy_gfx_replace_surface(g->scanout[i].con, NULL);
598 }
599 dpy_gl_scanout_disable(g->scanout[i].con);
600 }
601 }
602
603 int virtio_gpu_virgl_init(VirtIOGPU *g)
604 {
605 int ret;
606
607 ret = virgl_renderer_init(g, 0, &virtio_gpu_3d_cbs);
608 if (ret != 0) {
609 return ret;
610 }
611
612 g->fence_poll = timer_new_ms(QEMU_CLOCK_VIRTUAL,
613 virtio_gpu_fence_poll, g);
614
615 if (virtio_gpu_stats_enabled(g->conf)) {
616 g->print_stats = timer_new_ms(QEMU_CLOCK_VIRTUAL,
617 virtio_gpu_print_stats, g);
618 timer_mod(g->print_stats, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000);
619 }
620 return 0;
621 }
622
623 #endif /* CONFIG_VIRGL */