sm501: Add missing arbitration control register
[qemu.git] / hw / display / xlnx_dp.c
1 /*
2 * xlnx_dp.c
3 *
4 * Copyright (C) 2015 : GreenSocs Ltd
5 * http://www.greensocs.com/ , email: info@greensocs.com
6 *
7 * Developed by :
8 * Frederic Konrad <fred.konrad@greensocs.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation, either version 2 of the License, or
13 * (at your option)any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 *
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/log.h"
27 #include "hw/display/xlnx_dp.h"
28
29 #ifndef DEBUG_DP
30 #define DEBUG_DP 0
31 #endif
32
33 #define DPRINTF(fmt, ...) do { \
34 if (DEBUG_DP) { \
35 qemu_log("xlnx_dp: " fmt , ## __VA_ARGS__); \
36 } \
37 } while (0);
38
39 /*
40 * Register offset for DP.
41 */
42 #define DP_LINK_BW_SET (0x0000 >> 2)
43 #define DP_LANE_COUNT_SET (0x0004 >> 2)
44 #define DP_ENHANCED_FRAME_EN (0x0008 >> 2)
45 #define DP_TRAINING_PATTERN_SET (0x000C >> 2)
46 #define DP_LINK_QUAL_PATTERN_SET (0x0010 >> 2)
47 #define DP_SCRAMBLING_DISABLE (0x0014 >> 2)
48 #define DP_DOWNSPREAD_CTRL (0x0018 >> 2)
49 #define DP_SOFTWARE_RESET (0x001C >> 2)
50 #define DP_TRANSMITTER_ENABLE (0x0080 >> 2)
51 #define DP_MAIN_STREAM_ENABLE (0x0084 >> 2)
52 #define DP_FORCE_SCRAMBLER_RESET (0x00C0 >> 2)
53 #define DP_VERSION_REGISTER (0x00F8 >> 2)
54 #define DP_CORE_ID (0x00FC >> 2)
55
56 #define DP_AUX_COMMAND_REGISTER (0x0100 >> 2)
57 #define AUX_ADDR_ONLY_MASK (0x1000)
58 #define AUX_COMMAND_MASK (0x0F00)
59 #define AUX_COMMAND_SHIFT (8)
60 #define AUX_COMMAND_NBYTES (0x000F)
61
62 #define DP_AUX_WRITE_FIFO (0x0104 >> 2)
63 #define DP_AUX_ADDRESS (0x0108 >> 2)
64 #define DP_AUX_CLOCK_DIVIDER (0x010C >> 2)
65 #define DP_TX_USER_FIFO_OVERFLOW (0x0110 >> 2)
66 #define DP_INTERRUPT_SIGNAL_STATE (0x0130 >> 2)
67 #define DP_AUX_REPLY_DATA (0x0134 >> 2)
68 #define DP_AUX_REPLY_CODE (0x0138 >> 2)
69 #define DP_AUX_REPLY_COUNT (0x013C >> 2)
70 #define DP_REPLY_DATA_COUNT (0x0148 >> 2)
71 #define DP_REPLY_STATUS (0x014C >> 2)
72 #define DP_HPD_DURATION (0x0150 >> 2)
73 #define DP_MAIN_STREAM_HTOTAL (0x0180 >> 2)
74 #define DP_MAIN_STREAM_VTOTAL (0x0184 >> 2)
75 #define DP_MAIN_STREAM_POLARITY (0x0188 >> 2)
76 #define DP_MAIN_STREAM_HSWIDTH (0x018C >> 2)
77 #define DP_MAIN_STREAM_VSWIDTH (0x0190 >> 2)
78 #define DP_MAIN_STREAM_HRES (0x0194 >> 2)
79 #define DP_MAIN_STREAM_VRES (0x0198 >> 2)
80 #define DP_MAIN_STREAM_HSTART (0x019C >> 2)
81 #define DP_MAIN_STREAM_VSTART (0x01A0 >> 2)
82 #define DP_MAIN_STREAM_MISC0 (0x01A4 >> 2)
83 #define DP_MAIN_STREAM_MISC1 (0x01A8 >> 2)
84 #define DP_MAIN_STREAM_M_VID (0x01AC >> 2)
85 #define DP_MSA_TRANSFER_UNIT_SIZE (0x01B0 >> 2)
86 #define DP_MAIN_STREAM_N_VID (0x01B4 >> 2)
87 #define DP_USER_DATA_COUNT_PER_LANE (0x01BC >> 2)
88 #define DP_MIN_BYTES_PER_TU (0x01C4 >> 2)
89 #define DP_FRAC_BYTES_PER_TU (0x01C8 >> 2)
90 #define DP_INIT_WAIT (0x01CC >> 2)
91 #define DP_PHY_RESET (0x0200 >> 2)
92 #define DP_PHY_VOLTAGE_DIFF_LANE_0 (0x0220 >> 2)
93 #define DP_PHY_VOLTAGE_DIFF_LANE_1 (0x0224 >> 2)
94 #define DP_TRANSMIT_PRBS7 (0x0230 >> 2)
95 #define DP_PHY_CLOCK_SELECT (0x0234 >> 2)
96 #define DP_TX_PHY_POWER_DOWN (0x0238 >> 2)
97 #define DP_PHY_PRECURSOR_LANE_0 (0x023C >> 2)
98 #define DP_PHY_PRECURSOR_LANE_1 (0x0240 >> 2)
99 #define DP_PHY_POSTCURSOR_LANE_0 (0x024C >> 2)
100 #define DP_PHY_POSTCURSOR_LANE_1 (0x0250 >> 2)
101 #define DP_PHY_STATUS (0x0280 >> 2)
102
103 #define DP_TX_AUDIO_CONTROL (0x0300 >> 2)
104 #define DP_TX_AUD_CTRL (1)
105
106 #define DP_TX_AUDIO_CHANNELS (0x0304 >> 2)
107 #define DP_TX_AUDIO_INFO_DATA(n) ((0x0308 + 4 * n) >> 2)
108 #define DP_TX_M_AUD (0x0328 >> 2)
109 #define DP_TX_N_AUD (0x032C >> 2)
110 #define DP_TX_AUDIO_EXT_DATA(n) ((0x0330 + 4 * n) >> 2)
111 #define DP_INT_STATUS (0x03A0 >> 2)
112 #define DP_INT_MASK (0x03A4 >> 2)
113 #define DP_INT_EN (0x03A8 >> 2)
114 #define DP_INT_DS (0x03AC >> 2)
115
116 /*
117 * Registers offset for Audio Video Buffer configuration.
118 */
119 #define V_BLEND_OFFSET (0xA000)
120 #define V_BLEND_BG_CLR_0 (0x0000 >> 2)
121 #define V_BLEND_BG_CLR_1 (0x0004 >> 2)
122 #define V_BLEND_BG_CLR_2 (0x0008 >> 2)
123 #define V_BLEND_SET_GLOBAL_ALPHA_REG (0x000C >> 2)
124 #define V_BLEND_OUTPUT_VID_FORMAT (0x0014 >> 2)
125 #define V_BLEND_LAYER0_CONTROL (0x0018 >> 2)
126 #define V_BLEND_LAYER1_CONTROL (0x001C >> 2)
127
128 #define V_BLEND_RGB2YCBCR_COEFF(n) ((0x0020 + 4 * n) >> 2)
129 #define V_BLEND_IN1CSC_COEFF(n) ((0x0044 + 4 * n) >> 2)
130
131 #define V_BLEND_LUMA_IN1CSC_OFFSET (0x0068 >> 2)
132 #define V_BLEND_CR_IN1CSC_OFFSET (0x006C >> 2)
133 #define V_BLEND_CB_IN1CSC_OFFSET (0x0070 >> 2)
134 #define V_BLEND_LUMA_OUTCSC_OFFSET (0x0074 >> 2)
135 #define V_BLEND_CR_OUTCSC_OFFSET (0x0078 >> 2)
136 #define V_BLEND_CB_OUTCSC_OFFSET (0x007C >> 2)
137
138 #define V_BLEND_IN2CSC_COEFF(n) ((0x0080 + 4 * n) >> 2)
139
140 #define V_BLEND_LUMA_IN2CSC_OFFSET (0x00A4 >> 2)
141 #define V_BLEND_CR_IN2CSC_OFFSET (0x00A8 >> 2)
142 #define V_BLEND_CB_IN2CSC_OFFSET (0x00AC >> 2)
143 #define V_BLEND_CHROMA_KEY_ENABLE (0x01D0 >> 2)
144 #define V_BLEND_CHROMA_KEY_COMP1 (0x01D4 >> 2)
145 #define V_BLEND_CHROMA_KEY_COMP2 (0x01D8 >> 2)
146 #define V_BLEND_CHROMA_KEY_COMP3 (0x01DC >> 2)
147
148 /*
149 * Registers offset for Audio Video Buffer configuration.
150 */
151 #define AV_BUF_MANAGER_OFFSET (0xB000)
152 #define AV_BUF_FORMAT (0x0000 >> 2)
153 #define AV_BUF_NON_LIVE_LATENCY (0x0008 >> 2)
154 #define AV_CHBUF0 (0x0010 >> 2)
155 #define AV_CHBUF1 (0x0014 >> 2)
156 #define AV_CHBUF2 (0x0018 >> 2)
157 #define AV_CHBUF3 (0x001C >> 2)
158 #define AV_CHBUF4 (0x0020 >> 2)
159 #define AV_CHBUF5 (0x0024 >> 2)
160 #define AV_BUF_STC_CONTROL (0x002C >> 2)
161 #define AV_BUF_STC_INIT_VALUE0 (0x0030 >> 2)
162 #define AV_BUF_STC_INIT_VALUE1 (0x0034 >> 2)
163 #define AV_BUF_STC_ADJ (0x0038 >> 2)
164 #define AV_BUF_STC_VIDEO_VSYNC_TS_REG0 (0x003C >> 2)
165 #define AV_BUF_STC_VIDEO_VSYNC_TS_REG1 (0x0040 >> 2)
166 #define AV_BUF_STC_EXT_VSYNC_TS_REG0 (0x0044 >> 2)
167 #define AV_BUF_STC_EXT_VSYNC_TS_REG1 (0x0048 >> 2)
168 #define AV_BUF_STC_CUSTOM_EVENT_TS_REG0 (0x004C >> 2)
169 #define AV_BUF_STC_CUSTOM_EVENT_TS_REG1 (0x0050 >> 2)
170 #define AV_BUF_STC_CUSTOM_EVENT2_TS_REG0 (0x0054 >> 2)
171 #define AV_BUF_STC_CUSTOM_EVENT2_TS_REG1 (0x0058 >> 2)
172 #define AV_BUF_STC_SNAPSHOT0 (0x0060 >> 2)
173 #define AV_BUF_STC_SNAPSHOT1 (0x0064 >> 2)
174 #define AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT (0x0070 >> 2)
175 #define AV_BUF_HCOUNT_VCOUNT_INT0 (0x0074 >> 2)
176 #define AV_BUF_HCOUNT_VCOUNT_INT1 (0x0078 >> 2)
177 #define AV_BUF_DITHER_CONFIG (0x007C >> 2)
178 #define AV_BUF_DITHER_CONFIG_MAX (0x008C >> 2)
179 #define AV_BUF_DITHER_CONFIG_MIN (0x0090 >> 2)
180 #define AV_BUF_PATTERN_GEN_SELECT (0x0100 >> 2)
181 #define AV_BUF_AUD_VID_CLK_SOURCE (0x0120 >> 2)
182 #define AV_BUF_SRST_REG (0x0124 >> 2)
183 #define AV_BUF_AUDIO_RDY_INTERVAL (0x0128 >> 2)
184 #define AV_BUF_AUDIO_CH_CONFIG (0x012C >> 2)
185
186 #define AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(n)((0x0200 + 4 * n) >> 2)
187
188 #define AV_BUF_VIDEO_COMP_SCALE_FACTOR(n) ((0x020C + 4 * n) >> 2)
189
190 #define AV_BUF_LIVE_VIDEO_COMP_SF(n) ((0x0218 + 4 * n) >> 2)
191
192 #define AV_BUF_LIVE_VID_CONFIG (0x0224 >> 2)
193
194 #define AV_BUF_LIVE_GFX_COMP_SF(n) ((0x0228 + 4 * n) >> 2)
195
196 #define AV_BUF_LIVE_GFX_CONFIG (0x0234 >> 2)
197
198 #define AUDIO_MIXER_REGISTER_OFFSET (0xC000)
199 #define AUDIO_MIXER_VOLUME_CONTROL (0x0000 >> 2)
200 #define AUDIO_MIXER_META_DATA (0x0004 >> 2)
201 #define AUD_CH_STATUS_REG(n) ((0x0008 + 4 * n) >> 2)
202 #define AUD_CH_A_DATA_REG(n) ((0x0020 + 4 * n) >> 2)
203 #define AUD_CH_B_DATA_REG(n) ((0x0038 + 4 * n) >> 2)
204
205 #define DP_AUDIO_DMA_CHANNEL(n) (4 + n)
206 #define DP_GRAPHIC_DMA_CHANNEL (3)
207 #define DP_VIDEO_DMA_CHANNEL (0)
208
209 enum DPGraphicFmt {
210 DP_GRAPHIC_RGBA8888 = 0 << 8,
211 DP_GRAPHIC_ABGR8888 = 1 << 8,
212 DP_GRAPHIC_RGB888 = 2 << 8,
213 DP_GRAPHIC_BGR888 = 3 << 8,
214 DP_GRAPHIC_RGBA5551 = 4 << 8,
215 DP_GRAPHIC_RGBA4444 = 5 << 8,
216 DP_GRAPHIC_RGB565 = 6 << 8,
217 DP_GRAPHIC_8BPP = 7 << 8,
218 DP_GRAPHIC_4BPP = 8 << 8,
219 DP_GRAPHIC_2BPP = 9 << 8,
220 DP_GRAPHIC_1BPP = 10 << 8,
221 DP_GRAPHIC_MASK = 0xF << 8
222 };
223
224 enum DPVideoFmt {
225 DP_NL_VID_CB_Y0_CR_Y1 = 0,
226 DP_NL_VID_CR_Y0_CB_Y1 = 1,
227 DP_NL_VID_Y0_CR_Y1_CB = 2,
228 DP_NL_VID_Y0_CB_Y1_CR = 3,
229 DP_NL_VID_YV16 = 4,
230 DP_NL_VID_YV24 = 5,
231 DP_NL_VID_YV16CL = 6,
232 DP_NL_VID_MONO = 7,
233 DP_NL_VID_YV16CL2 = 8,
234 DP_NL_VID_YUV444 = 9,
235 DP_NL_VID_RGB888 = 10,
236 DP_NL_VID_RGBA8880 = 11,
237 DP_NL_VID_RGB888_10BPC = 12,
238 DP_NL_VID_YUV444_10BPC = 13,
239 DP_NL_VID_YV16CL2_10BPC = 14,
240 DP_NL_VID_YV16CL_10BPC = 15,
241 DP_NL_VID_YV16_10BPC = 16,
242 DP_NL_VID_YV24_10BPC = 17,
243 DP_NL_VID_Y_ONLY_10BPC = 18,
244 DP_NL_VID_YV16_420 = 19,
245 DP_NL_VID_YV16CL_420 = 20,
246 DP_NL_VID_YV16CL2_420 = 21,
247 DP_NL_VID_YV16_420_10BPC = 22,
248 DP_NL_VID_YV16CL_420_10BPC = 23,
249 DP_NL_VID_YV16CL2_420_10BPC = 24,
250 DP_NL_VID_FMT_MASK = 0x1F
251 };
252
253 typedef enum DPGraphicFmt DPGraphicFmt;
254 typedef enum DPVideoFmt DPVideoFmt;
255
256 static const VMStateDescription vmstate_dp = {
257 .name = TYPE_XLNX_DP,
258 .version_id = 1,
259 .fields = (VMStateField[]){
260 VMSTATE_UINT32_ARRAY(core_registers, XlnxDPState,
261 DP_CORE_REG_ARRAY_SIZE),
262 VMSTATE_UINT32_ARRAY(avbufm_registers, XlnxDPState,
263 DP_AVBUF_REG_ARRAY_SIZE),
264 VMSTATE_UINT32_ARRAY(vblend_registers, XlnxDPState,
265 DP_VBLEND_REG_ARRAY_SIZE),
266 VMSTATE_UINT32_ARRAY(audio_registers, XlnxDPState,
267 DP_AUDIO_REG_ARRAY_SIZE),
268 VMSTATE_END_OF_LIST()
269 }
270 };
271
272 static void xlnx_dp_update_irq(XlnxDPState *s);
273
274 static uint64_t xlnx_dp_audio_read(void *opaque, hwaddr offset, unsigned size)
275 {
276 XlnxDPState *s = XLNX_DP(opaque);
277
278 offset = offset >> 2;
279 return s->audio_registers[offset];
280 }
281
282 static void xlnx_dp_audio_write(void *opaque, hwaddr offset, uint64_t value,
283 unsigned size)
284 {
285 XlnxDPState *s = XLNX_DP(opaque);
286
287 offset = offset >> 2;
288
289 switch (offset) {
290 case AUDIO_MIXER_META_DATA:
291 s->audio_registers[offset] = value & 0x00000001;
292 break;
293 default:
294 s->audio_registers[offset] = value;
295 break;
296 }
297 }
298
299 static const MemoryRegionOps audio_ops = {
300 .read = xlnx_dp_audio_read,
301 .write = xlnx_dp_audio_write,
302 .endianness = DEVICE_NATIVE_ENDIAN,
303 };
304
305 static inline uint32_t xlnx_dp_audio_get_volume(XlnxDPState *s,
306 uint8_t channel)
307 {
308 switch (channel) {
309 case 0:
310 return extract32(s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL], 0, 16);
311 case 1:
312 return extract32(s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL], 16,
313 16);
314 default:
315 return 0;
316 }
317 }
318
319 static inline void xlnx_dp_audio_activate(XlnxDPState *s)
320 {
321 bool activated = ((s->core_registers[DP_TX_AUDIO_CONTROL]
322 & DP_TX_AUD_CTRL) != 0);
323 AUD_set_active_out(s->amixer_output_stream, activated);
324 xlnx_dpdma_set_host_data_location(s->dpdma, DP_AUDIO_DMA_CHANNEL(0),
325 &s->audio_buffer_0);
326 xlnx_dpdma_set_host_data_location(s->dpdma, DP_AUDIO_DMA_CHANNEL(1),
327 &s->audio_buffer_1);
328 }
329
330 static inline void xlnx_dp_audio_mix_buffer(XlnxDPState *s)
331 {
332 /*
333 * Audio packets are signed and have this shape:
334 * | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 |
335 * | R3 | L3 | R2 | L2 | R1 | L1 | R0 | L0 |
336 *
337 * Output audio is 16bits saturated.
338 */
339 int i;
340
341 if ((s->audio_data_available[0]) && (xlnx_dp_audio_get_volume(s, 0))) {
342 for (i = 0; i < s->audio_data_available[0] / 2; i++) {
343 s->temp_buffer[i] = (int64_t)(s->audio_buffer_0[i])
344 * xlnx_dp_audio_get_volume(s, 0) / 8192;
345 }
346 s->byte_left = s->audio_data_available[0];
347 } else {
348 memset(s->temp_buffer, 0, s->audio_data_available[1] / 2);
349 }
350
351 if ((s->audio_data_available[1]) && (xlnx_dp_audio_get_volume(s, 1))) {
352 if ((s->audio_data_available[0] == 0)
353 || (s->audio_data_available[1] == s->audio_data_available[0])) {
354 for (i = 0; i < s->audio_data_available[1] / 2; i++) {
355 s->temp_buffer[i] += (int64_t)(s->audio_buffer_1[i])
356 * xlnx_dp_audio_get_volume(s, 1) / 8192;
357 }
358 s->byte_left = s->audio_data_available[1];
359 }
360 }
361
362 for (i = 0; i < s->byte_left / 2; i++) {
363 s->out_buffer[i] = MAX(-32767, MIN(s->temp_buffer[i], 32767));
364 }
365
366 s->data_ptr = 0;
367 }
368
369 static void xlnx_dp_audio_callback(void *opaque, int avail)
370 {
371 /*
372 * Get some data from the DPDMA and compute these datas.
373 * Then wait for QEMU's audio subsystem to call this callback.
374 */
375 XlnxDPState *s = XLNX_DP(opaque);
376 size_t written = 0;
377
378 /* If there are already some data don't get more data. */
379 if (s->byte_left == 0) {
380 s->audio_data_available[0] = xlnx_dpdma_start_operation(s->dpdma, 4,
381 true);
382 s->audio_data_available[1] = xlnx_dpdma_start_operation(s->dpdma, 5,
383 true);
384 xlnx_dp_audio_mix_buffer(s);
385 }
386
387 /* Send the buffer through the audio. */
388 if (s->byte_left <= MAX_QEMU_BUFFER_SIZE) {
389 if (s->byte_left != 0) {
390 written = AUD_write(s->amixer_output_stream,
391 &s->out_buffer[s->data_ptr], s->byte_left);
392 } else {
393 /*
394 * There is nothing to play.. We don't have any data! Fill the
395 * buffer with zero's and send it.
396 */
397 written = 0;
398 memset(s->out_buffer, 0, 1024);
399 AUD_write(s->amixer_output_stream, s->out_buffer, 1024);
400 }
401 } else {
402 written = AUD_write(s->amixer_output_stream,
403 &s->out_buffer[s->data_ptr], MAX_QEMU_BUFFER_SIZE);
404 }
405 s->byte_left -= written;
406 s->data_ptr += written;
407 }
408
409 /*
410 * AUX channel related function.
411 */
412 static void xlnx_dp_aux_clear_rx_fifo(XlnxDPState *s)
413 {
414 fifo8_reset(&s->rx_fifo);
415 }
416
417 static void xlnx_dp_aux_push_rx_fifo(XlnxDPState *s, uint8_t *buf, size_t len)
418 {
419 DPRINTF("Push %u data in rx_fifo\n", (unsigned)len);
420 fifo8_push_all(&s->rx_fifo, buf, len);
421 }
422
423 static uint8_t xlnx_dp_aux_pop_rx_fifo(XlnxDPState *s)
424 {
425 uint8_t ret;
426
427 if (fifo8_is_empty(&s->rx_fifo)) {
428 DPRINTF("rx_fifo underflow..\n");
429 abort();
430 }
431 ret = fifo8_pop(&s->rx_fifo);
432 DPRINTF("pop 0x%" PRIX8 " from rx_fifo.\n", ret);
433 return ret;
434 }
435
436 static void xlnx_dp_aux_clear_tx_fifo(XlnxDPState *s)
437 {
438 fifo8_reset(&s->tx_fifo);
439 }
440
441 static void xlnx_dp_aux_push_tx_fifo(XlnxDPState *s, uint8_t *buf, size_t len)
442 {
443 DPRINTF("Push %u data in tx_fifo\n", (unsigned)len);
444 fifo8_push_all(&s->tx_fifo, buf, len);
445 }
446
447 static uint8_t xlnx_dp_aux_pop_tx_fifo(XlnxDPState *s)
448 {
449 uint8_t ret;
450
451 if (fifo8_is_empty(&s->tx_fifo)) {
452 DPRINTF("tx_fifo underflow..\n");
453 abort();
454 }
455 ret = fifo8_pop(&s->tx_fifo);
456 DPRINTF("pop 0x%2.2X from tx_fifo.\n", ret);
457 return ret;
458 }
459
460 static uint32_t xlnx_dp_aux_get_address(XlnxDPState *s)
461 {
462 return s->core_registers[DP_AUX_ADDRESS];
463 }
464
465 /*
466 * Get command from the register.
467 */
468 static void xlnx_dp_aux_set_command(XlnxDPState *s, uint32_t value)
469 {
470 bool address_only = (value & AUX_ADDR_ONLY_MASK) != 0;
471 AUXCommand cmd = (value & AUX_COMMAND_MASK) >> AUX_COMMAND_SHIFT;
472 uint8_t nbytes = (value & AUX_COMMAND_NBYTES) + 1;
473 uint8_t buf[16];
474 int i;
475
476 /*
477 * When an address_only command is executed nothing happen to the fifo, so
478 * just make nbytes = 0.
479 */
480 if (address_only) {
481 nbytes = 0;
482 }
483
484 switch (cmd) {
485 case READ_AUX:
486 case READ_I2C:
487 case READ_I2C_MOT:
488 s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd,
489 xlnx_dp_aux_get_address(s),
490 nbytes, buf);
491 s->core_registers[DP_REPLY_DATA_COUNT] = nbytes;
492
493 if (s->core_registers[DP_AUX_REPLY_CODE] == AUX_I2C_ACK) {
494 xlnx_dp_aux_push_rx_fifo(s, buf, nbytes);
495 }
496 break;
497 case WRITE_AUX:
498 case WRITE_I2C:
499 case WRITE_I2C_MOT:
500 for (i = 0; i < nbytes; i++) {
501 buf[i] = xlnx_dp_aux_pop_tx_fifo(s);
502 }
503 s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd,
504 xlnx_dp_aux_get_address(s),
505 nbytes, buf);
506 xlnx_dp_aux_clear_tx_fifo(s);
507 break;
508 case WRITE_I2C_STATUS:
509 qemu_log_mask(LOG_UNIMP, "xlnx_dp: Write i2c status not implemented\n");
510 break;
511 default:
512 abort();
513 }
514
515 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] |= 0x04;
516 }
517
518 static void xlnx_dp_set_dpdma(Object *obj, const char *name, Object *val,
519 Error **errp)
520 {
521 XlnxDPState *s = XLNX_DP(obj);
522 if (s->console) {
523 DisplaySurface *surface = qemu_console_surface(s->console);
524 XlnxDPDMAState *dma = XLNX_DPDMA(val);
525 xlnx_dpdma_set_host_data_location(dma, DP_GRAPHIC_DMA_CHANNEL,
526 surface_data(surface));
527 }
528 }
529
530 static inline uint8_t xlnx_dp_global_alpha_value(XlnxDPState *s)
531 {
532 return (s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x1FE) >> 1;
533 }
534
535 static inline bool xlnx_dp_global_alpha_enabled(XlnxDPState *s)
536 {
537 /*
538 * If the alpha is totally opaque (255) we consider the alpha is disabled to
539 * reduce CPU consumption.
540 */
541 return ((xlnx_dp_global_alpha_value(s) != 0xFF) &&
542 ((s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x01) != 0));
543 }
544
545 static void xlnx_dp_recreate_surface(XlnxDPState *s)
546 {
547 /*
548 * Two possibilities, if blending is enabled the console displays
549 * bout_plane, if not g_plane is displayed.
550 */
551 uint16_t width = s->core_registers[DP_MAIN_STREAM_HRES];
552 uint16_t height = s->core_registers[DP_MAIN_STREAM_VRES];
553 DisplaySurface *current_console_surface = qemu_console_surface(s->console);
554
555 if ((width != 0) && (height != 0)) {
556 /*
557 * As dpy_gfx_replace_surface calls qemu_free_displaysurface on the
558 * surface we need to be careful and don't free the surface associated
559 * to the console or double free will happen.
560 */
561 if (s->bout_plane.surface != current_console_surface) {
562 qemu_free_displaysurface(s->bout_plane.surface);
563 }
564 if (s->v_plane.surface != current_console_surface) {
565 qemu_free_displaysurface(s->v_plane.surface);
566 }
567 if (s->g_plane.surface != current_console_surface) {
568 qemu_free_displaysurface(s->g_plane.surface);
569 }
570
571 s->g_plane.surface
572 = qemu_create_displaysurface_from(width, height,
573 s->g_plane.format, 0, NULL);
574 s->v_plane.surface
575 = qemu_create_displaysurface_from(width, height,
576 s->v_plane.format, 0, NULL);
577 if (xlnx_dp_global_alpha_enabled(s)) {
578 s->bout_plane.surface =
579 qemu_create_displaysurface_from(width,
580 height,
581 s->g_plane.format,
582 0, NULL);
583 dpy_gfx_replace_surface(s->console, s->bout_plane.surface);
584 } else {
585 s->bout_plane.surface = NULL;
586 dpy_gfx_replace_surface(s->console, s->g_plane.surface);
587 }
588
589 xlnx_dpdma_set_host_data_location(s->dpdma, DP_GRAPHIC_DMA_CHANNEL,
590 surface_data(s->g_plane.surface));
591 xlnx_dpdma_set_host_data_location(s->dpdma, DP_VIDEO_DMA_CHANNEL,
592 surface_data(s->v_plane.surface));
593 }
594 }
595
596 /*
597 * Change the graphic format of the surface.
598 */
599 static void xlnx_dp_change_graphic_fmt(XlnxDPState *s)
600 {
601 switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK) {
602 case DP_GRAPHIC_RGBA8888:
603 s->g_plane.format = PIXMAN_r8g8b8a8;
604 break;
605 case DP_GRAPHIC_ABGR8888:
606 s->g_plane.format = PIXMAN_a8b8g8r8;
607 break;
608 case DP_GRAPHIC_RGB565:
609 s->g_plane.format = PIXMAN_r5g6b5;
610 break;
611 case DP_GRAPHIC_RGB888:
612 s->g_plane.format = PIXMAN_r8g8b8;
613 break;
614 case DP_GRAPHIC_BGR888:
615 s->g_plane.format = PIXMAN_b8g8r8;
616 break;
617 default:
618 DPRINTF("error: unsupported graphic format %u.\n",
619 s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK);
620 abort();
621 }
622
623 switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK) {
624 case 0:
625 s->v_plane.format = PIXMAN_x8b8g8r8;
626 break;
627 case DP_NL_VID_RGBA8880:
628 s->v_plane.format = PIXMAN_x8b8g8r8;
629 break;
630 default:
631 DPRINTF("error: unsupported video format %u.\n",
632 s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK);
633 abort();
634 }
635
636 xlnx_dp_recreate_surface(s);
637 }
638
639 static void xlnx_dp_update_irq(XlnxDPState *s)
640 {
641 uint32_t flags;
642
643 flags = s->core_registers[DP_INT_STATUS] & ~s->core_registers[DP_INT_MASK];
644 DPRINTF("update IRQ value = %" PRIx32 "\n", flags);
645 qemu_set_irq(s->irq, flags != 0);
646 }
647
648 static uint64_t xlnx_dp_read(void *opaque, hwaddr offset, unsigned size)
649 {
650 XlnxDPState *s = XLNX_DP(opaque);
651 uint64_t ret = 0;
652
653 offset = offset >> 2;
654
655 switch (offset) {
656 case DP_TX_USER_FIFO_OVERFLOW:
657 /* This register is cleared after a read */
658 ret = s->core_registers[DP_TX_USER_FIFO_OVERFLOW];
659 s->core_registers[DP_TX_USER_FIFO_OVERFLOW] = 0;
660 break;
661 case DP_AUX_REPLY_DATA:
662 ret = xlnx_dp_aux_pop_rx_fifo(s);
663 break;
664 case DP_INTERRUPT_SIGNAL_STATE:
665 /*
666 * XXX: Not sure it is the right thing to do actually.
667 * The register is not written by the device driver so it's stuck
668 * to 0x04.
669 */
670 ret = s->core_registers[DP_INTERRUPT_SIGNAL_STATE];
671 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] &= ~0x04;
672 break;
673 case DP_AUX_WRITE_FIFO:
674 case DP_TX_AUDIO_INFO_DATA(0):
675 case DP_TX_AUDIO_INFO_DATA(1):
676 case DP_TX_AUDIO_INFO_DATA(2):
677 case DP_TX_AUDIO_INFO_DATA(3):
678 case DP_TX_AUDIO_INFO_DATA(4):
679 case DP_TX_AUDIO_INFO_DATA(5):
680 case DP_TX_AUDIO_INFO_DATA(6):
681 case DP_TX_AUDIO_INFO_DATA(7):
682 case DP_TX_AUDIO_EXT_DATA(0):
683 case DP_TX_AUDIO_EXT_DATA(1):
684 case DP_TX_AUDIO_EXT_DATA(2):
685 case DP_TX_AUDIO_EXT_DATA(3):
686 case DP_TX_AUDIO_EXT_DATA(4):
687 case DP_TX_AUDIO_EXT_DATA(5):
688 case DP_TX_AUDIO_EXT_DATA(6):
689 case DP_TX_AUDIO_EXT_DATA(7):
690 case DP_TX_AUDIO_EXT_DATA(8):
691 /* write only registers */
692 ret = 0;
693 break;
694 default:
695 assert(offset <= (0x3AC >> 2));
696 ret = s->core_registers[offset];
697 break;
698 }
699
700 DPRINTF("core read @%" PRIx64 " = 0x%8.8" PRIX64 "\n", offset << 2, ret);
701 return ret;
702 }
703
704 static void xlnx_dp_write(void *opaque, hwaddr offset, uint64_t value,
705 unsigned size)
706 {
707 XlnxDPState *s = XLNX_DP(opaque);
708
709 DPRINTF("core write @%" PRIx64 " = 0x%8.8" PRIX64 "\n", offset, value);
710
711 offset = offset >> 2;
712
713 switch (offset) {
714 /*
715 * Only special write case are handled.
716 */
717 case DP_LINK_BW_SET:
718 s->core_registers[offset] = value & 0x000000FF;
719 break;
720 case DP_LANE_COUNT_SET:
721 case DP_MAIN_STREAM_MISC0:
722 s->core_registers[offset] = value & 0x0000000F;
723 break;
724 case DP_TRAINING_PATTERN_SET:
725 case DP_LINK_QUAL_PATTERN_SET:
726 case DP_MAIN_STREAM_POLARITY:
727 case DP_PHY_VOLTAGE_DIFF_LANE_0:
728 case DP_PHY_VOLTAGE_DIFF_LANE_1:
729 s->core_registers[offset] = value & 0x00000003;
730 break;
731 case DP_ENHANCED_FRAME_EN:
732 case DP_SCRAMBLING_DISABLE:
733 case DP_DOWNSPREAD_CTRL:
734 case DP_MAIN_STREAM_ENABLE:
735 case DP_TRANSMIT_PRBS7:
736 s->core_registers[offset] = value & 0x00000001;
737 break;
738 case DP_PHY_CLOCK_SELECT:
739 s->core_registers[offset] = value & 0x00000007;
740 break;
741 case DP_SOFTWARE_RESET:
742 /*
743 * No need to update this bit as it's read '0'.
744 */
745 /*
746 * TODO: reset IP.
747 */
748 break;
749 case DP_TRANSMITTER_ENABLE:
750 s->core_registers[offset] = value & 0x01;
751 break;
752 case DP_FORCE_SCRAMBLER_RESET:
753 /*
754 * No need to update this bit as it's read '0'.
755 */
756 /*
757 * TODO: force a scrambler reset??
758 */
759 break;
760 case DP_AUX_COMMAND_REGISTER:
761 s->core_registers[offset] = value & 0x00001F0F;
762 xlnx_dp_aux_set_command(s, s->core_registers[offset]);
763 break;
764 case DP_MAIN_STREAM_HTOTAL:
765 case DP_MAIN_STREAM_VTOTAL:
766 case DP_MAIN_STREAM_HSTART:
767 case DP_MAIN_STREAM_VSTART:
768 s->core_registers[offset] = value & 0x0000FFFF;
769 break;
770 case DP_MAIN_STREAM_HRES:
771 case DP_MAIN_STREAM_VRES:
772 s->core_registers[offset] = value & 0x0000FFFF;
773 xlnx_dp_recreate_surface(s);
774 break;
775 case DP_MAIN_STREAM_HSWIDTH:
776 case DP_MAIN_STREAM_VSWIDTH:
777 s->core_registers[offset] = value & 0x00007FFF;
778 break;
779 case DP_MAIN_STREAM_MISC1:
780 s->core_registers[offset] = value & 0x00000086;
781 break;
782 case DP_MAIN_STREAM_M_VID:
783 case DP_MAIN_STREAM_N_VID:
784 s->core_registers[offset] = value & 0x00FFFFFF;
785 break;
786 case DP_MSA_TRANSFER_UNIT_SIZE:
787 case DP_MIN_BYTES_PER_TU:
788 case DP_INIT_WAIT:
789 s->core_registers[offset] = value & 0x00000007;
790 break;
791 case DP_USER_DATA_COUNT_PER_LANE:
792 s->core_registers[offset] = value & 0x0003FFFF;
793 break;
794 case DP_FRAC_BYTES_PER_TU:
795 s->core_registers[offset] = value & 0x000003FF;
796 break;
797 case DP_PHY_RESET:
798 s->core_registers[offset] = value & 0x00010003;
799 /*
800 * TODO: Reset something?
801 */
802 break;
803 case DP_TX_PHY_POWER_DOWN:
804 s->core_registers[offset] = value & 0x0000000F;
805 /*
806 * TODO: Power down things?
807 */
808 break;
809 case DP_AUX_WRITE_FIFO: {
810 uint8_t c = value;
811 xlnx_dp_aux_push_tx_fifo(s, &c, 1);
812 break;
813 }
814 case DP_AUX_CLOCK_DIVIDER:
815 break;
816 case DP_AUX_REPLY_COUNT:
817 /*
818 * Writing to this register clear the counter.
819 */
820 s->core_registers[offset] = 0x00000000;
821 break;
822 case DP_AUX_ADDRESS:
823 s->core_registers[offset] = value & 0x000FFFFF;
824 break;
825 case DP_VERSION_REGISTER:
826 case DP_CORE_ID:
827 case DP_TX_USER_FIFO_OVERFLOW:
828 case DP_AUX_REPLY_DATA:
829 case DP_AUX_REPLY_CODE:
830 case DP_REPLY_DATA_COUNT:
831 case DP_REPLY_STATUS:
832 case DP_HPD_DURATION:
833 /*
834 * Write to read only location..
835 */
836 break;
837 case DP_TX_AUDIO_CONTROL:
838 s->core_registers[offset] = value & 0x00000001;
839 xlnx_dp_audio_activate(s);
840 break;
841 case DP_TX_AUDIO_CHANNELS:
842 s->core_registers[offset] = value & 0x00000007;
843 xlnx_dp_audio_activate(s);
844 break;
845 case DP_INT_STATUS:
846 s->core_registers[DP_INT_STATUS] &= ~value;
847 xlnx_dp_update_irq(s);
848 break;
849 case DP_INT_EN:
850 s->core_registers[DP_INT_MASK] &= ~value;
851 xlnx_dp_update_irq(s);
852 break;
853 case DP_INT_DS:
854 s->core_registers[DP_INT_MASK] |= ~value;
855 xlnx_dp_update_irq(s);
856 break;
857 default:
858 assert(offset <= (0x504C >> 2));
859 s->core_registers[offset] = value;
860 break;
861 }
862 }
863
864 static const MemoryRegionOps dp_ops = {
865 .read = xlnx_dp_read,
866 .write = xlnx_dp_write,
867 .endianness = DEVICE_NATIVE_ENDIAN,
868 .valid = {
869 .min_access_size = 4,
870 .max_access_size = 4,
871 },
872 .impl = {
873 .min_access_size = 4,
874 .max_access_size = 4,
875 },
876 };
877
878 /*
879 * This is to handle Read/Write to the Video Blender.
880 */
881 static void xlnx_dp_vblend_write(void *opaque, hwaddr offset,
882 uint64_t value, unsigned size)
883 {
884 XlnxDPState *s = XLNX_DP(opaque);
885 bool alpha_was_enabled;
886
887 DPRINTF("vblend: write @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset,
888 (uint32_t)value);
889 offset = offset >> 2;
890
891 switch (offset) {
892 case V_BLEND_BG_CLR_0:
893 case V_BLEND_BG_CLR_1:
894 case V_BLEND_BG_CLR_2:
895 s->vblend_registers[offset] = value & 0x00000FFF;
896 break;
897 case V_BLEND_SET_GLOBAL_ALPHA_REG:
898 /*
899 * A write to this register can enable or disable blending. Thus we need
900 * to recreate the surfaces.
901 */
902 alpha_was_enabled = xlnx_dp_global_alpha_enabled(s);
903 s->vblend_registers[offset] = value & 0x000001FF;
904 if (xlnx_dp_global_alpha_enabled(s) != alpha_was_enabled) {
905 xlnx_dp_recreate_surface(s);
906 }
907 break;
908 case V_BLEND_OUTPUT_VID_FORMAT:
909 s->vblend_registers[offset] = value & 0x00000017;
910 break;
911 case V_BLEND_LAYER0_CONTROL:
912 case V_BLEND_LAYER1_CONTROL:
913 s->vblend_registers[offset] = value & 0x00000103;
914 break;
915 case V_BLEND_RGB2YCBCR_COEFF(0):
916 case V_BLEND_RGB2YCBCR_COEFF(1):
917 case V_BLEND_RGB2YCBCR_COEFF(2):
918 case V_BLEND_RGB2YCBCR_COEFF(3):
919 case V_BLEND_RGB2YCBCR_COEFF(4):
920 case V_BLEND_RGB2YCBCR_COEFF(5):
921 case V_BLEND_RGB2YCBCR_COEFF(6):
922 case V_BLEND_RGB2YCBCR_COEFF(7):
923 case V_BLEND_RGB2YCBCR_COEFF(8):
924 case V_BLEND_IN1CSC_COEFF(0):
925 case V_BLEND_IN1CSC_COEFF(1):
926 case V_BLEND_IN1CSC_COEFF(2):
927 case V_BLEND_IN1CSC_COEFF(3):
928 case V_BLEND_IN1CSC_COEFF(4):
929 case V_BLEND_IN1CSC_COEFF(5):
930 case V_BLEND_IN1CSC_COEFF(6):
931 case V_BLEND_IN1CSC_COEFF(7):
932 case V_BLEND_IN1CSC_COEFF(8):
933 case V_BLEND_IN2CSC_COEFF(0):
934 case V_BLEND_IN2CSC_COEFF(1):
935 case V_BLEND_IN2CSC_COEFF(2):
936 case V_BLEND_IN2CSC_COEFF(3):
937 case V_BLEND_IN2CSC_COEFF(4):
938 case V_BLEND_IN2CSC_COEFF(5):
939 case V_BLEND_IN2CSC_COEFF(6):
940 case V_BLEND_IN2CSC_COEFF(7):
941 case V_BLEND_IN2CSC_COEFF(8):
942 s->vblend_registers[offset] = value & 0x0000FFFF;
943 break;
944 case V_BLEND_LUMA_IN1CSC_OFFSET:
945 case V_BLEND_CR_IN1CSC_OFFSET:
946 case V_BLEND_CB_IN1CSC_OFFSET:
947 case V_BLEND_LUMA_IN2CSC_OFFSET:
948 case V_BLEND_CR_IN2CSC_OFFSET:
949 case V_BLEND_CB_IN2CSC_OFFSET:
950 case V_BLEND_LUMA_OUTCSC_OFFSET:
951 case V_BLEND_CR_OUTCSC_OFFSET:
952 case V_BLEND_CB_OUTCSC_OFFSET:
953 s->vblend_registers[offset] = value & 0x3FFF7FFF;
954 break;
955 case V_BLEND_CHROMA_KEY_ENABLE:
956 s->vblend_registers[offset] = value & 0x00000003;
957 break;
958 case V_BLEND_CHROMA_KEY_COMP1:
959 case V_BLEND_CHROMA_KEY_COMP2:
960 case V_BLEND_CHROMA_KEY_COMP3:
961 s->vblend_registers[offset] = value & 0x0FFF0FFF;
962 break;
963 default:
964 s->vblend_registers[offset] = value;
965 break;
966 }
967 }
968
969 static uint64_t xlnx_dp_vblend_read(void *opaque, hwaddr offset,
970 unsigned size)
971 {
972 XlnxDPState *s = XLNX_DP(opaque);
973
974 DPRINTF("vblend: read @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset,
975 s->vblend_registers[offset >> 2]);
976 return s->vblend_registers[offset >> 2];
977 }
978
979 static const MemoryRegionOps vblend_ops = {
980 .read = xlnx_dp_vblend_read,
981 .write = xlnx_dp_vblend_write,
982 .endianness = DEVICE_NATIVE_ENDIAN,
983 .valid = {
984 .min_access_size = 4,
985 .max_access_size = 4,
986 },
987 .impl = {
988 .min_access_size = 4,
989 .max_access_size = 4,
990 },
991 };
992
993 /*
994 * This is to handle Read/Write to the Audio Video buffer manager.
995 */
996 static void xlnx_dp_avbufm_write(void *opaque, hwaddr offset, uint64_t value,
997 unsigned size)
998 {
999 XlnxDPState *s = XLNX_DP(opaque);
1000
1001 DPRINTF("avbufm: write @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset,
1002 (uint32_t)value);
1003 offset = offset >> 2;
1004
1005 switch (offset) {
1006 case AV_BUF_FORMAT:
1007 s->avbufm_registers[offset] = value & 0x00000FFF;
1008 xlnx_dp_change_graphic_fmt(s);
1009 break;
1010 case AV_CHBUF0:
1011 case AV_CHBUF1:
1012 case AV_CHBUF2:
1013 case AV_CHBUF3:
1014 case AV_CHBUF4:
1015 case AV_CHBUF5:
1016 s->avbufm_registers[offset] = value & 0x0000007F;
1017 break;
1018 case AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT:
1019 s->avbufm_registers[offset] = value & 0x0000007F;
1020 break;
1021 case AV_BUF_DITHER_CONFIG:
1022 s->avbufm_registers[offset] = value & 0x000007FF;
1023 break;
1024 case AV_BUF_DITHER_CONFIG_MAX:
1025 case AV_BUF_DITHER_CONFIG_MIN:
1026 s->avbufm_registers[offset] = value & 0x00000FFF;
1027 break;
1028 case AV_BUF_PATTERN_GEN_SELECT:
1029 s->avbufm_registers[offset] = value & 0xFFFFFF03;
1030 break;
1031 case AV_BUF_AUD_VID_CLK_SOURCE:
1032 s->avbufm_registers[offset] = value & 0x00000007;
1033 break;
1034 case AV_BUF_SRST_REG:
1035 s->avbufm_registers[offset] = value & 0x00000002;
1036 break;
1037 case AV_BUF_AUDIO_CH_CONFIG:
1038 s->avbufm_registers[offset] = value & 0x00000003;
1039 break;
1040 case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(0):
1041 case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(1):
1042 case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(2):
1043 case AV_BUF_VIDEO_COMP_SCALE_FACTOR(0):
1044 case AV_BUF_VIDEO_COMP_SCALE_FACTOR(1):
1045 case AV_BUF_VIDEO_COMP_SCALE_FACTOR(2):
1046 s->avbufm_registers[offset] = value & 0x0000FFFF;
1047 break;
1048 case AV_BUF_LIVE_VIDEO_COMP_SF(0):
1049 case AV_BUF_LIVE_VIDEO_COMP_SF(1):
1050 case AV_BUF_LIVE_VIDEO_COMP_SF(2):
1051 case AV_BUF_LIVE_VID_CONFIG:
1052 case AV_BUF_LIVE_GFX_COMP_SF(0):
1053 case AV_BUF_LIVE_GFX_COMP_SF(1):
1054 case AV_BUF_LIVE_GFX_COMP_SF(2):
1055 case AV_BUF_LIVE_GFX_CONFIG:
1056 case AV_BUF_NON_LIVE_LATENCY:
1057 case AV_BUF_STC_CONTROL:
1058 case AV_BUF_STC_INIT_VALUE0:
1059 case AV_BUF_STC_INIT_VALUE1:
1060 case AV_BUF_STC_ADJ:
1061 case AV_BUF_STC_VIDEO_VSYNC_TS_REG0:
1062 case AV_BUF_STC_VIDEO_VSYNC_TS_REG1:
1063 case AV_BUF_STC_EXT_VSYNC_TS_REG0:
1064 case AV_BUF_STC_EXT_VSYNC_TS_REG1:
1065 case AV_BUF_STC_CUSTOM_EVENT_TS_REG0:
1066 case AV_BUF_STC_CUSTOM_EVENT_TS_REG1:
1067 case AV_BUF_STC_CUSTOM_EVENT2_TS_REG0:
1068 case AV_BUF_STC_CUSTOM_EVENT2_TS_REG1:
1069 case AV_BUF_STC_SNAPSHOT0:
1070 case AV_BUF_STC_SNAPSHOT1:
1071 case AV_BUF_HCOUNT_VCOUNT_INT0:
1072 case AV_BUF_HCOUNT_VCOUNT_INT1:
1073 qemu_log_mask(LOG_UNIMP, "avbufm: unimplmented");
1074 break;
1075 default:
1076 s->avbufm_registers[offset] = value;
1077 break;
1078 }
1079 }
1080
1081 static uint64_t xlnx_dp_avbufm_read(void *opaque, hwaddr offset,
1082 unsigned size)
1083 {
1084 XlnxDPState *s = XLNX_DP(opaque);
1085
1086 offset = offset >> 2;
1087 return s->avbufm_registers[offset];
1088 }
1089
1090 static const MemoryRegionOps avbufm_ops = {
1091 .read = xlnx_dp_avbufm_read,
1092 .write = xlnx_dp_avbufm_write,
1093 .endianness = DEVICE_NATIVE_ENDIAN,
1094 .valid = {
1095 .min_access_size = 4,
1096 .max_access_size = 4,
1097 },
1098 .impl = {
1099 .min_access_size = 4,
1100 .max_access_size = 4,
1101 },
1102 };
1103
1104 /*
1105 * This is a global alpha blending using pixman.
1106 * Both graphic and video planes are multiplied with the global alpha
1107 * coefficient and added.
1108 */
1109 static inline void xlnx_dp_blend_surface(XlnxDPState *s)
1110 {
1111 pixman_fixed_t alpha1[] = { pixman_double_to_fixed(1),
1112 pixman_double_to_fixed(1),
1113 pixman_double_to_fixed(1.0) };
1114 pixman_fixed_t alpha2[] = { pixman_double_to_fixed(1),
1115 pixman_double_to_fixed(1),
1116 pixman_double_to_fixed(1.0) };
1117
1118 if ((surface_width(s->g_plane.surface)
1119 != surface_width(s->v_plane.surface)) ||
1120 (surface_height(s->g_plane.surface)
1121 != surface_height(s->v_plane.surface))) {
1122 return;
1123 }
1124
1125 alpha1[2] = pixman_double_to_fixed((double)(xlnx_dp_global_alpha_value(s))
1126 / 256.0);
1127 alpha2[2] = pixman_double_to_fixed((255.0
1128 - (double)xlnx_dp_global_alpha_value(s))
1129 / 256.0);
1130
1131 pixman_image_set_filter(s->g_plane.surface->image,
1132 PIXMAN_FILTER_CONVOLUTION, alpha1, 3);
1133 pixman_image_composite(PIXMAN_OP_SRC, s->g_plane.surface->image, 0,
1134 s->bout_plane.surface->image, 0, 0, 0, 0, 0, 0,
1135 surface_width(s->g_plane.surface),
1136 surface_height(s->g_plane.surface));
1137 pixman_image_set_filter(s->v_plane.surface->image,
1138 PIXMAN_FILTER_CONVOLUTION, alpha2, 3);
1139 pixman_image_composite(PIXMAN_OP_ADD, s->v_plane.surface->image, 0,
1140 s->bout_plane.surface->image, 0, 0, 0, 0, 0, 0,
1141 surface_width(s->g_plane.surface),
1142 surface_height(s->g_plane.surface));
1143 }
1144
1145 static void xlnx_dp_update_display(void *opaque)
1146 {
1147 XlnxDPState *s = XLNX_DP(opaque);
1148
1149 if ((s->core_registers[DP_TRANSMITTER_ENABLE] & 0x01) == 0) {
1150 return;
1151 }
1152
1153 s->core_registers[DP_INT_STATUS] |= (1 << 13);
1154 xlnx_dp_update_irq(s);
1155
1156 xlnx_dpdma_trigger_vsync_irq(s->dpdma);
1157
1158 /*
1159 * Trigger the DMA channel.
1160 */
1161 if (!xlnx_dpdma_start_operation(s->dpdma, 3, false)) {
1162 /*
1163 * An error occurred don't do anything with the data..
1164 * Trigger an underflow interrupt.
1165 */
1166 s->core_registers[DP_INT_STATUS] |= (1 << 21);
1167 xlnx_dp_update_irq(s);
1168 return;
1169 }
1170
1171 if (xlnx_dp_global_alpha_enabled(s)) {
1172 if (!xlnx_dpdma_start_operation(s->dpdma, 0, false)) {
1173 s->core_registers[DP_INT_STATUS] |= (1 << 21);
1174 xlnx_dp_update_irq(s);
1175 return;
1176 }
1177 xlnx_dp_blend_surface(s);
1178 }
1179
1180 /*
1181 * XXX: We might want to update only what changed.
1182 */
1183 dpy_gfx_update(s->console, 0, 0, surface_width(s->g_plane.surface),
1184 surface_height(s->g_plane.surface));
1185 }
1186
1187 static const GraphicHwOps xlnx_dp_gfx_ops = {
1188 .gfx_update = xlnx_dp_update_display,
1189 };
1190
1191 static void xlnx_dp_init(Object *obj)
1192 {
1193 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1194 XlnxDPState *s = XLNX_DP(obj);
1195
1196 memory_region_init(&s->container, obj, TYPE_XLNX_DP, 0xC050);
1197
1198 memory_region_init_io(&s->core_iomem, obj, &dp_ops, s, TYPE_XLNX_DP
1199 ".core", 0x3AF);
1200 memory_region_add_subregion(&s->container, 0x0000, &s->core_iomem);
1201
1202 memory_region_init_io(&s->vblend_iomem, obj, &vblend_ops, s, TYPE_XLNX_DP
1203 ".v_blend", 0x1DF);
1204 memory_region_add_subregion(&s->container, 0xA000, &s->vblend_iomem);
1205
1206 memory_region_init_io(&s->avbufm_iomem, obj, &avbufm_ops, s, TYPE_XLNX_DP
1207 ".av_buffer_manager", 0x238);
1208 memory_region_add_subregion(&s->container, 0xB000, &s->avbufm_iomem);
1209
1210 memory_region_init_io(&s->audio_iomem, obj, &audio_ops, s, TYPE_XLNX_DP
1211 ".audio", sizeof(s->audio_registers));
1212 memory_region_add_subregion(&s->container, 0xC000, &s->audio_iomem);
1213
1214 sysbus_init_mmio(sbd, &s->container);
1215 sysbus_init_irq(sbd, &s->irq);
1216
1217 object_property_add_link(obj, "dpdma", TYPE_XLNX_DPDMA,
1218 (Object **) &s->dpdma,
1219 xlnx_dp_set_dpdma,
1220 OBJ_PROP_LINK_UNREF_ON_RELEASE,
1221 &error_abort);
1222
1223 /*
1224 * Initialize AUX Bus.
1225 */
1226 s->aux_bus = aux_init_bus(DEVICE(obj), "aux");
1227
1228 /*
1229 * Initialize DPCD and EDID..
1230 */
1231 s->dpcd = DPCD(aux_create_slave(s->aux_bus, "dpcd", 0x00000));
1232 s->edid = I2CDDC(qdev_create(BUS(aux_get_i2c_bus(s->aux_bus)), "i2c-ddc"));
1233 i2c_set_slave_address(I2C_SLAVE(s->edid), 0x50);
1234
1235 fifo8_create(&s->rx_fifo, 16);
1236 fifo8_create(&s->tx_fifo, 16);
1237 }
1238
1239 static void xlnx_dp_realize(DeviceState *dev, Error **errp)
1240 {
1241 XlnxDPState *s = XLNX_DP(dev);
1242 DisplaySurface *surface;
1243 struct audsettings as;
1244
1245 s->console = graphic_console_init(dev, 0, &xlnx_dp_gfx_ops, s);
1246 surface = qemu_console_surface(s->console);
1247 xlnx_dpdma_set_host_data_location(s->dpdma, DP_GRAPHIC_DMA_CHANNEL,
1248 surface_data(surface));
1249
1250 as.freq = 44100;
1251 as.nchannels = 2;
1252 as.fmt = AUD_FMT_S16;
1253 as.endianness = 0;
1254
1255 AUD_register_card("xlnx_dp.audio", &s->aud_card);
1256
1257 s->amixer_output_stream = AUD_open_out(&s->aud_card,
1258 s->amixer_output_stream,
1259 "xlnx_dp.audio.out",
1260 s,
1261 xlnx_dp_audio_callback,
1262 &as);
1263 AUD_set_volume_out(s->amixer_output_stream, 0, 255, 255);
1264 xlnx_dp_audio_activate(s);
1265 }
1266
1267 static void xlnx_dp_reset(DeviceState *dev)
1268 {
1269 XlnxDPState *s = XLNX_DP(dev);
1270
1271 memset(s->core_registers, 0, sizeof(s->core_registers));
1272 s->core_registers[DP_VERSION_REGISTER] = 0x04010000;
1273 s->core_registers[DP_CORE_ID] = 0x01020000;
1274 s->core_registers[DP_REPLY_STATUS] = 0x00000010;
1275 s->core_registers[DP_MSA_TRANSFER_UNIT_SIZE] = 0x00000040;
1276 s->core_registers[DP_INIT_WAIT] = 0x00000020;
1277 s->core_registers[DP_PHY_RESET] = 0x00010003;
1278 s->core_registers[DP_INT_MASK] = 0xFFFFF03F;
1279 s->core_registers[DP_PHY_STATUS] = 0x00000043;
1280 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] = 0x00000001;
1281
1282 s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(0)] = 0x00001000;
1283 s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(4)] = 0x00001000;
1284 s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(8)] = 0x00001000;
1285 s->vblend_registers[V_BLEND_IN1CSC_COEFF(0)] = 0x00001000;
1286 s->vblend_registers[V_BLEND_IN1CSC_COEFF(4)] = 0x00001000;
1287 s->vblend_registers[V_BLEND_IN1CSC_COEFF(8)] = 0x00001000;
1288 s->vblend_registers[V_BLEND_IN2CSC_COEFF(0)] = 0x00001000;
1289 s->vblend_registers[V_BLEND_IN2CSC_COEFF(4)] = 0x00001000;
1290 s->vblend_registers[V_BLEND_IN2CSC_COEFF(8)] = 0x00001000;
1291
1292 s->avbufm_registers[AV_BUF_NON_LIVE_LATENCY] = 0x00000180;
1293 s->avbufm_registers[AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT] = 0x00000008;
1294 s->avbufm_registers[AV_BUF_DITHER_CONFIG_MAX] = 0x00000FFF;
1295 s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(0)] = 0x00010101;
1296 s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(1)] = 0x00010101;
1297 s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(2)] = 0x00010101;
1298 s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(0)] = 0x00010101;
1299 s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(1)] = 0x00010101;
1300 s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(2)] = 0x00010101;
1301 s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(0)] = 0x00010101;
1302 s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(1)] = 0x00010101;
1303 s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(2)] = 0x00010101;
1304 s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(0)] = 0x00010101;
1305 s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(1)] = 0x00010101;
1306 s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(2)] = 0x00010101;
1307
1308 memset(s->audio_registers, 0, sizeof(s->audio_registers));
1309 s->byte_left = 0;
1310
1311 xlnx_dp_aux_clear_rx_fifo(s);
1312 xlnx_dp_change_graphic_fmt(s);
1313 xlnx_dp_update_irq(s);
1314 }
1315
1316 static void xlnx_dp_class_init(ObjectClass *oc, void *data)
1317 {
1318 DeviceClass *dc = DEVICE_CLASS(oc);
1319
1320 dc->realize = xlnx_dp_realize;
1321 dc->vmsd = &vmstate_dp;
1322 dc->reset = xlnx_dp_reset;
1323 }
1324
1325 static const TypeInfo xlnx_dp_info = {
1326 .name = TYPE_XLNX_DP,
1327 .parent = TYPE_SYS_BUS_DEVICE,
1328 .instance_size = sizeof(XlnxDPState),
1329 .instance_init = xlnx_dp_init,
1330 .class_init = xlnx_dp_class_init,
1331 };
1332
1333 static void xlnx_dp_register_types(void)
1334 {
1335 type_register_static(&xlnx_dp_info);
1336 }
1337
1338 type_init(xlnx_dp_register_types)