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eepro100: Support byte/word writes to port address
[qemu.git] / hw / eepro100.c
1 /*
2 * QEMU i8255x (PRO100) emulation
3 *
4 * Copyright (C) 2006-2011 Stefan Weil
5 *
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 2 of the License, or
12 * (at your option) version 3 or any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 *
22 * Tested features (i82559):
23 * PXE boot (i386 guest, i386 / mips / mipsel / ppc host) ok
24 * Linux networking (i386) ok
25 *
26 * Untested:
27 * Windows networking
28 *
29 * References:
30 *
31 * Intel 8255x 10/100 Mbps Ethernet Controller Family
32 * Open Source Software Developer Manual
33 *
34 * TODO:
35 * * PHY emulation should be separated from nic emulation.
36 * Most nic emulations could share the same phy code.
37 * * i82550 is untested. It is programmed like the i82559.
38 * * i82562 is untested. It is programmed like the i82559.
39 * * Power management (i82558 and later) is not implemented.
40 * * Wake-on-LAN is not implemented.
41 */
42
43 #include <stddef.h> /* offsetof */
44 #include "hw.h"
45 #include "pci.h"
46 #include "net.h"
47 #include "eeprom93xx.h"
48 #include "sysemu.h"
49
50 /* QEMU sends frames smaller than 60 bytes to ethernet nics.
51 * Such frames are rejected by real nics and their emulations.
52 * To avoid this behaviour, other nic emulations pad received
53 * frames. The following definition enables this padding for
54 * eepro100, too. We keep the define around in case it might
55 * become useful the future if the core networking is ever
56 * changed to pad short packets itself. */
57 #define CONFIG_PAD_RECEIVED_FRAMES
58
59 #define KiB 1024
60
61 /* Debug EEPRO100 card. */
62 #if 0
63 # define DEBUG_EEPRO100
64 #endif
65
66 #ifdef DEBUG_EEPRO100
67 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
68 #else
69 #define logout(fmt, ...) ((void)0)
70 #endif
71
72 /* Set flags to 0 to disable debug output. */
73 #define INT 1 /* interrupt related actions */
74 #define MDI 1 /* mdi related actions */
75 #define OTHER 1
76 #define RXTX 1
77 #define EEPROM 1 /* eeprom related actions */
78
79 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
80
81 #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
82
83 #define MAX_ETH_FRAME_SIZE 1514
84
85 /* This driver supports several different devices which are declared here. */
86 #define i82550 0x82550
87 #define i82551 0x82551
88 #define i82557A 0x82557a
89 #define i82557B 0x82557b
90 #define i82557C 0x82557c
91 #define i82558A 0x82558a
92 #define i82558B 0x82558b
93 #define i82559A 0x82559a
94 #define i82559B 0x82559b
95 #define i82559C 0x82559c
96 #define i82559ER 0x82559e
97 #define i82562 0x82562
98 #define i82801 0x82801
99
100 /* Use 64 word EEPROM. TODO: could be a runtime option. */
101 #define EEPROM_SIZE 64
102
103 #define PCI_MEM_SIZE (4 * KiB)
104 #define PCI_IO_SIZE 64
105 #define PCI_FLASH_SIZE (128 * KiB)
106
107 #define BIT(n) (1 << (n))
108 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
109
110 /* The SCB accepts the following controls for the Tx and Rx units: */
111 #define CU_NOP 0x0000 /* No operation. */
112 #define CU_START 0x0010 /* CU start. */
113 #define CU_RESUME 0x0020 /* CU resume. */
114 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
115 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
116 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
117 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
118 #define CU_SRESUME 0x00a0 /* CU static resume. */
119
120 #define RU_NOP 0x0000
121 #define RX_START 0x0001
122 #define RX_RESUME 0x0002
123 #define RU_ABORT 0x0004
124 #define RX_ADDR_LOAD 0x0006
125 #define RX_RESUMENR 0x0007
126 #define INT_MASK 0x0100
127 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
128
129 typedef struct {
130 PCIDeviceInfo pci;
131 uint32_t device;
132 uint16_t device_id;
133 uint8_t revision;
134 uint8_t stats_size;
135 bool has_extended_tcb_support;
136 bool power_management;
137 } E100PCIDeviceInfo;
138
139 /* Offsets to the various registers.
140 All accesses need not be longword aligned. */
141 typedef enum {
142 SCBStatus = 0, /* Status Word. */
143 SCBAck = 1,
144 SCBCmd = 2, /* Rx/Command Unit command and status. */
145 SCBIntmask = 3,
146 SCBPointer = 4, /* General purpose pointer. */
147 SCBPort = 8, /* Misc. commands and operands. */
148 SCBflash = 12, /* Flash memory control. */
149 SCBeeprom = 14, /* EEPROM control. */
150 SCBCtrlMDI = 16, /* MDI interface control. */
151 SCBEarlyRx = 20, /* Early receive byte count. */
152 SCBFlow = 24, /* Flow Control. */
153 SCBpmdr = 27, /* Power Management Driver. */
154 SCBgctrl = 28, /* General Control. */
155 SCBgstat = 29, /* General Status. */
156 } E100RegisterOffset;
157
158 /* A speedo3 transmit buffer descriptor with two buffers... */
159 typedef struct {
160 uint16_t status;
161 uint16_t command;
162 uint32_t link; /* void * */
163 uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */
164 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
165 uint8_t tx_threshold; /* transmit threshold */
166 uint8_t tbd_count; /* TBD number */
167 #if 0
168 /* This constitutes two "TBD" entries: hdr and data */
169 uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
170 int32_t tx_buf_size0; /* Length of Tx hdr. */
171 uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
172 int32_t tx_buf_size1; /* Length of Tx data. */
173 #endif
174 } eepro100_tx_t;
175
176 /* Receive frame descriptor. */
177 typedef struct {
178 int16_t status;
179 uint16_t command;
180 uint32_t link; /* struct RxFD * */
181 uint32_t rx_buf_addr; /* void * */
182 uint16_t count;
183 uint16_t size;
184 /* Ethernet frame data follows. */
185 } eepro100_rx_t;
186
187 typedef enum {
188 COMMAND_EL = BIT(15),
189 COMMAND_S = BIT(14),
190 COMMAND_I = BIT(13),
191 COMMAND_NC = BIT(4),
192 COMMAND_SF = BIT(3),
193 COMMAND_CMD = BITS(2, 0),
194 } scb_command_bit;
195
196 typedef enum {
197 STATUS_C = BIT(15),
198 STATUS_OK = BIT(13),
199 } scb_status_bit;
200
201 typedef struct {
202 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
203 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
204 tx_multiple_collisions, tx_total_collisions;
205 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
206 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
207 rx_short_frame_errors;
208 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
209 uint16_t xmt_tco_frames, rcv_tco_frames;
210 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
211 uint32_t reserved[4];
212 } eepro100_stats_t;
213
214 typedef enum {
215 cu_idle = 0,
216 cu_suspended = 1,
217 cu_active = 2,
218 cu_lpq_active = 2,
219 cu_hqp_active = 3
220 } cu_state_t;
221
222 typedef enum {
223 ru_idle = 0,
224 ru_suspended = 1,
225 ru_no_resources = 2,
226 ru_ready = 4
227 } ru_state_t;
228
229 typedef struct {
230 PCIDevice dev;
231 /* Hash register (multicast mask array, multiple individual addresses). */
232 uint8_t mult[8];
233 int mmio_index;
234 NICState *nic;
235 NICConf conf;
236 uint8_t scb_stat; /* SCB stat/ack byte */
237 uint8_t int_stat; /* PCI interrupt status */
238 /* region must not be saved by nic_save. */
239 uint32_t region1; /* PCI region 1 address */
240 uint16_t mdimem[32];
241 eeprom_t *eeprom;
242 uint32_t device; /* device variant */
243 uint32_t pointer;
244 /* (cu_base + cu_offset) address the next command block in the command block list. */
245 uint32_t cu_base; /* CU base address */
246 uint32_t cu_offset; /* CU address offset */
247 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
248 uint32_t ru_base; /* RU base address */
249 uint32_t ru_offset; /* RU address offset */
250 uint32_t statsaddr; /* pointer to eepro100_stats_t */
251
252 /* Temporary status information (no need to save these values),
253 * used while processing CU commands. */
254 eepro100_tx_t tx; /* transmit buffer descriptor */
255 uint32_t cb_address; /* = cu_base + cu_offset */
256
257 /* Statistical counters. Also used for wake-up packet (i82559). */
258 eepro100_stats_t statistics;
259
260 /* Data in mem is always in the byte order of the controller (le).
261 * It must be dword aligned to allow direct access to 32 bit values. */
262 uint8_t mem[PCI_MEM_SIZE] __attribute__((aligned(8)));;
263
264 /* Configuration bytes. */
265 uint8_t configuration[22];
266
267 /* vmstate for each particular nic */
268 VMStateDescription *vmstate;
269
270 /* Quasi static device properties (no need to save them). */
271 uint16_t stats_size;
272 bool has_extended_tcb_support;
273 } EEPRO100State;
274
275 /* Word indices in EEPROM. */
276 typedef enum {
277 EEPROM_CNFG_MDIX = 0x03,
278 EEPROM_ID = 0x05,
279 EEPROM_PHY_ID = 0x06,
280 EEPROM_VENDOR_ID = 0x0c,
281 EEPROM_CONFIG_ASF = 0x0d,
282 EEPROM_DEVICE_ID = 0x23,
283 EEPROM_SMBUS_ADDR = 0x90,
284 } EEPROMOffset;
285
286 /* Bit values for EEPROM ID word. */
287 typedef enum {
288 EEPROM_ID_MDM = BIT(0), /* Modem */
289 EEPROM_ID_STB = BIT(1), /* Standby Enable */
290 EEPROM_ID_WMR = BIT(2), /* ??? */
291 EEPROM_ID_WOL = BIT(5), /* Wake on LAN */
292 EEPROM_ID_DPD = BIT(6), /* Deep Power Down */
293 EEPROM_ID_ALT = BIT(7), /* */
294 /* BITS(10, 8) device revision */
295 EEPROM_ID_BD = BIT(11), /* boot disable */
296 EEPROM_ID_ID = BIT(13), /* id bit */
297 /* BITS(15, 14) signature */
298 EEPROM_ID_VALID = BIT(14), /* signature for valid eeprom */
299 } eeprom_id_bit;
300
301 /* Default values for MDI (PHY) registers */
302 static const uint16_t eepro100_mdi_default[] = {
303 /* MDI Registers 0 - 6, 7 */
304 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
305 /* MDI Registers 8 - 15 */
306 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
307 /* MDI Registers 16 - 31 */
308 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
309 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
310 };
311
312 /* Readonly mask for MDI (PHY) registers */
313 static const uint16_t eepro100_mdi_mask[] = {
314 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
315 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
316 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
317 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
318 };
319
320 /* Read a 16 bit little endian value from physical memory. */
321 static uint16_t e100_ldw_le_phys(target_phys_addr_t addr)
322 {
323 /* Load 16 bit (little endian) word from emulated hardware. */
324 uint16_t val;
325 cpu_physical_memory_read(addr, &val, sizeof(val));
326 return le16_to_cpu(val);
327 }
328
329 /* Read a 32 bit little endian value from physical memory. */
330 static uint32_t e100_ldl_le_phys(target_phys_addr_t addr)
331 {
332 /* Load 32 bit (little endian) word from emulated hardware. */
333 uint32_t val;
334 cpu_physical_memory_read(addr, &val, sizeof(val));
335 return le32_to_cpu(val);
336 }
337
338 /* Write a 16 bit little endian value to physical memory. */
339 static void e100_stw_le_phys(target_phys_addr_t addr, uint16_t val)
340 {
341 val = cpu_to_le16(val);
342 cpu_physical_memory_write(addr, &val, sizeof(val));
343 }
344
345 /* Write a 32 bit little endian value to physical memory. */
346 static void e100_stl_le_phys(target_phys_addr_t addr, uint32_t val)
347 {
348 val = cpu_to_le32(val);
349 cpu_physical_memory_write(addr, &val, sizeof(val));
350 }
351
352 #define POLYNOMIAL 0x04c11db6
353
354 /* From FreeBSD */
355 /* XXX: optimize */
356 static unsigned compute_mcast_idx(const uint8_t * ep)
357 {
358 uint32_t crc;
359 int carry, i, j;
360 uint8_t b;
361
362 crc = 0xffffffff;
363 for (i = 0; i < 6; i++) {
364 b = *ep++;
365 for (j = 0; j < 8; j++) {
366 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
367 crc <<= 1;
368 b >>= 1;
369 if (carry) {
370 crc = ((crc ^ POLYNOMIAL) | carry);
371 }
372 }
373 }
374 return (crc & BITS(7, 2)) >> 2;
375 }
376
377 /* Read a 16 bit control/status (CSR) register. */
378 static uint16_t e100_read_reg2(EEPRO100State *s, E100RegisterOffset addr)
379 {
380 assert(!((uintptr_t)&s->mem[addr] & 1));
381 return le16_to_cpup((uint16_t *)&s->mem[addr]);
382 }
383
384 /* Read a 32 bit control/status (CSR) register. */
385 static uint32_t e100_read_reg4(EEPRO100State *s, E100RegisterOffset addr)
386 {
387 assert(!((uintptr_t)&s->mem[addr] & 3));
388 return le32_to_cpup((uint32_t *)&s->mem[addr]);
389 }
390
391 /* Write a 16 bit control/status (CSR) register. */
392 static void e100_write_reg2(EEPRO100State *s, E100RegisterOffset addr,
393 uint16_t val)
394 {
395 assert(!((uintptr_t)&s->mem[addr] & 1));
396 cpu_to_le16w((uint16_t *)&s->mem[addr], val);
397 }
398
399 /* Read a 32 bit control/status (CSR) register. */
400 static void e100_write_reg4(EEPRO100State *s, E100RegisterOffset addr,
401 uint32_t val)
402 {
403 assert(!((uintptr_t)&s->mem[addr] & 3));
404 cpu_to_le32w((uint32_t *)&s->mem[addr], val);
405 }
406
407 #if defined(DEBUG_EEPRO100)
408 static const char *nic_dump(const uint8_t * buf, unsigned size)
409 {
410 static char dump[3 * 16 + 1];
411 char *p = &dump[0];
412 if (size > 16) {
413 size = 16;
414 }
415 while (size-- > 0) {
416 p += sprintf(p, " %02x", *buf++);
417 }
418 return dump;
419 }
420 #endif /* DEBUG_EEPRO100 */
421
422 enum scb_stat_ack {
423 stat_ack_not_ours = 0x00,
424 stat_ack_sw_gen = 0x04,
425 stat_ack_rnr = 0x10,
426 stat_ack_cu_idle = 0x20,
427 stat_ack_frame_rx = 0x40,
428 stat_ack_cu_cmd_done = 0x80,
429 stat_ack_not_present = 0xFF,
430 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
431 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
432 };
433
434 static void disable_interrupt(EEPRO100State * s)
435 {
436 if (s->int_stat) {
437 TRACE(INT, logout("interrupt disabled\n"));
438 qemu_irq_lower(s->dev.irq[0]);
439 s->int_stat = 0;
440 }
441 }
442
443 static void enable_interrupt(EEPRO100State * s)
444 {
445 if (!s->int_stat) {
446 TRACE(INT, logout("interrupt enabled\n"));
447 qemu_irq_raise(s->dev.irq[0]);
448 s->int_stat = 1;
449 }
450 }
451
452 static void eepro100_acknowledge(EEPRO100State * s)
453 {
454 s->scb_stat &= ~s->mem[SCBAck];
455 s->mem[SCBAck] = s->scb_stat;
456 if (s->scb_stat == 0) {
457 disable_interrupt(s);
458 }
459 }
460
461 static void eepro100_interrupt(EEPRO100State * s, uint8_t status)
462 {
463 uint8_t mask = ~s->mem[SCBIntmask];
464 s->mem[SCBAck] |= status;
465 status = s->scb_stat = s->mem[SCBAck];
466 status &= (mask | 0x0f);
467 #if 0
468 status &= (~s->mem[SCBIntmask] | 0x0xf);
469 #endif
470 if (status && (mask & 0x01)) {
471 /* SCB mask and SCB Bit M do not disable interrupt. */
472 enable_interrupt(s);
473 } else if (s->int_stat) {
474 disable_interrupt(s);
475 }
476 }
477
478 static void eepro100_cx_interrupt(EEPRO100State * s)
479 {
480 /* CU completed action command. */
481 /* Transmit not ok (82557 only, not in emulation). */
482 eepro100_interrupt(s, 0x80);
483 }
484
485 static void eepro100_cna_interrupt(EEPRO100State * s)
486 {
487 /* CU left the active state. */
488 eepro100_interrupt(s, 0x20);
489 }
490
491 static void eepro100_fr_interrupt(EEPRO100State * s)
492 {
493 /* RU received a complete frame. */
494 eepro100_interrupt(s, 0x40);
495 }
496
497 static void eepro100_rnr_interrupt(EEPRO100State * s)
498 {
499 /* RU is not ready. */
500 eepro100_interrupt(s, 0x10);
501 }
502
503 static void eepro100_mdi_interrupt(EEPRO100State * s)
504 {
505 /* MDI completed read or write cycle. */
506 eepro100_interrupt(s, 0x08);
507 }
508
509 static void eepro100_swi_interrupt(EEPRO100State * s)
510 {
511 /* Software has requested an interrupt. */
512 eepro100_interrupt(s, 0x04);
513 }
514
515 #if 0
516 static void eepro100_fcp_interrupt(EEPRO100State * s)
517 {
518 /* Flow control pause interrupt (82558 and later). */
519 eepro100_interrupt(s, 0x01);
520 }
521 #endif
522
523 static void e100_pci_reset(EEPRO100State * s, E100PCIDeviceInfo *e100_device)
524 {
525 uint32_t device = s->device;
526 uint8_t *pci_conf = s->dev.config;
527
528 TRACE(OTHER, logout("%p\n", s));
529
530 /* PCI Vendor ID */
531 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
532 /* PCI Device ID */
533 pci_config_set_device_id(pci_conf, e100_device->device_id);
534 /* PCI Status */
535 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
536 PCI_STATUS_FAST_BACK);
537 /* PCI Revision ID */
538 pci_config_set_revision(pci_conf, e100_device->revision);
539 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
540 /* PCI Latency Timer */
541 pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */
542 /* Capability Pointer is set by PCI framework. */
543 /* Interrupt Line */
544 /* Interrupt Pin */
545 pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 1); /* interrupt pin A */
546 /* Minimum Grant */
547 pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08);
548 /* Maximum Latency */
549 pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18);
550
551 s->stats_size = e100_device->stats_size;
552 s->has_extended_tcb_support = e100_device->has_extended_tcb_support;
553
554 switch (device) {
555 case i82550:
556 case i82551:
557 case i82557A:
558 case i82557B:
559 case i82557C:
560 case i82558A:
561 case i82558B:
562 case i82559A:
563 case i82559B:
564 case i82559ER:
565 case i82562:
566 case i82801:
567 break;
568 case i82559C:
569 #if EEPROM_SIZE > 0
570 pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, PCI_VENDOR_ID_INTEL);
571 pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0040);
572 #endif
573 break;
574 default:
575 logout("Device %X is undefined!\n", device);
576 }
577
578 /* Standard TxCB. */
579 s->configuration[6] |= BIT(4);
580
581 /* Standard statistical counters. */
582 s->configuration[6] |= BIT(5);
583
584 if (s->stats_size == 80) {
585 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
586 if (s->configuration[6] & BIT(2)) {
587 /* TCO statistical counters. */
588 assert(s->configuration[6] & BIT(5));
589 } else {
590 if (s->configuration[6] & BIT(5)) {
591 /* No extended statistical counters, i82557 compatible. */
592 s->stats_size = 64;
593 } else {
594 /* i82558 compatible. */
595 s->stats_size = 76;
596 }
597 }
598 } else {
599 if (s->configuration[6] & BIT(5)) {
600 /* No extended statistical counters. */
601 s->stats_size = 64;
602 }
603 }
604 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
605
606 if (e100_device->power_management) {
607 /* Power Management Capabilities */
608 int cfg_offset = 0xdc;
609 int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM,
610 cfg_offset, PCI_PM_SIZEOF);
611 assert(r >= 0);
612 pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
613 #if 0 /* TODO: replace dummy code for power management emulation. */
614 /* TODO: Power Management Control / Status. */
615 pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000);
616 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
617 pci_set_byte(pci_conf + cfg_offset + PCI_PM_PPB_EXTENSIONS, 0x0000);
618 #endif
619 }
620
621 #if EEPROM_SIZE > 0
622 if (device == i82557C || device == i82558B || device == i82559C) {
623 /*
624 TODO: get vendor id from EEPROM for i82557C or later.
625 TODO: get device id from EEPROM for i82557C or later.
626 TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
627 TODO: header type is determined by EEPROM for i82559.
628 TODO: get subsystem id from EEPROM for i82557C or later.
629 TODO: get subsystem vendor id from EEPROM for i82557C or later.
630 TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
631 TODO: capability pointer depends on EEPROM for i82558.
632 */
633 logout("Get device id and revision from EEPROM!!!\n");
634 }
635 #endif /* EEPROM_SIZE > 0 */
636 }
637
638 static void nic_selective_reset(EEPRO100State * s)
639 {
640 size_t i;
641 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
642 #if 0
643 eeprom93xx_reset(s->eeprom);
644 #endif
645 memcpy(eeprom_contents, s->conf.macaddr.a, 6);
646 eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID;
647 if (s->device == i82557B || s->device == i82557C)
648 eeprom_contents[5] = 0x0100;
649 eeprom_contents[EEPROM_PHY_ID] = 1;
650 uint16_t sum = 0;
651 for (i = 0; i < EEPROM_SIZE - 1; i++) {
652 sum += eeprom_contents[i];
653 }
654 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
655 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
656
657 memset(s->mem, 0, sizeof(s->mem));
658 e100_write_reg4(s, SCBCtrlMDI, BIT(21));
659
660 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
661 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
662 }
663
664 static void nic_reset(void *opaque)
665 {
666 EEPRO100State *s = opaque;
667 TRACE(OTHER, logout("%p\n", s));
668 /* TODO: Clearing of hash register for selective reset, too? */
669 memset(&s->mult[0], 0, sizeof(s->mult));
670 nic_selective_reset(s);
671 }
672
673 #if defined(DEBUG_EEPRO100)
674 static const char * const e100_reg[PCI_IO_SIZE / 4] = {
675 "Command/Status",
676 "General Pointer",
677 "Port",
678 "EEPROM/Flash Control",
679 "MDI Control",
680 "Receive DMA Byte Count",
681 "Flow Control",
682 "General Status/Control"
683 };
684
685 static char *regname(uint32_t addr)
686 {
687 static char buf[32];
688 if (addr < PCI_IO_SIZE) {
689 const char *r = e100_reg[addr / 4];
690 if (r != 0) {
691 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
692 } else {
693 snprintf(buf, sizeof(buf), "0x%02x", addr);
694 }
695 } else {
696 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
697 }
698 return buf;
699 }
700 #endif /* DEBUG_EEPRO100 */
701
702 /*****************************************************************************
703 *
704 * Command emulation.
705 *
706 ****************************************************************************/
707
708 #if 0
709 static uint16_t eepro100_read_command(EEPRO100State * s)
710 {
711 uint16_t val = 0xffff;
712 TRACE(OTHER, logout("val=0x%04x\n", val));
713 return val;
714 }
715 #endif
716
717 /* Commands that can be put in a command list entry. */
718 enum commands {
719 CmdNOp = 0,
720 CmdIASetup = 1,
721 CmdConfigure = 2,
722 CmdMulticastList = 3,
723 CmdTx = 4,
724 CmdTDR = 5, /* load microcode */
725 CmdDump = 6,
726 CmdDiagnose = 7,
727
728 /* And some extra flags: */
729 CmdSuspend = 0x4000, /* Suspend after completion. */
730 CmdIntr = 0x2000, /* Interrupt after completion. */
731 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
732 };
733
734 static cu_state_t get_cu_state(EEPRO100State * s)
735 {
736 return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6);
737 }
738
739 static void set_cu_state(EEPRO100State * s, cu_state_t state)
740 {
741 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6);
742 }
743
744 static ru_state_t get_ru_state(EEPRO100State * s)
745 {
746 return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2);
747 }
748
749 static void set_ru_state(EEPRO100State * s, ru_state_t state)
750 {
751 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2);
752 }
753
754 static void dump_statistics(EEPRO100State * s)
755 {
756 /* Dump statistical data. Most data is never changed by the emulation
757 * and always 0, so we first just copy the whole block and then those
758 * values which really matter.
759 * Number of data should check configuration!!!
760 */
761 cpu_physical_memory_write(s->statsaddr, &s->statistics, s->stats_size);
762 e100_stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
763 e100_stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
764 e100_stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
765 e100_stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
766 #if 0
767 e100_stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
768 e100_stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
769 missing("CU dump statistical counters");
770 #endif
771 }
772
773 static void read_cb(EEPRO100State *s)
774 {
775 cpu_physical_memory_read(s->cb_address, &s->tx, sizeof(s->tx));
776 s->tx.status = le16_to_cpu(s->tx.status);
777 s->tx.command = le16_to_cpu(s->tx.command);
778 s->tx.link = le32_to_cpu(s->tx.link);
779 s->tx.tbd_array_addr = le32_to_cpu(s->tx.tbd_array_addr);
780 s->tx.tcb_bytes = le16_to_cpu(s->tx.tcb_bytes);
781 }
782
783 static void tx_command(EEPRO100State *s)
784 {
785 uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr);
786 uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
787 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
788 uint8_t buf[2600];
789 uint16_t size = 0;
790 uint32_t tbd_address = s->cb_address + 0x10;
791 TRACE(RXTX, logout
792 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
793 tbd_array, tcb_bytes, s->tx.tbd_count));
794
795 if (tcb_bytes > 2600) {
796 logout("TCB byte count too large, using 2600\n");
797 tcb_bytes = 2600;
798 }
799 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
800 logout
801 ("illegal values of TBD array address and TCB byte count!\n");
802 }
803 assert(tcb_bytes <= sizeof(buf));
804 while (size < tcb_bytes) {
805 uint32_t tx_buffer_address = e100_ldl_le_phys(tbd_address);
806 uint16_t tx_buffer_size = e100_ldw_le_phys(tbd_address + 4);
807 #if 0
808 uint16_t tx_buffer_el = e100_ldw_le_phys(tbd_address + 6);
809 #endif
810 tbd_address += 8;
811 TRACE(RXTX, logout
812 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
813 tx_buffer_address, tx_buffer_size));
814 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
815 cpu_physical_memory_read(tx_buffer_address, &buf[size],
816 tx_buffer_size);
817 size += tx_buffer_size;
818 }
819 if (tbd_array == 0xffffffff) {
820 /* Simplified mode. Was already handled by code above. */
821 } else {
822 /* Flexible mode. */
823 uint8_t tbd_count = 0;
824 if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
825 /* Extended Flexible TCB. */
826 for (; tbd_count < 2; tbd_count++) {
827 uint32_t tx_buffer_address = e100_ldl_le_phys(tbd_address);
828 uint16_t tx_buffer_size = e100_ldw_le_phys(tbd_address + 4);
829 uint16_t tx_buffer_el = e100_ldw_le_phys(tbd_address + 6);
830 tbd_address += 8;
831 TRACE(RXTX, logout
832 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
833 tx_buffer_address, tx_buffer_size));
834 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
835 cpu_physical_memory_read(tx_buffer_address, &buf[size],
836 tx_buffer_size);
837 size += tx_buffer_size;
838 if (tx_buffer_el & 1) {
839 break;
840 }
841 }
842 }
843 tbd_address = tbd_array;
844 for (; tbd_count < s->tx.tbd_count; tbd_count++) {
845 uint32_t tx_buffer_address = e100_ldl_le_phys(tbd_address);
846 uint16_t tx_buffer_size = e100_ldw_le_phys(tbd_address + 4);
847 uint16_t tx_buffer_el = e100_ldw_le_phys(tbd_address + 6);
848 tbd_address += 8;
849 TRACE(RXTX, logout
850 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
851 tx_buffer_address, tx_buffer_size));
852 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
853 cpu_physical_memory_read(tx_buffer_address, &buf[size],
854 tx_buffer_size);
855 size += tx_buffer_size;
856 if (tx_buffer_el & 1) {
857 break;
858 }
859 }
860 }
861 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
862 qemu_send_packet(&s->nic->nc, buf, size);
863 s->statistics.tx_good_frames++;
864 /* Transmit with bad status would raise an CX/TNO interrupt.
865 * (82557 only). Emulation never has bad status. */
866 #if 0
867 eepro100_cx_interrupt(s);
868 #endif
869 }
870
871 static void set_multicast_list(EEPRO100State *s)
872 {
873 uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0);
874 uint16_t i;
875 memset(&s->mult[0], 0, sizeof(s->mult));
876 TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
877 for (i = 0; i < multicast_count; i += 6) {
878 uint8_t multicast_addr[6];
879 cpu_physical_memory_read(s->cb_address + 10 + i, multicast_addr, 6);
880 TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6)));
881 unsigned mcast_idx = compute_mcast_idx(multicast_addr);
882 assert(mcast_idx < 64);
883 s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7));
884 }
885 }
886
887 static void action_command(EEPRO100State *s)
888 {
889 for (;;) {
890 bool bit_el;
891 bool bit_s;
892 bool bit_i;
893 bool bit_nc;
894 uint16_t ok_status = STATUS_OK;
895 s->cb_address = s->cu_base + s->cu_offset;
896 read_cb(s);
897 bit_el = ((s->tx.command & COMMAND_EL) != 0);
898 bit_s = ((s->tx.command & COMMAND_S) != 0);
899 bit_i = ((s->tx.command & COMMAND_I) != 0);
900 bit_nc = ((s->tx.command & COMMAND_NC) != 0);
901 #if 0
902 bool bit_sf = ((s->tx.command & COMMAND_SF) != 0);
903 #endif
904 s->cu_offset = s->tx.link;
905 TRACE(OTHER,
906 logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
907 s->tx.status, s->tx.command, s->tx.link));
908 switch (s->tx.command & COMMAND_CMD) {
909 case CmdNOp:
910 /* Do nothing. */
911 break;
912 case CmdIASetup:
913 cpu_physical_memory_read(s->cb_address + 8, &s->conf.macaddr.a[0], 6);
914 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)));
915 break;
916 case CmdConfigure:
917 cpu_physical_memory_read(s->cb_address + 8, &s->configuration[0],
918 sizeof(s->configuration));
919 TRACE(OTHER, logout("configuration: %s\n",
920 nic_dump(&s->configuration[0], 16)));
921 TRACE(OTHER, logout("configuration: %s\n",
922 nic_dump(&s->configuration[16],
923 ARRAY_SIZE(s->configuration) - 16)));
924 if (s->configuration[20] & BIT(6)) {
925 TRACE(OTHER, logout("Multiple IA bit\n"));
926 }
927 break;
928 case CmdMulticastList:
929 set_multicast_list(s);
930 break;
931 case CmdTx:
932 if (bit_nc) {
933 missing("CmdTx: NC = 0");
934 ok_status = 0;
935 break;
936 }
937 tx_command(s);
938 break;
939 case CmdTDR:
940 TRACE(OTHER, logout("load microcode\n"));
941 /* Starting with offset 8, the command contains
942 * 64 dwords microcode which we just ignore here. */
943 break;
944 case CmdDiagnose:
945 TRACE(OTHER, logout("diagnose\n"));
946 /* Make sure error flag is not set. */
947 s->tx.status = 0;
948 break;
949 default:
950 missing("undefined command");
951 ok_status = 0;
952 break;
953 }
954 /* Write new status. */
955 e100_stw_le_phys(s->cb_address, s->tx.status | ok_status | STATUS_C);
956 if (bit_i) {
957 /* CU completed action. */
958 eepro100_cx_interrupt(s);
959 }
960 if (bit_el) {
961 /* CU becomes idle. Terminate command loop. */
962 set_cu_state(s, cu_idle);
963 eepro100_cna_interrupt(s);
964 break;
965 } else if (bit_s) {
966 /* CU becomes suspended. Terminate command loop. */
967 set_cu_state(s, cu_suspended);
968 eepro100_cna_interrupt(s);
969 break;
970 } else {
971 /* More entries in list. */
972 TRACE(OTHER, logout("CU list with at least one more entry\n"));
973 }
974 }
975 TRACE(OTHER, logout("CU list empty\n"));
976 /* List is empty. Now CU is idle or suspended. */
977 }
978
979 static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
980 {
981 cu_state_t cu_state;
982 switch (val) {
983 case CU_NOP:
984 /* No operation. */
985 break;
986 case CU_START:
987 cu_state = get_cu_state(s);
988 if (cu_state != cu_idle && cu_state != cu_suspended) {
989 /* Intel documentation says that CU must be idle or suspended
990 * for the CU start command. */
991 logout("unexpected CU state is %u\n", cu_state);
992 }
993 set_cu_state(s, cu_active);
994 s->cu_offset = s->pointer;
995 action_command(s);
996 break;
997 case CU_RESUME:
998 if (get_cu_state(s) != cu_suspended) {
999 logout("bad CU resume from CU state %u\n", get_cu_state(s));
1000 /* Workaround for bad Linux eepro100 driver which resumes
1001 * from idle state. */
1002 #if 0
1003 missing("cu resume");
1004 #endif
1005 set_cu_state(s, cu_suspended);
1006 }
1007 if (get_cu_state(s) == cu_suspended) {
1008 TRACE(OTHER, logout("CU resuming\n"));
1009 set_cu_state(s, cu_active);
1010 action_command(s);
1011 }
1012 break;
1013 case CU_STATSADDR:
1014 /* Load dump counters address. */
1015 s->statsaddr = s->pointer;
1016 TRACE(OTHER, logout("val=0x%02x (status address)\n", val));
1017 break;
1018 case CU_SHOWSTATS:
1019 /* Dump statistical counters. */
1020 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
1021 dump_statistics(s);
1022 e100_stl_le_phys(s->statsaddr + s->stats_size, 0xa005);
1023 break;
1024 case CU_CMD_BASE:
1025 /* Load CU base. */
1026 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
1027 s->cu_base = s->pointer;
1028 break;
1029 case CU_DUMPSTATS:
1030 /* Dump and reset statistical counters. */
1031 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
1032 dump_statistics(s);
1033 e100_stl_le_phys(s->statsaddr + s->stats_size, 0xa007);
1034 memset(&s->statistics, 0, sizeof(s->statistics));
1035 break;
1036 case CU_SRESUME:
1037 /* CU static resume. */
1038 missing("CU static resume");
1039 break;
1040 default:
1041 missing("Undefined CU command");
1042 }
1043 }
1044
1045 static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
1046 {
1047 switch (val) {
1048 case RU_NOP:
1049 /* No operation. */
1050 break;
1051 case RX_START:
1052 /* RU start. */
1053 if (get_ru_state(s) != ru_idle) {
1054 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
1055 #if 0
1056 assert(!"wrong RU state");
1057 #endif
1058 }
1059 set_ru_state(s, ru_ready);
1060 s->ru_offset = s->pointer;
1061 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
1062 break;
1063 case RX_RESUME:
1064 /* Restart RU. */
1065 if (get_ru_state(s) != ru_suspended) {
1066 logout("RU state is %u, should be %u\n", get_ru_state(s),
1067 ru_suspended);
1068 #if 0
1069 assert(!"wrong RU state");
1070 #endif
1071 }
1072 set_ru_state(s, ru_ready);
1073 break;
1074 case RU_ABORT:
1075 /* RU abort. */
1076 if (get_ru_state(s) == ru_ready) {
1077 eepro100_rnr_interrupt(s);
1078 }
1079 set_ru_state(s, ru_idle);
1080 break;
1081 case RX_ADDR_LOAD:
1082 /* Load RU base. */
1083 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
1084 s->ru_base = s->pointer;
1085 break;
1086 default:
1087 logout("val=0x%02x (undefined RU command)\n", val);
1088 missing("Undefined SU command");
1089 }
1090 }
1091
1092 static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1093 {
1094 eepro100_ru_command(s, val & 0x0f);
1095 eepro100_cu_command(s, val & 0xf0);
1096 if ((val) == 0) {
1097 TRACE(OTHER, logout("val=0x%02x\n", val));
1098 }
1099 /* Clear command byte after command was accepted. */
1100 s->mem[SCBCmd] = 0;
1101 }
1102
1103 /*****************************************************************************
1104 *
1105 * EEPROM emulation.
1106 *
1107 ****************************************************************************/
1108
1109 #define EEPROM_CS 0x02
1110 #define EEPROM_SK 0x01
1111 #define EEPROM_DI 0x04
1112 #define EEPROM_DO 0x08
1113
1114 static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1115 {
1116 uint16_t val = e100_read_reg2(s, SCBeeprom);
1117 if (eeprom93xx_read(s->eeprom)) {
1118 val |= EEPROM_DO;
1119 } else {
1120 val &= ~EEPROM_DO;
1121 }
1122 TRACE(EEPROM, logout("val=0x%04x\n", val));
1123 return val;
1124 }
1125
1126 static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
1127 {
1128 TRACE(EEPROM, logout("val=0x%02x\n", val));
1129
1130 /* mask unwriteable bits */
1131 #if 0
1132 val = SET_MASKED(val, 0x31, eeprom->value);
1133 #endif
1134
1135 int eecs = ((val & EEPROM_CS) != 0);
1136 int eesk = ((val & EEPROM_SK) != 0);
1137 int eedi = ((val & EEPROM_DI) != 0);
1138 eeprom93xx_write(eeprom, eecs, eesk, eedi);
1139 }
1140
1141 static void eepro100_write_pointer(EEPRO100State * s, uint32_t val)
1142 {
1143 s->pointer = le32_to_cpu(val);
1144 TRACE(OTHER, logout("val=0x%08x\n", val));
1145 }
1146
1147 /*****************************************************************************
1148 *
1149 * MDI emulation.
1150 *
1151 ****************************************************************************/
1152
1153 #if defined(DEBUG_EEPRO100)
1154 static const char * const mdi_op_name[] = {
1155 "opcode 0",
1156 "write",
1157 "read",
1158 "opcode 3"
1159 };
1160
1161 static const char * const mdi_reg_name[] = {
1162 "Control",
1163 "Status",
1164 "PHY Identification (Word 1)",
1165 "PHY Identification (Word 2)",
1166 "Auto-Negotiation Advertisement",
1167 "Auto-Negotiation Link Partner Ability",
1168 "Auto-Negotiation Expansion"
1169 };
1170
1171 static const char *reg2name(uint8_t reg)
1172 {
1173 static char buffer[10];
1174 const char *p = buffer;
1175 if (reg < ARRAY_SIZE(mdi_reg_name)) {
1176 p = mdi_reg_name[reg];
1177 } else {
1178 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1179 }
1180 return p;
1181 }
1182 #endif /* DEBUG_EEPRO100 */
1183
1184 static uint32_t eepro100_read_mdi(EEPRO100State * s)
1185 {
1186 uint32_t val = e100_read_reg4(s, SCBCtrlMDI);
1187
1188 #ifdef DEBUG_EEPRO100
1189 uint8_t raiseint = (val & BIT(29)) >> 29;
1190 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1191 uint8_t phy = (val & BITS(25, 21)) >> 21;
1192 uint8_t reg = (val & BITS(20, 16)) >> 16;
1193 uint16_t data = (val & BITS(15, 0));
1194 #endif
1195 /* Emulation takes no time to finish MDI transaction. */
1196 val |= BIT(28);
1197 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1198 val, raiseint, mdi_op_name[opcode], phy,
1199 reg2name(reg), data));
1200 return val;
1201 }
1202
1203 static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
1204 {
1205 uint8_t raiseint = (val & BIT(29)) >> 29;
1206 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1207 uint8_t phy = (val & BITS(25, 21)) >> 21;
1208 uint8_t reg = (val & BITS(20, 16)) >> 16;
1209 uint16_t data = (val & BITS(15, 0));
1210 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1211 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
1212 if (phy != 1) {
1213 /* Unsupported PHY address. */
1214 #if 0
1215 logout("phy must be 1 but is %u\n", phy);
1216 #endif
1217 data = 0;
1218 } else if (opcode != 1 && opcode != 2) {
1219 /* Unsupported opcode. */
1220 logout("opcode must be 1 or 2 but is %u\n", opcode);
1221 data = 0;
1222 } else if (reg > 6) {
1223 /* Unsupported register. */
1224 logout("register must be 0...6 but is %u\n", reg);
1225 data = 0;
1226 } else {
1227 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1228 val, raiseint, mdi_op_name[opcode], phy,
1229 reg2name(reg), data));
1230 if (opcode == 1) {
1231 /* MDI write */
1232 switch (reg) {
1233 case 0: /* Control Register */
1234 if (data & 0x8000) {
1235 /* Reset status and control registers to default. */
1236 s->mdimem[0] = eepro100_mdi_default[0];
1237 s->mdimem[1] = eepro100_mdi_default[1];
1238 data = s->mdimem[reg];
1239 } else {
1240 /* Restart Auto Configuration = Normal Operation */
1241 data &= ~0x0200;
1242 }
1243 break;
1244 case 1: /* Status Register */
1245 missing("not writable");
1246 data = s->mdimem[reg];
1247 break;
1248 case 2: /* PHY Identification Register (Word 1) */
1249 case 3: /* PHY Identification Register (Word 2) */
1250 missing("not implemented");
1251 break;
1252 case 4: /* Auto-Negotiation Advertisement Register */
1253 case 5: /* Auto-Negotiation Link Partner Ability Register */
1254 break;
1255 case 6: /* Auto-Negotiation Expansion Register */
1256 default:
1257 missing("not implemented");
1258 }
1259 s->mdimem[reg] = data;
1260 } else if (opcode == 2) {
1261 /* MDI read */
1262 switch (reg) {
1263 case 0: /* Control Register */
1264 if (data & 0x8000) {
1265 /* Reset status and control registers to default. */
1266 s->mdimem[0] = eepro100_mdi_default[0];
1267 s->mdimem[1] = eepro100_mdi_default[1];
1268 }
1269 break;
1270 case 1: /* Status Register */
1271 s->mdimem[reg] |= 0x0020;
1272 break;
1273 case 2: /* PHY Identification Register (Word 1) */
1274 case 3: /* PHY Identification Register (Word 2) */
1275 case 4: /* Auto-Negotiation Advertisement Register */
1276 break;
1277 case 5: /* Auto-Negotiation Link Partner Ability Register */
1278 s->mdimem[reg] = 0x41fe;
1279 break;
1280 case 6: /* Auto-Negotiation Expansion Register */
1281 s->mdimem[reg] = 0x0001;
1282 break;
1283 }
1284 data = s->mdimem[reg];
1285 }
1286 /* Emulation takes no time to finish MDI transaction.
1287 * Set MDI bit in SCB status register. */
1288 s->mem[SCBAck] |= 0x08;
1289 val |= BIT(28);
1290 if (raiseint) {
1291 eepro100_mdi_interrupt(s);
1292 }
1293 }
1294 val = (val & 0xffff0000) + data;
1295 e100_write_reg4(s, SCBCtrlMDI, val);
1296 }
1297
1298 /*****************************************************************************
1299 *
1300 * Port emulation.
1301 *
1302 ****************************************************************************/
1303
1304 #define PORT_SOFTWARE_RESET 0
1305 #define PORT_SELFTEST 1
1306 #define PORT_SELECTIVE_RESET 2
1307 #define PORT_DUMP 3
1308 #define PORT_SELECTION_MASK 3
1309
1310 typedef struct {
1311 uint32_t st_sign; /* Self Test Signature */
1312 uint32_t st_result; /* Self Test Results */
1313 } eepro100_selftest_t;
1314
1315 static uint32_t eepro100_read_port(EEPRO100State * s)
1316 {
1317 return 0;
1318 }
1319
1320 static void eepro100_write_port(EEPRO100State *s)
1321 {
1322 uint32_t val = e100_read_reg4(s, SCBPort);
1323 uint32_t address = (val & ~PORT_SELECTION_MASK);
1324 uint8_t selection = (val & PORT_SELECTION_MASK);
1325 switch (selection) {
1326 case PORT_SOFTWARE_RESET:
1327 nic_reset(s);
1328 break;
1329 case PORT_SELFTEST:
1330 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
1331 eepro100_selftest_t data;
1332 cpu_physical_memory_read(address, &data, sizeof(data));
1333 data.st_sign = 0xffffffff;
1334 data.st_result = 0;
1335 cpu_physical_memory_write(address, &data, sizeof(data));
1336 break;
1337 case PORT_SELECTIVE_RESET:
1338 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
1339 nic_selective_reset(s);
1340 break;
1341 default:
1342 logout("val=0x%08x\n", val);
1343 missing("unknown port selection");
1344 }
1345 }
1346
1347 /*****************************************************************************
1348 *
1349 * General hardware emulation.
1350 *
1351 ****************************************************************************/
1352
1353 static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1354 {
1355 uint8_t val = 0;
1356 if (addr <= sizeof(s->mem) - sizeof(val)) {
1357 val = s->mem[addr];
1358 }
1359
1360 switch (addr) {
1361 case SCBStatus:
1362 case SCBAck:
1363 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1364 break;
1365 case SCBCmd:
1366 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1367 #if 0
1368 val = eepro100_read_command(s);
1369 #endif
1370 break;
1371 case SCBIntmask:
1372 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1373 break;
1374 case SCBPort + 3:
1375 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1376 break;
1377 case SCBeeprom:
1378 val = eepro100_read_eeprom(s);
1379 break;
1380 case SCBpmdr: /* Power Management Driver Register */
1381 val = 0;
1382 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1383 break;
1384 case SCBgstat: /* General Status Register */
1385 /* 100 Mbps full duplex, valid link */
1386 val = 0x07;
1387 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
1388 break;
1389 default:
1390 logout("addr=%s val=0x%02x\n", regname(addr), val);
1391 missing("unknown byte read");
1392 }
1393 return val;
1394 }
1395
1396 static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1397 {
1398 uint16_t val = 0;
1399 if (addr <= sizeof(s->mem) - sizeof(val)) {
1400 val = e100_read_reg2(s, addr);
1401 }
1402
1403 switch (addr) {
1404 case SCBStatus:
1405 case SCBCmd:
1406 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1407 break;
1408 case SCBeeprom:
1409 val = eepro100_read_eeprom(s);
1410 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1411 break;
1412 default:
1413 logout("addr=%s val=0x%04x\n", regname(addr), val);
1414 missing("unknown word read");
1415 }
1416 return val;
1417 }
1418
1419 static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1420 {
1421 uint32_t val = 0;
1422 if (addr <= sizeof(s->mem) - sizeof(val)) {
1423 val = e100_read_reg4(s, addr);
1424 }
1425
1426 switch (addr) {
1427 case SCBStatus:
1428 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1429 break;
1430 case SCBPointer:
1431 #if 0
1432 val = eepro100_read_pointer(s);
1433 #endif
1434 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1435 break;
1436 case SCBPort:
1437 val = eepro100_read_port(s);
1438 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1439 break;
1440 case SCBCtrlMDI:
1441 val = eepro100_read_mdi(s);
1442 break;
1443 default:
1444 logout("addr=%s val=0x%08x\n", regname(addr), val);
1445 missing("unknown longword read");
1446 }
1447 return val;
1448 }
1449
1450 static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1451 {
1452 /* SCBStatus is readonly. */
1453 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
1454 s->mem[addr] = val;
1455 }
1456
1457 switch (addr) {
1458 case SCBStatus:
1459 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1460 break;
1461 case SCBAck:
1462 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1463 eepro100_acknowledge(s);
1464 break;
1465 case SCBCmd:
1466 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1467 eepro100_write_command(s, val);
1468 break;
1469 case SCBIntmask:
1470 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1471 if (val & BIT(1)) {
1472 eepro100_swi_interrupt(s);
1473 }
1474 eepro100_interrupt(s, 0);
1475 break;
1476 case SCBPort:
1477 case SCBPort + 1:
1478 case SCBPort + 2:
1479 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1480 break;
1481 case SCBPort + 3:
1482 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1483 eepro100_write_port(s);
1484 break;
1485 case SCBFlow: /* does not exist on 82557 */
1486 case SCBFlow + 1:
1487 case SCBFlow + 2:
1488 case SCBpmdr: /* does not exist on 82557 */
1489 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1490 break;
1491 case SCBeeprom:
1492 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1493 eepro100_write_eeprom(s->eeprom, val);
1494 break;
1495 default:
1496 logout("addr=%s val=0x%02x\n", regname(addr), val);
1497 missing("unknown byte write");
1498 }
1499 }
1500
1501 static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1502 {
1503 /* SCBStatus is readonly. */
1504 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
1505 e100_write_reg2(s, addr, val);
1506 }
1507
1508 switch (addr) {
1509 case SCBStatus:
1510 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1511 s->mem[SCBAck] = (val >> 8);
1512 eepro100_acknowledge(s);
1513 break;
1514 case SCBCmd:
1515 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1516 eepro100_write_command(s, val);
1517 eepro100_write1(s, SCBIntmask, val >> 8);
1518 break;
1519 case SCBPort:
1520 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1521 break;
1522 case SCBPort + 2:
1523 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1524 eepro100_write_port(s);
1525 break;
1526 case SCBeeprom:
1527 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1528 eepro100_write_eeprom(s->eeprom, val);
1529 break;
1530 default:
1531 logout("addr=%s val=0x%04x\n", regname(addr), val);
1532 missing("unknown word write");
1533 }
1534 }
1535
1536 static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1537 {
1538 if (addr <= sizeof(s->mem) - sizeof(val)) {
1539 e100_write_reg4(s, addr, val);
1540 }
1541
1542 switch (addr) {
1543 case SCBPointer:
1544 eepro100_write_pointer(s, val);
1545 break;
1546 case SCBPort:
1547 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1548 eepro100_write_port(s);
1549 break;
1550 case SCBCtrlMDI:
1551 eepro100_write_mdi(s, val);
1552 break;
1553 default:
1554 logout("addr=%s val=0x%08x\n", regname(addr), val);
1555 missing("unknown longword write");
1556 }
1557 }
1558
1559 /*****************************************************************************
1560 *
1561 * Port mapped I/O.
1562 *
1563 ****************************************************************************/
1564
1565 static uint32_t ioport_read1(void *opaque, uint32_t addr)
1566 {
1567 EEPRO100State *s = opaque;
1568 #if 0
1569 logout("addr=%s\n", regname(addr));
1570 #endif
1571 return eepro100_read1(s, addr - s->region1);
1572 }
1573
1574 static uint32_t ioport_read2(void *opaque, uint32_t addr)
1575 {
1576 EEPRO100State *s = opaque;
1577 return eepro100_read2(s, addr - s->region1);
1578 }
1579
1580 static uint32_t ioport_read4(void *opaque, uint32_t addr)
1581 {
1582 EEPRO100State *s = opaque;
1583 return eepro100_read4(s, addr - s->region1);
1584 }
1585
1586 static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
1587 {
1588 EEPRO100State *s = opaque;
1589 #if 0
1590 logout("addr=%s val=0x%02x\n", regname(addr), val);
1591 #endif
1592 eepro100_write1(s, addr - s->region1, val);
1593 }
1594
1595 static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
1596 {
1597 EEPRO100State *s = opaque;
1598 eepro100_write2(s, addr - s->region1, val);
1599 }
1600
1601 static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
1602 {
1603 EEPRO100State *s = opaque;
1604 eepro100_write4(s, addr - s->region1, val);
1605 }
1606
1607 /***********************************************************/
1608 /* PCI EEPRO100 definitions */
1609
1610 static void pci_map(PCIDevice * pci_dev, int region_num,
1611 pcibus_t addr, pcibus_t size, int type)
1612 {
1613 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1614
1615 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1616 "size=0x%08"FMT_PCIBUS", type=%d\n",
1617 region_num, addr, size, type));
1618
1619 assert(region_num == 1);
1620 register_ioport_write(addr, size, 1, ioport_write1, s);
1621 register_ioport_read(addr, size, 1, ioport_read1, s);
1622 register_ioport_write(addr, size, 2, ioport_write2, s);
1623 register_ioport_read(addr, size, 2, ioport_read2, s);
1624 register_ioport_write(addr, size, 4, ioport_write4, s);
1625 register_ioport_read(addr, size, 4, ioport_read4, s);
1626
1627 s->region1 = addr;
1628 }
1629
1630 /*****************************************************************************
1631 *
1632 * Memory mapped I/O.
1633 *
1634 ****************************************************************************/
1635
1636 static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1637 {
1638 EEPRO100State *s = opaque;
1639 #if 0
1640 logout("addr=%s val=0x%02x\n", regname(addr), val);
1641 #endif
1642 eepro100_write1(s, addr, val);
1643 }
1644
1645 static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1646 {
1647 EEPRO100State *s = opaque;
1648 #if 0
1649 logout("addr=%s val=0x%02x\n", regname(addr), val);
1650 #endif
1651 eepro100_write2(s, addr, val);
1652 }
1653
1654 static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1655 {
1656 EEPRO100State *s = opaque;
1657 #if 0
1658 logout("addr=%s val=0x%02x\n", regname(addr), val);
1659 #endif
1660 eepro100_write4(s, addr, val);
1661 }
1662
1663 static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
1664 {
1665 EEPRO100State *s = opaque;
1666 #if 0
1667 logout("addr=%s\n", regname(addr));
1668 #endif
1669 return eepro100_read1(s, addr);
1670 }
1671
1672 static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
1673 {
1674 EEPRO100State *s = opaque;
1675 #if 0
1676 logout("addr=%s\n", regname(addr));
1677 #endif
1678 return eepro100_read2(s, addr);
1679 }
1680
1681 static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
1682 {
1683 EEPRO100State *s = opaque;
1684 #if 0
1685 logout("addr=%s\n", regname(addr));
1686 #endif
1687 return eepro100_read4(s, addr);
1688 }
1689
1690 static CPUWriteMemoryFunc * const pci_mmio_write[] = {
1691 pci_mmio_writeb,
1692 pci_mmio_writew,
1693 pci_mmio_writel
1694 };
1695
1696 static CPUReadMemoryFunc * const pci_mmio_read[] = {
1697 pci_mmio_readb,
1698 pci_mmio_readw,
1699 pci_mmio_readl
1700 };
1701
1702 static int nic_can_receive(VLANClientState *nc)
1703 {
1704 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1705 TRACE(RXTX, logout("%p\n", s));
1706 return get_ru_state(s) == ru_ready;
1707 #if 0
1708 return !eepro100_buffer_full(s);
1709 #endif
1710 }
1711
1712 static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size)
1713 {
1714 /* TODO:
1715 * - Magic packets should set bit 30 in power management driver register.
1716 * - Interesting packets should set bit 29 in power management driver register.
1717 */
1718 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1719 uint16_t rfd_status = 0xa000;
1720 #if defined(CONFIG_PAD_RECEIVED_FRAMES)
1721 uint8_t min_buf[60];
1722 #endif
1723 static const uint8_t broadcast_macaddr[6] =
1724 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1725
1726 #if defined(CONFIG_PAD_RECEIVED_FRAMES)
1727 /* Pad to minimum Ethernet frame length */
1728 if (size < sizeof(min_buf)) {
1729 memcpy(min_buf, buf, size);
1730 memset(&min_buf[size], 0, sizeof(min_buf) - size);
1731 buf = min_buf;
1732 size = sizeof(min_buf);
1733 }
1734 #endif
1735
1736 if (s->configuration[8] & 0x80) {
1737 /* CSMA is disabled. */
1738 logout("%p received while CSMA is disabled\n", s);
1739 return -1;
1740 #if !defined(CONFIG_PAD_RECEIVED_FRAMES)
1741 } else if (size < 64 && (s->configuration[7] & BIT(0))) {
1742 /* Short frame and configuration byte 7/0 (discard short receive) set:
1743 * Short frame is discarded */
1744 logout("%p received short frame (%zu byte)\n", s, size);
1745 s->statistics.rx_short_frame_errors++;
1746 return -1;
1747 #endif
1748 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) {
1749 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1750 * Long frames are discarded. */
1751 logout("%p received long frame (%zu byte), ignored\n", s, size);
1752 return -1;
1753 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { /* !!! */
1754 /* Frame matches individual address. */
1755 /* TODO: check configuration byte 15/4 (ignore U/L). */
1756 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
1757 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1758 /* Broadcast frame. */
1759 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
1760 rfd_status |= 0x0002;
1761 } else if (buf[0] & 0x01) {
1762 /* Multicast frame. */
1763 TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size)));
1764 if (s->configuration[21] & BIT(3)) {
1765 /* Multicast all bit is set, receive all multicast frames. */
1766 } else {
1767 unsigned mcast_idx = compute_mcast_idx(buf);
1768 assert(mcast_idx < 64);
1769 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1770 /* Multicast frame is allowed in hash table. */
1771 } else if (s->configuration[15] & BIT(0)) {
1772 /* Promiscuous: receive all. */
1773 rfd_status |= 0x0004;
1774 } else {
1775 TRACE(RXTX, logout("%p multicast ignored\n", s));
1776 return -1;
1777 }
1778 }
1779 /* TODO: Next not for promiscuous mode? */
1780 rfd_status |= 0x0002;
1781 } else if (s->configuration[15] & BIT(0)) {
1782 /* Promiscuous: receive all. */
1783 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
1784 rfd_status |= 0x0004;
1785 } else if (s->configuration[20] & BIT(6)) {
1786 /* Multiple IA bit set. */
1787 unsigned mcast_idx = compute_mcast_idx(buf);
1788 assert(mcast_idx < 64);
1789 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1790 TRACE(RXTX, logout("%p accepted, multiple IA bit set\n", s));
1791 } else {
1792 TRACE(RXTX, logout("%p frame ignored, multiple IA bit set\n", s));
1793 return -1;
1794 }
1795 } else {
1796 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
1797 nic_dump(buf, size)));
1798 return size;
1799 }
1800
1801 if (get_ru_state(s) != ru_ready) {
1802 /* No resources available. */
1803 logout("no resources, state=%u\n", get_ru_state(s));
1804 /* TODO: RNR interrupt only at first failed frame? */
1805 eepro100_rnr_interrupt(s);
1806 s->statistics.rx_resource_errors++;
1807 #if 0
1808 assert(!"no resources");
1809 #endif
1810 return -1;
1811 }
1812 /* !!! */
1813 eepro100_rx_t rx;
1814 cpu_physical_memory_read(s->ru_base + s->ru_offset, &rx,
1815 sizeof(eepro100_rx_t));
1816 uint16_t rfd_command = le16_to_cpu(rx.command);
1817 uint16_t rfd_size = le16_to_cpu(rx.size);
1818
1819 if (size > rfd_size) {
1820 logout("Receive buffer (%" PRId16 " bytes) too small for data "
1821 "(%zu bytes); data truncated\n", rfd_size, size);
1822 size = rfd_size;
1823 }
1824 #if !defined(CONFIG_PAD_RECEIVED_FRAMES)
1825 if (size < 64) {
1826 rfd_status |= 0x0080;
1827 }
1828 #endif
1829 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1830 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
1831 e100_stw_le_phys(s->ru_base + s->ru_offset +
1832 offsetof(eepro100_rx_t, status), rfd_status);
1833 e100_stw_le_phys(s->ru_base + s->ru_offset +
1834 offsetof(eepro100_rx_t, count), size);
1835 /* Early receive interrupt not supported. */
1836 #if 0
1837 eepro100_er_interrupt(s);
1838 #endif
1839 /* Receive CRC Transfer not supported. */
1840 if (s->configuration[18] & BIT(2)) {
1841 missing("Receive CRC Transfer");
1842 return -1;
1843 }
1844 /* TODO: check stripping enable bit. */
1845 #if 0
1846 assert(!(s->configuration[17] & BIT(0)));
1847 #endif
1848 cpu_physical_memory_write(s->ru_base + s->ru_offset +
1849 sizeof(eepro100_rx_t), buf, size);
1850 s->statistics.rx_good_frames++;
1851 eepro100_fr_interrupt(s);
1852 s->ru_offset = le32_to_cpu(rx.link);
1853 if (rfd_command & COMMAND_EL) {
1854 /* EL bit is set, so this was the last frame. */
1855 logout("receive: Running out of frames\n");
1856 set_ru_state(s, ru_suspended);
1857 }
1858 if (rfd_command & COMMAND_S) {
1859 /* S bit is set. */
1860 set_ru_state(s, ru_suspended);
1861 }
1862 return size;
1863 }
1864
1865 static const VMStateDescription vmstate_eepro100 = {
1866 .version_id = 3,
1867 .minimum_version_id = 2,
1868 .minimum_version_id_old = 2,
1869 .fields = (VMStateField []) {
1870 VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1871 VMSTATE_UNUSED(32),
1872 VMSTATE_BUFFER(mult, EEPRO100State),
1873 VMSTATE_BUFFER(mem, EEPRO100State),
1874 /* Save all members of struct between scb_stat and mem. */
1875 VMSTATE_UINT8(scb_stat, EEPRO100State),
1876 VMSTATE_UINT8(int_stat, EEPRO100State),
1877 VMSTATE_UNUSED(3*4),
1878 VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1879 VMSTATE_UNUSED(19*4),
1880 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1881 /* The eeprom should be saved and restored by its own routines. */
1882 VMSTATE_UINT32(device, EEPRO100State),
1883 /* TODO check device. */
1884 VMSTATE_UINT32(pointer, EEPRO100State),
1885 VMSTATE_UINT32(cu_base, EEPRO100State),
1886 VMSTATE_UINT32(cu_offset, EEPRO100State),
1887 VMSTATE_UINT32(ru_base, EEPRO100State),
1888 VMSTATE_UINT32(ru_offset, EEPRO100State),
1889 VMSTATE_UINT32(statsaddr, EEPRO100State),
1890 /* Save eepro100_stats_t statistics. */
1891 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1892 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1893 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1894 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1895 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1896 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1897 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1898 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1899 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1900 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1901 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1902 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1903 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1904 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1905 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1906 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1907 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1908 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1909 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1910 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1911 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
1912 /* Configuration bytes. */
1913 VMSTATE_BUFFER(configuration, EEPRO100State),
1914 VMSTATE_END_OF_LIST()
1915 }
1916 };
1917
1918 static void nic_cleanup(VLANClientState *nc)
1919 {
1920 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1921
1922 s->nic = NULL;
1923 }
1924
1925 static int pci_nic_uninit(PCIDevice *pci_dev)
1926 {
1927 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1928
1929 cpu_unregister_io_memory(s->mmio_index);
1930 vmstate_unregister(&pci_dev->qdev, s->vmstate, s);
1931 eeprom93xx_free(&pci_dev->qdev, s->eeprom);
1932 qemu_del_vlan_client(&s->nic->nc);
1933 return 0;
1934 }
1935
1936 static NetClientInfo net_eepro100_info = {
1937 .type = NET_CLIENT_TYPE_NIC,
1938 .size = sizeof(NICState),
1939 .can_receive = nic_can_receive,
1940 .receive = nic_receive,
1941 .cleanup = nic_cleanup,
1942 };
1943
1944 static int e100_nic_init(PCIDevice *pci_dev)
1945 {
1946 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1947 E100PCIDeviceInfo *e100_device = DO_UPCAST(E100PCIDeviceInfo, pci.qdev,
1948 pci_dev->qdev.info);
1949
1950 TRACE(OTHER, logout("\n"));
1951
1952 s->device = e100_device->device;
1953
1954 e100_pci_reset(s, e100_device);
1955
1956 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1957 * i82559 and later support 64 or 256 word EEPROM. */
1958 s->eeprom = eeprom93xx_new(&pci_dev->qdev, EEPROM_SIZE);
1959
1960 /* Handler for memory-mapped I/O */
1961 s->mmio_index =
1962 cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s,
1963 DEVICE_LITTLE_ENDIAN);
1964
1965 pci_register_bar_simple(&s->dev, 0, PCI_MEM_SIZE,
1966 PCI_BASE_ADDRESS_MEM_PREFETCH, s->mmio_index);
1967
1968 pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
1969 pci_map);
1970 pci_register_bar_simple(&s->dev, 2, PCI_FLASH_SIZE, 0, s->mmio_index);
1971
1972 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1973 logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));
1974 assert(s->region1 == 0);
1975
1976 nic_reset(s);
1977
1978 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
1979 pci_dev->qdev.info->name, pci_dev->qdev.id, s);
1980
1981 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
1982 TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
1983
1984 qemu_register_reset(nic_reset, s);
1985
1986 s->vmstate = qemu_malloc(sizeof(vmstate_eepro100));
1987 memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
1988 s->vmstate->name = s->nic->nc.model;
1989 vmstate_register(&pci_dev->qdev, -1, s->vmstate, s);
1990
1991 add_boot_device_path(s->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
1992
1993 return 0;
1994 }
1995
1996 static E100PCIDeviceInfo e100_devices[] = {
1997 {
1998 .pci.qdev.name = "i82550",
1999 .pci.qdev.desc = "Intel i82550 Ethernet",
2000 .device = i82550,
2001 /* TODO: check device id. */
2002 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
2003 /* Revision ID: 0x0c, 0x0d, 0x0e. */
2004 .revision = 0x0e,
2005 /* TODO: check size of statistical counters. */
2006 .stats_size = 80,
2007 /* TODO: check extended tcb support. */
2008 .has_extended_tcb_support = true,
2009 .power_management = true,
2010 },{
2011 .pci.qdev.name = "i82551",
2012 .pci.qdev.desc = "Intel i82551 Ethernet",
2013 .device = i82551,
2014 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
2015 /* Revision ID: 0x0f, 0x10. */
2016 .revision = 0x0f,
2017 /* TODO: check size of statistical counters. */
2018 .stats_size = 80,
2019 .has_extended_tcb_support = true,
2020 .power_management = true,
2021 },{
2022 .pci.qdev.name = "i82557a",
2023 .pci.qdev.desc = "Intel i82557A Ethernet",
2024 .device = i82557A,
2025 .device_id = PCI_DEVICE_ID_INTEL_82557,
2026 .revision = 0x01,
2027 .power_management = false,
2028 },{
2029 .pci.qdev.name = "i82557b",
2030 .pci.qdev.desc = "Intel i82557B Ethernet",
2031 .device = i82557B,
2032 .device_id = PCI_DEVICE_ID_INTEL_82557,
2033 .revision = 0x02,
2034 .power_management = false,
2035 },{
2036 .pci.qdev.name = "i82557c",
2037 .pci.qdev.desc = "Intel i82557C Ethernet",
2038 .device = i82557C,
2039 .device_id = PCI_DEVICE_ID_INTEL_82557,
2040 .revision = 0x03,
2041 .power_management = false,
2042 },{
2043 .pci.qdev.name = "i82558a",
2044 .pci.qdev.desc = "Intel i82558A Ethernet",
2045 .device = i82558A,
2046 .device_id = PCI_DEVICE_ID_INTEL_82557,
2047 .revision = 0x04,
2048 .stats_size = 76,
2049 .has_extended_tcb_support = true,
2050 .power_management = true,
2051 },{
2052 .pci.qdev.name = "i82558b",
2053 .pci.qdev.desc = "Intel i82558B Ethernet",
2054 .device = i82558B,
2055 .device_id = PCI_DEVICE_ID_INTEL_82557,
2056 .revision = 0x05,
2057 .stats_size = 76,
2058 .has_extended_tcb_support = true,
2059 .power_management = true,
2060 },{
2061 .pci.qdev.name = "i82559a",
2062 .pci.qdev.desc = "Intel i82559A Ethernet",
2063 .device = i82559A,
2064 .device_id = PCI_DEVICE_ID_INTEL_82557,
2065 .revision = 0x06,
2066 .stats_size = 80,
2067 .has_extended_tcb_support = true,
2068 .power_management = true,
2069 },{
2070 .pci.qdev.name = "i82559b",
2071 .pci.qdev.desc = "Intel i82559B Ethernet",
2072 .device = i82559B,
2073 .device_id = PCI_DEVICE_ID_INTEL_82557,
2074 .revision = 0x07,
2075 .stats_size = 80,
2076 .has_extended_tcb_support = true,
2077 .power_management = true,
2078 },{
2079 .pci.qdev.name = "i82559c",
2080 .pci.qdev.desc = "Intel i82559C Ethernet",
2081 .device = i82559C,
2082 .device_id = PCI_DEVICE_ID_INTEL_82557,
2083 #if 0
2084 .revision = 0x08,
2085 #endif
2086 /* TODO: Windows wants revision id 0x0c. */
2087 .revision = 0x0c,
2088 .stats_size = 80,
2089 .has_extended_tcb_support = true,
2090 .power_management = true,
2091 },{
2092 .pci.qdev.name = "i82559er",
2093 .pci.qdev.desc = "Intel i82559ER Ethernet",
2094 .device = i82559ER,
2095 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
2096 .revision = 0x09,
2097 .stats_size = 80,
2098 .has_extended_tcb_support = true,
2099 .power_management = true,
2100 },{
2101 .pci.qdev.name = "i82562",
2102 .pci.qdev.desc = "Intel i82562 Ethernet",
2103 .device = i82562,
2104 /* TODO: check device id. */
2105 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
2106 /* TODO: wrong revision id. */
2107 .revision = 0x0e,
2108 .stats_size = 80,
2109 .has_extended_tcb_support = true,
2110 .power_management = true,
2111 },{
2112 /* Toshiba Tecra 8200. */
2113 .pci.qdev.name = "i82801",
2114 .pci.qdev.desc = "Intel i82801 Ethernet",
2115 .device = i82801,
2116 .device_id = 0x2449,
2117 .revision = 0x03,
2118 .stats_size = 80,
2119 .has_extended_tcb_support = true,
2120 .power_management = true,
2121 }
2122 };
2123
2124 static Property e100_properties[] = {
2125 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2126 DEFINE_PROP_END_OF_LIST(),
2127 };
2128
2129 static void eepro100_register_devices(void)
2130 {
2131 size_t i;
2132 for (i = 0; i < ARRAY_SIZE(e100_devices); i++) {
2133 PCIDeviceInfo *pci_dev = &e100_devices[i].pci;
2134 /* We use the same rom file for all device ids.
2135 QEMU fixes the device id during rom load. */
2136 pci_dev->romfile = "gpxe-eepro100-80861209.rom";
2137 pci_dev->init = e100_nic_init;
2138 pci_dev->exit = pci_nic_uninit;
2139 pci_dev->qdev.props = e100_properties;
2140 pci_dev->qdev.size = sizeof(EEPRO100State);
2141 pci_qdev_register(pci_dev);
2142 }
2143 }
2144
2145 device_init(eepro100_register_devices)
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