eepro100: Support byte/word writes to pointer register
[qemu.git] / hw / eepro100.c
1 /*
2 * QEMU i8255x (PRO100) emulation
3 *
4 * Copyright (C) 2006-2011 Stefan Weil
5 *
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 2 of the License, or
12 * (at your option) version 3 or any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 *
22 * Tested features (i82559):
23 * PXE boot (i386 guest, i386 / mips / mipsel / ppc host) ok
24 * Linux networking (i386) ok
25 *
26 * Untested:
27 * Windows networking
28 *
29 * References:
30 *
31 * Intel 8255x 10/100 Mbps Ethernet Controller Family
32 * Open Source Software Developer Manual
33 *
34 * TODO:
35 * * PHY emulation should be separated from nic emulation.
36 * Most nic emulations could share the same phy code.
37 * * i82550 is untested. It is programmed like the i82559.
38 * * i82562 is untested. It is programmed like the i82559.
39 * * Power management (i82558 and later) is not implemented.
40 * * Wake-on-LAN is not implemented.
41 */
42
43 #include <stddef.h> /* offsetof */
44 #include "hw.h"
45 #include "pci.h"
46 #include "net.h"
47 #include "eeprom93xx.h"
48 #include "sysemu.h"
49
50 /* QEMU sends frames smaller than 60 bytes to ethernet nics.
51 * Such frames are rejected by real nics and their emulations.
52 * To avoid this behaviour, other nic emulations pad received
53 * frames. The following definition enables this padding for
54 * eepro100, too. We keep the define around in case it might
55 * become useful the future if the core networking is ever
56 * changed to pad short packets itself. */
57 #define CONFIG_PAD_RECEIVED_FRAMES
58
59 #define KiB 1024
60
61 /* Debug EEPRO100 card. */
62 #if 0
63 # define DEBUG_EEPRO100
64 #endif
65
66 #ifdef DEBUG_EEPRO100
67 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
68 #else
69 #define logout(fmt, ...) ((void)0)
70 #endif
71
72 /* Set flags to 0 to disable debug output. */
73 #define INT 1 /* interrupt related actions */
74 #define MDI 1 /* mdi related actions */
75 #define OTHER 1
76 #define RXTX 1
77 #define EEPROM 1 /* eeprom related actions */
78
79 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
80
81 #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
82
83 #define MAX_ETH_FRAME_SIZE 1514
84
85 /* This driver supports several different devices which are declared here. */
86 #define i82550 0x82550
87 #define i82551 0x82551
88 #define i82557A 0x82557a
89 #define i82557B 0x82557b
90 #define i82557C 0x82557c
91 #define i82558A 0x82558a
92 #define i82558B 0x82558b
93 #define i82559A 0x82559a
94 #define i82559B 0x82559b
95 #define i82559C 0x82559c
96 #define i82559ER 0x82559e
97 #define i82562 0x82562
98 #define i82801 0x82801
99
100 /* Use 64 word EEPROM. TODO: could be a runtime option. */
101 #define EEPROM_SIZE 64
102
103 #define PCI_MEM_SIZE (4 * KiB)
104 #define PCI_IO_SIZE 64
105 #define PCI_FLASH_SIZE (128 * KiB)
106
107 #define BIT(n) (1 << (n))
108 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
109
110 /* The SCB accepts the following controls for the Tx and Rx units: */
111 #define CU_NOP 0x0000 /* No operation. */
112 #define CU_START 0x0010 /* CU start. */
113 #define CU_RESUME 0x0020 /* CU resume. */
114 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
115 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
116 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
117 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
118 #define CU_SRESUME 0x00a0 /* CU static resume. */
119
120 #define RU_NOP 0x0000
121 #define RX_START 0x0001
122 #define RX_RESUME 0x0002
123 #define RU_ABORT 0x0004
124 #define RX_ADDR_LOAD 0x0006
125 #define RX_RESUMENR 0x0007
126 #define INT_MASK 0x0100
127 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
128
129 typedef struct {
130 PCIDeviceInfo pci;
131 uint32_t device;
132 uint16_t device_id;
133 uint8_t revision;
134 uint8_t stats_size;
135 bool has_extended_tcb_support;
136 bool power_management;
137 } E100PCIDeviceInfo;
138
139 /* Offsets to the various registers.
140 All accesses need not be longword aligned. */
141 typedef enum {
142 SCBStatus = 0, /* Status Word. */
143 SCBAck = 1,
144 SCBCmd = 2, /* Rx/Command Unit command and status. */
145 SCBIntmask = 3,
146 SCBPointer = 4, /* General purpose pointer. */
147 SCBPort = 8, /* Misc. commands and operands. */
148 SCBflash = 12, /* Flash memory control. */
149 SCBeeprom = 14, /* EEPROM control. */
150 SCBCtrlMDI = 16, /* MDI interface control. */
151 SCBEarlyRx = 20, /* Early receive byte count. */
152 SCBFlow = 24, /* Flow Control. */
153 SCBpmdr = 27, /* Power Management Driver. */
154 SCBgctrl = 28, /* General Control. */
155 SCBgstat = 29, /* General Status. */
156 } E100RegisterOffset;
157
158 /* A speedo3 transmit buffer descriptor with two buffers... */
159 typedef struct {
160 uint16_t status;
161 uint16_t command;
162 uint32_t link; /* void * */
163 uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */
164 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
165 uint8_t tx_threshold; /* transmit threshold */
166 uint8_t tbd_count; /* TBD number */
167 #if 0
168 /* This constitutes two "TBD" entries: hdr and data */
169 uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
170 int32_t tx_buf_size0; /* Length of Tx hdr. */
171 uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
172 int32_t tx_buf_size1; /* Length of Tx data. */
173 #endif
174 } eepro100_tx_t;
175
176 /* Receive frame descriptor. */
177 typedef struct {
178 int16_t status;
179 uint16_t command;
180 uint32_t link; /* struct RxFD * */
181 uint32_t rx_buf_addr; /* void * */
182 uint16_t count;
183 uint16_t size;
184 /* Ethernet frame data follows. */
185 } eepro100_rx_t;
186
187 typedef enum {
188 COMMAND_EL = BIT(15),
189 COMMAND_S = BIT(14),
190 COMMAND_I = BIT(13),
191 COMMAND_NC = BIT(4),
192 COMMAND_SF = BIT(3),
193 COMMAND_CMD = BITS(2, 0),
194 } scb_command_bit;
195
196 typedef enum {
197 STATUS_C = BIT(15),
198 STATUS_OK = BIT(13),
199 } scb_status_bit;
200
201 typedef struct {
202 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
203 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
204 tx_multiple_collisions, tx_total_collisions;
205 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
206 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
207 rx_short_frame_errors;
208 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
209 uint16_t xmt_tco_frames, rcv_tco_frames;
210 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
211 uint32_t reserved[4];
212 } eepro100_stats_t;
213
214 typedef enum {
215 cu_idle = 0,
216 cu_suspended = 1,
217 cu_active = 2,
218 cu_lpq_active = 2,
219 cu_hqp_active = 3
220 } cu_state_t;
221
222 typedef enum {
223 ru_idle = 0,
224 ru_suspended = 1,
225 ru_no_resources = 2,
226 ru_ready = 4
227 } ru_state_t;
228
229 typedef struct {
230 PCIDevice dev;
231 /* Hash register (multicast mask array, multiple individual addresses). */
232 uint8_t mult[8];
233 int mmio_index;
234 NICState *nic;
235 NICConf conf;
236 uint8_t scb_stat; /* SCB stat/ack byte */
237 uint8_t int_stat; /* PCI interrupt status */
238 /* region must not be saved by nic_save. */
239 uint32_t region1; /* PCI region 1 address */
240 uint16_t mdimem[32];
241 eeprom_t *eeprom;
242 uint32_t device; /* device variant */
243 /* (cu_base + cu_offset) address the next command block in the command block list. */
244 uint32_t cu_base; /* CU base address */
245 uint32_t cu_offset; /* CU address offset */
246 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
247 uint32_t ru_base; /* RU base address */
248 uint32_t ru_offset; /* RU address offset */
249 uint32_t statsaddr; /* pointer to eepro100_stats_t */
250
251 /* Temporary status information (no need to save these values),
252 * used while processing CU commands. */
253 eepro100_tx_t tx; /* transmit buffer descriptor */
254 uint32_t cb_address; /* = cu_base + cu_offset */
255
256 /* Statistical counters. Also used for wake-up packet (i82559). */
257 eepro100_stats_t statistics;
258
259 /* Data in mem is always in the byte order of the controller (le).
260 * It must be dword aligned to allow direct access to 32 bit values. */
261 uint8_t mem[PCI_MEM_SIZE] __attribute__((aligned(8)));;
262
263 /* Configuration bytes. */
264 uint8_t configuration[22];
265
266 /* vmstate for each particular nic */
267 VMStateDescription *vmstate;
268
269 /* Quasi static device properties (no need to save them). */
270 uint16_t stats_size;
271 bool has_extended_tcb_support;
272 } EEPRO100State;
273
274 /* Word indices in EEPROM. */
275 typedef enum {
276 EEPROM_CNFG_MDIX = 0x03,
277 EEPROM_ID = 0x05,
278 EEPROM_PHY_ID = 0x06,
279 EEPROM_VENDOR_ID = 0x0c,
280 EEPROM_CONFIG_ASF = 0x0d,
281 EEPROM_DEVICE_ID = 0x23,
282 EEPROM_SMBUS_ADDR = 0x90,
283 } EEPROMOffset;
284
285 /* Bit values for EEPROM ID word. */
286 typedef enum {
287 EEPROM_ID_MDM = BIT(0), /* Modem */
288 EEPROM_ID_STB = BIT(1), /* Standby Enable */
289 EEPROM_ID_WMR = BIT(2), /* ??? */
290 EEPROM_ID_WOL = BIT(5), /* Wake on LAN */
291 EEPROM_ID_DPD = BIT(6), /* Deep Power Down */
292 EEPROM_ID_ALT = BIT(7), /* */
293 /* BITS(10, 8) device revision */
294 EEPROM_ID_BD = BIT(11), /* boot disable */
295 EEPROM_ID_ID = BIT(13), /* id bit */
296 /* BITS(15, 14) signature */
297 EEPROM_ID_VALID = BIT(14), /* signature for valid eeprom */
298 } eeprom_id_bit;
299
300 /* Default values for MDI (PHY) registers */
301 static const uint16_t eepro100_mdi_default[] = {
302 /* MDI Registers 0 - 6, 7 */
303 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
304 /* MDI Registers 8 - 15 */
305 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
306 /* MDI Registers 16 - 31 */
307 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
308 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
309 };
310
311 /* Readonly mask for MDI (PHY) registers */
312 static const uint16_t eepro100_mdi_mask[] = {
313 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
314 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
315 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
316 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
317 };
318
319 /* Read a 16 bit little endian value from physical memory. */
320 static uint16_t e100_ldw_le_phys(target_phys_addr_t addr)
321 {
322 /* Load 16 bit (little endian) word from emulated hardware. */
323 uint16_t val;
324 cpu_physical_memory_read(addr, &val, sizeof(val));
325 return le16_to_cpu(val);
326 }
327
328 /* Read a 32 bit little endian value from physical memory. */
329 static uint32_t e100_ldl_le_phys(target_phys_addr_t addr)
330 {
331 /* Load 32 bit (little endian) word from emulated hardware. */
332 uint32_t val;
333 cpu_physical_memory_read(addr, &val, sizeof(val));
334 return le32_to_cpu(val);
335 }
336
337 /* Write a 16 bit little endian value to physical memory. */
338 static void e100_stw_le_phys(target_phys_addr_t addr, uint16_t val)
339 {
340 val = cpu_to_le16(val);
341 cpu_physical_memory_write(addr, &val, sizeof(val));
342 }
343
344 /* Write a 32 bit little endian value to physical memory. */
345 static void e100_stl_le_phys(target_phys_addr_t addr, uint32_t val)
346 {
347 val = cpu_to_le32(val);
348 cpu_physical_memory_write(addr, &val, sizeof(val));
349 }
350
351 #define POLYNOMIAL 0x04c11db6
352
353 /* From FreeBSD */
354 /* XXX: optimize */
355 static unsigned compute_mcast_idx(const uint8_t * ep)
356 {
357 uint32_t crc;
358 int carry, i, j;
359 uint8_t b;
360
361 crc = 0xffffffff;
362 for (i = 0; i < 6; i++) {
363 b = *ep++;
364 for (j = 0; j < 8; j++) {
365 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
366 crc <<= 1;
367 b >>= 1;
368 if (carry) {
369 crc = ((crc ^ POLYNOMIAL) | carry);
370 }
371 }
372 }
373 return (crc & BITS(7, 2)) >> 2;
374 }
375
376 /* Read a 16 bit control/status (CSR) register. */
377 static uint16_t e100_read_reg2(EEPRO100State *s, E100RegisterOffset addr)
378 {
379 assert(!((uintptr_t)&s->mem[addr] & 1));
380 return le16_to_cpup((uint16_t *)&s->mem[addr]);
381 }
382
383 /* Read a 32 bit control/status (CSR) register. */
384 static uint32_t e100_read_reg4(EEPRO100State *s, E100RegisterOffset addr)
385 {
386 assert(!((uintptr_t)&s->mem[addr] & 3));
387 return le32_to_cpup((uint32_t *)&s->mem[addr]);
388 }
389
390 /* Write a 16 bit control/status (CSR) register. */
391 static void e100_write_reg2(EEPRO100State *s, E100RegisterOffset addr,
392 uint16_t val)
393 {
394 assert(!((uintptr_t)&s->mem[addr] & 1));
395 cpu_to_le16w((uint16_t *)&s->mem[addr], val);
396 }
397
398 /* Read a 32 bit control/status (CSR) register. */
399 static void e100_write_reg4(EEPRO100State *s, E100RegisterOffset addr,
400 uint32_t val)
401 {
402 assert(!((uintptr_t)&s->mem[addr] & 3));
403 cpu_to_le32w((uint32_t *)&s->mem[addr], val);
404 }
405
406 #if defined(DEBUG_EEPRO100)
407 static const char *nic_dump(const uint8_t * buf, unsigned size)
408 {
409 static char dump[3 * 16 + 1];
410 char *p = &dump[0];
411 if (size > 16) {
412 size = 16;
413 }
414 while (size-- > 0) {
415 p += sprintf(p, " %02x", *buf++);
416 }
417 return dump;
418 }
419 #endif /* DEBUG_EEPRO100 */
420
421 enum scb_stat_ack {
422 stat_ack_not_ours = 0x00,
423 stat_ack_sw_gen = 0x04,
424 stat_ack_rnr = 0x10,
425 stat_ack_cu_idle = 0x20,
426 stat_ack_frame_rx = 0x40,
427 stat_ack_cu_cmd_done = 0x80,
428 stat_ack_not_present = 0xFF,
429 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
430 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
431 };
432
433 static void disable_interrupt(EEPRO100State * s)
434 {
435 if (s->int_stat) {
436 TRACE(INT, logout("interrupt disabled\n"));
437 qemu_irq_lower(s->dev.irq[0]);
438 s->int_stat = 0;
439 }
440 }
441
442 static void enable_interrupt(EEPRO100State * s)
443 {
444 if (!s->int_stat) {
445 TRACE(INT, logout("interrupt enabled\n"));
446 qemu_irq_raise(s->dev.irq[0]);
447 s->int_stat = 1;
448 }
449 }
450
451 static void eepro100_acknowledge(EEPRO100State * s)
452 {
453 s->scb_stat &= ~s->mem[SCBAck];
454 s->mem[SCBAck] = s->scb_stat;
455 if (s->scb_stat == 0) {
456 disable_interrupt(s);
457 }
458 }
459
460 static void eepro100_interrupt(EEPRO100State * s, uint8_t status)
461 {
462 uint8_t mask = ~s->mem[SCBIntmask];
463 s->mem[SCBAck] |= status;
464 status = s->scb_stat = s->mem[SCBAck];
465 status &= (mask | 0x0f);
466 #if 0
467 status &= (~s->mem[SCBIntmask] | 0x0xf);
468 #endif
469 if (status && (mask & 0x01)) {
470 /* SCB mask and SCB Bit M do not disable interrupt. */
471 enable_interrupt(s);
472 } else if (s->int_stat) {
473 disable_interrupt(s);
474 }
475 }
476
477 static void eepro100_cx_interrupt(EEPRO100State * s)
478 {
479 /* CU completed action command. */
480 /* Transmit not ok (82557 only, not in emulation). */
481 eepro100_interrupt(s, 0x80);
482 }
483
484 static void eepro100_cna_interrupt(EEPRO100State * s)
485 {
486 /* CU left the active state. */
487 eepro100_interrupt(s, 0x20);
488 }
489
490 static void eepro100_fr_interrupt(EEPRO100State * s)
491 {
492 /* RU received a complete frame. */
493 eepro100_interrupt(s, 0x40);
494 }
495
496 static void eepro100_rnr_interrupt(EEPRO100State * s)
497 {
498 /* RU is not ready. */
499 eepro100_interrupt(s, 0x10);
500 }
501
502 static void eepro100_mdi_interrupt(EEPRO100State * s)
503 {
504 /* MDI completed read or write cycle. */
505 eepro100_interrupt(s, 0x08);
506 }
507
508 static void eepro100_swi_interrupt(EEPRO100State * s)
509 {
510 /* Software has requested an interrupt. */
511 eepro100_interrupt(s, 0x04);
512 }
513
514 #if 0
515 static void eepro100_fcp_interrupt(EEPRO100State * s)
516 {
517 /* Flow control pause interrupt (82558 and later). */
518 eepro100_interrupt(s, 0x01);
519 }
520 #endif
521
522 static void e100_pci_reset(EEPRO100State * s, E100PCIDeviceInfo *e100_device)
523 {
524 uint32_t device = s->device;
525 uint8_t *pci_conf = s->dev.config;
526
527 TRACE(OTHER, logout("%p\n", s));
528
529 /* PCI Vendor ID */
530 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
531 /* PCI Device ID */
532 pci_config_set_device_id(pci_conf, e100_device->device_id);
533 /* PCI Status */
534 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
535 PCI_STATUS_FAST_BACK);
536 /* PCI Revision ID */
537 pci_config_set_revision(pci_conf, e100_device->revision);
538 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
539 /* PCI Latency Timer */
540 pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */
541 /* Capability Pointer is set by PCI framework. */
542 /* Interrupt Line */
543 /* Interrupt Pin */
544 pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 1); /* interrupt pin A */
545 /* Minimum Grant */
546 pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08);
547 /* Maximum Latency */
548 pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18);
549
550 s->stats_size = e100_device->stats_size;
551 s->has_extended_tcb_support = e100_device->has_extended_tcb_support;
552
553 switch (device) {
554 case i82550:
555 case i82551:
556 case i82557A:
557 case i82557B:
558 case i82557C:
559 case i82558A:
560 case i82558B:
561 case i82559A:
562 case i82559B:
563 case i82559ER:
564 case i82562:
565 case i82801:
566 break;
567 case i82559C:
568 #if EEPROM_SIZE > 0
569 pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, PCI_VENDOR_ID_INTEL);
570 pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0040);
571 #endif
572 break;
573 default:
574 logout("Device %X is undefined!\n", device);
575 }
576
577 /* Standard TxCB. */
578 s->configuration[6] |= BIT(4);
579
580 /* Standard statistical counters. */
581 s->configuration[6] |= BIT(5);
582
583 if (s->stats_size == 80) {
584 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
585 if (s->configuration[6] & BIT(2)) {
586 /* TCO statistical counters. */
587 assert(s->configuration[6] & BIT(5));
588 } else {
589 if (s->configuration[6] & BIT(5)) {
590 /* No extended statistical counters, i82557 compatible. */
591 s->stats_size = 64;
592 } else {
593 /* i82558 compatible. */
594 s->stats_size = 76;
595 }
596 }
597 } else {
598 if (s->configuration[6] & BIT(5)) {
599 /* No extended statistical counters. */
600 s->stats_size = 64;
601 }
602 }
603 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
604
605 if (e100_device->power_management) {
606 /* Power Management Capabilities */
607 int cfg_offset = 0xdc;
608 int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM,
609 cfg_offset, PCI_PM_SIZEOF);
610 assert(r >= 0);
611 pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
612 #if 0 /* TODO: replace dummy code for power management emulation. */
613 /* TODO: Power Management Control / Status. */
614 pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000);
615 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
616 pci_set_byte(pci_conf + cfg_offset + PCI_PM_PPB_EXTENSIONS, 0x0000);
617 #endif
618 }
619
620 #if EEPROM_SIZE > 0
621 if (device == i82557C || device == i82558B || device == i82559C) {
622 /*
623 TODO: get vendor id from EEPROM for i82557C or later.
624 TODO: get device id from EEPROM for i82557C or later.
625 TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
626 TODO: header type is determined by EEPROM for i82559.
627 TODO: get subsystem id from EEPROM for i82557C or later.
628 TODO: get subsystem vendor id from EEPROM for i82557C or later.
629 TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
630 TODO: capability pointer depends on EEPROM for i82558.
631 */
632 logout("Get device id and revision from EEPROM!!!\n");
633 }
634 #endif /* EEPROM_SIZE > 0 */
635 }
636
637 static void nic_selective_reset(EEPRO100State * s)
638 {
639 size_t i;
640 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
641 #if 0
642 eeprom93xx_reset(s->eeprom);
643 #endif
644 memcpy(eeprom_contents, s->conf.macaddr.a, 6);
645 eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID;
646 if (s->device == i82557B || s->device == i82557C)
647 eeprom_contents[5] = 0x0100;
648 eeprom_contents[EEPROM_PHY_ID] = 1;
649 uint16_t sum = 0;
650 for (i = 0; i < EEPROM_SIZE - 1; i++) {
651 sum += eeprom_contents[i];
652 }
653 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
654 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
655
656 memset(s->mem, 0, sizeof(s->mem));
657 e100_write_reg4(s, SCBCtrlMDI, BIT(21));
658
659 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
660 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
661 }
662
663 static void nic_reset(void *opaque)
664 {
665 EEPRO100State *s = opaque;
666 TRACE(OTHER, logout("%p\n", s));
667 /* TODO: Clearing of hash register for selective reset, too? */
668 memset(&s->mult[0], 0, sizeof(s->mult));
669 nic_selective_reset(s);
670 }
671
672 #if defined(DEBUG_EEPRO100)
673 static const char * const e100_reg[PCI_IO_SIZE / 4] = {
674 "Command/Status",
675 "General Pointer",
676 "Port",
677 "EEPROM/Flash Control",
678 "MDI Control",
679 "Receive DMA Byte Count",
680 "Flow Control",
681 "General Status/Control"
682 };
683
684 static char *regname(uint32_t addr)
685 {
686 static char buf[32];
687 if (addr < PCI_IO_SIZE) {
688 const char *r = e100_reg[addr / 4];
689 if (r != 0) {
690 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
691 } else {
692 snprintf(buf, sizeof(buf), "0x%02x", addr);
693 }
694 } else {
695 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
696 }
697 return buf;
698 }
699 #endif /* DEBUG_EEPRO100 */
700
701 /*****************************************************************************
702 *
703 * Command emulation.
704 *
705 ****************************************************************************/
706
707 #if 0
708 static uint16_t eepro100_read_command(EEPRO100State * s)
709 {
710 uint16_t val = 0xffff;
711 TRACE(OTHER, logout("val=0x%04x\n", val));
712 return val;
713 }
714 #endif
715
716 /* Commands that can be put in a command list entry. */
717 enum commands {
718 CmdNOp = 0,
719 CmdIASetup = 1,
720 CmdConfigure = 2,
721 CmdMulticastList = 3,
722 CmdTx = 4,
723 CmdTDR = 5, /* load microcode */
724 CmdDump = 6,
725 CmdDiagnose = 7,
726
727 /* And some extra flags: */
728 CmdSuspend = 0x4000, /* Suspend after completion. */
729 CmdIntr = 0x2000, /* Interrupt after completion. */
730 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
731 };
732
733 static cu_state_t get_cu_state(EEPRO100State * s)
734 {
735 return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6);
736 }
737
738 static void set_cu_state(EEPRO100State * s, cu_state_t state)
739 {
740 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6);
741 }
742
743 static ru_state_t get_ru_state(EEPRO100State * s)
744 {
745 return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2);
746 }
747
748 static void set_ru_state(EEPRO100State * s, ru_state_t state)
749 {
750 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2);
751 }
752
753 static void dump_statistics(EEPRO100State * s)
754 {
755 /* Dump statistical data. Most data is never changed by the emulation
756 * and always 0, so we first just copy the whole block and then those
757 * values which really matter.
758 * Number of data should check configuration!!!
759 */
760 cpu_physical_memory_write(s->statsaddr, &s->statistics, s->stats_size);
761 e100_stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
762 e100_stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
763 e100_stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
764 e100_stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
765 #if 0
766 e100_stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
767 e100_stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
768 missing("CU dump statistical counters");
769 #endif
770 }
771
772 static void read_cb(EEPRO100State *s)
773 {
774 cpu_physical_memory_read(s->cb_address, &s->tx, sizeof(s->tx));
775 s->tx.status = le16_to_cpu(s->tx.status);
776 s->tx.command = le16_to_cpu(s->tx.command);
777 s->tx.link = le32_to_cpu(s->tx.link);
778 s->tx.tbd_array_addr = le32_to_cpu(s->tx.tbd_array_addr);
779 s->tx.tcb_bytes = le16_to_cpu(s->tx.tcb_bytes);
780 }
781
782 static void tx_command(EEPRO100State *s)
783 {
784 uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr);
785 uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
786 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
787 uint8_t buf[2600];
788 uint16_t size = 0;
789 uint32_t tbd_address = s->cb_address + 0x10;
790 TRACE(RXTX, logout
791 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
792 tbd_array, tcb_bytes, s->tx.tbd_count));
793
794 if (tcb_bytes > 2600) {
795 logout("TCB byte count too large, using 2600\n");
796 tcb_bytes = 2600;
797 }
798 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
799 logout
800 ("illegal values of TBD array address and TCB byte count!\n");
801 }
802 assert(tcb_bytes <= sizeof(buf));
803 while (size < tcb_bytes) {
804 uint32_t tx_buffer_address = e100_ldl_le_phys(tbd_address);
805 uint16_t tx_buffer_size = e100_ldw_le_phys(tbd_address + 4);
806 #if 0
807 uint16_t tx_buffer_el = e100_ldw_le_phys(tbd_address + 6);
808 #endif
809 tbd_address += 8;
810 TRACE(RXTX, logout
811 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
812 tx_buffer_address, tx_buffer_size));
813 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
814 cpu_physical_memory_read(tx_buffer_address, &buf[size],
815 tx_buffer_size);
816 size += tx_buffer_size;
817 }
818 if (tbd_array == 0xffffffff) {
819 /* Simplified mode. Was already handled by code above. */
820 } else {
821 /* Flexible mode. */
822 uint8_t tbd_count = 0;
823 if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
824 /* Extended Flexible TCB. */
825 for (; tbd_count < 2; tbd_count++) {
826 uint32_t tx_buffer_address = e100_ldl_le_phys(tbd_address);
827 uint16_t tx_buffer_size = e100_ldw_le_phys(tbd_address + 4);
828 uint16_t tx_buffer_el = e100_ldw_le_phys(tbd_address + 6);
829 tbd_address += 8;
830 TRACE(RXTX, logout
831 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
832 tx_buffer_address, tx_buffer_size));
833 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
834 cpu_physical_memory_read(tx_buffer_address, &buf[size],
835 tx_buffer_size);
836 size += tx_buffer_size;
837 if (tx_buffer_el & 1) {
838 break;
839 }
840 }
841 }
842 tbd_address = tbd_array;
843 for (; tbd_count < s->tx.tbd_count; tbd_count++) {
844 uint32_t tx_buffer_address = e100_ldl_le_phys(tbd_address);
845 uint16_t tx_buffer_size = e100_ldw_le_phys(tbd_address + 4);
846 uint16_t tx_buffer_el = e100_ldw_le_phys(tbd_address + 6);
847 tbd_address += 8;
848 TRACE(RXTX, logout
849 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
850 tx_buffer_address, tx_buffer_size));
851 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
852 cpu_physical_memory_read(tx_buffer_address, &buf[size],
853 tx_buffer_size);
854 size += tx_buffer_size;
855 if (tx_buffer_el & 1) {
856 break;
857 }
858 }
859 }
860 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
861 qemu_send_packet(&s->nic->nc, buf, size);
862 s->statistics.tx_good_frames++;
863 /* Transmit with bad status would raise an CX/TNO interrupt.
864 * (82557 only). Emulation never has bad status. */
865 #if 0
866 eepro100_cx_interrupt(s);
867 #endif
868 }
869
870 static void set_multicast_list(EEPRO100State *s)
871 {
872 uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0);
873 uint16_t i;
874 memset(&s->mult[0], 0, sizeof(s->mult));
875 TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
876 for (i = 0; i < multicast_count; i += 6) {
877 uint8_t multicast_addr[6];
878 cpu_physical_memory_read(s->cb_address + 10 + i, multicast_addr, 6);
879 TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6)));
880 unsigned mcast_idx = compute_mcast_idx(multicast_addr);
881 assert(mcast_idx < 64);
882 s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7));
883 }
884 }
885
886 static void action_command(EEPRO100State *s)
887 {
888 for (;;) {
889 bool bit_el;
890 bool bit_s;
891 bool bit_i;
892 bool bit_nc;
893 uint16_t ok_status = STATUS_OK;
894 s->cb_address = s->cu_base + s->cu_offset;
895 read_cb(s);
896 bit_el = ((s->tx.command & COMMAND_EL) != 0);
897 bit_s = ((s->tx.command & COMMAND_S) != 0);
898 bit_i = ((s->tx.command & COMMAND_I) != 0);
899 bit_nc = ((s->tx.command & COMMAND_NC) != 0);
900 #if 0
901 bool bit_sf = ((s->tx.command & COMMAND_SF) != 0);
902 #endif
903 s->cu_offset = s->tx.link;
904 TRACE(OTHER,
905 logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
906 s->tx.status, s->tx.command, s->tx.link));
907 switch (s->tx.command & COMMAND_CMD) {
908 case CmdNOp:
909 /* Do nothing. */
910 break;
911 case CmdIASetup:
912 cpu_physical_memory_read(s->cb_address + 8, &s->conf.macaddr.a[0], 6);
913 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)));
914 break;
915 case CmdConfigure:
916 cpu_physical_memory_read(s->cb_address + 8, &s->configuration[0],
917 sizeof(s->configuration));
918 TRACE(OTHER, logout("configuration: %s\n",
919 nic_dump(&s->configuration[0], 16)));
920 TRACE(OTHER, logout("configuration: %s\n",
921 nic_dump(&s->configuration[16],
922 ARRAY_SIZE(s->configuration) - 16)));
923 if (s->configuration[20] & BIT(6)) {
924 TRACE(OTHER, logout("Multiple IA bit\n"));
925 }
926 break;
927 case CmdMulticastList:
928 set_multicast_list(s);
929 break;
930 case CmdTx:
931 if (bit_nc) {
932 missing("CmdTx: NC = 0");
933 ok_status = 0;
934 break;
935 }
936 tx_command(s);
937 break;
938 case CmdTDR:
939 TRACE(OTHER, logout("load microcode\n"));
940 /* Starting with offset 8, the command contains
941 * 64 dwords microcode which we just ignore here. */
942 break;
943 case CmdDiagnose:
944 TRACE(OTHER, logout("diagnose\n"));
945 /* Make sure error flag is not set. */
946 s->tx.status = 0;
947 break;
948 default:
949 missing("undefined command");
950 ok_status = 0;
951 break;
952 }
953 /* Write new status. */
954 e100_stw_le_phys(s->cb_address, s->tx.status | ok_status | STATUS_C);
955 if (bit_i) {
956 /* CU completed action. */
957 eepro100_cx_interrupt(s);
958 }
959 if (bit_el) {
960 /* CU becomes idle. Terminate command loop. */
961 set_cu_state(s, cu_idle);
962 eepro100_cna_interrupt(s);
963 break;
964 } else if (bit_s) {
965 /* CU becomes suspended. Terminate command loop. */
966 set_cu_state(s, cu_suspended);
967 eepro100_cna_interrupt(s);
968 break;
969 } else {
970 /* More entries in list. */
971 TRACE(OTHER, logout("CU list with at least one more entry\n"));
972 }
973 }
974 TRACE(OTHER, logout("CU list empty\n"));
975 /* List is empty. Now CU is idle or suspended. */
976 }
977
978 static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
979 {
980 cu_state_t cu_state;
981 switch (val) {
982 case CU_NOP:
983 /* No operation. */
984 break;
985 case CU_START:
986 cu_state = get_cu_state(s);
987 if (cu_state != cu_idle && cu_state != cu_suspended) {
988 /* Intel documentation says that CU must be idle or suspended
989 * for the CU start command. */
990 logout("unexpected CU state is %u\n", cu_state);
991 }
992 set_cu_state(s, cu_active);
993 s->cu_offset = e100_read_reg4(s, SCBPointer);
994 action_command(s);
995 break;
996 case CU_RESUME:
997 if (get_cu_state(s) != cu_suspended) {
998 logout("bad CU resume from CU state %u\n", get_cu_state(s));
999 /* Workaround for bad Linux eepro100 driver which resumes
1000 * from idle state. */
1001 #if 0
1002 missing("cu resume");
1003 #endif
1004 set_cu_state(s, cu_suspended);
1005 }
1006 if (get_cu_state(s) == cu_suspended) {
1007 TRACE(OTHER, logout("CU resuming\n"));
1008 set_cu_state(s, cu_active);
1009 action_command(s);
1010 }
1011 break;
1012 case CU_STATSADDR:
1013 /* Load dump counters address. */
1014 s->statsaddr = e100_read_reg4(s, SCBPointer);
1015 TRACE(OTHER, logout("val=0x%02x (status address)\n", val));
1016 break;
1017 case CU_SHOWSTATS:
1018 /* Dump statistical counters. */
1019 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
1020 dump_statistics(s);
1021 e100_stl_le_phys(s->statsaddr + s->stats_size, 0xa005);
1022 break;
1023 case CU_CMD_BASE:
1024 /* Load CU base. */
1025 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
1026 s->cu_base = e100_read_reg4(s, SCBPointer);
1027 break;
1028 case CU_DUMPSTATS:
1029 /* Dump and reset statistical counters. */
1030 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
1031 dump_statistics(s);
1032 e100_stl_le_phys(s->statsaddr + s->stats_size, 0xa007);
1033 memset(&s->statistics, 0, sizeof(s->statistics));
1034 break;
1035 case CU_SRESUME:
1036 /* CU static resume. */
1037 missing("CU static resume");
1038 break;
1039 default:
1040 missing("Undefined CU command");
1041 }
1042 }
1043
1044 static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
1045 {
1046 switch (val) {
1047 case RU_NOP:
1048 /* No operation. */
1049 break;
1050 case RX_START:
1051 /* RU start. */
1052 if (get_ru_state(s) != ru_idle) {
1053 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
1054 #if 0
1055 assert(!"wrong RU state");
1056 #endif
1057 }
1058 set_ru_state(s, ru_ready);
1059 s->ru_offset = e100_read_reg4(s, SCBPointer);
1060 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
1061 break;
1062 case RX_RESUME:
1063 /* Restart RU. */
1064 if (get_ru_state(s) != ru_suspended) {
1065 logout("RU state is %u, should be %u\n", get_ru_state(s),
1066 ru_suspended);
1067 #if 0
1068 assert(!"wrong RU state");
1069 #endif
1070 }
1071 set_ru_state(s, ru_ready);
1072 break;
1073 case RU_ABORT:
1074 /* RU abort. */
1075 if (get_ru_state(s) == ru_ready) {
1076 eepro100_rnr_interrupt(s);
1077 }
1078 set_ru_state(s, ru_idle);
1079 break;
1080 case RX_ADDR_LOAD:
1081 /* Load RU base. */
1082 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
1083 s->ru_base = e100_read_reg4(s, SCBPointer);
1084 break;
1085 default:
1086 logout("val=0x%02x (undefined RU command)\n", val);
1087 missing("Undefined SU command");
1088 }
1089 }
1090
1091 static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1092 {
1093 eepro100_ru_command(s, val & 0x0f);
1094 eepro100_cu_command(s, val & 0xf0);
1095 if ((val) == 0) {
1096 TRACE(OTHER, logout("val=0x%02x\n", val));
1097 }
1098 /* Clear command byte after command was accepted. */
1099 s->mem[SCBCmd] = 0;
1100 }
1101
1102 /*****************************************************************************
1103 *
1104 * EEPROM emulation.
1105 *
1106 ****************************************************************************/
1107
1108 #define EEPROM_CS 0x02
1109 #define EEPROM_SK 0x01
1110 #define EEPROM_DI 0x04
1111 #define EEPROM_DO 0x08
1112
1113 static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1114 {
1115 uint16_t val = e100_read_reg2(s, SCBeeprom);
1116 if (eeprom93xx_read(s->eeprom)) {
1117 val |= EEPROM_DO;
1118 } else {
1119 val &= ~EEPROM_DO;
1120 }
1121 TRACE(EEPROM, logout("val=0x%04x\n", val));
1122 return val;
1123 }
1124
1125 static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
1126 {
1127 TRACE(EEPROM, logout("val=0x%02x\n", val));
1128
1129 /* mask unwriteable bits */
1130 #if 0
1131 val = SET_MASKED(val, 0x31, eeprom->value);
1132 #endif
1133
1134 int eecs = ((val & EEPROM_CS) != 0);
1135 int eesk = ((val & EEPROM_SK) != 0);
1136 int eedi = ((val & EEPROM_DI) != 0);
1137 eeprom93xx_write(eeprom, eecs, eesk, eedi);
1138 }
1139
1140 /*****************************************************************************
1141 *
1142 * MDI emulation.
1143 *
1144 ****************************************************************************/
1145
1146 #if defined(DEBUG_EEPRO100)
1147 static const char * const mdi_op_name[] = {
1148 "opcode 0",
1149 "write",
1150 "read",
1151 "opcode 3"
1152 };
1153
1154 static const char * const mdi_reg_name[] = {
1155 "Control",
1156 "Status",
1157 "PHY Identification (Word 1)",
1158 "PHY Identification (Word 2)",
1159 "Auto-Negotiation Advertisement",
1160 "Auto-Negotiation Link Partner Ability",
1161 "Auto-Negotiation Expansion"
1162 };
1163
1164 static const char *reg2name(uint8_t reg)
1165 {
1166 static char buffer[10];
1167 const char *p = buffer;
1168 if (reg < ARRAY_SIZE(mdi_reg_name)) {
1169 p = mdi_reg_name[reg];
1170 } else {
1171 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1172 }
1173 return p;
1174 }
1175 #endif /* DEBUG_EEPRO100 */
1176
1177 static uint32_t eepro100_read_mdi(EEPRO100State * s)
1178 {
1179 uint32_t val = e100_read_reg4(s, SCBCtrlMDI);
1180
1181 #ifdef DEBUG_EEPRO100
1182 uint8_t raiseint = (val & BIT(29)) >> 29;
1183 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1184 uint8_t phy = (val & BITS(25, 21)) >> 21;
1185 uint8_t reg = (val & BITS(20, 16)) >> 16;
1186 uint16_t data = (val & BITS(15, 0));
1187 #endif
1188 /* Emulation takes no time to finish MDI transaction. */
1189 val |= BIT(28);
1190 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1191 val, raiseint, mdi_op_name[opcode], phy,
1192 reg2name(reg), data));
1193 return val;
1194 }
1195
1196 static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
1197 {
1198 uint8_t raiseint = (val & BIT(29)) >> 29;
1199 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1200 uint8_t phy = (val & BITS(25, 21)) >> 21;
1201 uint8_t reg = (val & BITS(20, 16)) >> 16;
1202 uint16_t data = (val & BITS(15, 0));
1203 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1204 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
1205 if (phy != 1) {
1206 /* Unsupported PHY address. */
1207 #if 0
1208 logout("phy must be 1 but is %u\n", phy);
1209 #endif
1210 data = 0;
1211 } else if (opcode != 1 && opcode != 2) {
1212 /* Unsupported opcode. */
1213 logout("opcode must be 1 or 2 but is %u\n", opcode);
1214 data = 0;
1215 } else if (reg > 6) {
1216 /* Unsupported register. */
1217 logout("register must be 0...6 but is %u\n", reg);
1218 data = 0;
1219 } else {
1220 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1221 val, raiseint, mdi_op_name[opcode], phy,
1222 reg2name(reg), data));
1223 if (opcode == 1) {
1224 /* MDI write */
1225 switch (reg) {
1226 case 0: /* Control Register */
1227 if (data & 0x8000) {
1228 /* Reset status and control registers to default. */
1229 s->mdimem[0] = eepro100_mdi_default[0];
1230 s->mdimem[1] = eepro100_mdi_default[1];
1231 data = s->mdimem[reg];
1232 } else {
1233 /* Restart Auto Configuration = Normal Operation */
1234 data &= ~0x0200;
1235 }
1236 break;
1237 case 1: /* Status Register */
1238 missing("not writable");
1239 data = s->mdimem[reg];
1240 break;
1241 case 2: /* PHY Identification Register (Word 1) */
1242 case 3: /* PHY Identification Register (Word 2) */
1243 missing("not implemented");
1244 break;
1245 case 4: /* Auto-Negotiation Advertisement Register */
1246 case 5: /* Auto-Negotiation Link Partner Ability Register */
1247 break;
1248 case 6: /* Auto-Negotiation Expansion Register */
1249 default:
1250 missing("not implemented");
1251 }
1252 s->mdimem[reg] = data;
1253 } else if (opcode == 2) {
1254 /* MDI read */
1255 switch (reg) {
1256 case 0: /* Control Register */
1257 if (data & 0x8000) {
1258 /* Reset status and control registers to default. */
1259 s->mdimem[0] = eepro100_mdi_default[0];
1260 s->mdimem[1] = eepro100_mdi_default[1];
1261 }
1262 break;
1263 case 1: /* Status Register */
1264 s->mdimem[reg] |= 0x0020;
1265 break;
1266 case 2: /* PHY Identification Register (Word 1) */
1267 case 3: /* PHY Identification Register (Word 2) */
1268 case 4: /* Auto-Negotiation Advertisement Register */
1269 break;
1270 case 5: /* Auto-Negotiation Link Partner Ability Register */
1271 s->mdimem[reg] = 0x41fe;
1272 break;
1273 case 6: /* Auto-Negotiation Expansion Register */
1274 s->mdimem[reg] = 0x0001;
1275 break;
1276 }
1277 data = s->mdimem[reg];
1278 }
1279 /* Emulation takes no time to finish MDI transaction.
1280 * Set MDI bit in SCB status register. */
1281 s->mem[SCBAck] |= 0x08;
1282 val |= BIT(28);
1283 if (raiseint) {
1284 eepro100_mdi_interrupt(s);
1285 }
1286 }
1287 val = (val & 0xffff0000) + data;
1288 e100_write_reg4(s, SCBCtrlMDI, val);
1289 }
1290
1291 /*****************************************************************************
1292 *
1293 * Port emulation.
1294 *
1295 ****************************************************************************/
1296
1297 #define PORT_SOFTWARE_RESET 0
1298 #define PORT_SELFTEST 1
1299 #define PORT_SELECTIVE_RESET 2
1300 #define PORT_DUMP 3
1301 #define PORT_SELECTION_MASK 3
1302
1303 typedef struct {
1304 uint32_t st_sign; /* Self Test Signature */
1305 uint32_t st_result; /* Self Test Results */
1306 } eepro100_selftest_t;
1307
1308 static uint32_t eepro100_read_port(EEPRO100State * s)
1309 {
1310 return 0;
1311 }
1312
1313 static void eepro100_write_port(EEPRO100State *s)
1314 {
1315 uint32_t val = e100_read_reg4(s, SCBPort);
1316 uint32_t address = (val & ~PORT_SELECTION_MASK);
1317 uint8_t selection = (val & PORT_SELECTION_MASK);
1318 switch (selection) {
1319 case PORT_SOFTWARE_RESET:
1320 nic_reset(s);
1321 break;
1322 case PORT_SELFTEST:
1323 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
1324 eepro100_selftest_t data;
1325 cpu_physical_memory_read(address, &data, sizeof(data));
1326 data.st_sign = 0xffffffff;
1327 data.st_result = 0;
1328 cpu_physical_memory_write(address, &data, sizeof(data));
1329 break;
1330 case PORT_SELECTIVE_RESET:
1331 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
1332 nic_selective_reset(s);
1333 break;
1334 default:
1335 logout("val=0x%08x\n", val);
1336 missing("unknown port selection");
1337 }
1338 }
1339
1340 /*****************************************************************************
1341 *
1342 * General hardware emulation.
1343 *
1344 ****************************************************************************/
1345
1346 static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1347 {
1348 uint8_t val = 0;
1349 if (addr <= sizeof(s->mem) - sizeof(val)) {
1350 val = s->mem[addr];
1351 }
1352
1353 switch (addr) {
1354 case SCBStatus:
1355 case SCBAck:
1356 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1357 break;
1358 case SCBCmd:
1359 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1360 #if 0
1361 val = eepro100_read_command(s);
1362 #endif
1363 break;
1364 case SCBIntmask:
1365 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1366 break;
1367 case SCBPort + 3:
1368 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1369 break;
1370 case SCBeeprom:
1371 val = eepro100_read_eeprom(s);
1372 break;
1373 case SCBpmdr: /* Power Management Driver Register */
1374 val = 0;
1375 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1376 break;
1377 case SCBgstat: /* General Status Register */
1378 /* 100 Mbps full duplex, valid link */
1379 val = 0x07;
1380 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
1381 break;
1382 default:
1383 logout("addr=%s val=0x%02x\n", regname(addr), val);
1384 missing("unknown byte read");
1385 }
1386 return val;
1387 }
1388
1389 static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1390 {
1391 uint16_t val = 0;
1392 if (addr <= sizeof(s->mem) - sizeof(val)) {
1393 val = e100_read_reg2(s, addr);
1394 }
1395
1396 switch (addr) {
1397 case SCBStatus:
1398 case SCBCmd:
1399 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1400 break;
1401 case SCBeeprom:
1402 val = eepro100_read_eeprom(s);
1403 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1404 break;
1405 default:
1406 logout("addr=%s val=0x%04x\n", regname(addr), val);
1407 missing("unknown word read");
1408 }
1409 return val;
1410 }
1411
1412 static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1413 {
1414 uint32_t val = 0;
1415 if (addr <= sizeof(s->mem) - sizeof(val)) {
1416 val = e100_read_reg4(s, addr);
1417 }
1418
1419 switch (addr) {
1420 case SCBStatus:
1421 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1422 break;
1423 case SCBPointer:
1424 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1425 break;
1426 case SCBPort:
1427 val = eepro100_read_port(s);
1428 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1429 break;
1430 case SCBCtrlMDI:
1431 val = eepro100_read_mdi(s);
1432 break;
1433 default:
1434 logout("addr=%s val=0x%08x\n", regname(addr), val);
1435 missing("unknown longword read");
1436 }
1437 return val;
1438 }
1439
1440 static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1441 {
1442 /* SCBStatus is readonly. */
1443 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
1444 s->mem[addr] = val;
1445 }
1446
1447 switch (addr) {
1448 case SCBStatus:
1449 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1450 break;
1451 case SCBAck:
1452 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1453 eepro100_acknowledge(s);
1454 break;
1455 case SCBCmd:
1456 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1457 eepro100_write_command(s, val);
1458 break;
1459 case SCBIntmask:
1460 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1461 if (val & BIT(1)) {
1462 eepro100_swi_interrupt(s);
1463 }
1464 eepro100_interrupt(s, 0);
1465 break;
1466 case SCBPointer:
1467 case SCBPointer + 1:
1468 case SCBPointer + 2:
1469 case SCBPointer + 3:
1470 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1471 break;
1472 case SCBPort:
1473 case SCBPort + 1:
1474 case SCBPort + 2:
1475 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1476 break;
1477 case SCBPort + 3:
1478 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1479 eepro100_write_port(s);
1480 break;
1481 case SCBFlow: /* does not exist on 82557 */
1482 case SCBFlow + 1:
1483 case SCBFlow + 2:
1484 case SCBpmdr: /* does not exist on 82557 */
1485 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1486 break;
1487 case SCBeeprom:
1488 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1489 eepro100_write_eeprom(s->eeprom, val);
1490 break;
1491 default:
1492 logout("addr=%s val=0x%02x\n", regname(addr), val);
1493 missing("unknown byte write");
1494 }
1495 }
1496
1497 static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1498 {
1499 /* SCBStatus is readonly. */
1500 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
1501 e100_write_reg2(s, addr, val);
1502 }
1503
1504 switch (addr) {
1505 case SCBStatus:
1506 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1507 s->mem[SCBAck] = (val >> 8);
1508 eepro100_acknowledge(s);
1509 break;
1510 case SCBCmd:
1511 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1512 eepro100_write_command(s, val);
1513 eepro100_write1(s, SCBIntmask, val >> 8);
1514 break;
1515 case SCBPointer:
1516 case SCBPointer + 2:
1517 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1518 break;
1519 case SCBPort:
1520 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1521 break;
1522 case SCBPort + 2:
1523 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1524 eepro100_write_port(s);
1525 break;
1526 case SCBeeprom:
1527 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1528 eepro100_write_eeprom(s->eeprom, val);
1529 break;
1530 default:
1531 logout("addr=%s val=0x%04x\n", regname(addr), val);
1532 missing("unknown word write");
1533 }
1534 }
1535
1536 static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1537 {
1538 if (addr <= sizeof(s->mem) - sizeof(val)) {
1539 e100_write_reg4(s, addr, val);
1540 }
1541
1542 switch (addr) {
1543 case SCBPointer:
1544 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1545 break;
1546 case SCBPort:
1547 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1548 eepro100_write_port(s);
1549 break;
1550 case SCBCtrlMDI:
1551 eepro100_write_mdi(s, val);
1552 break;
1553 default:
1554 logout("addr=%s val=0x%08x\n", regname(addr), val);
1555 missing("unknown longword write");
1556 }
1557 }
1558
1559 /*****************************************************************************
1560 *
1561 * Port mapped I/O.
1562 *
1563 ****************************************************************************/
1564
1565 static uint32_t ioport_read1(void *opaque, uint32_t addr)
1566 {
1567 EEPRO100State *s = opaque;
1568 #if 0
1569 logout("addr=%s\n", regname(addr));
1570 #endif
1571 return eepro100_read1(s, addr - s->region1);
1572 }
1573
1574 static uint32_t ioport_read2(void *opaque, uint32_t addr)
1575 {
1576 EEPRO100State *s = opaque;
1577 return eepro100_read2(s, addr - s->region1);
1578 }
1579
1580 static uint32_t ioport_read4(void *opaque, uint32_t addr)
1581 {
1582 EEPRO100State *s = opaque;
1583 return eepro100_read4(s, addr - s->region1);
1584 }
1585
1586 static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
1587 {
1588 EEPRO100State *s = opaque;
1589 #if 0
1590 logout("addr=%s val=0x%02x\n", regname(addr), val);
1591 #endif
1592 eepro100_write1(s, addr - s->region1, val);
1593 }
1594
1595 static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
1596 {
1597 EEPRO100State *s = opaque;
1598 eepro100_write2(s, addr - s->region1, val);
1599 }
1600
1601 static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
1602 {
1603 EEPRO100State *s = opaque;
1604 eepro100_write4(s, addr - s->region1, val);
1605 }
1606
1607 /***********************************************************/
1608 /* PCI EEPRO100 definitions */
1609
1610 static void pci_map(PCIDevice * pci_dev, int region_num,
1611 pcibus_t addr, pcibus_t size, int type)
1612 {
1613 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1614
1615 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1616 "size=0x%08"FMT_PCIBUS", type=%d\n",
1617 region_num, addr, size, type));
1618
1619 assert(region_num == 1);
1620 register_ioport_write(addr, size, 1, ioport_write1, s);
1621 register_ioport_read(addr, size, 1, ioport_read1, s);
1622 register_ioport_write(addr, size, 2, ioport_write2, s);
1623 register_ioport_read(addr, size, 2, ioport_read2, s);
1624 register_ioport_write(addr, size, 4, ioport_write4, s);
1625 register_ioport_read(addr, size, 4, ioport_read4, s);
1626
1627 s->region1 = addr;
1628 }
1629
1630 /*****************************************************************************
1631 *
1632 * Memory mapped I/O.
1633 *
1634 ****************************************************************************/
1635
1636 static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1637 {
1638 EEPRO100State *s = opaque;
1639 #if 0
1640 logout("addr=%s val=0x%02x\n", regname(addr), val);
1641 #endif
1642 eepro100_write1(s, addr, val);
1643 }
1644
1645 static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1646 {
1647 EEPRO100State *s = opaque;
1648 #if 0
1649 logout("addr=%s val=0x%02x\n", regname(addr), val);
1650 #endif
1651 eepro100_write2(s, addr, val);
1652 }
1653
1654 static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1655 {
1656 EEPRO100State *s = opaque;
1657 #if 0
1658 logout("addr=%s val=0x%02x\n", regname(addr), val);
1659 #endif
1660 eepro100_write4(s, addr, val);
1661 }
1662
1663 static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
1664 {
1665 EEPRO100State *s = opaque;
1666 #if 0
1667 logout("addr=%s\n", regname(addr));
1668 #endif
1669 return eepro100_read1(s, addr);
1670 }
1671
1672 static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
1673 {
1674 EEPRO100State *s = opaque;
1675 #if 0
1676 logout("addr=%s\n", regname(addr));
1677 #endif
1678 return eepro100_read2(s, addr);
1679 }
1680
1681 static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
1682 {
1683 EEPRO100State *s = opaque;
1684 #if 0
1685 logout("addr=%s\n", regname(addr));
1686 #endif
1687 return eepro100_read4(s, addr);
1688 }
1689
1690 static CPUWriteMemoryFunc * const pci_mmio_write[] = {
1691 pci_mmio_writeb,
1692 pci_mmio_writew,
1693 pci_mmio_writel
1694 };
1695
1696 static CPUReadMemoryFunc * const pci_mmio_read[] = {
1697 pci_mmio_readb,
1698 pci_mmio_readw,
1699 pci_mmio_readl
1700 };
1701
1702 static int nic_can_receive(VLANClientState *nc)
1703 {
1704 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1705 TRACE(RXTX, logout("%p\n", s));
1706 return get_ru_state(s) == ru_ready;
1707 #if 0
1708 return !eepro100_buffer_full(s);
1709 #endif
1710 }
1711
1712 static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size)
1713 {
1714 /* TODO:
1715 * - Magic packets should set bit 30 in power management driver register.
1716 * - Interesting packets should set bit 29 in power management driver register.
1717 */
1718 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1719 uint16_t rfd_status = 0xa000;
1720 #if defined(CONFIG_PAD_RECEIVED_FRAMES)
1721 uint8_t min_buf[60];
1722 #endif
1723 static const uint8_t broadcast_macaddr[6] =
1724 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1725
1726 #if defined(CONFIG_PAD_RECEIVED_FRAMES)
1727 /* Pad to minimum Ethernet frame length */
1728 if (size < sizeof(min_buf)) {
1729 memcpy(min_buf, buf, size);
1730 memset(&min_buf[size], 0, sizeof(min_buf) - size);
1731 buf = min_buf;
1732 size = sizeof(min_buf);
1733 }
1734 #endif
1735
1736 if (s->configuration[8] & 0x80) {
1737 /* CSMA is disabled. */
1738 logout("%p received while CSMA is disabled\n", s);
1739 return -1;
1740 #if !defined(CONFIG_PAD_RECEIVED_FRAMES)
1741 } else if (size < 64 && (s->configuration[7] & BIT(0))) {
1742 /* Short frame and configuration byte 7/0 (discard short receive) set:
1743 * Short frame is discarded */
1744 logout("%p received short frame (%zu byte)\n", s, size);
1745 s->statistics.rx_short_frame_errors++;
1746 return -1;
1747 #endif
1748 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) {
1749 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1750 * Long frames are discarded. */
1751 logout("%p received long frame (%zu byte), ignored\n", s, size);
1752 return -1;
1753 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { /* !!! */
1754 /* Frame matches individual address. */
1755 /* TODO: check configuration byte 15/4 (ignore U/L). */
1756 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
1757 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1758 /* Broadcast frame. */
1759 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
1760 rfd_status |= 0x0002;
1761 } else if (buf[0] & 0x01) {
1762 /* Multicast frame. */
1763 TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size)));
1764 if (s->configuration[21] & BIT(3)) {
1765 /* Multicast all bit is set, receive all multicast frames. */
1766 } else {
1767 unsigned mcast_idx = compute_mcast_idx(buf);
1768 assert(mcast_idx < 64);
1769 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1770 /* Multicast frame is allowed in hash table. */
1771 } else if (s->configuration[15] & BIT(0)) {
1772 /* Promiscuous: receive all. */
1773 rfd_status |= 0x0004;
1774 } else {
1775 TRACE(RXTX, logout("%p multicast ignored\n", s));
1776 return -1;
1777 }
1778 }
1779 /* TODO: Next not for promiscuous mode? */
1780 rfd_status |= 0x0002;
1781 } else if (s->configuration[15] & BIT(0)) {
1782 /* Promiscuous: receive all. */
1783 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
1784 rfd_status |= 0x0004;
1785 } else if (s->configuration[20] & BIT(6)) {
1786 /* Multiple IA bit set. */
1787 unsigned mcast_idx = compute_mcast_idx(buf);
1788 assert(mcast_idx < 64);
1789 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1790 TRACE(RXTX, logout("%p accepted, multiple IA bit set\n", s));
1791 } else {
1792 TRACE(RXTX, logout("%p frame ignored, multiple IA bit set\n", s));
1793 return -1;
1794 }
1795 } else {
1796 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
1797 nic_dump(buf, size)));
1798 return size;
1799 }
1800
1801 if (get_ru_state(s) != ru_ready) {
1802 /* No resources available. */
1803 logout("no resources, state=%u\n", get_ru_state(s));
1804 /* TODO: RNR interrupt only at first failed frame? */
1805 eepro100_rnr_interrupt(s);
1806 s->statistics.rx_resource_errors++;
1807 #if 0
1808 assert(!"no resources");
1809 #endif
1810 return -1;
1811 }
1812 /* !!! */
1813 eepro100_rx_t rx;
1814 cpu_physical_memory_read(s->ru_base + s->ru_offset, &rx,
1815 sizeof(eepro100_rx_t));
1816 uint16_t rfd_command = le16_to_cpu(rx.command);
1817 uint16_t rfd_size = le16_to_cpu(rx.size);
1818
1819 if (size > rfd_size) {
1820 logout("Receive buffer (%" PRId16 " bytes) too small for data "
1821 "(%zu bytes); data truncated\n", rfd_size, size);
1822 size = rfd_size;
1823 }
1824 #if !defined(CONFIG_PAD_RECEIVED_FRAMES)
1825 if (size < 64) {
1826 rfd_status |= 0x0080;
1827 }
1828 #endif
1829 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1830 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
1831 e100_stw_le_phys(s->ru_base + s->ru_offset +
1832 offsetof(eepro100_rx_t, status), rfd_status);
1833 e100_stw_le_phys(s->ru_base + s->ru_offset +
1834 offsetof(eepro100_rx_t, count), size);
1835 /* Early receive interrupt not supported. */
1836 #if 0
1837 eepro100_er_interrupt(s);
1838 #endif
1839 /* Receive CRC Transfer not supported. */
1840 if (s->configuration[18] & BIT(2)) {
1841 missing("Receive CRC Transfer");
1842 return -1;
1843 }
1844 /* TODO: check stripping enable bit. */
1845 #if 0
1846 assert(!(s->configuration[17] & BIT(0)));
1847 #endif
1848 cpu_physical_memory_write(s->ru_base + s->ru_offset +
1849 sizeof(eepro100_rx_t), buf, size);
1850 s->statistics.rx_good_frames++;
1851 eepro100_fr_interrupt(s);
1852 s->ru_offset = le32_to_cpu(rx.link);
1853 if (rfd_command & COMMAND_EL) {
1854 /* EL bit is set, so this was the last frame. */
1855 logout("receive: Running out of frames\n");
1856 set_ru_state(s, ru_suspended);
1857 }
1858 if (rfd_command & COMMAND_S) {
1859 /* S bit is set. */
1860 set_ru_state(s, ru_suspended);
1861 }
1862 return size;
1863 }
1864
1865 static const VMStateDescription vmstate_eepro100 = {
1866 .version_id = 3,
1867 .minimum_version_id = 2,
1868 .minimum_version_id_old = 2,
1869 .fields = (VMStateField []) {
1870 VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1871 VMSTATE_UNUSED(32),
1872 VMSTATE_BUFFER(mult, EEPRO100State),
1873 VMSTATE_BUFFER(mem, EEPRO100State),
1874 /* Save all members of struct between scb_stat and mem. */
1875 VMSTATE_UINT8(scb_stat, EEPRO100State),
1876 VMSTATE_UINT8(int_stat, EEPRO100State),
1877 VMSTATE_UNUSED(3*4),
1878 VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1879 VMSTATE_UNUSED(19*4),
1880 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1881 /* The eeprom should be saved and restored by its own routines. */
1882 VMSTATE_UINT32(device, EEPRO100State),
1883 /* TODO check device. */
1884 VMSTATE_UINT32(cu_base, EEPRO100State),
1885 VMSTATE_UINT32(cu_offset, EEPRO100State),
1886 VMSTATE_UINT32(ru_base, EEPRO100State),
1887 VMSTATE_UINT32(ru_offset, EEPRO100State),
1888 VMSTATE_UINT32(statsaddr, EEPRO100State),
1889 /* Save eepro100_stats_t statistics. */
1890 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1891 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1892 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1893 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1894 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1895 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1896 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1897 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1898 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1899 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1900 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1901 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1902 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1903 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1904 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1905 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1906 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1907 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1908 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1909 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1910 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
1911 /* Configuration bytes. */
1912 VMSTATE_BUFFER(configuration, EEPRO100State),
1913 VMSTATE_END_OF_LIST()
1914 }
1915 };
1916
1917 static void nic_cleanup(VLANClientState *nc)
1918 {
1919 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1920
1921 s->nic = NULL;
1922 }
1923
1924 static int pci_nic_uninit(PCIDevice *pci_dev)
1925 {
1926 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1927
1928 cpu_unregister_io_memory(s->mmio_index);
1929 vmstate_unregister(&pci_dev->qdev, s->vmstate, s);
1930 eeprom93xx_free(&pci_dev->qdev, s->eeprom);
1931 qemu_del_vlan_client(&s->nic->nc);
1932 return 0;
1933 }
1934
1935 static NetClientInfo net_eepro100_info = {
1936 .type = NET_CLIENT_TYPE_NIC,
1937 .size = sizeof(NICState),
1938 .can_receive = nic_can_receive,
1939 .receive = nic_receive,
1940 .cleanup = nic_cleanup,
1941 };
1942
1943 static int e100_nic_init(PCIDevice *pci_dev)
1944 {
1945 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1946 E100PCIDeviceInfo *e100_device = DO_UPCAST(E100PCIDeviceInfo, pci.qdev,
1947 pci_dev->qdev.info);
1948
1949 TRACE(OTHER, logout("\n"));
1950
1951 s->device = e100_device->device;
1952
1953 e100_pci_reset(s, e100_device);
1954
1955 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1956 * i82559 and later support 64 or 256 word EEPROM. */
1957 s->eeprom = eeprom93xx_new(&pci_dev->qdev, EEPROM_SIZE);
1958
1959 /* Handler for memory-mapped I/O */
1960 s->mmio_index =
1961 cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s,
1962 DEVICE_LITTLE_ENDIAN);
1963
1964 pci_register_bar_simple(&s->dev, 0, PCI_MEM_SIZE,
1965 PCI_BASE_ADDRESS_MEM_PREFETCH, s->mmio_index);
1966
1967 pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
1968 pci_map);
1969 pci_register_bar_simple(&s->dev, 2, PCI_FLASH_SIZE, 0, s->mmio_index);
1970
1971 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1972 logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));
1973 assert(s->region1 == 0);
1974
1975 nic_reset(s);
1976
1977 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
1978 pci_dev->qdev.info->name, pci_dev->qdev.id, s);
1979
1980 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
1981 TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
1982
1983 qemu_register_reset(nic_reset, s);
1984
1985 s->vmstate = qemu_malloc(sizeof(vmstate_eepro100));
1986 memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
1987 s->vmstate->name = s->nic->nc.model;
1988 vmstate_register(&pci_dev->qdev, -1, s->vmstate, s);
1989
1990 add_boot_device_path(s->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
1991
1992 return 0;
1993 }
1994
1995 static E100PCIDeviceInfo e100_devices[] = {
1996 {
1997 .pci.qdev.name = "i82550",
1998 .pci.qdev.desc = "Intel i82550 Ethernet",
1999 .device = i82550,
2000 /* TODO: check device id. */
2001 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
2002 /* Revision ID: 0x0c, 0x0d, 0x0e. */
2003 .revision = 0x0e,
2004 /* TODO: check size of statistical counters. */
2005 .stats_size = 80,
2006 /* TODO: check extended tcb support. */
2007 .has_extended_tcb_support = true,
2008 .power_management = true,
2009 },{
2010 .pci.qdev.name = "i82551",
2011 .pci.qdev.desc = "Intel i82551 Ethernet",
2012 .device = i82551,
2013 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
2014 /* Revision ID: 0x0f, 0x10. */
2015 .revision = 0x0f,
2016 /* TODO: check size of statistical counters. */
2017 .stats_size = 80,
2018 .has_extended_tcb_support = true,
2019 .power_management = true,
2020 },{
2021 .pci.qdev.name = "i82557a",
2022 .pci.qdev.desc = "Intel i82557A Ethernet",
2023 .device = i82557A,
2024 .device_id = PCI_DEVICE_ID_INTEL_82557,
2025 .revision = 0x01,
2026 .power_management = false,
2027 },{
2028 .pci.qdev.name = "i82557b",
2029 .pci.qdev.desc = "Intel i82557B Ethernet",
2030 .device = i82557B,
2031 .device_id = PCI_DEVICE_ID_INTEL_82557,
2032 .revision = 0x02,
2033 .power_management = false,
2034 },{
2035 .pci.qdev.name = "i82557c",
2036 .pci.qdev.desc = "Intel i82557C Ethernet",
2037 .device = i82557C,
2038 .device_id = PCI_DEVICE_ID_INTEL_82557,
2039 .revision = 0x03,
2040 .power_management = false,
2041 },{
2042 .pci.qdev.name = "i82558a",
2043 .pci.qdev.desc = "Intel i82558A Ethernet",
2044 .device = i82558A,
2045 .device_id = PCI_DEVICE_ID_INTEL_82557,
2046 .revision = 0x04,
2047 .stats_size = 76,
2048 .has_extended_tcb_support = true,
2049 .power_management = true,
2050 },{
2051 .pci.qdev.name = "i82558b",
2052 .pci.qdev.desc = "Intel i82558B Ethernet",
2053 .device = i82558B,
2054 .device_id = PCI_DEVICE_ID_INTEL_82557,
2055 .revision = 0x05,
2056 .stats_size = 76,
2057 .has_extended_tcb_support = true,
2058 .power_management = true,
2059 },{
2060 .pci.qdev.name = "i82559a",
2061 .pci.qdev.desc = "Intel i82559A Ethernet",
2062 .device = i82559A,
2063 .device_id = PCI_DEVICE_ID_INTEL_82557,
2064 .revision = 0x06,
2065 .stats_size = 80,
2066 .has_extended_tcb_support = true,
2067 .power_management = true,
2068 },{
2069 .pci.qdev.name = "i82559b",
2070 .pci.qdev.desc = "Intel i82559B Ethernet",
2071 .device = i82559B,
2072 .device_id = PCI_DEVICE_ID_INTEL_82557,
2073 .revision = 0x07,
2074 .stats_size = 80,
2075 .has_extended_tcb_support = true,
2076 .power_management = true,
2077 },{
2078 .pci.qdev.name = "i82559c",
2079 .pci.qdev.desc = "Intel i82559C Ethernet",
2080 .device = i82559C,
2081 .device_id = PCI_DEVICE_ID_INTEL_82557,
2082 #if 0
2083 .revision = 0x08,
2084 #endif
2085 /* TODO: Windows wants revision id 0x0c. */
2086 .revision = 0x0c,
2087 .stats_size = 80,
2088 .has_extended_tcb_support = true,
2089 .power_management = true,
2090 },{
2091 .pci.qdev.name = "i82559er",
2092 .pci.qdev.desc = "Intel i82559ER Ethernet",
2093 .device = i82559ER,
2094 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
2095 .revision = 0x09,
2096 .stats_size = 80,
2097 .has_extended_tcb_support = true,
2098 .power_management = true,
2099 },{
2100 .pci.qdev.name = "i82562",
2101 .pci.qdev.desc = "Intel i82562 Ethernet",
2102 .device = i82562,
2103 /* TODO: check device id. */
2104 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
2105 /* TODO: wrong revision id. */
2106 .revision = 0x0e,
2107 .stats_size = 80,
2108 .has_extended_tcb_support = true,
2109 .power_management = true,
2110 },{
2111 /* Toshiba Tecra 8200. */
2112 .pci.qdev.name = "i82801",
2113 .pci.qdev.desc = "Intel i82801 Ethernet",
2114 .device = i82801,
2115 .device_id = 0x2449,
2116 .revision = 0x03,
2117 .stats_size = 80,
2118 .has_extended_tcb_support = true,
2119 .power_management = true,
2120 }
2121 };
2122
2123 static Property e100_properties[] = {
2124 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2125 DEFINE_PROP_END_OF_LIST(),
2126 };
2127
2128 static void eepro100_register_devices(void)
2129 {
2130 size_t i;
2131 for (i = 0; i < ARRAY_SIZE(e100_devices); i++) {
2132 PCIDeviceInfo *pci_dev = &e100_devices[i].pci;
2133 /* We use the same rom file for all device ids.
2134 QEMU fixes the device id during rom load. */
2135 pci_dev->romfile = "gpxe-eepro100-80861209.rom";
2136 pci_dev->init = e100_nic_init;
2137 pci_dev->exit = pci_nic_uninit;
2138 pci_dev->qdev.props = e100_properties;
2139 pci_dev->qdev.size = sizeof(EEPRO100State);
2140 pci_qdev_register(pci_dev);
2141 }
2142 }
2143
2144 device_init(eepro100_register_devices)