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eepro100: Remove type casts which are no longer needed
[qemu.git] / hw / eepro100.c
1 /*
2 * QEMU i8255x (PRO100) emulation
3 *
4 * Copyright (C) 2006-2011 Stefan Weil
5 *
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 2 of the License, or
12 * (at your option) version 3 or any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 *
22 * Tested features (i82559):
23 * PXE boot (i386) ok
24 * Linux networking (i386) ok
25 *
26 * Untested:
27 * non-i386 platforms
28 * Windows networking
29 *
30 * References:
31 *
32 * Intel 8255x 10/100 Mbps Ethernet Controller Family
33 * Open Source Software Developer Manual
34 *
35 * TODO:
36 * * PHY emulation should be separated from nic emulation.
37 * Most nic emulations could share the same phy code.
38 * * i82550 is untested. It is programmed like the i82559.
39 * * i82562 is untested. It is programmed like the i82559.
40 * * Power management (i82558 and later) is not implemented.
41 * * Wake-on-LAN is not implemented.
42 */
43
44 #include <stddef.h> /* offsetof */
45 #include "hw.h"
46 #include "pci.h"
47 #include "net.h"
48 #include "eeprom93xx.h"
49 #include "sysemu.h"
50
51 #define KiB 1024
52
53 /* Debug EEPRO100 card. */
54 #if 0
55 # define DEBUG_EEPRO100
56 #endif
57
58 #ifdef DEBUG_EEPRO100
59 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
60 #else
61 #define logout(fmt, ...) ((void)0)
62 #endif
63
64 /* Set flags to 0 to disable debug output. */
65 #define INT 1 /* interrupt related actions */
66 #define MDI 1 /* mdi related actions */
67 #define OTHER 1
68 #define RXTX 1
69 #define EEPROM 1 /* eeprom related actions */
70
71 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
72
73 #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
74
75 #define MAX_ETH_FRAME_SIZE 1514
76
77 /* This driver supports several different devices which are declared here. */
78 #define i82550 0x82550
79 #define i82551 0x82551
80 #define i82557A 0x82557a
81 #define i82557B 0x82557b
82 #define i82557C 0x82557c
83 #define i82558A 0x82558a
84 #define i82558B 0x82558b
85 #define i82559A 0x82559a
86 #define i82559B 0x82559b
87 #define i82559C 0x82559c
88 #define i82559ER 0x82559e
89 #define i82562 0x82562
90 #define i82801 0x82801
91
92 /* Use 64 word EEPROM. TODO: could be a runtime option. */
93 #define EEPROM_SIZE 64
94
95 #define PCI_MEM_SIZE (4 * KiB)
96 #define PCI_IO_SIZE 64
97 #define PCI_FLASH_SIZE (128 * KiB)
98
99 #define BIT(n) (1 << (n))
100 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
101
102 /* The SCB accepts the following controls for the Tx and Rx units: */
103 #define CU_NOP 0x0000 /* No operation. */
104 #define CU_START 0x0010 /* CU start. */
105 #define CU_RESUME 0x0020 /* CU resume. */
106 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
107 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
108 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
109 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
110 #define CU_SRESUME 0x00a0 /* CU static resume. */
111
112 #define RU_NOP 0x0000
113 #define RX_START 0x0001
114 #define RX_RESUME 0x0002
115 #define RU_ABORT 0x0004
116 #define RX_ADDR_LOAD 0x0006
117 #define RX_RESUMENR 0x0007
118 #define INT_MASK 0x0100
119 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
120
121 typedef struct {
122 PCIDeviceInfo pci;
123 uint32_t device;
124 uint16_t device_id;
125 uint8_t revision;
126 uint8_t stats_size;
127 bool has_extended_tcb_support;
128 bool power_management;
129 } E100PCIDeviceInfo;
130
131 /* Offsets to the various registers.
132 All accesses need not be longword aligned. */
133 enum speedo_offsets {
134 SCBStatus = 0, /* Status Word. */
135 SCBAck = 1,
136 SCBCmd = 2, /* Rx/Command Unit command and status. */
137 SCBIntmask = 3,
138 SCBPointer = 4, /* General purpose pointer. */
139 SCBPort = 8, /* Misc. commands and operands. */
140 SCBflash = 12, /* Flash memory control. */
141 SCBeeprom = 14, /* EEPROM control. */
142 SCBCtrlMDI = 16, /* MDI interface control. */
143 SCBEarlyRx = 20, /* Early receive byte count. */
144 SCBFlow = 24, /* Flow Control. */
145 SCBpmdr = 27, /* Power Management Driver. */
146 SCBgctrl = 28, /* General Control. */
147 SCBgstat = 29, /* General Status. */
148 };
149
150 /* A speedo3 transmit buffer descriptor with two buffers... */
151 typedef struct {
152 uint16_t status;
153 uint16_t command;
154 uint32_t link; /* void * */
155 uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */
156 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
157 uint8_t tx_threshold; /* transmit threshold */
158 uint8_t tbd_count; /* TBD number */
159 #if 0
160 /* This constitutes two "TBD" entries: hdr and data */
161 uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
162 int32_t tx_buf_size0; /* Length of Tx hdr. */
163 uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
164 int32_t tx_buf_size1; /* Length of Tx data. */
165 #endif
166 } eepro100_tx_t;
167
168 /* Receive frame descriptor. */
169 typedef struct {
170 int16_t status;
171 uint16_t command;
172 uint32_t link; /* struct RxFD * */
173 uint32_t rx_buf_addr; /* void * */
174 uint16_t count;
175 uint16_t size;
176 char packet[MAX_ETH_FRAME_SIZE + 4];
177 } eepro100_rx_t;
178
179 typedef enum {
180 COMMAND_EL = BIT(15),
181 COMMAND_S = BIT(14),
182 COMMAND_I = BIT(13),
183 COMMAND_NC = BIT(4),
184 COMMAND_SF = BIT(3),
185 COMMAND_CMD = BITS(2, 0),
186 } scb_command_bit;
187
188 typedef enum {
189 STATUS_C = BIT(15),
190 STATUS_OK = BIT(13),
191 } scb_status_bit;
192
193 typedef struct {
194 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
195 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
196 tx_multiple_collisions, tx_total_collisions;
197 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
198 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
199 rx_short_frame_errors;
200 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
201 uint16_t xmt_tco_frames, rcv_tco_frames;
202 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
203 uint32_t reserved[4];
204 } eepro100_stats_t;
205
206 typedef enum {
207 cu_idle = 0,
208 cu_suspended = 1,
209 cu_active = 2,
210 cu_lpq_active = 2,
211 cu_hqp_active = 3
212 } cu_state_t;
213
214 typedef enum {
215 ru_idle = 0,
216 ru_suspended = 1,
217 ru_no_resources = 2,
218 ru_ready = 4
219 } ru_state_t;
220
221 typedef struct {
222 PCIDevice dev;
223 /* Hash register (multicast mask array, multiple individual addresses). */
224 uint8_t mult[8];
225 int mmio_index;
226 NICState *nic;
227 NICConf conf;
228 uint8_t scb_stat; /* SCB stat/ack byte */
229 uint8_t int_stat; /* PCI interrupt status */
230 /* region must not be saved by nic_save. */
231 uint32_t region1; /* PCI region 1 address */
232 uint16_t mdimem[32];
233 eeprom_t *eeprom;
234 uint32_t device; /* device variant */
235 uint32_t pointer;
236 /* (cu_base + cu_offset) address the next command block in the command block list. */
237 uint32_t cu_base; /* CU base address */
238 uint32_t cu_offset; /* CU address offset */
239 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
240 uint32_t ru_base; /* RU base address */
241 uint32_t ru_offset; /* RU address offset */
242 uint32_t statsaddr; /* pointer to eepro100_stats_t */
243
244 /* Temporary status information (no need to save these values),
245 * used while processing CU commands. */
246 eepro100_tx_t tx; /* transmit buffer descriptor */
247 uint32_t cb_address; /* = cu_base + cu_offset */
248
249 /* Statistical counters. Also used for wake-up packet (i82559). */
250 eepro100_stats_t statistics;
251
252 /* Configuration bytes. */
253 uint8_t configuration[22];
254
255 /* Data in mem is always in the byte order of the controller (le). */
256 uint8_t mem[PCI_MEM_SIZE];
257 /* vmstate for each particular nic */
258 VMStateDescription *vmstate;
259
260 /* Quasi static device properties (no need to save them). */
261 uint16_t stats_size;
262 bool has_extended_tcb_support;
263 } EEPRO100State;
264
265 /* Word indices in EEPROM. */
266 typedef enum {
267 EEPROM_CNFG_MDIX = 0x03,
268 EEPROM_ID = 0x05,
269 EEPROM_PHY_ID = 0x06,
270 EEPROM_VENDOR_ID = 0x0c,
271 EEPROM_CONFIG_ASF = 0x0d,
272 EEPROM_DEVICE_ID = 0x23,
273 EEPROM_SMBUS_ADDR = 0x90,
274 } EEPROMOffset;
275
276 /* Bit values for EEPROM ID word. */
277 typedef enum {
278 EEPROM_ID_MDM = BIT(0), /* Modem */
279 EEPROM_ID_STB = BIT(1), /* Standby Enable */
280 EEPROM_ID_WMR = BIT(2), /* ??? */
281 EEPROM_ID_WOL = BIT(5), /* Wake on LAN */
282 EEPROM_ID_DPD = BIT(6), /* Deep Power Down */
283 EEPROM_ID_ALT = BIT(7), /* */
284 /* BITS(10, 8) device revision */
285 EEPROM_ID_BD = BIT(11), /* boot disable */
286 EEPROM_ID_ID = BIT(13), /* id bit */
287 /* BITS(15, 14) signature */
288 EEPROM_ID_VALID = BIT(14), /* signature for valid eeprom */
289 } eeprom_id_bit;
290
291 /* Default values for MDI (PHY) registers */
292 static const uint16_t eepro100_mdi_default[] = {
293 /* MDI Registers 0 - 6, 7 */
294 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
295 /* MDI Registers 8 - 15 */
296 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
297 /* MDI Registers 16 - 31 */
298 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
299 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
300 };
301
302 /* Readonly mask for MDI (PHY) registers */
303 static const uint16_t eepro100_mdi_mask[] = {
304 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
305 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
306 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
307 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
308 };
309
310 /* XXX: optimize */
311 static void stl_le_phys(target_phys_addr_t addr, uint32_t val)
312 {
313 val = cpu_to_le32(val);
314 cpu_physical_memory_write(addr, &val, sizeof(val));
315 }
316
317 #define POLYNOMIAL 0x04c11db6
318
319 /* From FreeBSD */
320 /* XXX: optimize */
321 static unsigned compute_mcast_idx(const uint8_t * ep)
322 {
323 uint32_t crc;
324 int carry, i, j;
325 uint8_t b;
326
327 crc = 0xffffffff;
328 for (i = 0; i < 6; i++) {
329 b = *ep++;
330 for (j = 0; j < 8; j++) {
331 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
332 crc <<= 1;
333 b >>= 1;
334 if (carry) {
335 crc = ((crc ^ POLYNOMIAL) | carry);
336 }
337 }
338 }
339 return (crc & BITS(7, 2)) >> 2;
340 }
341
342 #if defined(DEBUG_EEPRO100)
343 static const char *nic_dump(const uint8_t * buf, unsigned size)
344 {
345 static char dump[3 * 16 + 1];
346 char *p = &dump[0];
347 if (size > 16) {
348 size = 16;
349 }
350 while (size-- > 0) {
351 p += sprintf(p, " %02x", *buf++);
352 }
353 return dump;
354 }
355 #endif /* DEBUG_EEPRO100 */
356
357 enum scb_stat_ack {
358 stat_ack_not_ours = 0x00,
359 stat_ack_sw_gen = 0x04,
360 stat_ack_rnr = 0x10,
361 stat_ack_cu_idle = 0x20,
362 stat_ack_frame_rx = 0x40,
363 stat_ack_cu_cmd_done = 0x80,
364 stat_ack_not_present = 0xFF,
365 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
366 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
367 };
368
369 static void disable_interrupt(EEPRO100State * s)
370 {
371 if (s->int_stat) {
372 TRACE(INT, logout("interrupt disabled\n"));
373 qemu_irq_lower(s->dev.irq[0]);
374 s->int_stat = 0;
375 }
376 }
377
378 static void enable_interrupt(EEPRO100State * s)
379 {
380 if (!s->int_stat) {
381 TRACE(INT, logout("interrupt enabled\n"));
382 qemu_irq_raise(s->dev.irq[0]);
383 s->int_stat = 1;
384 }
385 }
386
387 static void eepro100_acknowledge(EEPRO100State * s)
388 {
389 s->scb_stat &= ~s->mem[SCBAck];
390 s->mem[SCBAck] = s->scb_stat;
391 if (s->scb_stat == 0) {
392 disable_interrupt(s);
393 }
394 }
395
396 static void eepro100_interrupt(EEPRO100State * s, uint8_t status)
397 {
398 uint8_t mask = ~s->mem[SCBIntmask];
399 s->mem[SCBAck] |= status;
400 status = s->scb_stat = s->mem[SCBAck];
401 status &= (mask | 0x0f);
402 #if 0
403 status &= (~s->mem[SCBIntmask] | 0x0xf);
404 #endif
405 if (status && (mask & 0x01)) {
406 /* SCB mask and SCB Bit M do not disable interrupt. */
407 enable_interrupt(s);
408 } else if (s->int_stat) {
409 disable_interrupt(s);
410 }
411 }
412
413 static void eepro100_cx_interrupt(EEPRO100State * s)
414 {
415 /* CU completed action command. */
416 /* Transmit not ok (82557 only, not in emulation). */
417 eepro100_interrupt(s, 0x80);
418 }
419
420 static void eepro100_cna_interrupt(EEPRO100State * s)
421 {
422 /* CU left the active state. */
423 eepro100_interrupt(s, 0x20);
424 }
425
426 static void eepro100_fr_interrupt(EEPRO100State * s)
427 {
428 /* RU received a complete frame. */
429 eepro100_interrupt(s, 0x40);
430 }
431
432 static void eepro100_rnr_interrupt(EEPRO100State * s)
433 {
434 /* RU is not ready. */
435 eepro100_interrupt(s, 0x10);
436 }
437
438 static void eepro100_mdi_interrupt(EEPRO100State * s)
439 {
440 /* MDI completed read or write cycle. */
441 eepro100_interrupt(s, 0x08);
442 }
443
444 static void eepro100_swi_interrupt(EEPRO100State * s)
445 {
446 /* Software has requested an interrupt. */
447 eepro100_interrupt(s, 0x04);
448 }
449
450 #if 0
451 static void eepro100_fcp_interrupt(EEPRO100State * s)
452 {
453 /* Flow control pause interrupt (82558 and later). */
454 eepro100_interrupt(s, 0x01);
455 }
456 #endif
457
458 static void e100_pci_reset(EEPRO100State * s, E100PCIDeviceInfo *e100_device)
459 {
460 uint32_t device = s->device;
461 uint8_t *pci_conf = s->dev.config;
462
463 TRACE(OTHER, logout("%p\n", s));
464
465 /* PCI Vendor ID */
466 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
467 /* PCI Device ID */
468 pci_config_set_device_id(pci_conf, e100_device->device_id);
469 /* PCI Status */
470 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
471 PCI_STATUS_FAST_BACK);
472 /* PCI Revision ID */
473 pci_config_set_revision(pci_conf, e100_device->revision);
474 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
475 /* PCI Latency Timer */
476 pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */
477 /* Capability Pointer is set by PCI framework. */
478 /* Interrupt Line */
479 /* Interrupt Pin */
480 pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 1); /* interrupt pin A */
481 /* Minimum Grant */
482 pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08);
483 /* Maximum Latency */
484 pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18);
485
486 s->stats_size = e100_device->stats_size;
487 s->has_extended_tcb_support = e100_device->has_extended_tcb_support;
488
489 switch (device) {
490 case i82550:
491 case i82551:
492 case i82557A:
493 case i82557B:
494 case i82557C:
495 case i82558A:
496 case i82558B:
497 case i82559A:
498 case i82559B:
499 case i82559ER:
500 case i82562:
501 case i82801:
502 break;
503 case i82559C:
504 #if EEPROM_SIZE > 0
505 pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, PCI_VENDOR_ID_INTEL);
506 pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0040);
507 #endif
508 break;
509 default:
510 logout("Device %X is undefined!\n", device);
511 }
512
513 /* Standard TxCB. */
514 s->configuration[6] |= BIT(4);
515
516 /* Standard statistical counters. */
517 s->configuration[6] |= BIT(5);
518
519 if (s->stats_size == 80) {
520 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
521 if (s->configuration[6] & BIT(2)) {
522 /* TCO statistical counters. */
523 assert(s->configuration[6] & BIT(5));
524 } else {
525 if (s->configuration[6] & BIT(5)) {
526 /* No extended statistical counters, i82557 compatible. */
527 s->stats_size = 64;
528 } else {
529 /* i82558 compatible. */
530 s->stats_size = 76;
531 }
532 }
533 } else {
534 if (s->configuration[6] & BIT(5)) {
535 /* No extended statistical counters. */
536 s->stats_size = 64;
537 }
538 }
539 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
540
541 if (e100_device->power_management) {
542 /* Power Management Capabilities */
543 int cfg_offset = 0xdc;
544 int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM,
545 cfg_offset, PCI_PM_SIZEOF);
546 assert(r >= 0);
547 pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
548 #if 0 /* TODO: replace dummy code for power management emulation. */
549 /* TODO: Power Management Control / Status. */
550 pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000);
551 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
552 pci_set_byte(pci_conf + cfg_offset + PCI_PM_PPB_EXTENSIONS, 0x0000);
553 #endif
554 }
555
556 #if EEPROM_SIZE > 0
557 if (device == i82557C || device == i82558B || device == i82559C) {
558 /*
559 TODO: get vendor id from EEPROM for i82557C or later.
560 TODO: get device id from EEPROM for i82557C or later.
561 TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
562 TODO: header type is determined by EEPROM for i82559.
563 TODO: get subsystem id from EEPROM for i82557C or later.
564 TODO: get subsystem vendor id from EEPROM for i82557C or later.
565 TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
566 TODO: capability pointer depends on EEPROM for i82558.
567 */
568 logout("Get device id and revision from EEPROM!!!\n");
569 }
570 #endif /* EEPROM_SIZE > 0 */
571 }
572
573 static void nic_selective_reset(EEPRO100State * s)
574 {
575 size_t i;
576 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
577 #if 0
578 eeprom93xx_reset(s->eeprom);
579 #endif
580 memcpy(eeprom_contents, s->conf.macaddr.a, 6);
581 eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID;
582 if (s->device == i82557B || s->device == i82557C)
583 eeprom_contents[5] = 0x0100;
584 eeprom_contents[EEPROM_PHY_ID] = 1;
585 uint16_t sum = 0;
586 for (i = 0; i < EEPROM_SIZE - 1; i++) {
587 sum += eeprom_contents[i];
588 }
589 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
590 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
591
592 memset(s->mem, 0, sizeof(s->mem));
593 uint32_t val = BIT(21);
594 memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
595
596 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
597 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
598 }
599
600 static void nic_reset(void *opaque)
601 {
602 EEPRO100State *s = opaque;
603 TRACE(OTHER, logout("%p\n", s));
604 /* TODO: Clearing of hash register for selective reset, too? */
605 memset(&s->mult[0], 0, sizeof(s->mult));
606 nic_selective_reset(s);
607 }
608
609 #if defined(DEBUG_EEPRO100)
610 static const char * const e100_reg[PCI_IO_SIZE / 4] = {
611 "Command/Status",
612 "General Pointer",
613 "Port",
614 "EEPROM/Flash Control",
615 "MDI Control",
616 "Receive DMA Byte Count",
617 "Flow Control",
618 "General Status/Control"
619 };
620
621 static char *regname(uint32_t addr)
622 {
623 static char buf[32];
624 if (addr < PCI_IO_SIZE) {
625 const char *r = e100_reg[addr / 4];
626 if (r != 0) {
627 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
628 } else {
629 snprintf(buf, sizeof(buf), "0x%02x", addr);
630 }
631 } else {
632 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
633 }
634 return buf;
635 }
636 #endif /* DEBUG_EEPRO100 */
637
638 /*****************************************************************************
639 *
640 * Command emulation.
641 *
642 ****************************************************************************/
643
644 #if 0
645 static uint16_t eepro100_read_command(EEPRO100State * s)
646 {
647 uint16_t val = 0xffff;
648 TRACE(OTHER, logout("val=0x%04x\n", val));
649 return val;
650 }
651 #endif
652
653 /* Commands that can be put in a command list entry. */
654 enum commands {
655 CmdNOp = 0,
656 CmdIASetup = 1,
657 CmdConfigure = 2,
658 CmdMulticastList = 3,
659 CmdTx = 4,
660 CmdTDR = 5, /* load microcode */
661 CmdDump = 6,
662 CmdDiagnose = 7,
663
664 /* And some extra flags: */
665 CmdSuspend = 0x4000, /* Suspend after completion. */
666 CmdIntr = 0x2000, /* Interrupt after completion. */
667 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
668 };
669
670 static cu_state_t get_cu_state(EEPRO100State * s)
671 {
672 return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6);
673 }
674
675 static void set_cu_state(EEPRO100State * s, cu_state_t state)
676 {
677 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6);
678 }
679
680 static ru_state_t get_ru_state(EEPRO100State * s)
681 {
682 return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2);
683 }
684
685 static void set_ru_state(EEPRO100State * s, ru_state_t state)
686 {
687 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2);
688 }
689
690 static void dump_statistics(EEPRO100State * s)
691 {
692 /* Dump statistical data. Most data is never changed by the emulation
693 * and always 0, so we first just copy the whole block and then those
694 * values which really matter.
695 * Number of data should check configuration!!!
696 */
697 cpu_physical_memory_write(s->statsaddr, &s->statistics, s->stats_size);
698 stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
699 stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
700 stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
701 stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
702 #if 0
703 stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
704 stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
705 missing("CU dump statistical counters");
706 #endif
707 }
708
709 static void read_cb(EEPRO100State *s)
710 {
711 cpu_physical_memory_read(s->cb_address, &s->tx, sizeof(s->tx));
712 s->tx.status = le16_to_cpu(s->tx.status);
713 s->tx.command = le16_to_cpu(s->tx.command);
714 s->tx.link = le32_to_cpu(s->tx.link);
715 s->tx.tbd_array_addr = le32_to_cpu(s->tx.tbd_array_addr);
716 s->tx.tcb_bytes = le16_to_cpu(s->tx.tcb_bytes);
717 }
718
719 static void tx_command(EEPRO100State *s)
720 {
721 uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr);
722 uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
723 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
724 uint8_t buf[2600];
725 uint16_t size = 0;
726 uint32_t tbd_address = s->cb_address + 0x10;
727 TRACE(RXTX, logout
728 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
729 tbd_array, tcb_bytes, s->tx.tbd_count));
730
731 if (tcb_bytes > 2600) {
732 logout("TCB byte count too large, using 2600\n");
733 tcb_bytes = 2600;
734 }
735 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
736 logout
737 ("illegal values of TBD array address and TCB byte count!\n");
738 }
739 assert(tcb_bytes <= sizeof(buf));
740 while (size < tcb_bytes) {
741 uint32_t tx_buffer_address = ldl_phys(tbd_address);
742 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
743 #if 0
744 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
745 #endif
746 tbd_address += 8;
747 TRACE(RXTX, logout
748 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
749 tx_buffer_address, tx_buffer_size));
750 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
751 cpu_physical_memory_read(tx_buffer_address, &buf[size],
752 tx_buffer_size);
753 size += tx_buffer_size;
754 }
755 if (tbd_array == 0xffffffff) {
756 /* Simplified mode. Was already handled by code above. */
757 } else {
758 /* Flexible mode. */
759 uint8_t tbd_count = 0;
760 if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
761 /* Extended Flexible TCB. */
762 for (; tbd_count < 2; tbd_count++) {
763 uint32_t tx_buffer_address = ldl_phys(tbd_address);
764 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
765 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
766 tbd_address += 8;
767 TRACE(RXTX, logout
768 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
769 tx_buffer_address, tx_buffer_size));
770 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
771 cpu_physical_memory_read(tx_buffer_address, &buf[size],
772 tx_buffer_size);
773 size += tx_buffer_size;
774 if (tx_buffer_el & 1) {
775 break;
776 }
777 }
778 }
779 tbd_address = tbd_array;
780 for (; tbd_count < s->tx.tbd_count; tbd_count++) {
781 uint32_t tx_buffer_address = ldl_phys(tbd_address);
782 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
783 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
784 tbd_address += 8;
785 TRACE(RXTX, logout
786 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
787 tx_buffer_address, tx_buffer_size));
788 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
789 cpu_physical_memory_read(tx_buffer_address, &buf[size],
790 tx_buffer_size);
791 size += tx_buffer_size;
792 if (tx_buffer_el & 1) {
793 break;
794 }
795 }
796 }
797 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
798 qemu_send_packet(&s->nic->nc, buf, size);
799 s->statistics.tx_good_frames++;
800 /* Transmit with bad status would raise an CX/TNO interrupt.
801 * (82557 only). Emulation never has bad status. */
802 #if 0
803 eepro100_cx_interrupt(s);
804 #endif
805 }
806
807 static void set_multicast_list(EEPRO100State *s)
808 {
809 uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0);
810 uint16_t i;
811 memset(&s->mult[0], 0, sizeof(s->mult));
812 TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
813 for (i = 0; i < multicast_count; i += 6) {
814 uint8_t multicast_addr[6];
815 cpu_physical_memory_read(s->cb_address + 10 + i, multicast_addr, 6);
816 TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6)));
817 unsigned mcast_idx = compute_mcast_idx(multicast_addr);
818 assert(mcast_idx < 64);
819 s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7));
820 }
821 }
822
823 static void action_command(EEPRO100State *s)
824 {
825 for (;;) {
826 bool bit_el;
827 bool bit_s;
828 bool bit_i;
829 bool bit_nc;
830 uint16_t ok_status = STATUS_OK;
831 s->cb_address = s->cu_base + s->cu_offset;
832 read_cb(s);
833 bit_el = ((s->tx.command & COMMAND_EL) != 0);
834 bit_s = ((s->tx.command & COMMAND_S) != 0);
835 bit_i = ((s->tx.command & COMMAND_I) != 0);
836 bit_nc = ((s->tx.command & COMMAND_NC) != 0);
837 #if 0
838 bool bit_sf = ((s->tx.command & COMMAND_SF) != 0);
839 #endif
840 s->cu_offset = s->tx.link;
841 TRACE(OTHER,
842 logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
843 s->tx.status, s->tx.command, s->tx.link));
844 switch (s->tx.command & COMMAND_CMD) {
845 case CmdNOp:
846 /* Do nothing. */
847 break;
848 case CmdIASetup:
849 cpu_physical_memory_read(s->cb_address + 8, &s->conf.macaddr.a[0], 6);
850 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)));
851 break;
852 case CmdConfigure:
853 cpu_physical_memory_read(s->cb_address + 8, &s->configuration[0],
854 sizeof(s->configuration));
855 TRACE(OTHER, logout("configuration: %s\n",
856 nic_dump(&s->configuration[0], 16)));
857 TRACE(OTHER, logout("configuration: %s\n",
858 nic_dump(&s->configuration[16],
859 ARRAY_SIZE(s->configuration) - 16)));
860 if (s->configuration[20] & BIT(6)) {
861 TRACE(OTHER, logout("Multiple IA bit\n"));
862 }
863 break;
864 case CmdMulticastList:
865 set_multicast_list(s);
866 break;
867 case CmdTx:
868 if (bit_nc) {
869 missing("CmdTx: NC = 0");
870 ok_status = 0;
871 break;
872 }
873 tx_command(s);
874 break;
875 case CmdTDR:
876 TRACE(OTHER, logout("load microcode\n"));
877 /* Starting with offset 8, the command contains
878 * 64 dwords microcode which we just ignore here. */
879 break;
880 case CmdDiagnose:
881 TRACE(OTHER, logout("diagnose\n"));
882 /* Make sure error flag is not set. */
883 s->tx.status = 0;
884 break;
885 default:
886 missing("undefined command");
887 ok_status = 0;
888 break;
889 }
890 /* Write new status. */
891 stw_phys(s->cb_address, s->tx.status | ok_status | STATUS_C);
892 if (bit_i) {
893 /* CU completed action. */
894 eepro100_cx_interrupt(s);
895 }
896 if (bit_el) {
897 /* CU becomes idle. Terminate command loop. */
898 set_cu_state(s, cu_idle);
899 eepro100_cna_interrupt(s);
900 break;
901 } else if (bit_s) {
902 /* CU becomes suspended. Terminate command loop. */
903 set_cu_state(s, cu_suspended);
904 eepro100_cna_interrupt(s);
905 break;
906 } else {
907 /* More entries in list. */
908 TRACE(OTHER, logout("CU list with at least one more entry\n"));
909 }
910 }
911 TRACE(OTHER, logout("CU list empty\n"));
912 /* List is empty. Now CU is idle or suspended. */
913 }
914
915 static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
916 {
917 cu_state_t cu_state;
918 switch (val) {
919 case CU_NOP:
920 /* No operation. */
921 break;
922 case CU_START:
923 cu_state = get_cu_state(s);
924 if (cu_state != cu_idle && cu_state != cu_suspended) {
925 /* Intel documentation says that CU must be idle or suspended
926 * for the CU start command. */
927 logout("unexpected CU state is %u\n", cu_state);
928 }
929 set_cu_state(s, cu_active);
930 s->cu_offset = s->pointer;
931 action_command(s);
932 break;
933 case CU_RESUME:
934 if (get_cu_state(s) != cu_suspended) {
935 logout("bad CU resume from CU state %u\n", get_cu_state(s));
936 /* Workaround for bad Linux eepro100 driver which resumes
937 * from idle state. */
938 #if 0
939 missing("cu resume");
940 #endif
941 set_cu_state(s, cu_suspended);
942 }
943 if (get_cu_state(s) == cu_suspended) {
944 TRACE(OTHER, logout("CU resuming\n"));
945 set_cu_state(s, cu_active);
946 action_command(s);
947 }
948 break;
949 case CU_STATSADDR:
950 /* Load dump counters address. */
951 s->statsaddr = s->pointer;
952 TRACE(OTHER, logout("val=0x%02x (status address)\n", val));
953 break;
954 case CU_SHOWSTATS:
955 /* Dump statistical counters. */
956 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
957 dump_statistics(s);
958 stl_le_phys(s->statsaddr + s->stats_size, 0xa005);
959 break;
960 case CU_CMD_BASE:
961 /* Load CU base. */
962 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
963 s->cu_base = s->pointer;
964 break;
965 case CU_DUMPSTATS:
966 /* Dump and reset statistical counters. */
967 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
968 dump_statistics(s);
969 stl_le_phys(s->statsaddr + s->stats_size, 0xa007);
970 memset(&s->statistics, 0, sizeof(s->statistics));
971 break;
972 case CU_SRESUME:
973 /* CU static resume. */
974 missing("CU static resume");
975 break;
976 default:
977 missing("Undefined CU command");
978 }
979 }
980
981 static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
982 {
983 switch (val) {
984 case RU_NOP:
985 /* No operation. */
986 break;
987 case RX_START:
988 /* RU start. */
989 if (get_ru_state(s) != ru_idle) {
990 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
991 #if 0
992 assert(!"wrong RU state");
993 #endif
994 }
995 set_ru_state(s, ru_ready);
996 s->ru_offset = s->pointer;
997 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
998 break;
999 case RX_RESUME:
1000 /* Restart RU. */
1001 if (get_ru_state(s) != ru_suspended) {
1002 logout("RU state is %u, should be %u\n", get_ru_state(s),
1003 ru_suspended);
1004 #if 0
1005 assert(!"wrong RU state");
1006 #endif
1007 }
1008 set_ru_state(s, ru_ready);
1009 break;
1010 case RU_ABORT:
1011 /* RU abort. */
1012 if (get_ru_state(s) == ru_ready) {
1013 eepro100_rnr_interrupt(s);
1014 }
1015 set_ru_state(s, ru_idle);
1016 break;
1017 case RX_ADDR_LOAD:
1018 /* Load RU base. */
1019 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
1020 s->ru_base = s->pointer;
1021 break;
1022 default:
1023 logout("val=0x%02x (undefined RU command)\n", val);
1024 missing("Undefined SU command");
1025 }
1026 }
1027
1028 static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1029 {
1030 eepro100_ru_command(s, val & 0x0f);
1031 eepro100_cu_command(s, val & 0xf0);
1032 if ((val) == 0) {
1033 TRACE(OTHER, logout("val=0x%02x\n", val));
1034 }
1035 /* Clear command byte after command was accepted. */
1036 s->mem[SCBCmd] = 0;
1037 }
1038
1039 /*****************************************************************************
1040 *
1041 * EEPROM emulation.
1042 *
1043 ****************************************************************************/
1044
1045 #define EEPROM_CS 0x02
1046 #define EEPROM_SK 0x01
1047 #define EEPROM_DI 0x04
1048 #define EEPROM_DO 0x08
1049
1050 static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1051 {
1052 uint16_t val;
1053 memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
1054 if (eeprom93xx_read(s->eeprom)) {
1055 val |= EEPROM_DO;
1056 } else {
1057 val &= ~EEPROM_DO;
1058 }
1059 TRACE(EEPROM, logout("val=0x%04x\n", val));
1060 return val;
1061 }
1062
1063 static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
1064 {
1065 TRACE(EEPROM, logout("val=0x%02x\n", val));
1066
1067 /* mask unwriteable bits */
1068 #if 0
1069 val = SET_MASKED(val, 0x31, eeprom->value);
1070 #endif
1071
1072 int eecs = ((val & EEPROM_CS) != 0);
1073 int eesk = ((val & EEPROM_SK) != 0);
1074 int eedi = ((val & EEPROM_DI) != 0);
1075 eeprom93xx_write(eeprom, eecs, eesk, eedi);
1076 }
1077
1078 static void eepro100_write_pointer(EEPRO100State * s, uint32_t val)
1079 {
1080 s->pointer = le32_to_cpu(val);
1081 TRACE(OTHER, logout("val=0x%08x\n", val));
1082 }
1083
1084 /*****************************************************************************
1085 *
1086 * MDI emulation.
1087 *
1088 ****************************************************************************/
1089
1090 #if defined(DEBUG_EEPRO100)
1091 static const char * const mdi_op_name[] = {
1092 "opcode 0",
1093 "write",
1094 "read",
1095 "opcode 3"
1096 };
1097
1098 static const char * const mdi_reg_name[] = {
1099 "Control",
1100 "Status",
1101 "PHY Identification (Word 1)",
1102 "PHY Identification (Word 2)",
1103 "Auto-Negotiation Advertisement",
1104 "Auto-Negotiation Link Partner Ability",
1105 "Auto-Negotiation Expansion"
1106 };
1107
1108 static const char *reg2name(uint8_t reg)
1109 {
1110 static char buffer[10];
1111 const char *p = buffer;
1112 if (reg < ARRAY_SIZE(mdi_reg_name)) {
1113 p = mdi_reg_name[reg];
1114 } else {
1115 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1116 }
1117 return p;
1118 }
1119 #endif /* DEBUG_EEPRO100 */
1120
1121 static uint32_t eepro100_read_mdi(EEPRO100State * s)
1122 {
1123 uint32_t val;
1124 memcpy(&val, &s->mem[0x10], sizeof(val));
1125
1126 #ifdef DEBUG_EEPRO100
1127 uint8_t raiseint = (val & BIT(29)) >> 29;
1128 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1129 uint8_t phy = (val & BITS(25, 21)) >> 21;
1130 uint8_t reg = (val & BITS(20, 16)) >> 16;
1131 uint16_t data = (val & BITS(15, 0));
1132 #endif
1133 /* Emulation takes no time to finish MDI transaction. */
1134 val |= BIT(28);
1135 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1136 val, raiseint, mdi_op_name[opcode], phy,
1137 reg2name(reg), data));
1138 return val;
1139 }
1140
1141 static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
1142 {
1143 uint8_t raiseint = (val & BIT(29)) >> 29;
1144 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1145 uint8_t phy = (val & BITS(25, 21)) >> 21;
1146 uint8_t reg = (val & BITS(20, 16)) >> 16;
1147 uint16_t data = (val & BITS(15, 0));
1148 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1149 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
1150 if (phy != 1) {
1151 /* Unsupported PHY address. */
1152 #if 0
1153 logout("phy must be 1 but is %u\n", phy);
1154 #endif
1155 data = 0;
1156 } else if (opcode != 1 && opcode != 2) {
1157 /* Unsupported opcode. */
1158 logout("opcode must be 1 or 2 but is %u\n", opcode);
1159 data = 0;
1160 } else if (reg > 6) {
1161 /* Unsupported register. */
1162 logout("register must be 0...6 but is %u\n", reg);
1163 data = 0;
1164 } else {
1165 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1166 val, raiseint, mdi_op_name[opcode], phy,
1167 reg2name(reg), data));
1168 if (opcode == 1) {
1169 /* MDI write */
1170 switch (reg) {
1171 case 0: /* Control Register */
1172 if (data & 0x8000) {
1173 /* Reset status and control registers to default. */
1174 s->mdimem[0] = eepro100_mdi_default[0];
1175 s->mdimem[1] = eepro100_mdi_default[1];
1176 data = s->mdimem[reg];
1177 } else {
1178 /* Restart Auto Configuration = Normal Operation */
1179 data &= ~0x0200;
1180 }
1181 break;
1182 case 1: /* Status Register */
1183 missing("not writable");
1184 data = s->mdimem[reg];
1185 break;
1186 case 2: /* PHY Identification Register (Word 1) */
1187 case 3: /* PHY Identification Register (Word 2) */
1188 missing("not implemented");
1189 break;
1190 case 4: /* Auto-Negotiation Advertisement Register */
1191 case 5: /* Auto-Negotiation Link Partner Ability Register */
1192 break;
1193 case 6: /* Auto-Negotiation Expansion Register */
1194 default:
1195 missing("not implemented");
1196 }
1197 s->mdimem[reg] = data;
1198 } else if (opcode == 2) {
1199 /* MDI read */
1200 switch (reg) {
1201 case 0: /* Control Register */
1202 if (data & 0x8000) {
1203 /* Reset status and control registers to default. */
1204 s->mdimem[0] = eepro100_mdi_default[0];
1205 s->mdimem[1] = eepro100_mdi_default[1];
1206 }
1207 break;
1208 case 1: /* Status Register */
1209 s->mdimem[reg] |= 0x0020;
1210 break;
1211 case 2: /* PHY Identification Register (Word 1) */
1212 case 3: /* PHY Identification Register (Word 2) */
1213 case 4: /* Auto-Negotiation Advertisement Register */
1214 break;
1215 case 5: /* Auto-Negotiation Link Partner Ability Register */
1216 s->mdimem[reg] = 0x41fe;
1217 break;
1218 case 6: /* Auto-Negotiation Expansion Register */
1219 s->mdimem[reg] = 0x0001;
1220 break;
1221 }
1222 data = s->mdimem[reg];
1223 }
1224 /* Emulation takes no time to finish MDI transaction.
1225 * Set MDI bit in SCB status register. */
1226 s->mem[SCBAck] |= 0x08;
1227 val |= BIT(28);
1228 if (raiseint) {
1229 eepro100_mdi_interrupt(s);
1230 }
1231 }
1232 val = (val & 0xffff0000) + data;
1233 memcpy(&s->mem[0x10], &val, sizeof(val));
1234 }
1235
1236 /*****************************************************************************
1237 *
1238 * Port emulation.
1239 *
1240 ****************************************************************************/
1241
1242 #define PORT_SOFTWARE_RESET 0
1243 #define PORT_SELFTEST 1
1244 #define PORT_SELECTIVE_RESET 2
1245 #define PORT_DUMP 3
1246 #define PORT_SELECTION_MASK 3
1247
1248 typedef struct {
1249 uint32_t st_sign; /* Self Test Signature */
1250 uint32_t st_result; /* Self Test Results */
1251 } eepro100_selftest_t;
1252
1253 static uint32_t eepro100_read_port(EEPRO100State * s)
1254 {
1255 return 0;
1256 }
1257
1258 static void eepro100_write_port(EEPRO100State * s, uint32_t val)
1259 {
1260 val = le32_to_cpu(val);
1261 uint32_t address = (val & ~PORT_SELECTION_MASK);
1262 uint8_t selection = (val & PORT_SELECTION_MASK);
1263 switch (selection) {
1264 case PORT_SOFTWARE_RESET:
1265 nic_reset(s);
1266 break;
1267 case PORT_SELFTEST:
1268 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
1269 eepro100_selftest_t data;
1270 cpu_physical_memory_read(address, &data, sizeof(data));
1271 data.st_sign = 0xffffffff;
1272 data.st_result = 0;
1273 cpu_physical_memory_write(address, &data, sizeof(data));
1274 break;
1275 case PORT_SELECTIVE_RESET:
1276 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
1277 nic_selective_reset(s);
1278 break;
1279 default:
1280 logout("val=0x%08x\n", val);
1281 missing("unknown port selection");
1282 }
1283 }
1284
1285 /*****************************************************************************
1286 *
1287 * General hardware emulation.
1288 *
1289 ****************************************************************************/
1290
1291 static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1292 {
1293 uint8_t val = 0;
1294 if (addr <= sizeof(s->mem) - sizeof(val)) {
1295 memcpy(&val, &s->mem[addr], sizeof(val));
1296 }
1297
1298 switch (addr) {
1299 case SCBStatus:
1300 case SCBAck:
1301 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1302 break;
1303 case SCBCmd:
1304 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1305 #if 0
1306 val = eepro100_read_command(s);
1307 #endif
1308 break;
1309 case SCBIntmask:
1310 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1311 break;
1312 case SCBPort + 3:
1313 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1314 break;
1315 case SCBeeprom:
1316 val = eepro100_read_eeprom(s);
1317 break;
1318 case SCBpmdr: /* Power Management Driver Register */
1319 val = 0;
1320 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1321 break;
1322 case SCBgstat: /* General Status Register */
1323 /* 100 Mbps full duplex, valid link */
1324 val = 0x07;
1325 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
1326 break;
1327 default:
1328 logout("addr=%s val=0x%02x\n", regname(addr), val);
1329 missing("unknown byte read");
1330 }
1331 return val;
1332 }
1333
1334 static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1335 {
1336 uint16_t val = 0;
1337 if (addr <= sizeof(s->mem) - sizeof(val)) {
1338 memcpy(&val, &s->mem[addr], sizeof(val));
1339 }
1340
1341 switch (addr) {
1342 case SCBStatus:
1343 case SCBCmd:
1344 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1345 break;
1346 case SCBeeprom:
1347 val = eepro100_read_eeprom(s);
1348 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1349 break;
1350 default:
1351 logout("addr=%s val=0x%04x\n", regname(addr), val);
1352 missing("unknown word read");
1353 }
1354 return val;
1355 }
1356
1357 static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1358 {
1359 uint32_t val = 0;
1360 if (addr <= sizeof(s->mem) - sizeof(val)) {
1361 memcpy(&val, &s->mem[addr], sizeof(val));
1362 }
1363
1364 switch (addr) {
1365 case SCBStatus:
1366 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1367 break;
1368 case SCBPointer:
1369 #if 0
1370 val = eepro100_read_pointer(s);
1371 #endif
1372 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1373 break;
1374 case SCBPort:
1375 val = eepro100_read_port(s);
1376 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1377 break;
1378 case SCBCtrlMDI:
1379 val = eepro100_read_mdi(s);
1380 break;
1381 default:
1382 logout("addr=%s val=0x%08x\n", regname(addr), val);
1383 missing("unknown longword read");
1384 }
1385 return val;
1386 }
1387
1388 static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1389 {
1390 /* SCBStatus is readonly. */
1391 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
1392 memcpy(&s->mem[addr], &val, sizeof(val));
1393 }
1394
1395 switch (addr) {
1396 case SCBStatus:
1397 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1398 break;
1399 case SCBAck:
1400 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1401 eepro100_acknowledge(s);
1402 break;
1403 case SCBCmd:
1404 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1405 eepro100_write_command(s, val);
1406 break;
1407 case SCBIntmask:
1408 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1409 if (val & BIT(1)) {
1410 eepro100_swi_interrupt(s);
1411 }
1412 eepro100_interrupt(s, 0);
1413 break;
1414 case SCBPort + 3:
1415 case SCBFlow: /* does not exist on 82557 */
1416 case SCBFlow + 1:
1417 case SCBFlow + 2:
1418 case SCBpmdr: /* does not exist on 82557 */
1419 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1420 break;
1421 case SCBeeprom:
1422 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1423 eepro100_write_eeprom(s->eeprom, val);
1424 break;
1425 default:
1426 logout("addr=%s val=0x%02x\n", regname(addr), val);
1427 missing("unknown byte write");
1428 }
1429 }
1430
1431 static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1432 {
1433 /* SCBStatus is readonly. */
1434 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
1435 memcpy(&s->mem[addr], &val, sizeof(val));
1436 }
1437
1438 switch (addr) {
1439 case SCBStatus:
1440 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1441 s->mem[SCBAck] = (val >> 8);
1442 eepro100_acknowledge(s);
1443 break;
1444 case SCBCmd:
1445 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1446 eepro100_write_command(s, val);
1447 eepro100_write1(s, SCBIntmask, val >> 8);
1448 break;
1449 case SCBeeprom:
1450 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1451 eepro100_write_eeprom(s->eeprom, val);
1452 break;
1453 default:
1454 logout("addr=%s val=0x%04x\n", regname(addr), val);
1455 missing("unknown word write");
1456 }
1457 }
1458
1459 static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1460 {
1461 if (addr <= sizeof(s->mem) - sizeof(val)) {
1462 memcpy(&s->mem[addr], &val, sizeof(val));
1463 }
1464
1465 switch (addr) {
1466 case SCBPointer:
1467 eepro100_write_pointer(s, val);
1468 break;
1469 case SCBPort:
1470 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1471 eepro100_write_port(s, val);
1472 break;
1473 case SCBCtrlMDI:
1474 eepro100_write_mdi(s, val);
1475 break;
1476 default:
1477 logout("addr=%s val=0x%08x\n", regname(addr), val);
1478 missing("unknown longword write");
1479 }
1480 }
1481
1482 /*****************************************************************************
1483 *
1484 * Port mapped I/O.
1485 *
1486 ****************************************************************************/
1487
1488 static uint32_t ioport_read1(void *opaque, uint32_t addr)
1489 {
1490 EEPRO100State *s = opaque;
1491 #if 0
1492 logout("addr=%s\n", regname(addr));
1493 #endif
1494 return eepro100_read1(s, addr - s->region1);
1495 }
1496
1497 static uint32_t ioport_read2(void *opaque, uint32_t addr)
1498 {
1499 EEPRO100State *s = opaque;
1500 return eepro100_read2(s, addr - s->region1);
1501 }
1502
1503 static uint32_t ioport_read4(void *opaque, uint32_t addr)
1504 {
1505 EEPRO100State *s = opaque;
1506 return eepro100_read4(s, addr - s->region1);
1507 }
1508
1509 static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
1510 {
1511 EEPRO100State *s = opaque;
1512 #if 0
1513 logout("addr=%s val=0x%02x\n", regname(addr), val);
1514 #endif
1515 eepro100_write1(s, addr - s->region1, val);
1516 }
1517
1518 static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
1519 {
1520 EEPRO100State *s = opaque;
1521 eepro100_write2(s, addr - s->region1, val);
1522 }
1523
1524 static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
1525 {
1526 EEPRO100State *s = opaque;
1527 eepro100_write4(s, addr - s->region1, val);
1528 }
1529
1530 /***********************************************************/
1531 /* PCI EEPRO100 definitions */
1532
1533 static void pci_map(PCIDevice * pci_dev, int region_num,
1534 pcibus_t addr, pcibus_t size, int type)
1535 {
1536 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1537
1538 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1539 "size=0x%08"FMT_PCIBUS", type=%d\n",
1540 region_num, addr, size, type));
1541
1542 assert(region_num == 1);
1543 register_ioport_write(addr, size, 1, ioport_write1, s);
1544 register_ioport_read(addr, size, 1, ioport_read1, s);
1545 register_ioport_write(addr, size, 2, ioport_write2, s);
1546 register_ioport_read(addr, size, 2, ioport_read2, s);
1547 register_ioport_write(addr, size, 4, ioport_write4, s);
1548 register_ioport_read(addr, size, 4, ioport_read4, s);
1549
1550 s->region1 = addr;
1551 }
1552
1553 /*****************************************************************************
1554 *
1555 * Memory mapped I/O.
1556 *
1557 ****************************************************************************/
1558
1559 static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1560 {
1561 EEPRO100State *s = opaque;
1562 #if 0
1563 logout("addr=%s val=0x%02x\n", regname(addr), val);
1564 #endif
1565 eepro100_write1(s, addr, val);
1566 }
1567
1568 static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1569 {
1570 EEPRO100State *s = opaque;
1571 #if 0
1572 logout("addr=%s val=0x%02x\n", regname(addr), val);
1573 #endif
1574 eepro100_write2(s, addr, val);
1575 }
1576
1577 static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1578 {
1579 EEPRO100State *s = opaque;
1580 #if 0
1581 logout("addr=%s val=0x%02x\n", regname(addr), val);
1582 #endif
1583 eepro100_write4(s, addr, val);
1584 }
1585
1586 static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
1587 {
1588 EEPRO100State *s = opaque;
1589 #if 0
1590 logout("addr=%s\n", regname(addr));
1591 #endif
1592 return eepro100_read1(s, addr);
1593 }
1594
1595 static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
1596 {
1597 EEPRO100State *s = opaque;
1598 #if 0
1599 logout("addr=%s\n", regname(addr));
1600 #endif
1601 return eepro100_read2(s, addr);
1602 }
1603
1604 static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
1605 {
1606 EEPRO100State *s = opaque;
1607 #if 0
1608 logout("addr=%s\n", regname(addr));
1609 #endif
1610 return eepro100_read4(s, addr);
1611 }
1612
1613 static CPUWriteMemoryFunc * const pci_mmio_write[] = {
1614 pci_mmio_writeb,
1615 pci_mmio_writew,
1616 pci_mmio_writel
1617 };
1618
1619 static CPUReadMemoryFunc * const pci_mmio_read[] = {
1620 pci_mmio_readb,
1621 pci_mmio_readw,
1622 pci_mmio_readl
1623 };
1624
1625 static int nic_can_receive(VLANClientState *nc)
1626 {
1627 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1628 TRACE(RXTX, logout("%p\n", s));
1629 return get_ru_state(s) == ru_ready;
1630 #if 0
1631 return !eepro100_buffer_full(s);
1632 #endif
1633 }
1634
1635 static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size)
1636 {
1637 /* TODO:
1638 * - Magic packets should set bit 30 in power management driver register.
1639 * - Interesting packets should set bit 29 in power management driver register.
1640 */
1641 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1642 uint16_t rfd_status = 0xa000;
1643 static const uint8_t broadcast_macaddr[6] =
1644 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1645
1646 if (s->configuration[8] & 0x80) {
1647 /* CSMA is disabled. */
1648 logout("%p received while CSMA is disabled\n", s);
1649 return -1;
1650 } else if (size < 64 && (s->configuration[7] & BIT(0))) {
1651 /* Short frame and configuration byte 7/0 (discard short receive) set:
1652 * Short frame is discarded */
1653 logout("%p received short frame (%zu byte)\n", s, size);
1654 s->statistics.rx_short_frame_errors++;
1655 #if 0
1656 return -1;
1657 #endif
1658 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) {
1659 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1660 * Long frames are discarded. */
1661 logout("%p received long frame (%zu byte), ignored\n", s, size);
1662 return -1;
1663 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { /* !!! */
1664 /* Frame matches individual address. */
1665 /* TODO: check configuration byte 15/4 (ignore U/L). */
1666 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
1667 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1668 /* Broadcast frame. */
1669 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
1670 rfd_status |= 0x0002;
1671 } else if (buf[0] & 0x01) {
1672 /* Multicast frame. */
1673 TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size)));
1674 if (s->configuration[21] & BIT(3)) {
1675 /* Multicast all bit is set, receive all multicast frames. */
1676 } else {
1677 unsigned mcast_idx = compute_mcast_idx(buf);
1678 assert(mcast_idx < 64);
1679 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1680 /* Multicast frame is allowed in hash table. */
1681 } else if (s->configuration[15] & BIT(0)) {
1682 /* Promiscuous: receive all. */
1683 rfd_status |= 0x0004;
1684 } else {
1685 TRACE(RXTX, logout("%p multicast ignored\n", s));
1686 return -1;
1687 }
1688 }
1689 /* TODO: Next not for promiscuous mode? */
1690 rfd_status |= 0x0002;
1691 } else if (s->configuration[15] & BIT(0)) {
1692 /* Promiscuous: receive all. */
1693 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
1694 rfd_status |= 0x0004;
1695 } else if (s->configuration[20] & BIT(6)) {
1696 /* Multiple IA bit set. */
1697 unsigned mcast_idx = compute_mcast_idx(buf);
1698 assert(mcast_idx < 64);
1699 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1700 TRACE(RXTX, logout("%p accepted, multiple IA bit set\n", s));
1701 } else {
1702 TRACE(RXTX, logout("%p frame ignored, multiple IA bit set\n", s));
1703 return -1;
1704 }
1705 } else {
1706 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
1707 nic_dump(buf, size)));
1708 return size;
1709 }
1710
1711 if (get_ru_state(s) != ru_ready) {
1712 /* No resources available. */
1713 logout("no resources, state=%u\n", get_ru_state(s));
1714 /* TODO: RNR interrupt only at first failed frame? */
1715 eepro100_rnr_interrupt(s);
1716 s->statistics.rx_resource_errors++;
1717 #if 0
1718 assert(!"no resources");
1719 #endif
1720 return -1;
1721 }
1722 /* !!! */
1723 eepro100_rx_t rx;
1724 cpu_physical_memory_read(s->ru_base + s->ru_offset, &rx,
1725 offsetof(eepro100_rx_t, packet));
1726 uint16_t rfd_command = le16_to_cpu(rx.command);
1727 uint16_t rfd_size = le16_to_cpu(rx.size);
1728
1729 if (size > rfd_size) {
1730 logout("Receive buffer (%" PRId16 " bytes) too small for data "
1731 "(%zu bytes); data truncated\n", rfd_size, size);
1732 size = rfd_size;
1733 }
1734 if (size < 64) {
1735 rfd_status |= 0x0080;
1736 }
1737 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1738 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
1739 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
1740 rfd_status);
1741 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
1742 /* Early receive interrupt not supported. */
1743 #if 0
1744 eepro100_er_interrupt(s);
1745 #endif
1746 /* Receive CRC Transfer not supported. */
1747 if (s->configuration[18] & BIT(2)) {
1748 missing("Receive CRC Transfer");
1749 return -1;
1750 }
1751 /* TODO: check stripping enable bit. */
1752 #if 0
1753 assert(!(s->configuration[17] & BIT(0)));
1754 #endif
1755 cpu_physical_memory_write(s->ru_base + s->ru_offset +
1756 offsetof(eepro100_rx_t, packet), buf, size);
1757 s->statistics.rx_good_frames++;
1758 eepro100_fr_interrupt(s);
1759 s->ru_offset = le32_to_cpu(rx.link);
1760 if (rfd_command & COMMAND_EL) {
1761 /* EL bit is set, so this was the last frame. */
1762 logout("receive: Running out of frames\n");
1763 set_ru_state(s, ru_suspended);
1764 }
1765 if (rfd_command & COMMAND_S) {
1766 /* S bit is set. */
1767 set_ru_state(s, ru_suspended);
1768 }
1769 return size;
1770 }
1771
1772 static const VMStateDescription vmstate_eepro100 = {
1773 .version_id = 3,
1774 .minimum_version_id = 2,
1775 .minimum_version_id_old = 2,
1776 .fields = (VMStateField []) {
1777 VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1778 VMSTATE_UNUSED(32),
1779 VMSTATE_BUFFER(mult, EEPRO100State),
1780 VMSTATE_BUFFER(mem, EEPRO100State),
1781 /* Save all members of struct between scb_stat and mem. */
1782 VMSTATE_UINT8(scb_stat, EEPRO100State),
1783 VMSTATE_UINT8(int_stat, EEPRO100State),
1784 VMSTATE_UNUSED(3*4),
1785 VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1786 VMSTATE_UNUSED(19*4),
1787 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1788 /* The eeprom should be saved and restored by its own routines. */
1789 VMSTATE_UINT32(device, EEPRO100State),
1790 /* TODO check device. */
1791 VMSTATE_UINT32(pointer, EEPRO100State),
1792 VMSTATE_UINT32(cu_base, EEPRO100State),
1793 VMSTATE_UINT32(cu_offset, EEPRO100State),
1794 VMSTATE_UINT32(ru_base, EEPRO100State),
1795 VMSTATE_UINT32(ru_offset, EEPRO100State),
1796 VMSTATE_UINT32(statsaddr, EEPRO100State),
1797 /* Save eepro100_stats_t statistics. */
1798 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1799 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1800 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1801 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1802 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1803 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1804 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1805 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1806 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1807 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1808 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1809 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1810 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1811 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1812 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1813 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1814 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1815 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1816 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1817 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1818 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
1819 /* Configuration bytes. */
1820 VMSTATE_BUFFER(configuration, EEPRO100State),
1821 VMSTATE_END_OF_LIST()
1822 }
1823 };
1824
1825 static void nic_cleanup(VLANClientState *nc)
1826 {
1827 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1828
1829 s->nic = NULL;
1830 }
1831
1832 static int pci_nic_uninit(PCIDevice *pci_dev)
1833 {
1834 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1835
1836 cpu_unregister_io_memory(s->mmio_index);
1837 vmstate_unregister(&pci_dev->qdev, s->vmstate, s);
1838 eeprom93xx_free(&pci_dev->qdev, s->eeprom);
1839 qemu_del_vlan_client(&s->nic->nc);
1840 return 0;
1841 }
1842
1843 static NetClientInfo net_eepro100_info = {
1844 .type = NET_CLIENT_TYPE_NIC,
1845 .size = sizeof(NICState),
1846 .can_receive = nic_can_receive,
1847 .receive = nic_receive,
1848 .cleanup = nic_cleanup,
1849 };
1850
1851 static int e100_nic_init(PCIDevice *pci_dev)
1852 {
1853 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1854 E100PCIDeviceInfo *e100_device = DO_UPCAST(E100PCIDeviceInfo, pci.qdev,
1855 pci_dev->qdev.info);
1856
1857 TRACE(OTHER, logout("\n"));
1858
1859 s->device = e100_device->device;
1860
1861 e100_pci_reset(s, e100_device);
1862
1863 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1864 * i82559 and later support 64 or 256 word EEPROM. */
1865 s->eeprom = eeprom93xx_new(&pci_dev->qdev, EEPROM_SIZE);
1866
1867 /* Handler for memory-mapped I/O */
1868 s->mmio_index =
1869 cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s,
1870 DEVICE_NATIVE_ENDIAN);
1871
1872 pci_register_bar_simple(&s->dev, 0, PCI_MEM_SIZE,
1873 PCI_BASE_ADDRESS_MEM_PREFETCH, s->mmio_index);
1874
1875 pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
1876 pci_map);
1877 pci_register_bar_simple(&s->dev, 2, PCI_FLASH_SIZE, 0, s->mmio_index);
1878
1879 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1880 logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));
1881 assert(s->region1 == 0);
1882
1883 nic_reset(s);
1884
1885 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
1886 pci_dev->qdev.info->name, pci_dev->qdev.id, s);
1887
1888 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
1889 TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
1890
1891 qemu_register_reset(nic_reset, s);
1892
1893 s->vmstate = qemu_malloc(sizeof(vmstate_eepro100));
1894 memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
1895 s->vmstate->name = s->nic->nc.model;
1896 vmstate_register(&pci_dev->qdev, -1, s->vmstate, s);
1897
1898 add_boot_device_path(s->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
1899
1900 return 0;
1901 }
1902
1903 static E100PCIDeviceInfo e100_devices[] = {
1904 {
1905 .pci.qdev.name = "i82550",
1906 .pci.qdev.desc = "Intel i82550 Ethernet",
1907 .device = i82550,
1908 /* TODO: check device id. */
1909 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
1910 /* Revision ID: 0x0c, 0x0d, 0x0e. */
1911 .revision = 0x0e,
1912 /* TODO: check size of statistical counters. */
1913 .stats_size = 80,
1914 /* TODO: check extended tcb support. */
1915 .has_extended_tcb_support = true,
1916 .power_management = true,
1917 },{
1918 .pci.qdev.name = "i82551",
1919 .pci.qdev.desc = "Intel i82551 Ethernet",
1920 .device = i82551,
1921 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
1922 /* Revision ID: 0x0f, 0x10. */
1923 .revision = 0x0f,
1924 /* TODO: check size of statistical counters. */
1925 .stats_size = 80,
1926 .has_extended_tcb_support = true,
1927 .power_management = true,
1928 },{
1929 .pci.qdev.name = "i82557a",
1930 .pci.qdev.desc = "Intel i82557A Ethernet",
1931 .device = i82557A,
1932 .device_id = PCI_DEVICE_ID_INTEL_82557,
1933 .revision = 0x01,
1934 .power_management = false,
1935 },{
1936 .pci.qdev.name = "i82557b",
1937 .pci.qdev.desc = "Intel i82557B Ethernet",
1938 .device = i82557B,
1939 .device_id = PCI_DEVICE_ID_INTEL_82557,
1940 .revision = 0x02,
1941 .power_management = false,
1942 },{
1943 .pci.qdev.name = "i82557c",
1944 .pci.qdev.desc = "Intel i82557C Ethernet",
1945 .device = i82557C,
1946 .device_id = PCI_DEVICE_ID_INTEL_82557,
1947 .revision = 0x03,
1948 .power_management = false,
1949 },{
1950 .pci.qdev.name = "i82558a",
1951 .pci.qdev.desc = "Intel i82558A Ethernet",
1952 .device = i82558A,
1953 .device_id = PCI_DEVICE_ID_INTEL_82557,
1954 .revision = 0x04,
1955 .stats_size = 76,
1956 .has_extended_tcb_support = true,
1957 .power_management = true,
1958 },{
1959 .pci.qdev.name = "i82558b",
1960 .pci.qdev.desc = "Intel i82558B Ethernet",
1961 .device = i82558B,
1962 .device_id = PCI_DEVICE_ID_INTEL_82557,
1963 .revision = 0x05,
1964 .stats_size = 76,
1965 .has_extended_tcb_support = true,
1966 .power_management = true,
1967 },{
1968 .pci.qdev.name = "i82559a",
1969 .pci.qdev.desc = "Intel i82559A Ethernet",
1970 .device = i82559A,
1971 .device_id = PCI_DEVICE_ID_INTEL_82557,
1972 .revision = 0x06,
1973 .stats_size = 80,
1974 .has_extended_tcb_support = true,
1975 .power_management = true,
1976 },{
1977 .pci.qdev.name = "i82559b",
1978 .pci.qdev.desc = "Intel i82559B Ethernet",
1979 .device = i82559B,
1980 .device_id = PCI_DEVICE_ID_INTEL_82557,
1981 .revision = 0x07,
1982 .stats_size = 80,
1983 .has_extended_tcb_support = true,
1984 .power_management = true,
1985 },{
1986 .pci.qdev.name = "i82559c",
1987 .pci.qdev.desc = "Intel i82559C Ethernet",
1988 .device = i82559C,
1989 .device_id = PCI_DEVICE_ID_INTEL_82557,
1990 #if 0
1991 .revision = 0x08,
1992 #endif
1993 /* TODO: Windows wants revision id 0x0c. */
1994 .revision = 0x0c,
1995 .stats_size = 80,
1996 .has_extended_tcb_support = true,
1997 .power_management = true,
1998 },{
1999 .pci.qdev.name = "i82559er",
2000 .pci.qdev.desc = "Intel i82559ER Ethernet",
2001 .device = i82559ER,
2002 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
2003 .revision = 0x09,
2004 .stats_size = 80,
2005 .has_extended_tcb_support = true,
2006 .power_management = true,
2007 },{
2008 .pci.qdev.name = "i82562",
2009 .pci.qdev.desc = "Intel i82562 Ethernet",
2010 .device = i82562,
2011 /* TODO: check device id. */
2012 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
2013 /* TODO: wrong revision id. */
2014 .revision = 0x0e,
2015 .stats_size = 80,
2016 .has_extended_tcb_support = true,
2017 .power_management = true,
2018 },{
2019 /* Toshiba Tecra 8200. */
2020 .pci.qdev.name = "i82801",
2021 .pci.qdev.desc = "Intel i82801 Ethernet",
2022 .device = i82801,
2023 .device_id = 0x2449,
2024 .revision = 0x03,
2025 .stats_size = 80,
2026 .has_extended_tcb_support = true,
2027 .power_management = true,
2028 }
2029 };
2030
2031 static Property e100_properties[] = {
2032 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2033 DEFINE_PROP_END_OF_LIST(),
2034 };
2035
2036 static void eepro100_register_devices(void)
2037 {
2038 size_t i;
2039 for (i = 0; i < ARRAY_SIZE(e100_devices); i++) {
2040 PCIDeviceInfo *pci_dev = &e100_devices[i].pci;
2041 /* We use the same rom file for all device ids.
2042 QEMU fixes the device id during rom load. */
2043 pci_dev->romfile = "gpxe-eepro100-80861209.rom";
2044 pci_dev->init = e100_nic_init;
2045 pci_dev->exit = pci_nic_uninit;
2046 pci_dev->qdev.props = e100_properties;
2047 pci_dev->qdev.size = sizeof(EEPRO100State);
2048 pci_qdev_register(pci_dev);
2049 }
2050 }
2051
2052 device_init(eepro100_register_devices)
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