Add access control support to qemu bridge helper
[qemu.git] / hw / fdc.c
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "hw.h"
31 #include "fdc.h"
32 #include "qemu-error.h"
33 #include "qemu-timer.h"
34 #include "isa.h"
35 #include "sysbus.h"
36 #include "qdev-addr.h"
37 #include "blockdev.h"
38 #include "sysemu.h"
39
40 /********************************************************/
41 /* debug Floppy devices */
42 //#define DEBUG_FLOPPY
43
44 #ifdef DEBUG_FLOPPY
45 #define FLOPPY_DPRINTF(fmt, ...) \
46 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
47 #else
48 #define FLOPPY_DPRINTF(fmt, ...)
49 #endif
50
51 #define FLOPPY_ERROR(fmt, ...) \
52 do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
53
54 /********************************************************/
55 /* Floppy drive emulation */
56
57 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
58 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
59
60 /* Will always be a fixed parameter for us */
61 #define FD_SECTOR_LEN 512
62 #define FD_SECTOR_SC 2 /* Sector size code */
63 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
64
65 /* Floppy disk drive emulation */
66 typedef enum FDiskFlags {
67 FDISK_DBL_SIDES = 0x01,
68 } FDiskFlags;
69
70 typedef struct FDrive {
71 BlockDriverState *bs;
72 /* Drive status */
73 FDriveType drive;
74 uint8_t perpendicular; /* 2.88 MB access mode */
75 /* Position */
76 uint8_t head;
77 uint8_t track;
78 uint8_t sect;
79 /* Media */
80 FDiskFlags flags;
81 uint8_t last_sect; /* Nb sector per track */
82 uint8_t max_track; /* Nb of tracks */
83 uint16_t bps; /* Bytes per sector */
84 uint8_t ro; /* Is read-only */
85 uint8_t media_changed; /* Is media changed */
86 } FDrive;
87
88 static void fd_init(FDrive *drv)
89 {
90 /* Drive */
91 drv->drive = FDRIVE_DRV_NONE;
92 drv->perpendicular = 0;
93 /* Disk */
94 drv->last_sect = 0;
95 drv->max_track = 0;
96 }
97
98 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
99 uint8_t last_sect)
100 {
101 return (((track * 2) + head) * last_sect) + sect - 1;
102 }
103
104 /* Returns current position, in sectors, for given drive */
105 static int fd_sector(FDrive *drv)
106 {
107 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect);
108 }
109
110 /* Seek to a new position:
111 * returns 0 if already on right track
112 * returns 1 if track changed
113 * returns 2 if track is invalid
114 * returns 3 if sector is invalid
115 * returns 4 if seek is disabled
116 */
117 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
118 int enable_seek)
119 {
120 uint32_t sector;
121 int ret;
122
123 if (track > drv->max_track ||
124 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
125 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
126 head, track, sect, 1,
127 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
128 drv->max_track, drv->last_sect);
129 return 2;
130 }
131 if (sect > drv->last_sect) {
132 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
133 head, track, sect, 1,
134 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
135 drv->max_track, drv->last_sect);
136 return 3;
137 }
138 sector = fd_sector_calc(head, track, sect, drv->last_sect);
139 ret = 0;
140 if (sector != fd_sector(drv)) {
141 #if 0
142 if (!enable_seek) {
143 FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
144 head, track, sect, 1, drv->max_track, drv->last_sect);
145 return 4;
146 }
147 #endif
148 drv->head = head;
149 if (drv->track != track)
150 ret = 1;
151 drv->track = track;
152 drv->sect = sect;
153 }
154
155 return ret;
156 }
157
158 /* Set drive back to track 0 */
159 static void fd_recalibrate(FDrive *drv)
160 {
161 FLOPPY_DPRINTF("recalibrate\n");
162 drv->head = 0;
163 drv->track = 0;
164 drv->sect = 1;
165 }
166
167 /* Revalidate a disk drive after a disk change */
168 static void fd_revalidate(FDrive *drv)
169 {
170 int nb_heads, max_track, last_sect, ro;
171 FDriveType drive;
172
173 FLOPPY_DPRINTF("revalidate\n");
174 if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
175 ro = bdrv_is_read_only(drv->bs);
176 bdrv_get_floppy_geometry_hint(drv->bs, &nb_heads, &max_track,
177 &last_sect, drv->drive, &drive);
178 if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
179 FLOPPY_DPRINTF("User defined disk (%d %d %d)",
180 nb_heads - 1, max_track, last_sect);
181 } else {
182 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", nb_heads,
183 max_track, last_sect, ro ? "ro" : "rw");
184 }
185 if (nb_heads == 1) {
186 drv->flags &= ~FDISK_DBL_SIDES;
187 } else {
188 drv->flags |= FDISK_DBL_SIDES;
189 }
190 drv->max_track = max_track;
191 drv->last_sect = last_sect;
192 drv->ro = ro;
193 drv->drive = drive;
194 } else {
195 FLOPPY_DPRINTF("No disk in drive\n");
196 drv->last_sect = 0;
197 drv->max_track = 0;
198 drv->flags &= ~FDISK_DBL_SIDES;
199 }
200 }
201
202 /********************************************************/
203 /* Intel 82078 floppy disk controller emulation */
204
205 typedef struct FDCtrl FDCtrl;
206
207 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
208 static void fdctrl_reset_fifo(FDCtrl *fdctrl);
209 static int fdctrl_transfer_handler (void *opaque, int nchan,
210 int dma_pos, int dma_len);
211 static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0);
212
213 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
214 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
215 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
216 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
217 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
218 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
219 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
220 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
221 static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
222 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
223 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
224
225 enum {
226 FD_DIR_WRITE = 0,
227 FD_DIR_READ = 1,
228 FD_DIR_SCANE = 2,
229 FD_DIR_SCANL = 3,
230 FD_DIR_SCANH = 4,
231 };
232
233 enum {
234 FD_STATE_MULTI = 0x01, /* multi track flag */
235 FD_STATE_FORMAT = 0x02, /* format flag */
236 FD_STATE_SEEK = 0x04, /* seek flag */
237 };
238
239 enum {
240 FD_REG_SRA = 0x00,
241 FD_REG_SRB = 0x01,
242 FD_REG_DOR = 0x02,
243 FD_REG_TDR = 0x03,
244 FD_REG_MSR = 0x04,
245 FD_REG_DSR = 0x04,
246 FD_REG_FIFO = 0x05,
247 FD_REG_DIR = 0x07,
248 };
249
250 enum {
251 FD_CMD_READ_TRACK = 0x02,
252 FD_CMD_SPECIFY = 0x03,
253 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
254 FD_CMD_WRITE = 0x05,
255 FD_CMD_READ = 0x06,
256 FD_CMD_RECALIBRATE = 0x07,
257 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
258 FD_CMD_WRITE_DELETED = 0x09,
259 FD_CMD_READ_ID = 0x0a,
260 FD_CMD_READ_DELETED = 0x0c,
261 FD_CMD_FORMAT_TRACK = 0x0d,
262 FD_CMD_DUMPREG = 0x0e,
263 FD_CMD_SEEK = 0x0f,
264 FD_CMD_VERSION = 0x10,
265 FD_CMD_SCAN_EQUAL = 0x11,
266 FD_CMD_PERPENDICULAR_MODE = 0x12,
267 FD_CMD_CONFIGURE = 0x13,
268 FD_CMD_LOCK = 0x14,
269 FD_CMD_VERIFY = 0x16,
270 FD_CMD_POWERDOWN_MODE = 0x17,
271 FD_CMD_PART_ID = 0x18,
272 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
273 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
274 FD_CMD_SAVE = 0x2e,
275 FD_CMD_OPTION = 0x33,
276 FD_CMD_RESTORE = 0x4e,
277 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
278 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
279 FD_CMD_FORMAT_AND_WRITE = 0xcd,
280 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
281 };
282
283 enum {
284 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
285 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
286 FD_CONFIG_POLL = 0x10, /* Poll enabled */
287 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
288 FD_CONFIG_EIS = 0x40, /* No implied seeks */
289 };
290
291 enum {
292 FD_SR0_EQPMT = 0x10,
293 FD_SR0_SEEK = 0x20,
294 FD_SR0_ABNTERM = 0x40,
295 FD_SR0_INVCMD = 0x80,
296 FD_SR0_RDYCHG = 0xc0,
297 };
298
299 enum {
300 FD_SR1_EC = 0x80, /* End of cylinder */
301 };
302
303 enum {
304 FD_SR2_SNS = 0x04, /* Scan not satisfied */
305 FD_SR2_SEH = 0x08, /* Scan equal hit */
306 };
307
308 enum {
309 FD_SRA_DIR = 0x01,
310 FD_SRA_nWP = 0x02,
311 FD_SRA_nINDX = 0x04,
312 FD_SRA_HDSEL = 0x08,
313 FD_SRA_nTRK0 = 0x10,
314 FD_SRA_STEP = 0x20,
315 FD_SRA_nDRV2 = 0x40,
316 FD_SRA_INTPEND = 0x80,
317 };
318
319 enum {
320 FD_SRB_MTR0 = 0x01,
321 FD_SRB_MTR1 = 0x02,
322 FD_SRB_WGATE = 0x04,
323 FD_SRB_RDATA = 0x08,
324 FD_SRB_WDATA = 0x10,
325 FD_SRB_DR0 = 0x20,
326 };
327
328 enum {
329 #if MAX_FD == 4
330 FD_DOR_SELMASK = 0x03,
331 #else
332 FD_DOR_SELMASK = 0x01,
333 #endif
334 FD_DOR_nRESET = 0x04,
335 FD_DOR_DMAEN = 0x08,
336 FD_DOR_MOTEN0 = 0x10,
337 FD_DOR_MOTEN1 = 0x20,
338 FD_DOR_MOTEN2 = 0x40,
339 FD_DOR_MOTEN3 = 0x80,
340 };
341
342 enum {
343 #if MAX_FD == 4
344 FD_TDR_BOOTSEL = 0x0c,
345 #else
346 FD_TDR_BOOTSEL = 0x04,
347 #endif
348 };
349
350 enum {
351 FD_DSR_DRATEMASK= 0x03,
352 FD_DSR_PWRDOWN = 0x40,
353 FD_DSR_SWRESET = 0x80,
354 };
355
356 enum {
357 FD_MSR_DRV0BUSY = 0x01,
358 FD_MSR_DRV1BUSY = 0x02,
359 FD_MSR_DRV2BUSY = 0x04,
360 FD_MSR_DRV3BUSY = 0x08,
361 FD_MSR_CMDBUSY = 0x10,
362 FD_MSR_NONDMA = 0x20,
363 FD_MSR_DIO = 0x40,
364 FD_MSR_RQM = 0x80,
365 };
366
367 enum {
368 FD_DIR_DSKCHG = 0x80,
369 };
370
371 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
372 #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
373 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
374
375 struct FDCtrl {
376 MemoryRegion iomem;
377 qemu_irq irq;
378 /* Controller state */
379 QEMUTimer *result_timer;
380 int dma_chann;
381 /* Controller's identification */
382 uint8_t version;
383 /* HW */
384 uint8_t sra;
385 uint8_t srb;
386 uint8_t dor;
387 uint8_t dor_vmstate; /* only used as temp during vmstate */
388 uint8_t tdr;
389 uint8_t dsr;
390 uint8_t msr;
391 uint8_t cur_drv;
392 uint8_t status0;
393 uint8_t status1;
394 uint8_t status2;
395 /* Command FIFO */
396 uint8_t *fifo;
397 int32_t fifo_size;
398 uint32_t data_pos;
399 uint32_t data_len;
400 uint8_t data_state;
401 uint8_t data_dir;
402 uint8_t eot; /* last wanted sector */
403 /* States kept only to be returned back */
404 /* precompensation */
405 uint8_t precomp_trk;
406 uint8_t config;
407 uint8_t lock;
408 /* Power down config (also with status regB access mode */
409 uint8_t pwrd;
410 /* Floppy drives */
411 uint8_t num_floppies;
412 /* Sun4m quirks? */
413 int sun4m;
414 FDrive drives[MAX_FD];
415 int reset_sensei;
416 /* Timers state */
417 uint8_t timer0;
418 uint8_t timer1;
419 };
420
421 typedef struct FDCtrlSysBus {
422 SysBusDevice busdev;
423 struct FDCtrl state;
424 } FDCtrlSysBus;
425
426 typedef struct FDCtrlISABus {
427 ISADevice busdev;
428 struct FDCtrl state;
429 int32_t bootindexA;
430 int32_t bootindexB;
431 } FDCtrlISABus;
432
433 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
434 {
435 FDCtrl *fdctrl = opaque;
436 uint32_t retval;
437
438 reg &= 7;
439 switch (reg) {
440 case FD_REG_SRA:
441 retval = fdctrl_read_statusA(fdctrl);
442 break;
443 case FD_REG_SRB:
444 retval = fdctrl_read_statusB(fdctrl);
445 break;
446 case FD_REG_DOR:
447 retval = fdctrl_read_dor(fdctrl);
448 break;
449 case FD_REG_TDR:
450 retval = fdctrl_read_tape(fdctrl);
451 break;
452 case FD_REG_MSR:
453 retval = fdctrl_read_main_status(fdctrl);
454 break;
455 case FD_REG_FIFO:
456 retval = fdctrl_read_data(fdctrl);
457 break;
458 case FD_REG_DIR:
459 retval = fdctrl_read_dir(fdctrl);
460 break;
461 default:
462 retval = (uint32_t)(-1);
463 break;
464 }
465 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
466
467 return retval;
468 }
469
470 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
471 {
472 FDCtrl *fdctrl = opaque;
473
474 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
475
476 reg &= 7;
477 switch (reg) {
478 case FD_REG_DOR:
479 fdctrl_write_dor(fdctrl, value);
480 break;
481 case FD_REG_TDR:
482 fdctrl_write_tape(fdctrl, value);
483 break;
484 case FD_REG_DSR:
485 fdctrl_write_rate(fdctrl, value);
486 break;
487 case FD_REG_FIFO:
488 fdctrl_write_data(fdctrl, value);
489 break;
490 default:
491 break;
492 }
493 }
494
495 static uint64_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg,
496 unsigned ize)
497 {
498 return fdctrl_read(opaque, (uint32_t)reg);
499 }
500
501 static void fdctrl_write_mem (void *opaque, target_phys_addr_t reg,
502 uint64_t value, unsigned size)
503 {
504 fdctrl_write(opaque, (uint32_t)reg, value);
505 }
506
507 static const MemoryRegionOps fdctrl_mem_ops = {
508 .read = fdctrl_read_mem,
509 .write = fdctrl_write_mem,
510 .endianness = DEVICE_NATIVE_ENDIAN,
511 };
512
513 static const MemoryRegionOps fdctrl_mem_strict_ops = {
514 .read = fdctrl_read_mem,
515 .write = fdctrl_write_mem,
516 .endianness = DEVICE_NATIVE_ENDIAN,
517 .valid = {
518 .min_access_size = 1,
519 .max_access_size = 1,
520 },
521 };
522
523 static bool fdrive_media_changed_needed(void *opaque)
524 {
525 FDrive *drive = opaque;
526
527 return (drive->bs != NULL && drive->media_changed != 1);
528 }
529
530 static const VMStateDescription vmstate_fdrive_media_changed = {
531 .name = "fdrive/media_changed",
532 .version_id = 1,
533 .minimum_version_id = 1,
534 .minimum_version_id_old = 1,
535 .fields = (VMStateField[]) {
536 VMSTATE_UINT8(media_changed, FDrive),
537 VMSTATE_END_OF_LIST()
538 }
539 };
540
541 static const VMStateDescription vmstate_fdrive = {
542 .name = "fdrive",
543 .version_id = 1,
544 .minimum_version_id = 1,
545 .minimum_version_id_old = 1,
546 .fields = (VMStateField[]) {
547 VMSTATE_UINT8(head, FDrive),
548 VMSTATE_UINT8(track, FDrive),
549 VMSTATE_UINT8(sect, FDrive),
550 VMSTATE_END_OF_LIST()
551 },
552 .subsections = (VMStateSubsection[]) {
553 {
554 .vmsd = &vmstate_fdrive_media_changed,
555 .needed = &fdrive_media_changed_needed,
556 } , {
557 /* empty */
558 }
559 }
560 };
561
562 static void fdc_pre_save(void *opaque)
563 {
564 FDCtrl *s = opaque;
565
566 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
567 }
568
569 static int fdc_post_load(void *opaque, int version_id)
570 {
571 FDCtrl *s = opaque;
572
573 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
574 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
575 return 0;
576 }
577
578 static const VMStateDescription vmstate_fdc = {
579 .name = "fdc",
580 .version_id = 2,
581 .minimum_version_id = 2,
582 .minimum_version_id_old = 2,
583 .pre_save = fdc_pre_save,
584 .post_load = fdc_post_load,
585 .fields = (VMStateField []) {
586 /* Controller State */
587 VMSTATE_UINT8(sra, FDCtrl),
588 VMSTATE_UINT8(srb, FDCtrl),
589 VMSTATE_UINT8(dor_vmstate, FDCtrl),
590 VMSTATE_UINT8(tdr, FDCtrl),
591 VMSTATE_UINT8(dsr, FDCtrl),
592 VMSTATE_UINT8(msr, FDCtrl),
593 VMSTATE_UINT8(status0, FDCtrl),
594 VMSTATE_UINT8(status1, FDCtrl),
595 VMSTATE_UINT8(status2, FDCtrl),
596 /* Command FIFO */
597 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
598 uint8_t),
599 VMSTATE_UINT32(data_pos, FDCtrl),
600 VMSTATE_UINT32(data_len, FDCtrl),
601 VMSTATE_UINT8(data_state, FDCtrl),
602 VMSTATE_UINT8(data_dir, FDCtrl),
603 VMSTATE_UINT8(eot, FDCtrl),
604 /* States kept only to be returned back */
605 VMSTATE_UINT8(timer0, FDCtrl),
606 VMSTATE_UINT8(timer1, FDCtrl),
607 VMSTATE_UINT8(precomp_trk, FDCtrl),
608 VMSTATE_UINT8(config, FDCtrl),
609 VMSTATE_UINT8(lock, FDCtrl),
610 VMSTATE_UINT8(pwrd, FDCtrl),
611 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
612 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
613 vmstate_fdrive, FDrive),
614 VMSTATE_END_OF_LIST()
615 }
616 };
617
618 static void fdctrl_external_reset_sysbus(DeviceState *d)
619 {
620 FDCtrlSysBus *sys = container_of(d, FDCtrlSysBus, busdev.qdev);
621 FDCtrl *s = &sys->state;
622
623 fdctrl_reset(s, 0);
624 }
625
626 static void fdctrl_external_reset_isa(DeviceState *d)
627 {
628 FDCtrlISABus *isa = container_of(d, FDCtrlISABus, busdev.qdev);
629 FDCtrl *s = &isa->state;
630
631 fdctrl_reset(s, 0);
632 }
633
634 static void fdctrl_handle_tc(void *opaque, int irq, int level)
635 {
636 //FDCtrl *s = opaque;
637
638 if (level) {
639 // XXX
640 FLOPPY_DPRINTF("TC pulsed\n");
641 }
642 }
643
644 /* Change IRQ state */
645 static void fdctrl_reset_irq(FDCtrl *fdctrl)
646 {
647 if (!(fdctrl->sra & FD_SRA_INTPEND))
648 return;
649 FLOPPY_DPRINTF("Reset interrupt\n");
650 qemu_set_irq(fdctrl->irq, 0);
651 fdctrl->sra &= ~FD_SRA_INTPEND;
652 }
653
654 static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0)
655 {
656 /* Sparc mutation */
657 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
658 /* XXX: not sure */
659 fdctrl->msr &= ~FD_MSR_CMDBUSY;
660 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
661 fdctrl->status0 = status0;
662 return;
663 }
664 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
665 qemu_set_irq(fdctrl->irq, 1);
666 fdctrl->sra |= FD_SRA_INTPEND;
667 }
668 fdctrl->reset_sensei = 0;
669 fdctrl->status0 = status0;
670 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
671 }
672
673 /* Reset controller */
674 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
675 {
676 int i;
677
678 FLOPPY_DPRINTF("reset controller\n");
679 fdctrl_reset_irq(fdctrl);
680 /* Initialise controller */
681 fdctrl->sra = 0;
682 fdctrl->srb = 0xc0;
683 if (!fdctrl->drives[1].bs)
684 fdctrl->sra |= FD_SRA_nDRV2;
685 fdctrl->cur_drv = 0;
686 fdctrl->dor = FD_DOR_nRESET;
687 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
688 fdctrl->msr = FD_MSR_RQM;
689 /* FIFO state */
690 fdctrl->data_pos = 0;
691 fdctrl->data_len = 0;
692 fdctrl->data_state = 0;
693 fdctrl->data_dir = FD_DIR_WRITE;
694 for (i = 0; i < MAX_FD; i++)
695 fd_recalibrate(&fdctrl->drives[i]);
696 fdctrl_reset_fifo(fdctrl);
697 if (do_irq) {
698 fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
699 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
700 }
701 }
702
703 static inline FDrive *drv0(FDCtrl *fdctrl)
704 {
705 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
706 }
707
708 static inline FDrive *drv1(FDCtrl *fdctrl)
709 {
710 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
711 return &fdctrl->drives[1];
712 else
713 return &fdctrl->drives[0];
714 }
715
716 #if MAX_FD == 4
717 static inline FDrive *drv2(FDCtrl *fdctrl)
718 {
719 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
720 return &fdctrl->drives[2];
721 else
722 return &fdctrl->drives[1];
723 }
724
725 static inline FDrive *drv3(FDCtrl *fdctrl)
726 {
727 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
728 return &fdctrl->drives[3];
729 else
730 return &fdctrl->drives[2];
731 }
732 #endif
733
734 static FDrive *get_cur_drv(FDCtrl *fdctrl)
735 {
736 switch (fdctrl->cur_drv) {
737 case 0: return drv0(fdctrl);
738 case 1: return drv1(fdctrl);
739 #if MAX_FD == 4
740 case 2: return drv2(fdctrl);
741 case 3: return drv3(fdctrl);
742 #endif
743 default: return NULL;
744 }
745 }
746
747 /* Status A register : 0x00 (read-only) */
748 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
749 {
750 uint32_t retval = fdctrl->sra;
751
752 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
753
754 return retval;
755 }
756
757 /* Status B register : 0x01 (read-only) */
758 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
759 {
760 uint32_t retval = fdctrl->srb;
761
762 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
763
764 return retval;
765 }
766
767 /* Digital output register : 0x02 */
768 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
769 {
770 uint32_t retval = fdctrl->dor;
771
772 /* Selected drive */
773 retval |= fdctrl->cur_drv;
774 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
775
776 return retval;
777 }
778
779 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
780 {
781 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
782
783 /* Motors */
784 if (value & FD_DOR_MOTEN0)
785 fdctrl->srb |= FD_SRB_MTR0;
786 else
787 fdctrl->srb &= ~FD_SRB_MTR0;
788 if (value & FD_DOR_MOTEN1)
789 fdctrl->srb |= FD_SRB_MTR1;
790 else
791 fdctrl->srb &= ~FD_SRB_MTR1;
792
793 /* Drive */
794 if (value & 1)
795 fdctrl->srb |= FD_SRB_DR0;
796 else
797 fdctrl->srb &= ~FD_SRB_DR0;
798
799 /* Reset */
800 if (!(value & FD_DOR_nRESET)) {
801 if (fdctrl->dor & FD_DOR_nRESET) {
802 FLOPPY_DPRINTF("controller enter RESET state\n");
803 }
804 } else {
805 if (!(fdctrl->dor & FD_DOR_nRESET)) {
806 FLOPPY_DPRINTF("controller out of RESET state\n");
807 fdctrl_reset(fdctrl, 1);
808 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
809 }
810 }
811 /* Selected drive */
812 fdctrl->cur_drv = value & FD_DOR_SELMASK;
813
814 fdctrl->dor = value;
815 }
816
817 /* Tape drive register : 0x03 */
818 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
819 {
820 uint32_t retval = fdctrl->tdr;
821
822 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
823
824 return retval;
825 }
826
827 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
828 {
829 /* Reset mode */
830 if (!(fdctrl->dor & FD_DOR_nRESET)) {
831 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
832 return;
833 }
834 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
835 /* Disk boot selection indicator */
836 fdctrl->tdr = value & FD_TDR_BOOTSEL;
837 /* Tape indicators: never allow */
838 }
839
840 /* Main status register : 0x04 (read) */
841 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
842 {
843 uint32_t retval = fdctrl->msr;
844
845 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
846 fdctrl->dor |= FD_DOR_nRESET;
847
848 /* Sparc mutation */
849 if (fdctrl->sun4m) {
850 retval |= FD_MSR_DIO;
851 fdctrl_reset_irq(fdctrl);
852 };
853
854 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
855
856 return retval;
857 }
858
859 /* Data select rate register : 0x04 (write) */
860 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
861 {
862 /* Reset mode */
863 if (!(fdctrl->dor & FD_DOR_nRESET)) {
864 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
865 return;
866 }
867 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
868 /* Reset: autoclear */
869 if (value & FD_DSR_SWRESET) {
870 fdctrl->dor &= ~FD_DOR_nRESET;
871 fdctrl_reset(fdctrl, 1);
872 fdctrl->dor |= FD_DOR_nRESET;
873 }
874 if (value & FD_DSR_PWRDOWN) {
875 fdctrl_reset(fdctrl, 1);
876 }
877 fdctrl->dsr = value;
878 }
879
880 static int fdctrl_media_changed(FDrive *drv)
881 {
882 int ret;
883
884 if (!drv->bs)
885 return 0;
886 if (drv->media_changed) {
887 drv->media_changed = 0;
888 ret = 1;
889 } else {
890 ret = bdrv_media_changed(drv->bs);
891 if (ret < 0) {
892 ret = 0; /* we don't know, assume no */
893 }
894 }
895 if (ret) {
896 fd_revalidate(drv);
897 }
898 return ret;
899 }
900
901 /* Digital input register : 0x07 (read-only) */
902 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
903 {
904 uint32_t retval = 0;
905
906 if (fdctrl_media_changed(drv0(fdctrl))
907 || fdctrl_media_changed(drv1(fdctrl))
908 #if MAX_FD == 4
909 || fdctrl_media_changed(drv2(fdctrl))
910 || fdctrl_media_changed(drv3(fdctrl))
911 #endif
912 )
913 retval |= FD_DIR_DSKCHG;
914 if (retval != 0) {
915 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
916 }
917
918 return retval;
919 }
920
921 /* FIFO state control */
922 static void fdctrl_reset_fifo(FDCtrl *fdctrl)
923 {
924 fdctrl->data_dir = FD_DIR_WRITE;
925 fdctrl->data_pos = 0;
926 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
927 }
928
929 /* Set FIFO status for the host to read */
930 static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len, int do_irq)
931 {
932 fdctrl->data_dir = FD_DIR_READ;
933 fdctrl->data_len = fifo_len;
934 fdctrl->data_pos = 0;
935 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
936 if (do_irq)
937 fdctrl_raise_irq(fdctrl, 0x00);
938 }
939
940 /* Set an error: unimplemented/unknown command */
941 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
942 {
943 FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
944 fdctrl->fifo[0] = FD_SR0_INVCMD;
945 fdctrl_set_fifo(fdctrl, 1, 0);
946 }
947
948 /* Seek to next sector */
949 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
950 {
951 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
952 cur_drv->head, cur_drv->track, cur_drv->sect,
953 fd_sector(cur_drv));
954 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
955 error in fact */
956 if (cur_drv->sect >= cur_drv->last_sect ||
957 cur_drv->sect == fdctrl->eot) {
958 cur_drv->sect = 1;
959 if (FD_MULTI_TRACK(fdctrl->data_state)) {
960 if (cur_drv->head == 0 &&
961 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
962 cur_drv->head = 1;
963 } else {
964 cur_drv->head = 0;
965 cur_drv->track++;
966 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
967 return 0;
968 }
969 } else {
970 cur_drv->track++;
971 return 0;
972 }
973 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
974 cur_drv->head, cur_drv->track,
975 cur_drv->sect, fd_sector(cur_drv));
976 } else {
977 cur_drv->sect++;
978 }
979 return 1;
980 }
981
982 /* Callback for transfer end (stop or abort) */
983 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
984 uint8_t status1, uint8_t status2)
985 {
986 FDrive *cur_drv;
987
988 cur_drv = get_cur_drv(fdctrl);
989 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
990 status0, status1, status2,
991 status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
992 fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
993 fdctrl->fifo[1] = status1;
994 fdctrl->fifo[2] = status2;
995 fdctrl->fifo[3] = cur_drv->track;
996 fdctrl->fifo[4] = cur_drv->head;
997 fdctrl->fifo[5] = cur_drv->sect;
998 fdctrl->fifo[6] = FD_SECTOR_SC;
999 fdctrl->data_dir = FD_DIR_READ;
1000 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1001 DMA_release_DREQ(fdctrl->dma_chann);
1002 }
1003 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1004 fdctrl->msr &= ~FD_MSR_NONDMA;
1005 fdctrl_set_fifo(fdctrl, 7, 1);
1006 }
1007
1008 /* Prepare a data transfer (either DMA or FIFO) */
1009 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
1010 {
1011 FDrive *cur_drv;
1012 uint8_t kh, kt, ks;
1013 int did_seek = 0;
1014
1015 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1016 cur_drv = get_cur_drv(fdctrl);
1017 kt = fdctrl->fifo[2];
1018 kh = fdctrl->fifo[3];
1019 ks = fdctrl->fifo[4];
1020 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1021 GET_CUR_DRV(fdctrl), kh, kt, ks,
1022 fd_sector_calc(kh, kt, ks, cur_drv->last_sect));
1023 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1024 case 2:
1025 /* sect too big */
1026 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1027 fdctrl->fifo[3] = kt;
1028 fdctrl->fifo[4] = kh;
1029 fdctrl->fifo[5] = ks;
1030 return;
1031 case 3:
1032 /* track too big */
1033 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1034 fdctrl->fifo[3] = kt;
1035 fdctrl->fifo[4] = kh;
1036 fdctrl->fifo[5] = ks;
1037 return;
1038 case 4:
1039 /* No seek enabled */
1040 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1041 fdctrl->fifo[3] = kt;
1042 fdctrl->fifo[4] = kh;
1043 fdctrl->fifo[5] = ks;
1044 return;
1045 case 1:
1046 did_seek = 1;
1047 break;
1048 default:
1049 break;
1050 }
1051
1052 /* Set the FIFO state */
1053 fdctrl->data_dir = direction;
1054 fdctrl->data_pos = 0;
1055 fdctrl->msr |= FD_MSR_CMDBUSY;
1056 if (fdctrl->fifo[0] & 0x80)
1057 fdctrl->data_state |= FD_STATE_MULTI;
1058 else
1059 fdctrl->data_state &= ~FD_STATE_MULTI;
1060 if (did_seek)
1061 fdctrl->data_state |= FD_STATE_SEEK;
1062 else
1063 fdctrl->data_state &= ~FD_STATE_SEEK;
1064 if (fdctrl->fifo[5] == 00) {
1065 fdctrl->data_len = fdctrl->fifo[8];
1066 } else {
1067 int tmp;
1068 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1069 tmp = (fdctrl->fifo[6] - ks + 1);
1070 if (fdctrl->fifo[0] & 0x80)
1071 tmp += fdctrl->fifo[6];
1072 fdctrl->data_len *= tmp;
1073 }
1074 fdctrl->eot = fdctrl->fifo[6];
1075 if (fdctrl->dor & FD_DOR_DMAEN) {
1076 int dma_mode;
1077 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1078 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1079 dma_mode = (dma_mode >> 2) & 3;
1080 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1081 dma_mode, direction,
1082 (128 << fdctrl->fifo[5]) *
1083 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1084 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1085 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1086 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1087 (direction == FD_DIR_READ && dma_mode == 1)) {
1088 /* No access is allowed until DMA transfer has completed */
1089 fdctrl->msr &= ~FD_MSR_RQM;
1090 /* Now, we just have to wait for the DMA controller to
1091 * recall us...
1092 */
1093 DMA_hold_DREQ(fdctrl->dma_chann);
1094 DMA_schedule(fdctrl->dma_chann);
1095 return;
1096 } else {
1097 FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1098 }
1099 }
1100 FLOPPY_DPRINTF("start non-DMA transfer\n");
1101 fdctrl->msr |= FD_MSR_NONDMA;
1102 if (direction != FD_DIR_WRITE)
1103 fdctrl->msr |= FD_MSR_DIO;
1104 /* IO based transfer: calculate len */
1105 fdctrl_raise_irq(fdctrl, 0x00);
1106
1107 return;
1108 }
1109
1110 /* Prepare a transfer of deleted data */
1111 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
1112 {
1113 FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1114
1115 /* We don't handle deleted data,
1116 * so we don't return *ANYTHING*
1117 */
1118 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1119 }
1120
1121 /* handlers for DMA transfers */
1122 static int fdctrl_transfer_handler (void *opaque, int nchan,
1123 int dma_pos, int dma_len)
1124 {
1125 FDCtrl *fdctrl;
1126 FDrive *cur_drv;
1127 int len, start_pos, rel_pos;
1128 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1129
1130 fdctrl = opaque;
1131 if (fdctrl->msr & FD_MSR_RQM) {
1132 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1133 return 0;
1134 }
1135 cur_drv = get_cur_drv(fdctrl);
1136 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1137 fdctrl->data_dir == FD_DIR_SCANH)
1138 status2 = FD_SR2_SNS;
1139 if (dma_len > fdctrl->data_len)
1140 dma_len = fdctrl->data_len;
1141 if (cur_drv->bs == NULL) {
1142 if (fdctrl->data_dir == FD_DIR_WRITE)
1143 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1144 else
1145 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1146 len = 0;
1147 goto transfer_error;
1148 }
1149 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1150 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1151 len = dma_len - fdctrl->data_pos;
1152 if (len + rel_pos > FD_SECTOR_LEN)
1153 len = FD_SECTOR_LEN - rel_pos;
1154 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1155 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1156 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1157 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1158 fd_sector(cur_drv) * FD_SECTOR_LEN);
1159 if (fdctrl->data_dir != FD_DIR_WRITE ||
1160 len < FD_SECTOR_LEN || rel_pos != 0) {
1161 /* READ & SCAN commands and realign to a sector for WRITE */
1162 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1163 fdctrl->fifo, 1) < 0) {
1164 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1165 fd_sector(cur_drv));
1166 /* Sure, image size is too small... */
1167 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1168 }
1169 }
1170 switch (fdctrl->data_dir) {
1171 case FD_DIR_READ:
1172 /* READ commands */
1173 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1174 fdctrl->data_pos, len);
1175 break;
1176 case FD_DIR_WRITE:
1177 /* WRITE commands */
1178 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1179 fdctrl->data_pos, len);
1180 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1181 fdctrl->fifo, 1) < 0) {
1182 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1183 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1184 goto transfer_error;
1185 }
1186 break;
1187 default:
1188 /* SCAN commands */
1189 {
1190 uint8_t tmpbuf[FD_SECTOR_LEN];
1191 int ret;
1192 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1193 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1194 if (ret == 0) {
1195 status2 = FD_SR2_SEH;
1196 goto end_transfer;
1197 }
1198 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1199 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1200 status2 = 0x00;
1201 goto end_transfer;
1202 }
1203 }
1204 break;
1205 }
1206 fdctrl->data_pos += len;
1207 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1208 if (rel_pos == 0) {
1209 /* Seek to next sector */
1210 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1211 break;
1212 }
1213 }
1214 end_transfer:
1215 len = fdctrl->data_pos - start_pos;
1216 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1217 fdctrl->data_pos, len, fdctrl->data_len);
1218 if (fdctrl->data_dir == FD_DIR_SCANE ||
1219 fdctrl->data_dir == FD_DIR_SCANL ||
1220 fdctrl->data_dir == FD_DIR_SCANH)
1221 status2 = FD_SR2_SEH;
1222 if (FD_DID_SEEK(fdctrl->data_state))
1223 status0 |= FD_SR0_SEEK;
1224 fdctrl->data_len -= len;
1225 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1226 transfer_error:
1227
1228 return len;
1229 }
1230
1231 /* Data register : 0x05 */
1232 static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
1233 {
1234 FDrive *cur_drv;
1235 uint32_t retval = 0;
1236 int pos;
1237
1238 cur_drv = get_cur_drv(fdctrl);
1239 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1240 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1241 FLOPPY_ERROR("controller not ready for reading\n");
1242 return 0;
1243 }
1244 pos = fdctrl->data_pos;
1245 if (fdctrl->msr & FD_MSR_NONDMA) {
1246 pos %= FD_SECTOR_LEN;
1247 if (pos == 0) {
1248 if (fdctrl->data_pos != 0)
1249 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1250 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1251 fd_sector(cur_drv));
1252 return 0;
1253 }
1254 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1255 FLOPPY_DPRINTF("error getting sector %d\n",
1256 fd_sector(cur_drv));
1257 /* Sure, image size is too small... */
1258 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1259 }
1260 }
1261 }
1262 retval = fdctrl->fifo[pos];
1263 if (++fdctrl->data_pos == fdctrl->data_len) {
1264 fdctrl->data_pos = 0;
1265 /* Switch from transfer mode to status mode
1266 * then from status mode to command mode
1267 */
1268 if (fdctrl->msr & FD_MSR_NONDMA) {
1269 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1270 } else {
1271 fdctrl_reset_fifo(fdctrl);
1272 fdctrl_reset_irq(fdctrl);
1273 }
1274 }
1275 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1276
1277 return retval;
1278 }
1279
1280 static void fdctrl_format_sector(FDCtrl *fdctrl)
1281 {
1282 FDrive *cur_drv;
1283 uint8_t kh, kt, ks;
1284
1285 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1286 cur_drv = get_cur_drv(fdctrl);
1287 kt = fdctrl->fifo[6];
1288 kh = fdctrl->fifo[7];
1289 ks = fdctrl->fifo[8];
1290 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1291 GET_CUR_DRV(fdctrl), kh, kt, ks,
1292 fd_sector_calc(kh, kt, ks, cur_drv->last_sect));
1293 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1294 case 2:
1295 /* sect too big */
1296 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1297 fdctrl->fifo[3] = kt;
1298 fdctrl->fifo[4] = kh;
1299 fdctrl->fifo[5] = ks;
1300 return;
1301 case 3:
1302 /* track too big */
1303 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1304 fdctrl->fifo[3] = kt;
1305 fdctrl->fifo[4] = kh;
1306 fdctrl->fifo[5] = ks;
1307 return;
1308 case 4:
1309 /* No seek enabled */
1310 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1311 fdctrl->fifo[3] = kt;
1312 fdctrl->fifo[4] = kh;
1313 fdctrl->fifo[5] = ks;
1314 return;
1315 case 1:
1316 fdctrl->data_state |= FD_STATE_SEEK;
1317 break;
1318 default:
1319 break;
1320 }
1321 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1322 if (cur_drv->bs == NULL ||
1323 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1324 FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1325 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1326 } else {
1327 if (cur_drv->sect == cur_drv->last_sect) {
1328 fdctrl->data_state &= ~FD_STATE_FORMAT;
1329 /* Last sector done */
1330 if (FD_DID_SEEK(fdctrl->data_state))
1331 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1332 else
1333 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1334 } else {
1335 /* More to do */
1336 fdctrl->data_pos = 0;
1337 fdctrl->data_len = 4;
1338 }
1339 }
1340 }
1341
1342 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
1343 {
1344 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1345 fdctrl->fifo[0] = fdctrl->lock << 4;
1346 fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
1347 }
1348
1349 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
1350 {
1351 FDrive *cur_drv = get_cur_drv(fdctrl);
1352
1353 /* Drives position */
1354 fdctrl->fifo[0] = drv0(fdctrl)->track;
1355 fdctrl->fifo[1] = drv1(fdctrl)->track;
1356 #if MAX_FD == 4
1357 fdctrl->fifo[2] = drv2(fdctrl)->track;
1358 fdctrl->fifo[3] = drv3(fdctrl)->track;
1359 #else
1360 fdctrl->fifo[2] = 0;
1361 fdctrl->fifo[3] = 0;
1362 #endif
1363 /* timers */
1364 fdctrl->fifo[4] = fdctrl->timer0;
1365 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1366 fdctrl->fifo[6] = cur_drv->last_sect;
1367 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1368 (cur_drv->perpendicular << 2);
1369 fdctrl->fifo[8] = fdctrl->config;
1370 fdctrl->fifo[9] = fdctrl->precomp_trk;
1371 fdctrl_set_fifo(fdctrl, 10, 0);
1372 }
1373
1374 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
1375 {
1376 /* Controller's version */
1377 fdctrl->fifo[0] = fdctrl->version;
1378 fdctrl_set_fifo(fdctrl, 1, 1);
1379 }
1380
1381 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
1382 {
1383 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1384 fdctrl_set_fifo(fdctrl, 1, 0);
1385 }
1386
1387 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
1388 {
1389 FDrive *cur_drv = get_cur_drv(fdctrl);
1390
1391 /* Drives position */
1392 drv0(fdctrl)->track = fdctrl->fifo[3];
1393 drv1(fdctrl)->track = fdctrl->fifo[4];
1394 #if MAX_FD == 4
1395 drv2(fdctrl)->track = fdctrl->fifo[5];
1396 drv3(fdctrl)->track = fdctrl->fifo[6];
1397 #endif
1398 /* timers */
1399 fdctrl->timer0 = fdctrl->fifo[7];
1400 fdctrl->timer1 = fdctrl->fifo[8];
1401 cur_drv->last_sect = fdctrl->fifo[9];
1402 fdctrl->lock = fdctrl->fifo[10] >> 7;
1403 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1404 fdctrl->config = fdctrl->fifo[11];
1405 fdctrl->precomp_trk = fdctrl->fifo[12];
1406 fdctrl->pwrd = fdctrl->fifo[13];
1407 fdctrl_reset_fifo(fdctrl);
1408 }
1409
1410 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
1411 {
1412 FDrive *cur_drv = get_cur_drv(fdctrl);
1413
1414 fdctrl->fifo[0] = 0;
1415 fdctrl->fifo[1] = 0;
1416 /* Drives position */
1417 fdctrl->fifo[2] = drv0(fdctrl)->track;
1418 fdctrl->fifo[3] = drv1(fdctrl)->track;
1419 #if MAX_FD == 4
1420 fdctrl->fifo[4] = drv2(fdctrl)->track;
1421 fdctrl->fifo[5] = drv3(fdctrl)->track;
1422 #else
1423 fdctrl->fifo[4] = 0;
1424 fdctrl->fifo[5] = 0;
1425 #endif
1426 /* timers */
1427 fdctrl->fifo[6] = fdctrl->timer0;
1428 fdctrl->fifo[7] = fdctrl->timer1;
1429 fdctrl->fifo[8] = cur_drv->last_sect;
1430 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1431 (cur_drv->perpendicular << 2);
1432 fdctrl->fifo[10] = fdctrl->config;
1433 fdctrl->fifo[11] = fdctrl->precomp_trk;
1434 fdctrl->fifo[12] = fdctrl->pwrd;
1435 fdctrl->fifo[13] = 0;
1436 fdctrl->fifo[14] = 0;
1437 fdctrl_set_fifo(fdctrl, 15, 1);
1438 }
1439
1440 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
1441 {
1442 FDrive *cur_drv = get_cur_drv(fdctrl);
1443
1444 /* XXX: should set main status register to busy */
1445 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1446 qemu_mod_timer(fdctrl->result_timer,
1447 qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 50));
1448 }
1449
1450 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
1451 {
1452 FDrive *cur_drv;
1453
1454 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1455 cur_drv = get_cur_drv(fdctrl);
1456 fdctrl->data_state |= FD_STATE_FORMAT;
1457 if (fdctrl->fifo[0] & 0x80)
1458 fdctrl->data_state |= FD_STATE_MULTI;
1459 else
1460 fdctrl->data_state &= ~FD_STATE_MULTI;
1461 fdctrl->data_state &= ~FD_STATE_SEEK;
1462 cur_drv->bps =
1463 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1464 #if 0
1465 cur_drv->last_sect =
1466 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1467 fdctrl->fifo[3] / 2;
1468 #else
1469 cur_drv->last_sect = fdctrl->fifo[3];
1470 #endif
1471 /* TODO: implement format using DMA expected by the Bochs BIOS
1472 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1473 * the sector with the specified fill byte
1474 */
1475 fdctrl->data_state &= ~FD_STATE_FORMAT;
1476 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1477 }
1478
1479 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
1480 {
1481 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1482 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1483 if (fdctrl->fifo[2] & 1)
1484 fdctrl->dor &= ~FD_DOR_DMAEN;
1485 else
1486 fdctrl->dor |= FD_DOR_DMAEN;
1487 /* No result back */
1488 fdctrl_reset_fifo(fdctrl);
1489 }
1490
1491 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
1492 {
1493 FDrive *cur_drv;
1494
1495 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1496 cur_drv = get_cur_drv(fdctrl);
1497 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1498 /* 1 Byte status back */
1499 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1500 (cur_drv->track == 0 ? 0x10 : 0x00) |
1501 (cur_drv->head << 2) |
1502 GET_CUR_DRV(fdctrl) |
1503 0x28;
1504 fdctrl_set_fifo(fdctrl, 1, 0);
1505 }
1506
1507 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
1508 {
1509 FDrive *cur_drv;
1510
1511 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1512 cur_drv = get_cur_drv(fdctrl);
1513 fd_recalibrate(cur_drv);
1514 fdctrl_reset_fifo(fdctrl);
1515 /* Raise Interrupt */
1516 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1517 }
1518
1519 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
1520 {
1521 FDrive *cur_drv = get_cur_drv(fdctrl);
1522
1523 if(fdctrl->reset_sensei > 0) {
1524 fdctrl->fifo[0] =
1525 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1526 fdctrl->reset_sensei--;
1527 } else {
1528 /* XXX: status0 handling is broken for read/write
1529 commands, so we do this hack. It should be suppressed
1530 ASAP */
1531 fdctrl->fifo[0] =
1532 FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1533 }
1534
1535 fdctrl->fifo[1] = cur_drv->track;
1536 fdctrl_set_fifo(fdctrl, 2, 0);
1537 fdctrl_reset_irq(fdctrl);
1538 fdctrl->status0 = FD_SR0_RDYCHG;
1539 }
1540
1541 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
1542 {
1543 FDrive *cur_drv;
1544
1545 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1546 cur_drv = get_cur_drv(fdctrl);
1547 fdctrl_reset_fifo(fdctrl);
1548 if (fdctrl->fifo[2] > cur_drv->max_track) {
1549 fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK);
1550 } else {
1551 cur_drv->track = fdctrl->fifo[2];
1552 /* Raise Interrupt */
1553 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1554 }
1555 }
1556
1557 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
1558 {
1559 FDrive *cur_drv = get_cur_drv(fdctrl);
1560
1561 if (fdctrl->fifo[1] & 0x80)
1562 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1563 /* No result back */
1564 fdctrl_reset_fifo(fdctrl);
1565 }
1566
1567 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
1568 {
1569 fdctrl->config = fdctrl->fifo[2];
1570 fdctrl->precomp_trk = fdctrl->fifo[3];
1571 /* No result back */
1572 fdctrl_reset_fifo(fdctrl);
1573 }
1574
1575 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
1576 {
1577 fdctrl->pwrd = fdctrl->fifo[1];
1578 fdctrl->fifo[0] = fdctrl->fifo[1];
1579 fdctrl_set_fifo(fdctrl, 1, 1);
1580 }
1581
1582 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
1583 {
1584 /* No result back */
1585 fdctrl_reset_fifo(fdctrl);
1586 }
1587
1588 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
1589 {
1590 FDrive *cur_drv = get_cur_drv(fdctrl);
1591
1592 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1593 /* Command parameters done */
1594 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1595 fdctrl->fifo[0] = fdctrl->fifo[1];
1596 fdctrl->fifo[2] = 0;
1597 fdctrl->fifo[3] = 0;
1598 fdctrl_set_fifo(fdctrl, 4, 1);
1599 } else {
1600 fdctrl_reset_fifo(fdctrl);
1601 }
1602 } else if (fdctrl->data_len > 7) {
1603 /* ERROR */
1604 fdctrl->fifo[0] = 0x80 |
1605 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1606 fdctrl_set_fifo(fdctrl, 1, 1);
1607 }
1608 }
1609
1610 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
1611 {
1612 FDrive *cur_drv;
1613
1614 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1615 cur_drv = get_cur_drv(fdctrl);
1616 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1617 cur_drv->track = cur_drv->max_track - 1;
1618 } else {
1619 cur_drv->track += fdctrl->fifo[2];
1620 }
1621 fdctrl_reset_fifo(fdctrl);
1622 /* Raise Interrupt */
1623 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1624 }
1625
1626 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
1627 {
1628 FDrive *cur_drv;
1629
1630 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1631 cur_drv = get_cur_drv(fdctrl);
1632 if (fdctrl->fifo[2] > cur_drv->track) {
1633 cur_drv->track = 0;
1634 } else {
1635 cur_drv->track -= fdctrl->fifo[2];
1636 }
1637 fdctrl_reset_fifo(fdctrl);
1638 /* Raise Interrupt */
1639 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1640 }
1641
1642 static const struct {
1643 uint8_t value;
1644 uint8_t mask;
1645 const char* name;
1646 int parameters;
1647 void (*handler)(FDCtrl *fdctrl, int direction);
1648 int direction;
1649 } handlers[] = {
1650 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1651 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1652 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1653 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1654 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1655 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1656 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1657 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1658 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1659 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1660 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1661 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1662 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1663 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1664 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1665 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1666 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1667 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1668 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1669 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1670 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1671 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1672 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1673 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1674 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1675 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1676 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1677 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1678 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1679 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1680 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1681 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1682 };
1683 /* Associate command to an index in the 'handlers' array */
1684 static uint8_t command_to_handler[256];
1685
1686 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
1687 {
1688 FDrive *cur_drv;
1689 int pos;
1690
1691 /* Reset mode */
1692 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1693 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1694 return;
1695 }
1696 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1697 FLOPPY_ERROR("controller not ready for writing\n");
1698 return;
1699 }
1700 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1701 /* Is it write command time ? */
1702 if (fdctrl->msr & FD_MSR_NONDMA) {
1703 /* FIFO data write */
1704 pos = fdctrl->data_pos++;
1705 pos %= FD_SECTOR_LEN;
1706 fdctrl->fifo[pos] = value;
1707 if (pos == FD_SECTOR_LEN - 1 ||
1708 fdctrl->data_pos == fdctrl->data_len) {
1709 cur_drv = get_cur_drv(fdctrl);
1710 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1711 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1712 return;
1713 }
1714 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1715 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1716 fd_sector(cur_drv));
1717 return;
1718 }
1719 }
1720 /* Switch from transfer mode to status mode
1721 * then from status mode to command mode
1722 */
1723 if (fdctrl->data_pos == fdctrl->data_len)
1724 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1725 return;
1726 }
1727 if (fdctrl->data_pos == 0) {
1728 /* Command */
1729 pos = command_to_handler[value & 0xff];
1730 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1731 fdctrl->data_len = handlers[pos].parameters + 1;
1732 }
1733
1734 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1735 fdctrl->fifo[fdctrl->data_pos++] = value;
1736 if (fdctrl->data_pos == fdctrl->data_len) {
1737 /* We now have all parameters
1738 * and will be able to treat the command
1739 */
1740 if (fdctrl->data_state & FD_STATE_FORMAT) {
1741 fdctrl_format_sector(fdctrl);
1742 return;
1743 }
1744
1745 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1746 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1747 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1748 }
1749 }
1750
1751 static void fdctrl_result_timer(void *opaque)
1752 {
1753 FDCtrl *fdctrl = opaque;
1754 FDrive *cur_drv = get_cur_drv(fdctrl);
1755
1756 /* Pretend we are spinning.
1757 * This is needed for Coherent, which uses READ ID to check for
1758 * sector interleaving.
1759 */
1760 if (cur_drv->last_sect != 0) {
1761 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1762 }
1763 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1764 }
1765
1766 static void fdctrl_change_cb(void *opaque, bool load)
1767 {
1768 FDrive *drive = opaque;
1769
1770 drive->media_changed = 1;
1771 }
1772
1773 static const BlockDevOps fdctrl_block_ops = {
1774 .change_media_cb = fdctrl_change_cb,
1775 };
1776
1777 /* Init functions */
1778 static int fdctrl_connect_drives(FDCtrl *fdctrl)
1779 {
1780 unsigned int i;
1781 FDrive *drive;
1782
1783 for (i = 0; i < MAX_FD; i++) {
1784 drive = &fdctrl->drives[i];
1785
1786 if (drive->bs) {
1787 if (bdrv_get_on_error(drive->bs, 0) != BLOCK_ERR_STOP_ENOSPC) {
1788 error_report("fdc doesn't support drive option werror");
1789 return -1;
1790 }
1791 if (bdrv_get_on_error(drive->bs, 1) != BLOCK_ERR_REPORT) {
1792 error_report("fdc doesn't support drive option rerror");
1793 return -1;
1794 }
1795 }
1796
1797 fd_init(drive);
1798 fd_revalidate(drive);
1799 if (drive->bs) {
1800 drive->media_changed = 1;
1801 bdrv_set_dev_ops(drive->bs, &fdctrl_block_ops, drive);
1802 }
1803 }
1804 return 0;
1805 }
1806
1807 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
1808 target_phys_addr_t mmio_base, DriveInfo **fds)
1809 {
1810 FDCtrl *fdctrl;
1811 DeviceState *dev;
1812 FDCtrlSysBus *sys;
1813
1814 dev = qdev_create(NULL, "sysbus-fdc");
1815 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1816 fdctrl = &sys->state;
1817 fdctrl->dma_chann = dma_chann; /* FIXME */
1818 if (fds[0]) {
1819 qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv);
1820 }
1821 if (fds[1]) {
1822 qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv);
1823 }
1824 qdev_init_nofail(dev);
1825 sysbus_connect_irq(&sys->busdev, 0, irq);
1826 sysbus_mmio_map(&sys->busdev, 0, mmio_base);
1827 }
1828
1829 void sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
1830 DriveInfo **fds, qemu_irq *fdc_tc)
1831 {
1832 DeviceState *dev;
1833 FDCtrlSysBus *sys;
1834
1835 dev = qdev_create(NULL, "SUNW,fdtwo");
1836 if (fds[0]) {
1837 qdev_prop_set_drive_nofail(dev, "drive", fds[0]->bdrv);
1838 }
1839 qdev_init_nofail(dev);
1840 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1841 sysbus_connect_irq(&sys->busdev, 0, irq);
1842 sysbus_mmio_map(&sys->busdev, 0, io_base);
1843 *fdc_tc = qdev_get_gpio_in(dev, 0);
1844 }
1845
1846 static int fdctrl_init_common(FDCtrl *fdctrl)
1847 {
1848 int i, j;
1849 static int command_tables_inited = 0;
1850
1851 /* Fill 'command_to_handler' lookup table */
1852 if (!command_tables_inited) {
1853 command_tables_inited = 1;
1854 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1855 for (j = 0; j < sizeof(command_to_handler); j++) {
1856 if ((j & handlers[i].mask) == handlers[i].value) {
1857 command_to_handler[j] = i;
1858 }
1859 }
1860 }
1861 }
1862
1863 FLOPPY_DPRINTF("init controller\n");
1864 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1865 fdctrl->fifo_size = 512;
1866 fdctrl->result_timer = qemu_new_timer_ns(vm_clock,
1867 fdctrl_result_timer, fdctrl);
1868
1869 fdctrl->version = 0x90; /* Intel 82078 controller */
1870 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1871 fdctrl->num_floppies = MAX_FD;
1872
1873 if (fdctrl->dma_chann != -1)
1874 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
1875 return fdctrl_connect_drives(fdctrl);
1876 }
1877
1878 static const MemoryRegionPortio fdc_portio_list[] = {
1879 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
1880 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
1881 PORTIO_END_OF_LIST(),
1882 };
1883
1884 static int isabus_fdc_init1(ISADevice *dev)
1885 {
1886 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
1887 FDCtrl *fdctrl = &isa->state;
1888 int iobase = 0x3f0;
1889 int isairq = 6;
1890 int dma_chann = 2;
1891 int ret;
1892
1893 isa_register_portio_list(dev, iobase, fdc_portio_list, fdctrl, "fdc");
1894
1895 isa_init_irq(&isa->busdev, &fdctrl->irq, isairq);
1896 fdctrl->dma_chann = dma_chann;
1897
1898 qdev_set_legacy_instance_id(&dev->qdev, iobase, 2);
1899 ret = fdctrl_init_common(fdctrl);
1900
1901 add_boot_device_path(isa->bootindexA, &dev->qdev, "/floppy@0");
1902 add_boot_device_path(isa->bootindexB, &dev->qdev, "/floppy@1");
1903
1904 return ret;
1905 }
1906
1907 static int sysbus_fdc_init1(SysBusDevice *dev)
1908 {
1909 FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev);
1910 FDCtrl *fdctrl = &sys->state;
1911 int ret;
1912
1913 memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_ops, fdctrl, "fdc", 0x08);
1914 sysbus_init_mmio(dev, &fdctrl->iomem);
1915 sysbus_init_irq(dev, &fdctrl->irq);
1916 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
1917 fdctrl->dma_chann = -1;
1918
1919 qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */
1920 ret = fdctrl_init_common(fdctrl);
1921
1922 return ret;
1923 }
1924
1925 static int sun4m_fdc_init1(SysBusDevice *dev)
1926 {
1927 FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state);
1928
1929 memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_strict_ops, fdctrl,
1930 "fdctrl", 0x08);
1931 sysbus_init_mmio(dev, &fdctrl->iomem);
1932 sysbus_init_irq(dev, &fdctrl->irq);
1933 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
1934
1935 fdctrl->sun4m = 1;
1936 qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */
1937 return fdctrl_init_common(fdctrl);
1938 }
1939
1940 void fdc_get_bs(BlockDriverState *bs[], ISADevice *dev)
1941 {
1942 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
1943 FDCtrl *fdctrl = &isa->state;
1944 int i;
1945
1946 for (i = 0; i < MAX_FD; i++) {
1947 bs[i] = fdctrl->drives[i].bs;
1948 }
1949 }
1950
1951
1952 static const VMStateDescription vmstate_isa_fdc ={
1953 .name = "fdc",
1954 .version_id = 2,
1955 .minimum_version_id = 2,
1956 .fields = (VMStateField []) {
1957 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
1958 VMSTATE_END_OF_LIST()
1959 }
1960 };
1961
1962 static void isabus_fdc_class_init1(ObjectClass *klass, void *data)
1963 {
1964 ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
1965 ic->init = isabus_fdc_init1;
1966 }
1967
1968 static DeviceInfo isa_fdc_info = {
1969 .class_init = isabus_fdc_class_init1,
1970 .name = "isa-fdc",
1971 .fw_name = "fdc",
1972 .size = sizeof(FDCtrlISABus),
1973 .no_user = 1,
1974 .vmsd = &vmstate_isa_fdc,
1975 .reset = fdctrl_external_reset_isa,
1976 .props = (Property[]) {
1977 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].bs),
1978 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].bs),
1979 DEFINE_PROP_INT32("bootindexA", FDCtrlISABus, bootindexA, -1),
1980 DEFINE_PROP_INT32("bootindexB", FDCtrlISABus, bootindexB, -1),
1981 DEFINE_PROP_END_OF_LIST(),
1982 },
1983 };
1984
1985 static const VMStateDescription vmstate_sysbus_fdc ={
1986 .name = "fdc",
1987 .version_id = 2,
1988 .minimum_version_id = 2,
1989 .fields = (VMStateField []) {
1990 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
1991 VMSTATE_END_OF_LIST()
1992 }
1993 };
1994
1995 static Property sysbus_fdc_properties[] = {
1996 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].bs),
1997 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].bs),
1998 DEFINE_PROP_END_OF_LIST(),
1999 };
2000
2001 static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
2002 {
2003 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
2004
2005 k->init = sysbus_fdc_init1;
2006 }
2007
2008 static DeviceInfo sysbus_fdc_info = {
2009 .name = "sysbus-fdc",
2010 .size = sizeof(FDCtrlSysBus),
2011 .vmsd = &vmstate_sysbus_fdc,
2012 .reset = fdctrl_external_reset_sysbus,
2013 .props = sysbus_fdc_properties,
2014 .class_init = sysbus_fdc_class_init,
2015 };
2016
2017 static Property sun4m_fdc_properties[] = {
2018 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].bs),
2019 DEFINE_PROP_END_OF_LIST(),
2020 };
2021
2022 static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
2023 {
2024 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
2025
2026 k->init = sun4m_fdc_init1;
2027 }
2028
2029 static DeviceInfo sun4m_fdc_info = {
2030 .name = "SUNW,fdtwo",
2031 .size = sizeof(FDCtrlSysBus),
2032 .vmsd = &vmstate_sysbus_fdc,
2033 .reset = fdctrl_external_reset_sysbus,
2034 .props = sun4m_fdc_properties,
2035 .class_init = sun4m_fdc_class_init,
2036 };
2037
2038 static void fdc_register_devices(void)
2039 {
2040 isa_qdev_register(&isa_fdc_info);
2041 sysbus_register_withprop(&sysbus_fdc_info);
2042 sysbus_register_withprop(&sun4m_fdc_info);
2043 }
2044
2045 device_init(fdc_register_devices)