PPC: e500: msync is 440 only, e500 has real sync
[qemu.git] / hw / flash.h
1 /* NOR flash devices */
2
3 #include "memory.h"
4
5 typedef struct pflash_t pflash_t;
6
7 /* pflash_cfi01.c */
8 pflash_t *pflash_cfi01_register(target_phys_addr_t base,
9 DeviceState *qdev, const char *name,
10 target_phys_addr_t size,
11 BlockDriverState *bs,
12 uint32_t sector_len, int nb_blocs, int width,
13 uint16_t id0, uint16_t id1,
14 uint16_t id2, uint16_t id3, int be);
15
16 /* pflash_cfi02.c */
17 pflash_t *pflash_cfi02_register(target_phys_addr_t base,
18 DeviceState *qdev, const char *name,
19 target_phys_addr_t size,
20 BlockDriverState *bs, uint32_t sector_len,
21 int nb_blocs, int nb_mappings, int width,
22 uint16_t id0, uint16_t id1,
23 uint16_t id2, uint16_t id3,
24 uint16_t unlock_addr0, uint16_t unlock_addr1,
25 int be);
26
27 MemoryRegion *pflash_cfi01_get_memory(pflash_t *fl);
28
29 /* nand.c */
30 DeviceState *nand_init(BlockDriverState *bdrv, int manf_id, int chip_id);
31 void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale,
32 uint8_t ce, uint8_t wp, uint8_t gnd);
33 void nand_getpins(DeviceState *dev, int *rb);
34 void nand_setio(DeviceState *dev, uint32_t value);
35 uint32_t nand_getio(DeviceState *dev);
36 uint32_t nand_getbuswidth(DeviceState *dev);
37
38 #define NAND_MFR_TOSHIBA 0x98
39 #define NAND_MFR_SAMSUNG 0xec
40 #define NAND_MFR_FUJITSU 0x04
41 #define NAND_MFR_NATIONAL 0x8f
42 #define NAND_MFR_RENESAS 0x07
43 #define NAND_MFR_STMICRO 0x20
44 #define NAND_MFR_HYNIX 0xad
45 #define NAND_MFR_MICRON 0x2c
46
47 /* onenand.c */
48 void *onenand_raw_otp(DeviceState *onenand_device);
49
50 /* ecc.c */
51 typedef struct {
52 uint8_t cp; /* Column parity */
53 uint16_t lp[2]; /* Line parity */
54 uint16_t count;
55 } ECCState;
56
57 uint8_t ecc_digest(ECCState *s, uint8_t sample);
58 void ecc_reset(ECCState *s);
59 extern VMStateDescription vmstate_ecc_state;