Add access control support to qemu bridge helper
[qemu.git] / hw / g364fb.c
1 /*
2 * QEMU G364 framebuffer Emulator.
3 *
4 * Copyright (c) 2007-2011 Herve Poussineau
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "hw.h"
21 #include "console.h"
22 #include "pixel_ops.h"
23 #include "trace.h"
24 #include "sysbus.h"
25
26 typedef struct G364State {
27 /* hardware */
28 uint8_t *vram;
29 uint32_t vram_size;
30 qemu_irq irq;
31 MemoryRegion mem_vram;
32 MemoryRegion mem_ctrl;
33 /* registers */
34 uint8_t color_palette[256][3];
35 uint8_t cursor_palette[3][3];
36 uint16_t cursor[512];
37 uint32_t cursor_position;
38 uint32_t ctla;
39 uint32_t top_of_screen;
40 uint32_t width, height; /* in pixels */
41 /* display refresh support */
42 DisplayState *ds;
43 int depth;
44 int blanked;
45 } G364State;
46
47 #define REG_BOOT 0x000000
48 #define REG_DISPLAY 0x000118
49 #define REG_VDISPLAY 0x000150
50 #define REG_CTLA 0x000300
51 #define REG_TOP 0x000400
52 #define REG_CURS_PAL 0x000508
53 #define REG_CURS_POS 0x000638
54 #define REG_CLR_PAL 0x000800
55 #define REG_CURS_PAT 0x001000
56 #define REG_RESET 0x100000
57
58 #define CTLA_FORCE_BLANK 0x00000400
59 #define CTLA_NO_CURSOR 0x00800000
60
61 #define G364_PAGE_SIZE 4096
62
63 static inline int check_dirty(G364State *s, ram_addr_t page)
64 {
65 return memory_region_get_dirty(&s->mem_vram, page, DIRTY_MEMORY_VGA);
66 }
67
68 static inline void reset_dirty(G364State *s,
69 ram_addr_t page_min, ram_addr_t page_max)
70 {
71 memory_region_reset_dirty(&s->mem_vram,
72 page_min,
73 page_max + G364_PAGE_SIZE - page_min - 1,
74 DIRTY_MEMORY_VGA);
75 }
76
77 static void g364fb_draw_graphic8(G364State *s)
78 {
79 int i, w;
80 uint8_t *vram;
81 uint8_t *data_display, *dd;
82 ram_addr_t page, page_min, page_max;
83 int x, y;
84 int xmin, xmax;
85 int ymin, ymax;
86 int xcursor, ycursor;
87 unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned int b);
88
89 switch (ds_get_bits_per_pixel(s->ds)) {
90 case 8:
91 rgb_to_pixel = rgb_to_pixel8;
92 w = 1;
93 break;
94 case 15:
95 rgb_to_pixel = rgb_to_pixel15;
96 w = 2;
97 break;
98 case 16:
99 rgb_to_pixel = rgb_to_pixel16;
100 w = 2;
101 break;
102 case 32:
103 rgb_to_pixel = rgb_to_pixel32;
104 w = 4;
105 break;
106 default:
107 hw_error("g364: unknown host depth %d",
108 ds_get_bits_per_pixel(s->ds));
109 return;
110 }
111
112 page = 0;
113 page_min = (ram_addr_t)-1;
114 page_max = 0;
115
116 x = y = 0;
117 xmin = s->width;
118 xmax = 0;
119 ymin = s->height;
120 ymax = 0;
121
122 if (!(s->ctla & CTLA_NO_CURSOR)) {
123 xcursor = s->cursor_position >> 12;
124 ycursor = s->cursor_position & 0xfff;
125 } else {
126 xcursor = ycursor = -65;
127 }
128
129 vram = s->vram + s->top_of_screen;
130 /* XXX: out of range in vram? */
131 data_display = dd = ds_get_data(s->ds);
132 while (y < s->height) {
133 if (check_dirty(s, page)) {
134 if (y < ymin)
135 ymin = ymax = y;
136 if (page_min == (ram_addr_t)-1)
137 page_min = page;
138 page_max = page;
139 if (x < xmin)
140 xmin = x;
141 for (i = 0; i < G364_PAGE_SIZE; i++) {
142 uint8_t index;
143 unsigned int color;
144 if (unlikely((y >= ycursor && y < ycursor + 64) &&
145 (x >= xcursor && x < xcursor + 64))) {
146 /* pointer area */
147 int xdiff = x - xcursor;
148 uint16_t curs = s->cursor[(y - ycursor) * 8 + xdiff / 8];
149 int op = (curs >> ((xdiff & 7) * 2)) & 3;
150 if (likely(op == 0)) {
151 /* transparent */
152 index = *vram;
153 color = (*rgb_to_pixel)(
154 s->color_palette[index][0],
155 s->color_palette[index][1],
156 s->color_palette[index][2]);
157 } else {
158 /* get cursor color */
159 index = op - 1;
160 color = (*rgb_to_pixel)(
161 s->cursor_palette[index][0],
162 s->cursor_palette[index][1],
163 s->cursor_palette[index][2]);
164 }
165 } else {
166 /* normal area */
167 index = *vram;
168 color = (*rgb_to_pixel)(
169 s->color_palette[index][0],
170 s->color_palette[index][1],
171 s->color_palette[index][2]);
172 }
173 memcpy(dd, &color, w);
174 dd += w;
175 x++;
176 vram++;
177 if (x == s->width) {
178 xmax = s->width - 1;
179 y++;
180 if (y == s->height) {
181 ymax = s->height - 1;
182 goto done;
183 }
184 data_display = dd = data_display + ds_get_linesize(s->ds);
185 xmin = 0;
186 x = 0;
187 }
188 }
189 if (x > xmax)
190 xmax = x;
191 if (y > ymax)
192 ymax = y;
193 } else {
194 int dy;
195 if (page_min != (ram_addr_t)-1) {
196 reset_dirty(s, page_min, page_max);
197 page_min = (ram_addr_t)-1;
198 page_max = 0;
199 dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
200 xmin = s->width;
201 xmax = 0;
202 ymin = s->height;
203 ymax = 0;
204 }
205 x += G364_PAGE_SIZE;
206 dy = x / s->width;
207 x = x % s->width;
208 y += dy;
209 vram += G364_PAGE_SIZE;
210 data_display += dy * ds_get_linesize(s->ds);
211 dd = data_display + x * w;
212 }
213 page += G364_PAGE_SIZE;
214 }
215
216 done:
217 if (page_min != (ram_addr_t)-1) {
218 dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
219 reset_dirty(s, page_min, page_max);
220 }
221 }
222
223 static void g364fb_draw_blank(G364State *s)
224 {
225 int i, w;
226 uint8_t *d;
227
228 if (s->blanked) {
229 /* Screen is already blank. No need to redraw it */
230 return;
231 }
232
233 w = s->width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
234 d = ds_get_data(s->ds);
235 for (i = 0; i < s->height; i++) {
236 memset(d, 0, w);
237 d += ds_get_linesize(s->ds);
238 }
239
240 dpy_update(s->ds, 0, 0, s->width, s->height);
241 s->blanked = 1;
242 }
243
244 static void g364fb_update_display(void *opaque)
245 {
246 G364State *s = opaque;
247
248 qemu_flush_coalesced_mmio_buffer();
249
250 if (s->width == 0 || s->height == 0)
251 return;
252
253 if (s->width != ds_get_width(s->ds) || s->height != ds_get_height(s->ds)) {
254 qemu_console_resize(s->ds, s->width, s->height);
255 }
256
257 if (s->ctla & CTLA_FORCE_BLANK) {
258 g364fb_draw_blank(s);
259 } else if (s->depth == 8) {
260 g364fb_draw_graphic8(s);
261 } else {
262 error_report("g364: unknown guest depth %d", s->depth);
263 }
264
265 qemu_irq_raise(s->irq);
266 }
267
268 static inline void g364fb_invalidate_display(void *opaque)
269 {
270 G364State *s = opaque;
271
272 s->blanked = 0;
273 memory_region_set_dirty(&s->mem_vram, 0, s->vram_size);
274 }
275
276 static void g364fb_reset(G364State *s)
277 {
278 qemu_irq_lower(s->irq);
279
280 memset(s->color_palette, 0, sizeof(s->color_palette));
281 memset(s->cursor_palette, 0, sizeof(s->cursor_palette));
282 memset(s->cursor, 0, sizeof(s->cursor));
283 s->cursor_position = 0;
284 s->ctla = 0;
285 s->top_of_screen = 0;
286 s->width = s->height = 0;
287 memset(s->vram, 0, s->vram_size);
288 g364fb_invalidate_display(s);
289 }
290
291 static void g364fb_screen_dump(void *opaque, const char *filename)
292 {
293 G364State *s = opaque;
294 int y, x;
295 uint8_t index;
296 uint8_t *data_buffer;
297 FILE *f;
298
299 qemu_flush_coalesced_mmio_buffer();
300
301 if (s->depth != 8) {
302 error_report("g364: unknown guest depth %d", s->depth);
303 return;
304 }
305
306 f = fopen(filename, "wb");
307 if (!f)
308 return;
309
310 if (s->ctla & CTLA_FORCE_BLANK) {
311 /* blank screen */
312 fprintf(f, "P4\n%d %d\n",
313 s->width, s->height);
314 for (y = 0; y < s->height; y++)
315 for (x = 0; x < s->width; x++)
316 fputc(0, f);
317 } else {
318 data_buffer = s->vram + s->top_of_screen;
319 fprintf(f, "P6\n%d %d\n%d\n",
320 s->width, s->height, 255);
321 for (y = 0; y < s->height; y++)
322 for (x = 0; x < s->width; x++, data_buffer++) {
323 index = *data_buffer;
324 fputc(s->color_palette[index][0], f);
325 fputc(s->color_palette[index][1], f);
326 fputc(s->color_palette[index][2], f);
327 }
328 }
329
330 fclose(f);
331 }
332
333 /* called for accesses to io ports */
334 static uint64_t g364fb_ctrl_read(void *opaque,
335 target_phys_addr_t addr,
336 unsigned int size)
337 {
338 G364State *s = opaque;
339 uint32_t val;
340
341 if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) {
342 /* cursor pattern */
343 int idx = (addr - REG_CURS_PAT) >> 3;
344 val = s->cursor[idx];
345 } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) {
346 /* cursor palette */
347 int idx = (addr - REG_CURS_PAL) >> 3;
348 val = ((uint32_t)s->cursor_palette[idx][0] << 16);
349 val |= ((uint32_t)s->cursor_palette[idx][1] << 8);
350 val |= ((uint32_t)s->cursor_palette[idx][2] << 0);
351 } else {
352 switch (addr) {
353 case REG_DISPLAY:
354 val = s->width / 4;
355 break;
356 case REG_VDISPLAY:
357 val = s->height * 2;
358 break;
359 case REG_CTLA:
360 val = s->ctla;
361 break;
362 default:
363 {
364 error_report("g364: invalid read at [" TARGET_FMT_plx "]",
365 addr);
366 val = 0;
367 break;
368 }
369 }
370 }
371
372 trace_g364fb_read(addr, val);
373
374 return val;
375 }
376
377 static void g364fb_update_depth(G364State *s)
378 {
379 static const int depths[8] = { 1, 2, 4, 8, 15, 16, 0 };
380 s->depth = depths[(s->ctla & 0x00700000) >> 20];
381 }
382
383 static void g364_invalidate_cursor_position(G364State *s)
384 {
385 int ymin, ymax, start, end;
386
387 /* invalidate only near the cursor */
388 ymin = s->cursor_position & 0xfff;
389 ymax = MIN(s->height, ymin + 64);
390 start = ymin * ds_get_linesize(s->ds);
391 end = (ymax + 1) * ds_get_linesize(s->ds);
392
393 memory_region_set_dirty(&s->mem_vram, start, end - start);
394 }
395
396 static void g364fb_ctrl_write(void *opaque,
397 target_phys_addr_t addr,
398 uint64_t val,
399 unsigned int size)
400 {
401 G364State *s = opaque;
402
403 trace_g364fb_write(addr, val);
404
405 if (addr >= REG_CLR_PAL && addr < REG_CLR_PAL + 0x800) {
406 /* color palette */
407 int idx = (addr - REG_CLR_PAL) >> 3;
408 s->color_palette[idx][0] = (val >> 16) & 0xff;
409 s->color_palette[idx][1] = (val >> 8) & 0xff;
410 s->color_palette[idx][2] = val & 0xff;
411 g364fb_invalidate_display(s);
412 } else if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) {
413 /* cursor pattern */
414 int idx = (addr - REG_CURS_PAT) >> 3;
415 s->cursor[idx] = val;
416 g364fb_invalidate_display(s);
417 } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) {
418 /* cursor palette */
419 int idx = (addr - REG_CURS_PAL) >> 3;
420 s->cursor_palette[idx][0] = (val >> 16) & 0xff;
421 s->cursor_palette[idx][1] = (val >> 8) & 0xff;
422 s->cursor_palette[idx][2] = val & 0xff;
423 g364fb_invalidate_display(s);
424 } else {
425 switch (addr) {
426 case REG_BOOT: /* Boot timing */
427 case 0x00108: /* Line timing: half sync */
428 case 0x00110: /* Line timing: back porch */
429 case 0x00120: /* Line timing: short display */
430 case 0x00128: /* Frame timing: broad pulse */
431 case 0x00130: /* Frame timing: v sync */
432 case 0x00138: /* Frame timing: v preequalise */
433 case 0x00140: /* Frame timing: v postequalise */
434 case 0x00148: /* Frame timing: v blank */
435 case 0x00158: /* Line timing: line time */
436 case 0x00160: /* Frame store: line start */
437 case 0x00168: /* vram cycle: mem init */
438 case 0x00170: /* vram cycle: transfer delay */
439 case 0x00200: /* vram cycle: mask register */
440 /* ignore */
441 break;
442 case REG_TOP:
443 s->top_of_screen = val;
444 g364fb_invalidate_display(s);
445 break;
446 case REG_DISPLAY:
447 s->width = val * 4;
448 break;
449 case REG_VDISPLAY:
450 s->height = val / 2;
451 break;
452 case REG_CTLA:
453 s->ctla = val;
454 g364fb_update_depth(s);
455 g364fb_invalidate_display(s);
456 break;
457 case REG_CURS_POS:
458 g364_invalidate_cursor_position(s);
459 s->cursor_position = val;
460 g364_invalidate_cursor_position(s);
461 break;
462 case REG_RESET:
463 g364fb_reset(s);
464 break;
465 default:
466 error_report("g364: invalid write of 0x%" PRIx64
467 " at [" TARGET_FMT_plx "]", val, addr);
468 break;
469 }
470 }
471 qemu_irq_lower(s->irq);
472 }
473
474 static const MemoryRegionOps g364fb_ctrl_ops = {
475 .read = g364fb_ctrl_read,
476 .write = g364fb_ctrl_write,
477 .endianness = DEVICE_LITTLE_ENDIAN,
478 .impl.min_access_size = 4,
479 .impl.max_access_size = 4,
480 };
481
482 static int g364fb_post_load(void *opaque, int version_id)
483 {
484 G364State *s = opaque;
485
486 /* force refresh */
487 g364fb_update_depth(s);
488 g364fb_invalidate_display(s);
489
490 return 0;
491 }
492
493 static const VMStateDescription vmstate_g364fb = {
494 .name = "g364fb",
495 .version_id = 1,
496 .minimum_version_id = 1,
497 .minimum_version_id_old = 1,
498 .post_load = g364fb_post_load,
499 .fields = (VMStateField[]) {
500 VMSTATE_VBUFFER_UINT32(vram, G364State, 1, NULL, 0, vram_size),
501 VMSTATE_BUFFER_UNSAFE(color_palette, G364State, 0, 256 * 3),
502 VMSTATE_BUFFER_UNSAFE(cursor_palette, G364State, 0, 9),
503 VMSTATE_UINT16_ARRAY(cursor, G364State, 512),
504 VMSTATE_UINT32(cursor_position, G364State),
505 VMSTATE_UINT32(ctla, G364State),
506 VMSTATE_UINT32(top_of_screen, G364State),
507 VMSTATE_UINT32(width, G364State),
508 VMSTATE_UINT32(height, G364State),
509 VMSTATE_END_OF_LIST()
510 }
511 };
512
513 static void g364fb_init(DeviceState *dev, G364State *s)
514 {
515 s->vram = g_malloc0(s->vram_size);
516
517 s->ds = graphic_console_init(g364fb_update_display,
518 g364fb_invalidate_display,
519 g364fb_screen_dump, NULL, s);
520
521 memory_region_init_io(&s->mem_ctrl, &g364fb_ctrl_ops, s, "ctrl", 0x180000);
522 memory_region_init_ram_ptr(&s->mem_vram, "vram",
523 s->vram_size, s->vram);
524 vmstate_register_ram(&s->mem_vram, dev);
525 memory_region_set_coalescing(&s->mem_vram);
526 }
527
528 typedef struct {
529 SysBusDevice busdev;
530 G364State g364;
531 } G364SysBusState;
532
533 static int g364fb_sysbus_init(SysBusDevice *dev)
534 {
535 G364State *s = &FROM_SYSBUS(G364SysBusState, dev)->g364;
536
537 g364fb_init(&dev->qdev, s);
538 sysbus_init_irq(dev, &s->irq);
539 sysbus_init_mmio(dev, &s->mem_ctrl);
540 sysbus_init_mmio(dev, &s->mem_vram);
541
542 return 0;
543 }
544
545 static void g364fb_sysbus_reset(DeviceState *d)
546 {
547 G364SysBusState *s = DO_UPCAST(G364SysBusState, busdev.qdev, d);
548 g364fb_reset(&s->g364);
549 }
550
551 static Property g364fb_sysbus_properties[] = {
552 DEFINE_PROP_HEX32("vram_size", G364SysBusState, g364.vram_size,
553 8 * 1024 * 1024),
554 DEFINE_PROP_END_OF_LIST(),
555 };
556
557 static void g364fb_sysbus_class_init(ObjectClass *klass, void *data)
558 {
559 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
560
561 k->init = g364fb_sysbus_init;
562 }
563
564 static DeviceInfo g364fb_sysbus_info = {
565 .name = "sysbus-g364",
566 .desc = "G364 framebuffer",
567 .size = sizeof(G364SysBusState),
568 .vmsd = &vmstate_g364fb,
569 .reset = g364fb_sysbus_reset,
570 .props = g364fb_sysbus_properties,
571 .class_init = g364fb_sysbus_class_init,
572 };
573
574 static void g364fb_register(void)
575 {
576 sysbus_register_withprop(&g364fb_sysbus_info);
577 }
578
579 device_init(g364fb_register);