meson: convert hw/vfio
[qemu.git] / hw / gpio / omap_gpio.c
1 /*
2 * TI OMAP processors GPIO emulation.
3 *
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
5 * Copyright (C) 2007-2009 Nokia Corporation
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "hw/irq.h"
23 #include "hw/qdev-properties.h"
24 #include "hw/arm/omap.h"
25 #include "hw/sysbus.h"
26 #include "qemu/error-report.h"
27 #include "qemu/module.h"
28 #include "qapi/error.h"
29
30 struct omap_gpio_s {
31 qemu_irq irq;
32 qemu_irq handler[16];
33
34 uint16_t inputs;
35 uint16_t outputs;
36 uint16_t dir;
37 uint16_t edge;
38 uint16_t mask;
39 uint16_t ints;
40 uint16_t pins;
41 };
42
43 struct omap_gpif_s {
44 SysBusDevice parent_obj;
45
46 MemoryRegion iomem;
47 int mpu_model;
48 void *clk;
49 struct omap_gpio_s omap1;
50 };
51
52 /* General-Purpose I/O of OMAP1 */
53 static void omap_gpio_set(void *opaque, int line, int level)
54 {
55 struct omap_gpio_s *s = &((struct omap_gpif_s *) opaque)->omap1;
56 uint16_t prev = s->inputs;
57
58 if (level)
59 s->inputs |= 1 << line;
60 else
61 s->inputs &= ~(1 << line);
62
63 if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) &
64 (1 << line) & s->dir & ~s->mask) {
65 s->ints |= 1 << line;
66 qemu_irq_raise(s->irq);
67 }
68 }
69
70 static uint64_t omap_gpio_read(void *opaque, hwaddr addr,
71 unsigned size)
72 {
73 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
74 int offset = addr & OMAP_MPUI_REG_MASK;
75
76 if (size != 2) {
77 return omap_badwidth_read16(opaque, addr);
78 }
79
80 switch (offset) {
81 case 0x00: /* DATA_INPUT */
82 return s->inputs & s->pins;
83
84 case 0x04: /* DATA_OUTPUT */
85 return s->outputs;
86
87 case 0x08: /* DIRECTION_CONTROL */
88 return s->dir;
89
90 case 0x0c: /* INTERRUPT_CONTROL */
91 return s->edge;
92
93 case 0x10: /* INTERRUPT_MASK */
94 return s->mask;
95
96 case 0x14: /* INTERRUPT_STATUS */
97 return s->ints;
98
99 case 0x18: /* PIN_CONTROL (not in OMAP310) */
100 OMAP_BAD_REG(addr);
101 return s->pins;
102 }
103
104 OMAP_BAD_REG(addr);
105 return 0;
106 }
107
108 static void omap_gpio_write(void *opaque, hwaddr addr,
109 uint64_t value, unsigned size)
110 {
111 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
112 int offset = addr & OMAP_MPUI_REG_MASK;
113 uint16_t diff;
114 int ln;
115
116 if (size != 2) {
117 omap_badwidth_write16(opaque, addr, value);
118 return;
119 }
120
121 switch (offset) {
122 case 0x00: /* DATA_INPUT */
123 OMAP_RO_REG(addr);
124 return;
125
126 case 0x04: /* DATA_OUTPUT */
127 diff = (s->outputs ^ value) & ~s->dir;
128 s->outputs = value;
129 while ((ln = ctz32(diff)) != 32) {
130 if (s->handler[ln])
131 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
132 diff &= ~(1 << ln);
133 }
134 break;
135
136 case 0x08: /* DIRECTION_CONTROL */
137 diff = s->outputs & (s->dir ^ value);
138 s->dir = value;
139
140 value = s->outputs & ~s->dir;
141 while ((ln = ctz32(diff)) != 32) {
142 if (s->handler[ln])
143 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
144 diff &= ~(1 << ln);
145 }
146 break;
147
148 case 0x0c: /* INTERRUPT_CONTROL */
149 s->edge = value;
150 break;
151
152 case 0x10: /* INTERRUPT_MASK */
153 s->mask = value;
154 break;
155
156 case 0x14: /* INTERRUPT_STATUS */
157 s->ints &= ~value;
158 if (!s->ints)
159 qemu_irq_lower(s->irq);
160 break;
161
162 case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */
163 OMAP_BAD_REG(addr);
164 s->pins = value;
165 break;
166
167 default:
168 OMAP_BAD_REG(addr);
169 return;
170 }
171 }
172
173 /* *Some* sources say the memory region is 32-bit. */
174 static const MemoryRegionOps omap_gpio_ops = {
175 .read = omap_gpio_read,
176 .write = omap_gpio_write,
177 .endianness = DEVICE_NATIVE_ENDIAN,
178 };
179
180 static void omap_gpio_reset(struct omap_gpio_s *s)
181 {
182 s->inputs = 0;
183 s->outputs = ~0;
184 s->dir = ~0;
185 s->edge = ~0;
186 s->mask = ~0;
187 s->ints = 0;
188 s->pins = ~0;
189 }
190
191 struct omap2_gpio_s {
192 qemu_irq irq[2];
193 qemu_irq wkup;
194 qemu_irq *handler;
195 MemoryRegion iomem;
196
197 uint8_t revision;
198 uint8_t config[2];
199 uint32_t inputs;
200 uint32_t outputs;
201 uint32_t dir;
202 uint32_t level[2];
203 uint32_t edge[2];
204 uint32_t mask[2];
205 uint32_t wumask;
206 uint32_t ints[2];
207 uint32_t debounce;
208 uint8_t delay;
209 };
210
211 struct omap2_gpif_s {
212 SysBusDevice parent_obj;
213
214 MemoryRegion iomem;
215 int mpu_model;
216 void *iclk;
217 void *fclk[6];
218 int modulecount;
219 struct omap2_gpio_s *modules;
220 qemu_irq *handler;
221 int autoidle;
222 int gpo;
223 };
224
225 /* General-Purpose Interface of OMAP2/3 */
226 static inline void omap2_gpio_module_int_update(struct omap2_gpio_s *s,
227 int line)
228 {
229 qemu_set_irq(s->irq[line], s->ints[line] & s->mask[line]);
230 }
231
232 static void omap2_gpio_module_wake(struct omap2_gpio_s *s, int line)
233 {
234 if (!(s->config[0] & (1 << 2))) /* ENAWAKEUP */
235 return;
236 if (!(s->config[0] & (3 << 3))) /* Force Idle */
237 return;
238 if (!(s->wumask & (1 << line)))
239 return;
240
241 qemu_irq_raise(s->wkup);
242 }
243
244 static inline void omap2_gpio_module_out_update(struct omap2_gpio_s *s,
245 uint32_t diff)
246 {
247 int ln;
248
249 s->outputs ^= diff;
250 diff &= ~s->dir;
251 while ((ln = ctz32(diff)) != 32) {
252 qemu_set_irq(s->handler[ln], (s->outputs >> ln) & 1);
253 diff &= ~(1 << ln);
254 }
255 }
256
257 static void omap2_gpio_module_level_update(struct omap2_gpio_s *s, int line)
258 {
259 s->ints[line] |= s->dir &
260 ((s->inputs & s->level[1]) | (~s->inputs & s->level[0]));
261 omap2_gpio_module_int_update(s, line);
262 }
263
264 static inline void omap2_gpio_module_int(struct omap2_gpio_s *s, int line)
265 {
266 s->ints[0] |= 1 << line;
267 omap2_gpio_module_int_update(s, 0);
268 s->ints[1] |= 1 << line;
269 omap2_gpio_module_int_update(s, 1);
270 omap2_gpio_module_wake(s, line);
271 }
272
273 static void omap2_gpio_set(void *opaque, int line, int level)
274 {
275 struct omap2_gpif_s *p = opaque;
276 struct omap2_gpio_s *s = &p->modules[line >> 5];
277
278 line &= 31;
279 if (level) {
280 if (s->dir & (1 << line) & ((~s->inputs & s->edge[0]) | s->level[1]))
281 omap2_gpio_module_int(s, line);
282 s->inputs |= 1 << line;
283 } else {
284 if (s->dir & (1 << line) & ((s->inputs & s->edge[1]) | s->level[0]))
285 omap2_gpio_module_int(s, line);
286 s->inputs &= ~(1 << line);
287 }
288 }
289
290 static void omap2_gpio_module_reset(struct omap2_gpio_s *s)
291 {
292 s->config[0] = 0;
293 s->config[1] = 2;
294 s->ints[0] = 0;
295 s->ints[1] = 0;
296 s->mask[0] = 0;
297 s->mask[1] = 0;
298 s->wumask = 0;
299 s->dir = ~0;
300 s->level[0] = 0;
301 s->level[1] = 0;
302 s->edge[0] = 0;
303 s->edge[1] = 0;
304 s->debounce = 0;
305 s->delay = 0;
306 }
307
308 static uint32_t omap2_gpio_module_read(void *opaque, hwaddr addr)
309 {
310 struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
311
312 switch (addr) {
313 case 0x00: /* GPIO_REVISION */
314 return s->revision;
315
316 case 0x10: /* GPIO_SYSCONFIG */
317 return s->config[0];
318
319 case 0x14: /* GPIO_SYSSTATUS */
320 return 0x01;
321
322 case 0x18: /* GPIO_IRQSTATUS1 */
323 return s->ints[0];
324
325 case 0x1c: /* GPIO_IRQENABLE1 */
326 case 0x60: /* GPIO_CLEARIRQENABLE1 */
327 case 0x64: /* GPIO_SETIRQENABLE1 */
328 return s->mask[0];
329
330 case 0x20: /* GPIO_WAKEUPENABLE */
331 case 0x80: /* GPIO_CLEARWKUENA */
332 case 0x84: /* GPIO_SETWKUENA */
333 return s->wumask;
334
335 case 0x28: /* GPIO_IRQSTATUS2 */
336 return s->ints[1];
337
338 case 0x2c: /* GPIO_IRQENABLE2 */
339 case 0x70: /* GPIO_CLEARIRQENABLE2 */
340 case 0x74: /* GPIO_SETIREQNEABLE2 */
341 return s->mask[1];
342
343 case 0x30: /* GPIO_CTRL */
344 return s->config[1];
345
346 case 0x34: /* GPIO_OE */
347 return s->dir;
348
349 case 0x38: /* GPIO_DATAIN */
350 return s->inputs;
351
352 case 0x3c: /* GPIO_DATAOUT */
353 case 0x90: /* GPIO_CLEARDATAOUT */
354 case 0x94: /* GPIO_SETDATAOUT */
355 return s->outputs;
356
357 case 0x40: /* GPIO_LEVELDETECT0 */
358 return s->level[0];
359
360 case 0x44: /* GPIO_LEVELDETECT1 */
361 return s->level[1];
362
363 case 0x48: /* GPIO_RISINGDETECT */
364 return s->edge[0];
365
366 case 0x4c: /* GPIO_FALLINGDETECT */
367 return s->edge[1];
368
369 case 0x50: /* GPIO_DEBOUNCENABLE */
370 return s->debounce;
371
372 case 0x54: /* GPIO_DEBOUNCINGTIME */
373 return s->delay;
374 }
375
376 OMAP_BAD_REG(addr);
377 return 0;
378 }
379
380 static void omap2_gpio_module_write(void *opaque, hwaddr addr,
381 uint32_t value)
382 {
383 struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
384 uint32_t diff;
385 int ln;
386
387 switch (addr) {
388 case 0x00: /* GPIO_REVISION */
389 case 0x14: /* GPIO_SYSSTATUS */
390 case 0x38: /* GPIO_DATAIN */
391 OMAP_RO_REG(addr);
392 break;
393
394 case 0x10: /* GPIO_SYSCONFIG */
395 if (((value >> 3) & 3) == 3)
396 fprintf(stderr, "%s: bad IDLEMODE value\n", __func__);
397 if (value & 2)
398 omap2_gpio_module_reset(s);
399 s->config[0] = value & 0x1d;
400 break;
401
402 case 0x18: /* GPIO_IRQSTATUS1 */
403 if (s->ints[0] & value) {
404 s->ints[0] &= ~value;
405 omap2_gpio_module_level_update(s, 0);
406 }
407 break;
408
409 case 0x1c: /* GPIO_IRQENABLE1 */
410 s->mask[0] = value;
411 omap2_gpio_module_int_update(s, 0);
412 break;
413
414 case 0x20: /* GPIO_WAKEUPENABLE */
415 s->wumask = value;
416 break;
417
418 case 0x28: /* GPIO_IRQSTATUS2 */
419 if (s->ints[1] & value) {
420 s->ints[1] &= ~value;
421 omap2_gpio_module_level_update(s, 1);
422 }
423 break;
424
425 case 0x2c: /* GPIO_IRQENABLE2 */
426 s->mask[1] = value;
427 omap2_gpio_module_int_update(s, 1);
428 break;
429
430 case 0x30: /* GPIO_CTRL */
431 s->config[1] = value & 7;
432 break;
433
434 case 0x34: /* GPIO_OE */
435 diff = s->outputs & (s->dir ^ value);
436 s->dir = value;
437
438 value = s->outputs & ~s->dir;
439 while ((ln = ctz32(diff)) != 32) {
440 diff &= ~(1 << ln);
441 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
442 }
443
444 omap2_gpio_module_level_update(s, 0);
445 omap2_gpio_module_level_update(s, 1);
446 break;
447
448 case 0x3c: /* GPIO_DATAOUT */
449 omap2_gpio_module_out_update(s, s->outputs ^ value);
450 break;
451
452 case 0x40: /* GPIO_LEVELDETECT0 */
453 s->level[0] = value;
454 omap2_gpio_module_level_update(s, 0);
455 omap2_gpio_module_level_update(s, 1);
456 break;
457
458 case 0x44: /* GPIO_LEVELDETECT1 */
459 s->level[1] = value;
460 omap2_gpio_module_level_update(s, 0);
461 omap2_gpio_module_level_update(s, 1);
462 break;
463
464 case 0x48: /* GPIO_RISINGDETECT */
465 s->edge[0] = value;
466 break;
467
468 case 0x4c: /* GPIO_FALLINGDETECT */
469 s->edge[1] = value;
470 break;
471
472 case 0x50: /* GPIO_DEBOUNCENABLE */
473 s->debounce = value;
474 break;
475
476 case 0x54: /* GPIO_DEBOUNCINGTIME */
477 s->delay = value;
478 break;
479
480 case 0x60: /* GPIO_CLEARIRQENABLE1 */
481 s->mask[0] &= ~value;
482 omap2_gpio_module_int_update(s, 0);
483 break;
484
485 case 0x64: /* GPIO_SETIRQENABLE1 */
486 s->mask[0] |= value;
487 omap2_gpio_module_int_update(s, 0);
488 break;
489
490 case 0x70: /* GPIO_CLEARIRQENABLE2 */
491 s->mask[1] &= ~value;
492 omap2_gpio_module_int_update(s, 1);
493 break;
494
495 case 0x74: /* GPIO_SETIREQNEABLE2 */
496 s->mask[1] |= value;
497 omap2_gpio_module_int_update(s, 1);
498 break;
499
500 case 0x80: /* GPIO_CLEARWKUENA */
501 s->wumask &= ~value;
502 break;
503
504 case 0x84: /* GPIO_SETWKUENA */
505 s->wumask |= value;
506 break;
507
508 case 0x90: /* GPIO_CLEARDATAOUT */
509 omap2_gpio_module_out_update(s, s->outputs & value);
510 break;
511
512 case 0x94: /* GPIO_SETDATAOUT */
513 omap2_gpio_module_out_update(s, ~s->outputs & value);
514 break;
515
516 default:
517 OMAP_BAD_REG(addr);
518 return;
519 }
520 }
521
522 static uint64_t omap2_gpio_module_readp(void *opaque, hwaddr addr,
523 unsigned size)
524 {
525 return omap2_gpio_module_read(opaque, addr & ~3) >> ((addr & 3) << 3);
526 }
527
528 static void omap2_gpio_module_writep(void *opaque, hwaddr addr,
529 uint64_t value, unsigned size)
530 {
531 uint32_t cur = 0;
532 uint32_t mask = 0xffff;
533
534 if (size == 4) {
535 omap2_gpio_module_write(opaque, addr, value);
536 return;
537 }
538
539 switch (addr & ~3) {
540 case 0x00: /* GPIO_REVISION */
541 case 0x14: /* GPIO_SYSSTATUS */
542 case 0x38: /* GPIO_DATAIN */
543 OMAP_RO_REG(addr);
544 break;
545
546 case 0x10: /* GPIO_SYSCONFIG */
547 case 0x1c: /* GPIO_IRQENABLE1 */
548 case 0x20: /* GPIO_WAKEUPENABLE */
549 case 0x2c: /* GPIO_IRQENABLE2 */
550 case 0x30: /* GPIO_CTRL */
551 case 0x34: /* GPIO_OE */
552 case 0x3c: /* GPIO_DATAOUT */
553 case 0x40: /* GPIO_LEVELDETECT0 */
554 case 0x44: /* GPIO_LEVELDETECT1 */
555 case 0x48: /* GPIO_RISINGDETECT */
556 case 0x4c: /* GPIO_FALLINGDETECT */
557 case 0x50: /* GPIO_DEBOUNCENABLE */
558 case 0x54: /* GPIO_DEBOUNCINGTIME */
559 cur = omap2_gpio_module_read(opaque, addr & ~3) &
560 ~(mask << ((addr & 3) << 3));
561
562 /* Fall through. */
563 case 0x18: /* GPIO_IRQSTATUS1 */
564 case 0x28: /* GPIO_IRQSTATUS2 */
565 case 0x60: /* GPIO_CLEARIRQENABLE1 */
566 case 0x64: /* GPIO_SETIRQENABLE1 */
567 case 0x70: /* GPIO_CLEARIRQENABLE2 */
568 case 0x74: /* GPIO_SETIREQNEABLE2 */
569 case 0x80: /* GPIO_CLEARWKUENA */
570 case 0x84: /* GPIO_SETWKUENA */
571 case 0x90: /* GPIO_CLEARDATAOUT */
572 case 0x94: /* GPIO_SETDATAOUT */
573 value <<= (addr & 3) << 3;
574 omap2_gpio_module_write(opaque, addr, cur | value);
575 break;
576
577 default:
578 OMAP_BAD_REG(addr);
579 return;
580 }
581 }
582
583 static const MemoryRegionOps omap2_gpio_module_ops = {
584 .read = omap2_gpio_module_readp,
585 .write = omap2_gpio_module_writep,
586 .valid.min_access_size = 1,
587 .valid.max_access_size = 4,
588 .endianness = DEVICE_NATIVE_ENDIAN,
589 };
590
591 static void omap_gpif_reset(DeviceState *dev)
592 {
593 struct omap_gpif_s *s = OMAP1_GPIO(dev);
594
595 omap_gpio_reset(&s->omap1);
596 }
597
598 static void omap2_gpif_reset(DeviceState *dev)
599 {
600 struct omap2_gpif_s *s = OMAP2_GPIO(dev);
601 int i;
602
603 for (i = 0; i < s->modulecount; i++) {
604 omap2_gpio_module_reset(&s->modules[i]);
605 }
606 s->autoidle = 0;
607 s->gpo = 0;
608 }
609
610 static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr,
611 unsigned size)
612 {
613 struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
614
615 switch (addr) {
616 case 0x00: /* IPGENERICOCPSPL_REVISION */
617 return 0x18;
618
619 case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */
620 return s->autoidle;
621
622 case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */
623 return 0x01;
624
625 case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */
626 return 0x00;
627
628 case 0x40: /* IPGENERICOCPSPL_GPO */
629 return s->gpo;
630
631 case 0x50: /* IPGENERICOCPSPL_GPI */
632 return 0x00;
633 }
634
635 OMAP_BAD_REG(addr);
636 return 0;
637 }
638
639 static void omap2_gpif_top_write(void *opaque, hwaddr addr,
640 uint64_t value, unsigned size)
641 {
642 struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
643
644 switch (addr) {
645 case 0x00: /* IPGENERICOCPSPL_REVISION */
646 case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */
647 case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */
648 case 0x50: /* IPGENERICOCPSPL_GPI */
649 OMAP_RO_REG(addr);
650 break;
651
652 case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */
653 if (value & (1 << 1)) /* SOFTRESET */
654 omap2_gpif_reset(DEVICE(s));
655 s->autoidle = value & 1;
656 break;
657
658 case 0x40: /* IPGENERICOCPSPL_GPO */
659 s->gpo = value & 1;
660 break;
661
662 default:
663 OMAP_BAD_REG(addr);
664 return;
665 }
666 }
667
668 static const MemoryRegionOps omap2_gpif_top_ops = {
669 .read = omap2_gpif_top_read,
670 .write = omap2_gpif_top_write,
671 .endianness = DEVICE_NATIVE_ENDIAN,
672 };
673
674 static void omap_gpio_init(Object *obj)
675 {
676 DeviceState *dev = DEVICE(obj);
677 struct omap_gpif_s *s = OMAP1_GPIO(obj);
678 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
679
680 qdev_init_gpio_in(dev, omap_gpio_set, 16);
681 qdev_init_gpio_out(dev, s->omap1.handler, 16);
682 sysbus_init_irq(sbd, &s->omap1.irq);
683 memory_region_init_io(&s->iomem, obj, &omap_gpio_ops, &s->omap1,
684 "omap.gpio", 0x1000);
685 sysbus_init_mmio(sbd, &s->iomem);
686 }
687
688 static void omap_gpio_realize(DeviceState *dev, Error **errp)
689 {
690 struct omap_gpif_s *s = OMAP1_GPIO(dev);
691
692 if (!s->clk) {
693 error_setg(errp, "omap-gpio: clk not connected");
694 }
695 }
696
697 static void omap2_gpio_realize(DeviceState *dev, Error **errp)
698 {
699 struct omap2_gpif_s *s = OMAP2_GPIO(dev);
700 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
701 int i;
702
703 if (!s->iclk) {
704 error_setg(errp, "omap2-gpio: iclk not connected");
705 return;
706 }
707
708 s->modulecount = s->mpu_model < omap2430 ? 4
709 : s->mpu_model < omap3430 ? 5
710 : 6;
711
712 if (s->mpu_model < omap3430) {
713 memory_region_init_io(&s->iomem, OBJECT(dev), &omap2_gpif_top_ops, s,
714 "omap2.gpio", 0x1000);
715 sysbus_init_mmio(sbd, &s->iomem);
716 }
717
718 s->modules = g_new0(struct omap2_gpio_s, s->modulecount);
719 s->handler = g_new0(qemu_irq, s->modulecount * 32);
720 qdev_init_gpio_in(dev, omap2_gpio_set, s->modulecount * 32);
721 qdev_init_gpio_out(dev, s->handler, s->modulecount * 32);
722
723 for (i = 0; i < s->modulecount; i++) {
724 struct omap2_gpio_s *m = &s->modules[i];
725
726 if (!s->fclk[i]) {
727 error_setg(errp, "omap2-gpio: fclk%d not connected", i);
728 return;
729 }
730
731 m->revision = (s->mpu_model < omap3430) ? 0x18 : 0x25;
732 m->handler = &s->handler[i * 32];
733 sysbus_init_irq(sbd, &m->irq[0]); /* mpu irq */
734 sysbus_init_irq(sbd, &m->irq[1]); /* dsp irq */
735 sysbus_init_irq(sbd, &m->wkup);
736 memory_region_init_io(&m->iomem, OBJECT(dev), &omap2_gpio_module_ops, m,
737 "omap.gpio-module", 0x1000);
738 sysbus_init_mmio(sbd, &m->iomem);
739 }
740 }
741
742 void omap_gpio_set_clk(omap_gpif *gpio, omap_clk clk)
743 {
744 gpio->clk = clk;
745 }
746
747 static Property omap_gpio_properties[] = {
748 DEFINE_PROP_INT32("mpu_model", struct omap_gpif_s, mpu_model, 0),
749 DEFINE_PROP_END_OF_LIST(),
750 };
751
752 static void omap_gpio_class_init(ObjectClass *klass, void *data)
753 {
754 DeviceClass *dc = DEVICE_CLASS(klass);
755
756 dc->realize = omap_gpio_realize;
757 dc->reset = omap_gpif_reset;
758 device_class_set_props(dc, omap_gpio_properties);
759 /* Reason: pointer property "clk" */
760 dc->user_creatable = false;
761 }
762
763 static const TypeInfo omap_gpio_info = {
764 .name = TYPE_OMAP1_GPIO,
765 .parent = TYPE_SYS_BUS_DEVICE,
766 .instance_size = sizeof(struct omap_gpif_s),
767 .instance_init = omap_gpio_init,
768 .class_init = omap_gpio_class_init,
769 };
770
771 void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk)
772 {
773 gpio->iclk = clk;
774 }
775
776 void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk)
777 {
778 assert(i <= 5);
779 gpio->fclk[i] = clk;
780 }
781
782 static Property omap2_gpio_properties[] = {
783 DEFINE_PROP_INT32("mpu_model", struct omap2_gpif_s, mpu_model, 0),
784 DEFINE_PROP_END_OF_LIST(),
785 };
786
787 static void omap2_gpio_class_init(ObjectClass *klass, void *data)
788 {
789 DeviceClass *dc = DEVICE_CLASS(klass);
790
791 dc->realize = omap2_gpio_realize;
792 dc->reset = omap2_gpif_reset;
793 device_class_set_props(dc, omap2_gpio_properties);
794 /* Reason: pointer properties "iclk", "fclk0", ..., "fclk5" */
795 dc->user_creatable = false;
796 }
797
798 static const TypeInfo omap2_gpio_info = {
799 .name = TYPE_OMAP2_GPIO,
800 .parent = TYPE_SYS_BUS_DEVICE,
801 .instance_size = sizeof(struct omap2_gpif_s),
802 .class_init = omap2_gpio_class_init,
803 };
804
805 static void omap_gpio_register_types(void)
806 {
807 type_register_static(&omap_gpio_info);
808 type_register_static(&omap2_gpio_info);
809 }
810
811 type_init(omap_gpio_register_types)