meson: convert hw/vfio
[qemu.git] / hw / gpio / pl061.c
1 /*
2 * Arm PrimeCell PL061 General Purpose IO with additional
3 * Luminary Micro Stellaris bits.
4 *
5 * Copyright (c) 2007 CodeSourcery.
6 * Written by Paul Brook
7 *
8 * This code is licensed under the GPL.
9 */
10
11 #include "qemu/osdep.h"
12 #include "hw/irq.h"
13 #include "hw/sysbus.h"
14 #include "migration/vmstate.h"
15 #include "qemu/log.h"
16 #include "qemu/module.h"
17
18 //#define DEBUG_PL061 1
19
20 #ifdef DEBUG_PL061
21 #define DPRINTF(fmt, ...) \
22 do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0)
23 #define BADF(fmt, ...) \
24 do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
25 #else
26 #define DPRINTF(fmt, ...) do {} while(0)
27 #define BADF(fmt, ...) \
28 do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0)
29 #endif
30
31 static const uint8_t pl061_id[12] =
32 { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
33 static const uint8_t pl061_id_luminary[12] =
34 { 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };
35
36 #define TYPE_PL061 "pl061"
37 #define PL061(obj) OBJECT_CHECK(PL061State, (obj), TYPE_PL061)
38
39 #define N_GPIOS 8
40
41 typedef struct PL061State {
42 SysBusDevice parent_obj;
43
44 MemoryRegion iomem;
45 uint32_t locked;
46 uint32_t data;
47 uint32_t old_out_data;
48 uint32_t old_in_data;
49 uint32_t dir;
50 uint32_t isense;
51 uint32_t ibe;
52 uint32_t iev;
53 uint32_t im;
54 uint32_t istate;
55 uint32_t afsel;
56 uint32_t dr2r;
57 uint32_t dr4r;
58 uint32_t dr8r;
59 uint32_t odr;
60 uint32_t pur;
61 uint32_t pdr;
62 uint32_t slr;
63 uint32_t den;
64 uint32_t cr;
65 uint32_t amsel;
66 qemu_irq irq;
67 qemu_irq out[N_GPIOS];
68 const unsigned char *id;
69 uint32_t rsvd_start; /* reserved area: [rsvd_start, 0xfcc] */
70 } PL061State;
71
72 static const VMStateDescription vmstate_pl061 = {
73 .name = "pl061",
74 .version_id = 4,
75 .minimum_version_id = 4,
76 .fields = (VMStateField[]) {
77 VMSTATE_UINT32(locked, PL061State),
78 VMSTATE_UINT32(data, PL061State),
79 VMSTATE_UINT32(old_out_data, PL061State),
80 VMSTATE_UINT32(old_in_data, PL061State),
81 VMSTATE_UINT32(dir, PL061State),
82 VMSTATE_UINT32(isense, PL061State),
83 VMSTATE_UINT32(ibe, PL061State),
84 VMSTATE_UINT32(iev, PL061State),
85 VMSTATE_UINT32(im, PL061State),
86 VMSTATE_UINT32(istate, PL061State),
87 VMSTATE_UINT32(afsel, PL061State),
88 VMSTATE_UINT32(dr2r, PL061State),
89 VMSTATE_UINT32(dr4r, PL061State),
90 VMSTATE_UINT32(dr8r, PL061State),
91 VMSTATE_UINT32(odr, PL061State),
92 VMSTATE_UINT32(pur, PL061State),
93 VMSTATE_UINT32(pdr, PL061State),
94 VMSTATE_UINT32(slr, PL061State),
95 VMSTATE_UINT32(den, PL061State),
96 VMSTATE_UINT32(cr, PL061State),
97 VMSTATE_UINT32_V(amsel, PL061State, 2),
98 VMSTATE_END_OF_LIST()
99 }
100 };
101
102 static void pl061_update(PL061State *s)
103 {
104 uint8_t changed;
105 uint8_t mask;
106 uint8_t out;
107 int i;
108
109 DPRINTF("dir = %d, data = %d\n", s->dir, s->data);
110
111 /* Outputs float high. */
112 /* FIXME: This is board dependent. */
113 out = (s->data & s->dir) | ~s->dir;
114 changed = s->old_out_data ^ out;
115 if (changed) {
116 s->old_out_data = out;
117 for (i = 0; i < N_GPIOS; i++) {
118 mask = 1 << i;
119 if (changed & mask) {
120 DPRINTF("Set output %d = %d\n", i, (out & mask) != 0);
121 qemu_set_irq(s->out[i], (out & mask) != 0);
122 }
123 }
124 }
125
126 /* Inputs */
127 changed = (s->old_in_data ^ s->data) & ~s->dir;
128 if (changed) {
129 s->old_in_data = s->data;
130 for (i = 0; i < N_GPIOS; i++) {
131 mask = 1 << i;
132 if (changed & mask) {
133 DPRINTF("Changed input %d = %d\n", i, (s->data & mask) != 0);
134
135 if (!(s->isense & mask)) {
136 /* Edge interrupt */
137 if (s->ibe & mask) {
138 /* Any edge triggers the interrupt */
139 s->istate |= mask;
140 } else {
141 /* Edge is selected by IEV */
142 s->istate |= ~(s->data ^ s->iev) & mask;
143 }
144 }
145 }
146 }
147 }
148
149 /* Level interrupt */
150 s->istate |= ~(s->data ^ s->iev) & s->isense;
151
152 DPRINTF("istate = %02X\n", s->istate);
153
154 qemu_set_irq(s->irq, (s->istate & s->im) != 0);
155 }
156
157 static uint64_t pl061_read(void *opaque, hwaddr offset,
158 unsigned size)
159 {
160 PL061State *s = (PL061State *)opaque;
161
162 if (offset < 0x400) {
163 return s->data & (offset >> 2);
164 }
165 if (offset >= s->rsvd_start && offset <= 0xfcc) {
166 goto err_out;
167 }
168 if (offset >= 0xfd0 && offset < 0x1000) {
169 return s->id[(offset - 0xfd0) >> 2];
170 }
171 switch (offset) {
172 case 0x400: /* Direction */
173 return s->dir;
174 case 0x404: /* Interrupt sense */
175 return s->isense;
176 case 0x408: /* Interrupt both edges */
177 return s->ibe;
178 case 0x40c: /* Interrupt event */
179 return s->iev;
180 case 0x410: /* Interrupt mask */
181 return s->im;
182 case 0x414: /* Raw interrupt status */
183 return s->istate;
184 case 0x418: /* Masked interrupt status */
185 return s->istate & s->im;
186 case 0x420: /* Alternate function select */
187 return s->afsel;
188 case 0x500: /* 2mA drive */
189 return s->dr2r;
190 case 0x504: /* 4mA drive */
191 return s->dr4r;
192 case 0x508: /* 8mA drive */
193 return s->dr8r;
194 case 0x50c: /* Open drain */
195 return s->odr;
196 case 0x510: /* Pull-up */
197 return s->pur;
198 case 0x514: /* Pull-down */
199 return s->pdr;
200 case 0x518: /* Slew rate control */
201 return s->slr;
202 case 0x51c: /* Digital enable */
203 return s->den;
204 case 0x520: /* Lock */
205 return s->locked;
206 case 0x524: /* Commit */
207 return s->cr;
208 case 0x528: /* Analog mode select */
209 return s->amsel;
210 default:
211 break;
212 }
213 err_out:
214 qemu_log_mask(LOG_GUEST_ERROR,
215 "pl061_read: Bad offset %x\n", (int)offset);
216 return 0;
217 }
218
219 static void pl061_write(void *opaque, hwaddr offset,
220 uint64_t value, unsigned size)
221 {
222 PL061State *s = (PL061State *)opaque;
223 uint8_t mask;
224
225 if (offset < 0x400) {
226 mask = (offset >> 2) & s->dir;
227 s->data = (s->data & ~mask) | (value & mask);
228 pl061_update(s);
229 return;
230 }
231 if (offset >= s->rsvd_start) {
232 goto err_out;
233 }
234 switch (offset) {
235 case 0x400: /* Direction */
236 s->dir = value & 0xff;
237 break;
238 case 0x404: /* Interrupt sense */
239 s->isense = value & 0xff;
240 break;
241 case 0x408: /* Interrupt both edges */
242 s->ibe = value & 0xff;
243 break;
244 case 0x40c: /* Interrupt event */
245 s->iev = value & 0xff;
246 break;
247 case 0x410: /* Interrupt mask */
248 s->im = value & 0xff;
249 break;
250 case 0x41c: /* Interrupt clear */
251 s->istate &= ~value;
252 break;
253 case 0x420: /* Alternate function select */
254 mask = s->cr;
255 s->afsel = (s->afsel & ~mask) | (value & mask);
256 break;
257 case 0x500: /* 2mA drive */
258 s->dr2r = value & 0xff;
259 break;
260 case 0x504: /* 4mA drive */
261 s->dr4r = value & 0xff;
262 break;
263 case 0x508: /* 8mA drive */
264 s->dr8r = value & 0xff;
265 break;
266 case 0x50c: /* Open drain */
267 s->odr = value & 0xff;
268 break;
269 case 0x510: /* Pull-up */
270 s->pur = value & 0xff;
271 break;
272 case 0x514: /* Pull-down */
273 s->pdr = value & 0xff;
274 break;
275 case 0x518: /* Slew rate control */
276 s->slr = value & 0xff;
277 break;
278 case 0x51c: /* Digital enable */
279 s->den = value & 0xff;
280 break;
281 case 0x520: /* Lock */
282 s->locked = (value != 0xacce551);
283 break;
284 case 0x524: /* Commit */
285 if (!s->locked)
286 s->cr = value & 0xff;
287 break;
288 case 0x528:
289 s->amsel = value & 0xff;
290 break;
291 default:
292 goto err_out;
293 }
294 pl061_update(s);
295 return;
296 err_out:
297 qemu_log_mask(LOG_GUEST_ERROR,
298 "pl061_write: Bad offset %x\n", (int)offset);
299 }
300
301 static void pl061_reset(DeviceState *dev)
302 {
303 PL061State *s = PL061(dev);
304
305 /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */
306 s->data = 0;
307 s->old_out_data = 0;
308 s->old_in_data = 0;
309 s->dir = 0;
310 s->isense = 0;
311 s->ibe = 0;
312 s->iev = 0;
313 s->im = 0;
314 s->istate = 0;
315 s->afsel = 0;
316 s->dr2r = 0xff;
317 s->dr4r = 0;
318 s->dr8r = 0;
319 s->odr = 0;
320 s->pur = 0;
321 s->pdr = 0;
322 s->slr = 0;
323 s->den = 0;
324 s->locked = 1;
325 s->cr = 0xff;
326 s->amsel = 0;
327 }
328
329 static void pl061_set_irq(void * opaque, int irq, int level)
330 {
331 PL061State *s = (PL061State *)opaque;
332 uint8_t mask;
333
334 mask = 1 << irq;
335 if ((s->dir & mask) == 0) {
336 s->data &= ~mask;
337 if (level)
338 s->data |= mask;
339 pl061_update(s);
340 }
341 }
342
343 static const MemoryRegionOps pl061_ops = {
344 .read = pl061_read,
345 .write = pl061_write,
346 .endianness = DEVICE_NATIVE_ENDIAN,
347 };
348
349 static void pl061_luminary_init(Object *obj)
350 {
351 PL061State *s = PL061(obj);
352
353 s->id = pl061_id_luminary;
354 s->rsvd_start = 0x52c;
355 }
356
357 static void pl061_init(Object *obj)
358 {
359 PL061State *s = PL061(obj);
360 DeviceState *dev = DEVICE(obj);
361 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
362
363 s->id = pl061_id;
364 s->rsvd_start = 0x424;
365
366 memory_region_init_io(&s->iomem, obj, &pl061_ops, s, "pl061", 0x1000);
367 sysbus_init_mmio(sbd, &s->iomem);
368 sysbus_init_irq(sbd, &s->irq);
369 qdev_init_gpio_in(dev, pl061_set_irq, N_GPIOS);
370 qdev_init_gpio_out(dev, s->out, N_GPIOS);
371 }
372
373 static void pl061_class_init(ObjectClass *klass, void *data)
374 {
375 DeviceClass *dc = DEVICE_CLASS(klass);
376
377 dc->vmsd = &vmstate_pl061;
378 dc->reset = &pl061_reset;
379 }
380
381 static const TypeInfo pl061_info = {
382 .name = TYPE_PL061,
383 .parent = TYPE_SYS_BUS_DEVICE,
384 .instance_size = sizeof(PL061State),
385 .instance_init = pl061_init,
386 .class_init = pl061_class_init,
387 };
388
389 static const TypeInfo pl061_luminary_info = {
390 .name = "pl061_luminary",
391 .parent = TYPE_PL061,
392 .instance_init = pl061_luminary_init,
393 };
394
395 static void pl061_register_types(void)
396 {
397 type_register_static(&pl061_info);
398 type_register_static(&pl061_luminary_info);
399 }
400
401 type_init(pl061_register_types)