qdev: integrate with QEMU Object Model (v2)
[qemu.git] / hw / grlib_apbuart.c
1 /*
2 * QEMU GRLIB APB UART Emulator
3 *
4 * Copyright (c) 2010-2011 AdaCore
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "sysbus.h"
26 #include "qemu-char.h"
27 #include "ptimer.h"
28
29 #include "trace.h"
30
31 #define UART_REG_SIZE 20 /* Size of memory mapped registers */
32
33 /* UART status register fields */
34 #define UART_DATA_READY (1 << 0)
35 #define UART_TRANSMIT_SHIFT_EMPTY (1 << 1)
36 #define UART_TRANSMIT_FIFO_EMPTY (1 << 2)
37 #define UART_BREAK_RECEIVED (1 << 3)
38 #define UART_OVERRUN (1 << 4)
39 #define UART_PARITY_ERROR (1 << 5)
40 #define UART_FRAMING_ERROR (1 << 6)
41 #define UART_TRANSMIT_FIFO_HALF (1 << 7)
42 #define UART_RECEIVE_FIFO_HALF (1 << 8)
43 #define UART_TRANSMIT_FIFO_FULL (1 << 9)
44 #define UART_RECEIVE_FIFO_FULL (1 << 10)
45
46 /* UART control register fields */
47 #define UART_RECEIVE_ENABLE (1 << 0)
48 #define UART_TRANSMIT_ENABLE (1 << 1)
49 #define UART_RECEIVE_INTERRUPT (1 << 2)
50 #define UART_TRANSMIT_INTERRUPT (1 << 3)
51 #define UART_PARITY_SELECT (1 << 4)
52 #define UART_PARITY_ENABLE (1 << 5)
53 #define UART_FLOW_CONTROL (1 << 6)
54 #define UART_LOOPBACK (1 << 7)
55 #define UART_EXTERNAL_CLOCK (1 << 8)
56 #define UART_RECEIVE_FIFO_INTERRUPT (1 << 9)
57 #define UART_TRANSMIT_FIFO_INTERRUPT (1 << 10)
58 #define UART_FIFO_DEBUG_MODE (1 << 11)
59 #define UART_OUTPUT_ENABLE (1 << 12)
60 #define UART_FIFO_AVAILABLE (1 << 31)
61
62 /* Memory mapped register offsets */
63 #define DATA_OFFSET 0x00
64 #define STATUS_OFFSET 0x04
65 #define CONTROL_OFFSET 0x08
66 #define SCALER_OFFSET 0x0C /* not supported */
67 #define FIFO_DEBUG_OFFSET 0x10 /* not supported */
68
69 typedef struct UART {
70 SysBusDevice busdev;
71 MemoryRegion iomem;
72 qemu_irq irq;
73
74 CharDriverState *chr;
75
76 /* registers */
77 uint32_t receive;
78 uint32_t status;
79 uint32_t control;
80 } UART;
81
82 static int grlib_apbuart_can_receive(void *opaque)
83 {
84 UART *uart = opaque;
85
86 return !!(uart->status & UART_DATA_READY);
87 }
88
89 static void grlib_apbuart_receive(void *opaque, const uint8_t *buf, int size)
90 {
91 UART *uart = opaque;
92
93 uart->receive = *buf;
94 uart->status |= UART_DATA_READY;
95
96 if (uart->control & UART_RECEIVE_INTERRUPT) {
97 qemu_irq_pulse(uart->irq);
98 }
99 }
100
101 static void grlib_apbuart_event(void *opaque, int event)
102 {
103 trace_grlib_apbuart_event(event);
104 }
105
106 static void
107 grlib_apbuart_write(void *opaque, target_phys_addr_t addr,
108 uint64_t value, unsigned size)
109 {
110 UART *uart = opaque;
111 unsigned char c = 0;
112
113 addr &= 0xff;
114
115 /* Unit registers */
116 switch (addr) {
117 case DATA_OFFSET:
118 c = value & 0xFF;
119 qemu_chr_fe_write(uart->chr, &c, 1);
120 return;
121
122 case STATUS_OFFSET:
123 /* Read Only */
124 return;
125
126 case CONTROL_OFFSET:
127 /* Not supported */
128 return;
129
130 case SCALER_OFFSET:
131 /* Not supported */
132 return;
133
134 default:
135 break;
136 }
137
138 trace_grlib_apbuart_writel_unknown(addr, value);
139 }
140
141 static bool grlib_apbuart_accepts(void *opaque, target_phys_addr_t addr,
142 unsigned size, bool is_write)
143 {
144 return is_write && size == 4;
145 }
146
147 static const MemoryRegionOps grlib_apbuart_ops = {
148 .write = grlib_apbuart_write,
149 .valid.accepts = grlib_apbuart_accepts,
150 .endianness = DEVICE_NATIVE_ENDIAN,
151 };
152
153 static int grlib_apbuart_init(SysBusDevice *dev)
154 {
155 UART *uart = FROM_SYSBUS(typeof(*uart), dev);
156
157 qemu_chr_add_handlers(uart->chr,
158 grlib_apbuart_can_receive,
159 grlib_apbuart_receive,
160 grlib_apbuart_event,
161 uart);
162
163 sysbus_init_irq(dev, &uart->irq);
164
165 memory_region_init_io(&uart->iomem, &grlib_apbuart_ops, uart,
166 "uart", UART_REG_SIZE);
167
168 sysbus_init_mmio(dev, &uart->iomem);
169
170 return 0;
171 }
172
173 static SysBusDeviceInfo grlib_gptimer_info = {
174 .init = grlib_apbuart_init,
175 .qdev.name = "grlib,apbuart",
176 .qdev.size = sizeof(UART),
177 .qdev.props = (Property[]) {
178 DEFINE_PROP_CHR("chrdev", UART, chr),
179 DEFINE_PROP_END_OF_LIST()
180 }
181 };
182
183 static void grlib_gptimer_register(void)
184 {
185 sysbus_register_withprop(&grlib_gptimer_info);
186 }
187
188 device_init(grlib_gptimer_register)