qdev: don't access name through info
[qemu.git] / hw / highbank.c
1 /*
2 * Calxeda Highbank SoC emulation
3 *
4 * Copyright (c) 2010-2012 Calxeda
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 */
19
20 #include "sysbus.h"
21 #include "arm-misc.h"
22 #include "primecell.h"
23 #include "devices.h"
24 #include "loader.h"
25 #include "net.h"
26 #include "sysemu.h"
27 #include "boards.h"
28 #include "sysbus.h"
29 #include "blockdev.h"
30 #include "exec-memory.h"
31
32 #define SMP_BOOT_ADDR 0x100
33 #define SMP_BOOT_REG 0x40
34 #define GIC_BASE_ADDR 0xfff10000
35
36 #define NIRQ_GIC 160
37
38 /* Board init. */
39 static void highbank_cpu_reset(void *opaque)
40 {
41 CPUState *env = opaque;
42
43 env->cp15.c15_config_base_address = GIC_BASE_ADDR;
44 }
45
46 static void hb_write_secondary(CPUState *env, const struct arm_boot_info *info)
47 {
48 int n;
49 uint32_t smpboot[] = {
50 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
51 0xe210000f, /* ands r0, r0, #0x0f */
52 0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
53 0xe0830200, /* add r0, r3, r0, lsl #4 */
54 0xe59f2018, /* ldr r2, privbase */
55 0xe3a01001, /* mov r1, #1 */
56 0xe5821100, /* str r1, [r2, #256] */
57 0xe320f003, /* wfi */
58 0xe5901000, /* ldr r1, [r0] */
59 0xe1110001, /* tst r1, r1 */
60 0x0afffffb, /* beq <wfi> */
61 0xe12fff11, /* bx r1 */
62 GIC_BASE_ADDR /* privbase: gic address. */
63 };
64 for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
65 smpboot[n] = tswap32(smpboot[n]);
66 }
67 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
68 }
69
70 static void hb_reset_secondary(CPUState *env, const struct arm_boot_info *info)
71 {
72 switch (info->nb_cpus) {
73 case 4:
74 stl_phys_notdirty(SMP_BOOT_REG + 0x30, 0);
75 case 3:
76 stl_phys_notdirty(SMP_BOOT_REG + 0x20, 0);
77 case 2:
78 stl_phys_notdirty(SMP_BOOT_REG + 0x10, 0);
79 env->regs[15] = SMP_BOOT_ADDR;
80 break;
81 default:
82 break;
83 }
84 }
85
86 #define NUM_REGS 0x200
87 static void hb_regs_write(void *opaque, target_phys_addr_t offset,
88 uint64_t value, unsigned size)
89 {
90 uint32_t *regs = opaque;
91
92 if (offset == 0xf00) {
93 if (value == 1 || value == 2) {
94 qemu_system_reset_request();
95 } else if (value == 3) {
96 qemu_system_shutdown_request();
97 }
98 }
99
100 regs[offset/4] = value;
101 }
102
103 static uint64_t hb_regs_read(void *opaque, target_phys_addr_t offset,
104 unsigned size)
105 {
106 uint32_t *regs = opaque;
107 uint32_t value = regs[offset/4];
108
109 if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {
110 value |= 0x30000000;
111 }
112
113 return value;
114 }
115
116 static const MemoryRegionOps hb_mem_ops = {
117 .read = hb_regs_read,
118 .write = hb_regs_write,
119 .endianness = DEVICE_NATIVE_ENDIAN,
120 };
121
122 typedef struct {
123 SysBusDevice busdev;
124 MemoryRegion *iomem;
125 uint32_t regs[NUM_REGS];
126 } HighbankRegsState;
127
128 static VMStateDescription vmstate_highbank_regs = {
129 .name = "highbank-regs",
130 .version_id = 0,
131 .minimum_version_id = 0,
132 .minimum_version_id_old = 0,
133 .fields = (VMStateField[]) {
134 VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
135 VMSTATE_END_OF_LIST(),
136 },
137 };
138
139 static void highbank_regs_reset(DeviceState *dev)
140 {
141 SysBusDevice *sys_dev = sysbus_from_qdev(dev);
142 HighbankRegsState *s = FROM_SYSBUS(HighbankRegsState, sys_dev);
143
144 s->regs[0x40] = 0x05F20121;
145 s->regs[0x41] = 0x2;
146 s->regs[0x42] = 0x05F30121;
147 s->regs[0x43] = 0x05F40121;
148 }
149
150 static int highbank_regs_init(SysBusDevice *dev)
151 {
152 HighbankRegsState *s = FROM_SYSBUS(HighbankRegsState, dev);
153
154 s->iomem = g_new(MemoryRegion, 1);
155 memory_region_init_io(s->iomem, &hb_mem_ops, s->regs, "highbank_regs",
156 0x1000);
157 sysbus_init_mmio(dev, s->iomem);
158
159 return 0;
160 }
161
162 static SysBusDeviceInfo highbank_regs_info = {
163 .init = highbank_regs_init,
164 .qdev.name = "highbank-regs",
165 .qdev.desc = "Calxeda Highbank registers",
166 .qdev.size = sizeof(HighbankRegsState),
167 .qdev.vmsd = &vmstate_highbank_regs,
168 .qdev.reset = highbank_regs_reset,
169 };
170
171 static void highbank_regs_register_device(void)
172 {
173 sysbus_register_withprop(&highbank_regs_info);
174 }
175
176 device_init(highbank_regs_register_device)
177
178 static struct arm_boot_info highbank_binfo;
179
180 /* ram_size must be set to match the upper bound of memory in the
181 * device tree (linux/arch/arm/boot/dts/highbank.dts), which is
182 * normally 0xff900000 or -m 4089. When running this board on a
183 * 32-bit host, set the reg value of memory to 0xf7ff00000 in the
184 * device tree and pass -m 2047 to QEMU.
185 */
186 static void highbank_init(ram_addr_t ram_size,
187 const char *boot_device,
188 const char *kernel_filename, const char *kernel_cmdline,
189 const char *initrd_filename, const char *cpu_model)
190 {
191 CPUState *env = NULL;
192 DeviceState *dev;
193 SysBusDevice *busdev;
194 qemu_irq *irqp;
195 qemu_irq pic[128];
196 int n;
197 qemu_irq cpu_irq[4];
198 MemoryRegion *sysram;
199 MemoryRegion *dram;
200 MemoryRegion *sysmem;
201 char *sysboot_filename;
202
203 if (!cpu_model) {
204 cpu_model = "cortex-a9";
205 }
206
207 for (n = 0; n < smp_cpus; n++) {
208 env = cpu_init(cpu_model);
209 if (!env) {
210 fprintf(stderr, "Unable to find CPU definition\n");
211 exit(1);
212 }
213 irqp = arm_pic_init_cpu(env);
214 cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
215 qemu_register_reset(highbank_cpu_reset, env);
216 }
217
218 sysmem = get_system_memory();
219 dram = g_new(MemoryRegion, 1);
220 memory_region_init_ram(dram, "highbank.dram", ram_size);
221 /* SDRAM at address zero. */
222 memory_region_add_subregion(sysmem, 0, dram);
223
224 sysram = g_new(MemoryRegion, 1);
225 memory_region_init_ram(sysram, "highbank.sysram", 0x8000);
226 memory_region_add_subregion(sysmem, 0xfff88000, sysram);
227 if (bios_name != NULL) {
228 sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
229 if (sysboot_filename != NULL) {
230 uint32_t filesize = get_image_size(sysboot_filename);
231 if (load_image_targphys("sysram.bin", 0xfff88000, filesize) < 0) {
232 hw_error("Unable to load %s\n", bios_name);
233 }
234 } else {
235 hw_error("Unable to find %s\n", bios_name);
236 }
237 }
238
239 dev = qdev_create(NULL, "a9mpcore_priv");
240 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
241 qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
242 qdev_init_nofail(dev);
243 busdev = sysbus_from_qdev(dev);
244 sysbus_mmio_map(busdev, 0, GIC_BASE_ADDR);
245 for (n = 0; n < smp_cpus; n++) {
246 sysbus_connect_irq(busdev, n, cpu_irq[n]);
247 }
248
249 for (n = 0; n < 128; n++) {
250 pic[n] = qdev_get_gpio_in(dev, n);
251 }
252
253 dev = qdev_create(NULL, "l2x0");
254 qdev_init_nofail(dev);
255 busdev = sysbus_from_qdev(dev);
256 sysbus_mmio_map(busdev, 0, 0xfff12000);
257
258 dev = qdev_create(NULL, "sp804");
259 qdev_prop_set_uint32(dev, "freq0", 150000000);
260 qdev_prop_set_uint32(dev, "freq1", 150000000);
261 qdev_init_nofail(dev);
262 busdev = sysbus_from_qdev(dev);
263 sysbus_mmio_map(busdev, 0, 0xfff34000);
264 sysbus_connect_irq(busdev, 0, pic[18]);
265 sysbus_create_simple("pl011", 0xfff36000, pic[20]);
266
267 dev = qdev_create(NULL, "highbank-regs");
268 qdev_init_nofail(dev);
269 busdev = sysbus_from_qdev(dev);
270 sysbus_mmio_map(busdev, 0, 0xfff3c000);
271
272 sysbus_create_simple("pl061", 0xfff30000, pic[14]);
273 sysbus_create_simple("pl061", 0xfff31000, pic[15]);
274 sysbus_create_simple("pl061", 0xfff32000, pic[16]);
275 sysbus_create_simple("pl061", 0xfff33000, pic[17]);
276 sysbus_create_simple("pl031", 0xfff35000, pic[19]);
277 sysbus_create_simple("pl022", 0xfff39000, pic[23]);
278
279 sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]);
280
281 if (nd_table[0].vlan) {
282 qemu_check_nic_model(&nd_table[0], "xgmac");
283 dev = qdev_create(NULL, "xgmac");
284 qdev_set_nic_properties(dev, &nd_table[0]);
285 qdev_init_nofail(dev);
286 sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xfff50000);
287 sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[77]);
288 sysbus_connect_irq(sysbus_from_qdev(dev), 1, pic[78]);
289 sysbus_connect_irq(sysbus_from_qdev(dev), 2, pic[79]);
290
291 qemu_check_nic_model(&nd_table[1], "xgmac");
292 dev = qdev_create(NULL, "xgmac");
293 qdev_set_nic_properties(dev, &nd_table[1]);
294 qdev_init_nofail(dev);
295 sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xfff51000);
296 sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[80]);
297 sysbus_connect_irq(sysbus_from_qdev(dev), 1, pic[81]);
298 sysbus_connect_irq(sysbus_from_qdev(dev), 2, pic[82]);
299 }
300
301 highbank_binfo.ram_size = ram_size;
302 highbank_binfo.kernel_filename = kernel_filename;
303 highbank_binfo.kernel_cmdline = kernel_cmdline;
304 highbank_binfo.initrd_filename = initrd_filename;
305 /* highbank requires a dtb in order to boot, and the dtb will override
306 * the board ID. The following value is ignored, so set it to -1 to be
307 * clear that the value is meaningless.
308 */
309 highbank_binfo.board_id = -1;
310 highbank_binfo.nb_cpus = smp_cpus;
311 highbank_binfo.loader_start = 0;
312 highbank_binfo.write_secondary_boot = hb_write_secondary;
313 highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
314 arm_load_kernel(first_cpu, &highbank_binfo);
315 }
316
317 static QEMUMachine highbank_machine = {
318 .name = "highbank",
319 .desc = "Calxeda Highbank (ECX-1000)",
320 .init = highbank_init,
321 .use_scsi = 1,
322 .max_cpus = 4,
323 };
324
325 static void highbank_machine_init(void)
326 {
327 qemu_register_machine(&highbank_machine);
328 }
329
330 machine_init(highbank_machine_init);