Add access control support to qemu bridge helper
[qemu.git] / hw / hpet.c
1 /*
2 * High Precisition Event Timer emulation
3 *
4 * Copyright (c) 2007 Alexander Graf
5 * Copyright (c) 2008 IBM Corporation
6 *
7 * Authors: Beth Kon <bkon@us.ibm.com>
8 *
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
18 *
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 *
22 * *****************************************************************
23 *
24 * This driver attempts to emulate an HPET device in software.
25 */
26
27 #include "hw.h"
28 #include "pc.h"
29 #include "console.h"
30 #include "qemu-timer.h"
31 #include "hpet_emul.h"
32 #include "sysbus.h"
33 #include "mc146818rtc.h"
34
35 //#define HPET_DEBUG
36 #ifdef HPET_DEBUG
37 #define DPRINTF printf
38 #else
39 #define DPRINTF(...)
40 #endif
41
42 #define HPET_MSI_SUPPORT 0
43
44 struct HPETState;
45 typedef struct HPETTimer { /* timers */
46 uint8_t tn; /*timer number*/
47 QEMUTimer *qemu_timer;
48 struct HPETState *state;
49 /* Memory-mapped, software visible timer registers */
50 uint64_t config; /* configuration/cap */
51 uint64_t cmp; /* comparator */
52 uint64_t fsb; /* FSB route */
53 /* Hidden register state */
54 uint64_t period; /* Last value written to comparator */
55 uint8_t wrap_flag; /* timer pop will indicate wrap for one-shot 32-bit
56 * mode. Next pop will be actual timer expiration.
57 */
58 } HPETTimer;
59
60 typedef struct HPETState {
61 SysBusDevice busdev;
62 MemoryRegion iomem;
63 uint64_t hpet_offset;
64 qemu_irq irqs[HPET_NUM_IRQ_ROUTES];
65 uint32_t flags;
66 uint8_t rtc_irq_level;
67 uint8_t num_timers;
68 HPETTimer timer[HPET_MAX_TIMERS];
69
70 /* Memory-mapped, software visible registers */
71 uint64_t capability; /* capabilities */
72 uint64_t config; /* configuration */
73 uint64_t isr; /* interrupt status reg */
74 uint64_t hpet_counter; /* main counter */
75 uint8_t hpet_id; /* instance id */
76 } HPETState;
77
78 static uint32_t hpet_in_legacy_mode(HPETState *s)
79 {
80 return s->config & HPET_CFG_LEGACY;
81 }
82
83 static uint32_t timer_int_route(struct HPETTimer *timer)
84 {
85 return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
86 }
87
88 static uint32_t timer_fsb_route(HPETTimer *t)
89 {
90 return t->config & HPET_TN_FSB_ENABLE;
91 }
92
93 static uint32_t hpet_enabled(HPETState *s)
94 {
95 return s->config & HPET_CFG_ENABLE;
96 }
97
98 static uint32_t timer_is_periodic(HPETTimer *t)
99 {
100 return t->config & HPET_TN_PERIODIC;
101 }
102
103 static uint32_t timer_enabled(HPETTimer *t)
104 {
105 return t->config & HPET_TN_ENABLE;
106 }
107
108 static uint32_t hpet_time_after(uint64_t a, uint64_t b)
109 {
110 return ((int32_t)(b) - (int32_t)(a) < 0);
111 }
112
113 static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
114 {
115 return ((int64_t)(b) - (int64_t)(a) < 0);
116 }
117
118 static uint64_t ticks_to_ns(uint64_t value)
119 {
120 return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
121 }
122
123 static uint64_t ns_to_ticks(uint64_t value)
124 {
125 return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
126 }
127
128 static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
129 {
130 new &= mask;
131 new |= old & ~mask;
132 return new;
133 }
134
135 static int activating_bit(uint64_t old, uint64_t new, uint64_t mask)
136 {
137 return (!(old & mask) && (new & mask));
138 }
139
140 static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
141 {
142 return ((old & mask) && !(new & mask));
143 }
144
145 static uint64_t hpet_get_ticks(HPETState *s)
146 {
147 return ns_to_ticks(qemu_get_clock_ns(vm_clock) + s->hpet_offset);
148 }
149
150 /*
151 * calculate diff between comparator value and current ticks
152 */
153 static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current)
154 {
155
156 if (t->config & HPET_TN_32BIT) {
157 uint32_t diff, cmp;
158
159 cmp = (uint32_t)t->cmp;
160 diff = cmp - (uint32_t)current;
161 diff = (int32_t)diff > 0 ? diff : (uint32_t)1;
162 return (uint64_t)diff;
163 } else {
164 uint64_t diff, cmp;
165
166 cmp = t->cmp;
167 diff = cmp - current;
168 diff = (int64_t)diff > 0 ? diff : (uint64_t)1;
169 return diff;
170 }
171 }
172
173 static void update_irq(struct HPETTimer *timer, int set)
174 {
175 uint64_t mask;
176 HPETState *s;
177 int route;
178
179 if (timer->tn <= 1 && hpet_in_legacy_mode(timer->state)) {
180 /* if LegacyReplacementRoute bit is set, HPET specification requires
181 * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
182 * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
183 */
184 route = (timer->tn == 0) ? 0 : RTC_ISA_IRQ;
185 } else {
186 route = timer_int_route(timer);
187 }
188 s = timer->state;
189 mask = 1 << timer->tn;
190 if (!set || !timer_enabled(timer) || !hpet_enabled(timer->state)) {
191 s->isr &= ~mask;
192 if (!timer_fsb_route(timer)) {
193 qemu_irq_lower(s->irqs[route]);
194 }
195 } else if (timer_fsb_route(timer)) {
196 stl_le_phys(timer->fsb >> 32, timer->fsb & 0xffffffff);
197 } else if (timer->config & HPET_TN_TYPE_LEVEL) {
198 s->isr |= mask;
199 qemu_irq_raise(s->irqs[route]);
200 } else {
201 s->isr &= ~mask;
202 qemu_irq_pulse(s->irqs[route]);
203 }
204 }
205
206 static void hpet_pre_save(void *opaque)
207 {
208 HPETState *s = opaque;
209
210 /* save current counter value */
211 s->hpet_counter = hpet_get_ticks(s);
212 }
213
214 static int hpet_pre_load(void *opaque)
215 {
216 HPETState *s = opaque;
217
218 /* version 1 only supports 3, later versions will load the actual value */
219 s->num_timers = HPET_MIN_TIMERS;
220 return 0;
221 }
222
223 static int hpet_post_load(void *opaque, int version_id)
224 {
225 HPETState *s = opaque;
226
227 /* Recalculate the offset between the main counter and guest time */
228 s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock_ns(vm_clock);
229
230 /* Push number of timers into capability returned via HPET_ID */
231 s->capability &= ~HPET_ID_NUM_TIM_MASK;
232 s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
233 hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability;
234
235 /* Derive HPET_MSI_SUPPORT from the capability of the first timer. */
236 s->flags &= ~(1 << HPET_MSI_SUPPORT);
237 if (s->timer[0].config & HPET_TN_FSB_CAP) {
238 s->flags |= 1 << HPET_MSI_SUPPORT;
239 }
240 return 0;
241 }
242
243 static const VMStateDescription vmstate_hpet_timer = {
244 .name = "hpet_timer",
245 .version_id = 1,
246 .minimum_version_id = 1,
247 .minimum_version_id_old = 1,
248 .fields = (VMStateField []) {
249 VMSTATE_UINT8(tn, HPETTimer),
250 VMSTATE_UINT64(config, HPETTimer),
251 VMSTATE_UINT64(cmp, HPETTimer),
252 VMSTATE_UINT64(fsb, HPETTimer),
253 VMSTATE_UINT64(period, HPETTimer),
254 VMSTATE_UINT8(wrap_flag, HPETTimer),
255 VMSTATE_TIMER(qemu_timer, HPETTimer),
256 VMSTATE_END_OF_LIST()
257 }
258 };
259
260 static const VMStateDescription vmstate_hpet = {
261 .name = "hpet",
262 .version_id = 2,
263 .minimum_version_id = 1,
264 .minimum_version_id_old = 1,
265 .pre_save = hpet_pre_save,
266 .pre_load = hpet_pre_load,
267 .post_load = hpet_post_load,
268 .fields = (VMStateField []) {
269 VMSTATE_UINT64(config, HPETState),
270 VMSTATE_UINT64(isr, HPETState),
271 VMSTATE_UINT64(hpet_counter, HPETState),
272 VMSTATE_UINT8_V(num_timers, HPETState, 2),
273 VMSTATE_STRUCT_VARRAY_UINT8(timer, HPETState, num_timers, 0,
274 vmstate_hpet_timer, HPETTimer),
275 VMSTATE_END_OF_LIST()
276 }
277 };
278
279 /*
280 * timer expiration callback
281 */
282 static void hpet_timer(void *opaque)
283 {
284 HPETTimer *t = opaque;
285 uint64_t diff;
286
287 uint64_t period = t->period;
288 uint64_t cur_tick = hpet_get_ticks(t->state);
289
290 if (timer_is_periodic(t) && period != 0) {
291 if (t->config & HPET_TN_32BIT) {
292 while (hpet_time_after(cur_tick, t->cmp)) {
293 t->cmp = (uint32_t)(t->cmp + t->period);
294 }
295 } else {
296 while (hpet_time_after64(cur_tick, t->cmp)) {
297 t->cmp += period;
298 }
299 }
300 diff = hpet_calculate_diff(t, cur_tick);
301 qemu_mod_timer(t->qemu_timer,
302 qemu_get_clock_ns(vm_clock) + (int64_t)ticks_to_ns(diff));
303 } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
304 if (t->wrap_flag) {
305 diff = hpet_calculate_diff(t, cur_tick);
306 qemu_mod_timer(t->qemu_timer, qemu_get_clock_ns(vm_clock) +
307 (int64_t)ticks_to_ns(diff));
308 t->wrap_flag = 0;
309 }
310 }
311 update_irq(t, 1);
312 }
313
314 static void hpet_set_timer(HPETTimer *t)
315 {
316 uint64_t diff;
317 uint32_t wrap_diff; /* how many ticks until we wrap? */
318 uint64_t cur_tick = hpet_get_ticks(t->state);
319
320 /* whenever new timer is being set up, make sure wrap_flag is 0 */
321 t->wrap_flag = 0;
322 diff = hpet_calculate_diff(t, cur_tick);
323
324 /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
325 * counter wraps in addition to an interrupt with comparator match.
326 */
327 if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
328 wrap_diff = 0xffffffff - (uint32_t)cur_tick;
329 if (wrap_diff < (uint32_t)diff) {
330 diff = wrap_diff;
331 t->wrap_flag = 1;
332 }
333 }
334 qemu_mod_timer(t->qemu_timer,
335 qemu_get_clock_ns(vm_clock) + (int64_t)ticks_to_ns(diff));
336 }
337
338 static void hpet_del_timer(HPETTimer *t)
339 {
340 qemu_del_timer(t->qemu_timer);
341 update_irq(t, 0);
342 }
343
344 #ifdef HPET_DEBUG
345 static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr)
346 {
347 printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
348 return 0;
349 }
350
351 static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
352 {
353 printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
354 return 0;
355 }
356 #endif
357
358 static uint64_t hpet_ram_read(void *opaque, target_phys_addr_t addr,
359 unsigned size)
360 {
361 HPETState *s = opaque;
362 uint64_t cur_tick, index;
363
364 DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
365 index = addr;
366 /*address range of all TN regs*/
367 if (index >= 0x100 && index <= 0x3ff) {
368 uint8_t timer_id = (addr - 0x100) / 0x20;
369 HPETTimer *timer = &s->timer[timer_id];
370
371 if (timer_id > s->num_timers) {
372 DPRINTF("qemu: timer id out of range\n");
373 return 0;
374 }
375
376 switch ((addr - 0x100) % 0x20) {
377 case HPET_TN_CFG:
378 return timer->config;
379 case HPET_TN_CFG + 4: // Interrupt capabilities
380 return timer->config >> 32;
381 case HPET_TN_CMP: // comparator register
382 return timer->cmp;
383 case HPET_TN_CMP + 4:
384 return timer->cmp >> 32;
385 case HPET_TN_ROUTE:
386 return timer->fsb;
387 case HPET_TN_ROUTE + 4:
388 return timer->fsb >> 32;
389 default:
390 DPRINTF("qemu: invalid hpet_ram_readl\n");
391 break;
392 }
393 } else {
394 switch (index) {
395 case HPET_ID:
396 return s->capability;
397 case HPET_PERIOD:
398 return s->capability >> 32;
399 case HPET_CFG:
400 return s->config;
401 case HPET_CFG + 4:
402 DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl\n");
403 return 0;
404 case HPET_COUNTER:
405 if (hpet_enabled(s)) {
406 cur_tick = hpet_get_ticks(s);
407 } else {
408 cur_tick = s->hpet_counter;
409 }
410 DPRINTF("qemu: reading counter = %" PRIx64 "\n", cur_tick);
411 return cur_tick;
412 case HPET_COUNTER + 4:
413 if (hpet_enabled(s)) {
414 cur_tick = hpet_get_ticks(s);
415 } else {
416 cur_tick = s->hpet_counter;
417 }
418 DPRINTF("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick);
419 return cur_tick >> 32;
420 case HPET_STATUS:
421 return s->isr;
422 default:
423 DPRINTF("qemu: invalid hpet_ram_readl\n");
424 break;
425 }
426 }
427 return 0;
428 }
429
430 static void hpet_ram_write(void *opaque, target_phys_addr_t addr,
431 uint64_t value, unsigned size)
432 {
433 int i;
434 HPETState *s = opaque;
435 uint64_t old_val, new_val, val, index;
436
437 DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
438 index = addr;
439 old_val = hpet_ram_read(opaque, addr, 4);
440 new_val = value;
441
442 /*address range of all TN regs*/
443 if (index >= 0x100 && index <= 0x3ff) {
444 uint8_t timer_id = (addr - 0x100) / 0x20;
445 HPETTimer *timer = &s->timer[timer_id];
446
447 DPRINTF("qemu: hpet_ram_writel timer_id = %#x\n", timer_id);
448 if (timer_id > s->num_timers) {
449 DPRINTF("qemu: timer id out of range\n");
450 return;
451 }
452 switch ((addr - 0x100) % 0x20) {
453 case HPET_TN_CFG:
454 DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
455 if (activating_bit(old_val, new_val, HPET_TN_FSB_ENABLE)) {
456 update_irq(timer, 0);
457 }
458 val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK);
459 timer->config = (timer->config & 0xffffffff00000000ULL) | val;
460 if (new_val & HPET_TN_32BIT) {
461 timer->cmp = (uint32_t)timer->cmp;
462 timer->period = (uint32_t)timer->period;
463 }
464 if (activating_bit(old_val, new_val, HPET_TN_ENABLE)) {
465 hpet_set_timer(timer);
466 } else if (deactivating_bit(old_val, new_val, HPET_TN_ENABLE)) {
467 hpet_del_timer(timer);
468 }
469 break;
470 case HPET_TN_CFG + 4: // Interrupt capabilities
471 DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
472 break;
473 case HPET_TN_CMP: // comparator register
474 DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP\n");
475 if (timer->config & HPET_TN_32BIT) {
476 new_val = (uint32_t)new_val;
477 }
478 if (!timer_is_periodic(timer)
479 || (timer->config & HPET_TN_SETVAL)) {
480 timer->cmp = (timer->cmp & 0xffffffff00000000ULL) | new_val;
481 }
482 if (timer_is_periodic(timer)) {
483 /*
484 * FIXME: Clamp period to reasonable min value?
485 * Clamp period to reasonable max value
486 */
487 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
488 timer->period =
489 (timer->period & 0xffffffff00000000ULL) | new_val;
490 }
491 timer->config &= ~HPET_TN_SETVAL;
492 if (hpet_enabled(s)) {
493 hpet_set_timer(timer);
494 }
495 break;
496 case HPET_TN_CMP + 4: // comparator register high order
497 DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
498 if (!timer_is_periodic(timer)
499 || (timer->config & HPET_TN_SETVAL)) {
500 timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32;
501 } else {
502 /*
503 * FIXME: Clamp period to reasonable min value?
504 * Clamp period to reasonable max value
505 */
506 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
507 timer->period =
508 (timer->period & 0xffffffffULL) | new_val << 32;
509 }
510 timer->config &= ~HPET_TN_SETVAL;
511 if (hpet_enabled(s)) {
512 hpet_set_timer(timer);
513 }
514 break;
515 case HPET_TN_ROUTE:
516 timer->fsb = (timer->fsb & 0xffffffff00000000ULL) | new_val;
517 break;
518 case HPET_TN_ROUTE + 4:
519 timer->fsb = (new_val << 32) | (timer->fsb & 0xffffffff);
520 break;
521 default:
522 DPRINTF("qemu: invalid hpet_ram_writel\n");
523 break;
524 }
525 return;
526 } else {
527 switch (index) {
528 case HPET_ID:
529 return;
530 case HPET_CFG:
531 val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK);
532 s->config = (s->config & 0xffffffff00000000ULL) | val;
533 if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
534 /* Enable main counter and interrupt generation. */
535 s->hpet_offset =
536 ticks_to_ns(s->hpet_counter) - qemu_get_clock_ns(vm_clock);
537 for (i = 0; i < s->num_timers; i++) {
538 if ((&s->timer[i])->cmp != ~0ULL) {
539 hpet_set_timer(&s->timer[i]);
540 }
541 }
542 } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
543 /* Halt main counter and disable interrupt generation. */
544 s->hpet_counter = hpet_get_ticks(s);
545 for (i = 0; i < s->num_timers; i++) {
546 hpet_del_timer(&s->timer[i]);
547 }
548 }
549 /* i8254 and RTC are disabled when HPET is in legacy mode */
550 if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
551 hpet_pit_disable();
552 qemu_irq_lower(s->irqs[RTC_ISA_IRQ]);
553 } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
554 hpet_pit_enable();
555 qemu_set_irq(s->irqs[RTC_ISA_IRQ], s->rtc_irq_level);
556 }
557 break;
558 case HPET_CFG + 4:
559 DPRINTF("qemu: invalid HPET_CFG+4 write\n");
560 break;
561 case HPET_STATUS:
562 val = new_val & s->isr;
563 for (i = 0; i < s->num_timers; i++) {
564 if (val & (1 << i)) {
565 update_irq(&s->timer[i], 0);
566 }
567 }
568 break;
569 case HPET_COUNTER:
570 if (hpet_enabled(s)) {
571 DPRINTF("qemu: Writing counter while HPET enabled!\n");
572 }
573 s->hpet_counter =
574 (s->hpet_counter & 0xffffffff00000000ULL) | value;
575 DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
576 value, s->hpet_counter);
577 break;
578 case HPET_COUNTER + 4:
579 if (hpet_enabled(s)) {
580 DPRINTF("qemu: Writing counter while HPET enabled!\n");
581 }
582 s->hpet_counter =
583 (s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32);
584 DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
585 value, s->hpet_counter);
586 break;
587 default:
588 DPRINTF("qemu: invalid hpet_ram_writel\n");
589 break;
590 }
591 }
592 }
593
594 static const MemoryRegionOps hpet_ram_ops = {
595 .read = hpet_ram_read,
596 .write = hpet_ram_write,
597 .valid = {
598 .min_access_size = 4,
599 .max_access_size = 4,
600 },
601 .endianness = DEVICE_NATIVE_ENDIAN,
602 };
603
604 static void hpet_reset(DeviceState *d)
605 {
606 HPETState *s = FROM_SYSBUS(HPETState, sysbus_from_qdev(d));
607 int i;
608 static int count = 0;
609
610 for (i = 0; i < s->num_timers; i++) {
611 HPETTimer *timer = &s->timer[i];
612
613 hpet_del_timer(timer);
614 timer->cmp = ~0ULL;
615 timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP;
616 if (s->flags & (1 << HPET_MSI_SUPPORT)) {
617 timer->config |= HPET_TN_FSB_CAP;
618 }
619 /* advertise availability of ioapic inti2 */
620 timer->config |= 0x00000004ULL << 32;
621 timer->period = 0ULL;
622 timer->wrap_flag = 0;
623 }
624
625 s->hpet_counter = 0ULL;
626 s->hpet_offset = 0ULL;
627 s->config = 0ULL;
628 if (count > 0) {
629 /* we don't enable pit when hpet_reset is first called (by hpet_init)
630 * because hpet is taking over for pit here. On subsequent invocations,
631 * hpet_reset is called due to system reset. At this point control must
632 * be returned to pit until SW reenables hpet.
633 */
634 hpet_pit_enable();
635 }
636 hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability;
637 hpet_cfg.hpet[s->hpet_id].address = sysbus_from_qdev(d)->mmio[0].addr;
638 count = 1;
639 }
640
641 static void hpet_handle_rtc_irq(void *opaque, int n, int level)
642 {
643 HPETState *s = FROM_SYSBUS(HPETState, opaque);
644
645 s->rtc_irq_level = level;
646 if (!hpet_in_legacy_mode(s)) {
647 qemu_set_irq(s->irqs[RTC_ISA_IRQ], level);
648 }
649 }
650
651 static int hpet_init(SysBusDevice *dev)
652 {
653 HPETState *s = FROM_SYSBUS(HPETState, dev);
654 int i;
655 HPETTimer *timer;
656
657 if (hpet_cfg.count == UINT8_MAX) {
658 /* first instance */
659 hpet_cfg.count = 0;
660 }
661
662 if (hpet_cfg.count == 8) {
663 fprintf(stderr, "Only 8 instances of HPET is allowed\n");
664 return -1;
665 }
666
667 s->hpet_id = hpet_cfg.count++;
668
669 for (i = 0; i < HPET_NUM_IRQ_ROUTES; i++) {
670 sysbus_init_irq(dev, &s->irqs[i]);
671 }
672
673 if (s->num_timers < HPET_MIN_TIMERS) {
674 s->num_timers = HPET_MIN_TIMERS;
675 } else if (s->num_timers > HPET_MAX_TIMERS) {
676 s->num_timers = HPET_MAX_TIMERS;
677 }
678 for (i = 0; i < HPET_MAX_TIMERS; i++) {
679 timer = &s->timer[i];
680 timer->qemu_timer = qemu_new_timer_ns(vm_clock, hpet_timer, timer);
681 timer->tn = i;
682 timer->state = s;
683 }
684
685 /* 64-bit main counter; LegacyReplacementRoute. */
686 s->capability = 0x8086a001ULL;
687 s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
688 s->capability |= ((HPET_CLK_PERIOD) << 32);
689
690 qdev_init_gpio_in(&dev->qdev, hpet_handle_rtc_irq, 1);
691
692 /* HPET Area */
693 memory_region_init_io(&s->iomem, &hpet_ram_ops, s, "hpet", 0x400);
694 sysbus_init_mmio(dev, &s->iomem);
695 return 0;
696 }
697
698 static Property hpet_device_properties[] = {
699 DEFINE_PROP_UINT8("timers", HPETState, num_timers, HPET_MIN_TIMERS),
700 DEFINE_PROP_BIT("msi", HPETState, flags, HPET_MSI_SUPPORT, false),
701 DEFINE_PROP_END_OF_LIST(),
702 };
703
704 static void hpet_device_class_init(ObjectClass *klass, void *data)
705 {
706 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
707
708 k->init = hpet_init;
709 }
710
711 static DeviceInfo hpet_device_info = {
712 .name = "hpet",
713 .size = sizeof(HPETState),
714 .no_user = 1,
715 .vmsd = &vmstate_hpet,
716 .reset = hpet_reset,
717 .props = hpet_device_properties,
718 .class_init = hpet_device_class_init,
719 };
720
721 static void hpet_register_device(void)
722 {
723 sysbus_register_withprop(&hpet_device_info);
724 }
725
726 device_init(hpet_register_device)