hw/arm/bcm2836: Only provide "enabled-cpus" property to multicore SoCs
[qemu.git] / hw / hppa / lasi.c
1 /*
2 * HP-PARISC Lasi chipset emulation.
3 *
4 * (C) 2019 by Helge Deller <deller@gmx.de>
5 *
6 * This work is licensed under the GNU GPL license version 2 or later.
7 *
8 * Documentation available at:
9 * https://parisc.wiki.kernel.org/images-parisc/7/79/Lasi_ers.pdf
10 */
11
12 #include "qemu/osdep.h"
13 #include "qemu/units.h"
14 #include "qemu/log.h"
15 #include "qapi/error.h"
16 #include "cpu.h"
17 #include "trace.h"
18 #include "hw/hw.h"
19 #include "hw/irq.h"
20 #include "sysemu/sysemu.h"
21 #include "sysemu/runstate.h"
22 #include "hppa_sys.h"
23 #include "hw/net/lasi_82596.h"
24 #include "hw/char/parallel.h"
25 #include "hw/char/serial.h"
26 #include "hw/input/lasips2.h"
27 #include "exec/address-spaces.h"
28 #include "migration/vmstate.h"
29 #include "qom/object.h"
30
31 #define TYPE_LASI_CHIP "lasi-chip"
32
33 #define LASI_IRR 0x00 /* RO */
34 #define LASI_IMR 0x04
35 #define LASI_IPR 0x08
36 #define LASI_ICR 0x0c
37 #define LASI_IAR 0x10
38
39 #define LASI_PCR 0x0C000 /* LASI Power Control register */
40 #define LASI_ERRLOG 0x0C004 /* LASI Error Logging register */
41 #define LASI_VER 0x0C008 /* LASI Version Control register */
42 #define LASI_IORESET 0x0C00C /* LASI I/O Reset register */
43 #define LASI_AMR 0x0C010 /* LASI Arbitration Mask register */
44 #define LASI_IO_CONF 0x7FFFE /* LASI primary configuration register */
45 #define LASI_IO_CONF2 0x7FFFF /* LASI secondary configuration register */
46
47 #define LASI_BIT(x) (1ul << (x))
48 #define LASI_IRQ_BITS (LASI_BIT(5) | LASI_BIT(7) | LASI_BIT(8) | LASI_BIT(9) \
49 | LASI_BIT(13) | LASI_BIT(14) | LASI_BIT(16) | LASI_BIT(17) \
50 | LASI_BIT(18) | LASI_BIT(19) | LASI_BIT(20) | LASI_BIT(21) \
51 | LASI_BIT(26))
52
53 #define ICR_BUS_ERROR_BIT LASI_BIT(8) /* bit 8 in ICR */
54 #define ICR_TOC_BIT LASI_BIT(1) /* bit 1 in ICR */
55
56 OBJECT_DECLARE_SIMPLE_TYPE(LasiState, LASI_CHIP)
57
58 struct LasiState {
59 PCIHostState parent_obj;
60
61 uint32_t irr;
62 uint32_t imr;
63 uint32_t ipr;
64 uint32_t icr;
65 uint32_t iar;
66
67 uint32_t errlog;
68 uint32_t amr;
69 uint32_t rtc;
70 time_t rtc_ref;
71
72 MemoryRegion this_mem;
73 };
74
75 static bool lasi_chip_mem_valid(void *opaque, hwaddr addr,
76 unsigned size, bool is_write,
77 MemTxAttrs attrs)
78 {
79 bool ret = false;
80
81 switch (addr) {
82 case LASI_IRR:
83 case LASI_IMR:
84 case LASI_IPR:
85 case LASI_ICR:
86 case LASI_IAR:
87
88 case (LASI_LAN_HPA - LASI_HPA):
89 case (LASI_LPT_HPA - LASI_HPA):
90 case (LASI_UART_HPA - LASI_HPA):
91 case (LASI_RTC_HPA - LASI_HPA):
92
93 case LASI_PCR ... LASI_AMR:
94 ret = true;
95 }
96
97 trace_lasi_chip_mem_valid(addr, ret);
98 return ret;
99 }
100
101 static MemTxResult lasi_chip_read_with_attrs(void *opaque, hwaddr addr,
102 uint64_t *data, unsigned size,
103 MemTxAttrs attrs)
104 {
105 LasiState *s = opaque;
106 MemTxResult ret = MEMTX_OK;
107 uint32_t val;
108
109 switch (addr) {
110 case LASI_IRR:
111 val = s->irr;
112 break;
113 case LASI_IMR:
114 val = s->imr;
115 break;
116 case LASI_IPR:
117 val = s->ipr;
118 /* Any read to IPR clears the register. */
119 s->ipr = 0;
120 break;
121 case LASI_ICR:
122 val = s->icr & ICR_BUS_ERROR_BIT; /* bus_error */
123 break;
124 case LASI_IAR:
125 val = s->iar;
126 break;
127
128 case (LASI_LAN_HPA - LASI_HPA):
129 case (LASI_LPT_HPA - LASI_HPA):
130 case (LASI_UART_HPA - LASI_HPA):
131 val = 0;
132 break;
133 case (LASI_RTC_HPA - LASI_HPA):
134 val = time(NULL);
135 val += s->rtc_ref;
136 break;
137
138 case LASI_PCR:
139 case LASI_VER: /* only version 0 existed. */
140 case LASI_IORESET:
141 val = 0;
142 break;
143 case LASI_ERRLOG:
144 val = s->errlog;
145 break;
146 case LASI_AMR:
147 val = s->amr;
148 break;
149
150 default:
151 /* Controlled by lasi_chip_mem_valid above. */
152 g_assert_not_reached();
153 }
154
155 trace_lasi_chip_read(addr, val);
156
157 *data = val;
158 return ret;
159 }
160
161 static MemTxResult lasi_chip_write_with_attrs(void *opaque, hwaddr addr,
162 uint64_t val, unsigned size,
163 MemTxAttrs attrs)
164 {
165 LasiState *s = opaque;
166
167 trace_lasi_chip_write(addr, val);
168
169 switch (addr) {
170 case LASI_IRR:
171 /* read-only. */
172 break;
173 case LASI_IMR:
174 s->imr = val;
175 if (((val & LASI_IRQ_BITS) != val) && (val != 0xffffffff))
176 qemu_log_mask(LOG_GUEST_ERROR,
177 "LASI: tried to set invalid %lx IMR value.\n",
178 (unsigned long) val);
179 break;
180 case LASI_IPR:
181 /* Any write to IPR clears the register. */
182 s->ipr = 0;
183 break;
184 case LASI_ICR:
185 s->icr = val;
186 /* if (val & ICR_TOC_BIT) issue_toc(); */
187 break;
188 case LASI_IAR:
189 s->iar = val;
190 break;
191
192 case (LASI_LAN_HPA - LASI_HPA):
193 /* XXX: reset LAN card */
194 break;
195 case (LASI_LPT_HPA - LASI_HPA):
196 /* XXX: reset parallel port */
197 break;
198 case (LASI_UART_HPA - LASI_HPA):
199 /* XXX: reset serial port */
200 break;
201 case (LASI_RTC_HPA - LASI_HPA):
202 s->rtc_ref = val - time(NULL);
203 break;
204
205 case LASI_PCR:
206 if (val == 0x02) /* immediately power off */
207 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
208 break;
209 case LASI_ERRLOG:
210 s->errlog = val;
211 break;
212 case LASI_VER:
213 /* read-only. */
214 break;
215 case LASI_IORESET:
216 break; /* XXX: TODO: Reset various devices. */
217 case LASI_AMR:
218 s->amr = val;
219 break;
220
221 default:
222 /* Controlled by lasi_chip_mem_valid above. */
223 g_assert_not_reached();
224 }
225 return MEMTX_OK;
226 }
227
228 static const MemoryRegionOps lasi_chip_ops = {
229 .read_with_attrs = lasi_chip_read_with_attrs,
230 .write_with_attrs = lasi_chip_write_with_attrs,
231 .endianness = DEVICE_BIG_ENDIAN,
232 .valid = {
233 .min_access_size = 1,
234 .max_access_size = 4,
235 .accepts = lasi_chip_mem_valid,
236 },
237 .impl = {
238 .min_access_size = 1,
239 .max_access_size = 4,
240 },
241 };
242
243 static const VMStateDescription vmstate_lasi = {
244 .name = "Lasi",
245 .version_id = 1,
246 .minimum_version_id = 1,
247 .fields = (VMStateField[]) {
248 VMSTATE_UINT32(irr, LasiState),
249 VMSTATE_UINT32(imr, LasiState),
250 VMSTATE_UINT32(ipr, LasiState),
251 VMSTATE_UINT32(icr, LasiState),
252 VMSTATE_UINT32(iar, LasiState),
253 VMSTATE_UINT32(errlog, LasiState),
254 VMSTATE_UINT32(amr, LasiState),
255 VMSTATE_END_OF_LIST()
256 }
257 };
258
259
260 static void lasi_set_irq(void *opaque, int irq, int level)
261 {
262 LasiState *s = opaque;
263 uint32_t bit = 1u << irq;
264
265 if (level) {
266 s->ipr |= bit;
267 if (bit & s->imr) {
268 uint32_t iar = s->iar;
269 s->irr |= bit;
270 if ((s->icr & ICR_BUS_ERROR_BIT) == 0) {
271 stl_be_phys(&address_space_memory, iar & -32, iar & 31);
272 }
273 }
274 }
275 }
276
277 static int lasi_get_irq(unsigned long hpa)
278 {
279 switch (hpa) {
280 case LASI_HPA:
281 return 14;
282 case LASI_UART_HPA:
283 return 5;
284 case LASI_LPT_HPA:
285 return 7;
286 case LASI_LAN_HPA:
287 return 8;
288 case LASI_SCSI_HPA:
289 return 9;
290 case LASI_AUDIO_HPA:
291 return 13;
292 case LASI_PS2KBD_HPA:
293 case LASI_PS2MOU_HPA:
294 return 26;
295 default:
296 g_assert_not_reached();
297 }
298 }
299
300 DeviceState *lasi_init(MemoryRegion *address_space)
301 {
302 DeviceState *dev;
303 LasiState *s;
304
305 dev = qdev_new(TYPE_LASI_CHIP);
306 s = LASI_CHIP(dev);
307 s->iar = CPU_HPA + 3;
308
309 /* Lasi access from main memory. */
310 memory_region_init_io(&s->this_mem, OBJECT(s), &lasi_chip_ops,
311 s, "lasi", 0x100000);
312 memory_region_add_subregion(address_space, LASI_HPA, &s->this_mem);
313
314 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
315
316 /* LAN */
317 if (enable_lasi_lan()) {
318 qemu_irq lan_irq = qemu_allocate_irq(lasi_set_irq, s,
319 lasi_get_irq(LASI_LAN_HPA));
320 lasi_82596_init(address_space, LASI_LAN_HPA, lan_irq);
321 }
322
323 /* Parallel port */
324 qemu_irq lpt_irq = qemu_allocate_irq(lasi_set_irq, s,
325 lasi_get_irq(LASI_LPT_HPA));
326 parallel_mm_init(address_space, LASI_LPT_HPA + 0x800, 0,
327 lpt_irq, parallel_hds[0]);
328
329 /* Real time clock (RTC), it's only one 32-bit counter @9000 */
330
331 s->rtc = time(NULL);
332 s->rtc_ref = 0;
333
334 if (serial_hd(1)) {
335 /* Serial port */
336 qemu_irq serial_irq = qemu_allocate_irq(lasi_set_irq, s,
337 lasi_get_irq(LASI_UART_HPA));
338 serial_mm_init(address_space, LASI_UART_HPA + 0x800, 0,
339 serial_irq, 8000000 / 16,
340 serial_hd(0), DEVICE_NATIVE_ENDIAN);
341 }
342
343 /* PS/2 Keyboard/Mouse */
344 qemu_irq ps2kbd_irq = qemu_allocate_irq(lasi_set_irq, s,
345 lasi_get_irq(LASI_PS2KBD_HPA));
346 lasips2_init(address_space, LASI_PS2KBD_HPA, ps2kbd_irq);
347
348 return dev;
349 }
350
351 static void lasi_class_init(ObjectClass *klass, void *data)
352 {
353 DeviceClass *dc = DEVICE_CLASS(klass);
354
355 dc->vmsd = &vmstate_lasi;
356 }
357
358 static const TypeInfo lasi_pcihost_info = {
359 .name = TYPE_LASI_CHIP,
360 .parent = TYPE_SYS_BUS_DEVICE,
361 .instance_size = sizeof(LasiState),
362 .class_init = lasi_class_init,
363 };
364
365 static void lasi_register_types(void)
366 {
367 type_register_static(&lasi_pcihost_info);
368 }
369
370 type_init(lasi_register_types)