sm501: Add missing arbitration control register
[qemu.git] / hw / i2c / imx_i2c.c
1 /*
2 * i.MX I2C Bus Serial Interface Emulation
3 *
4 * Copyright (C) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
18 *
19 */
20
21 #include "qemu/osdep.h"
22 #include "hw/i2c/imx_i2c.h"
23 #include "hw/i2c/i2c.h"
24 #include "qemu/log.h"
25
26 #ifndef DEBUG_IMX_I2C
27 #define DEBUG_IMX_I2C 0
28 #endif
29
30 #define DPRINTF(fmt, args...) \
31 do { \
32 if (DEBUG_IMX_I2C) { \
33 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_I2C, \
34 __func__, ##args); \
35 } \
36 } while (0)
37
38 static const char *imx_i2c_get_regname(unsigned offset)
39 {
40 switch (offset) {
41 case IADR_ADDR:
42 return "IADR";
43 case IFDR_ADDR:
44 return "IFDR";
45 case I2CR_ADDR:
46 return "I2CR";
47 case I2SR_ADDR:
48 return "I2SR";
49 case I2DR_ADDR:
50 return "I2DR";
51 default:
52 return "[?]";
53 }
54 }
55
56 static inline bool imx_i2c_is_enabled(IMXI2CState *s)
57 {
58 return s->i2cr & I2CR_IEN;
59 }
60
61 static inline bool imx_i2c_interrupt_is_enabled(IMXI2CState *s)
62 {
63 return s->i2cr & I2CR_IIEN;
64 }
65
66 static inline bool imx_i2c_is_master(IMXI2CState *s)
67 {
68 return s->i2cr & I2CR_MSTA;
69 }
70
71 static void imx_i2c_reset(DeviceState *dev)
72 {
73 IMXI2CState *s = IMX_I2C(dev);
74
75 if (s->address != ADDR_RESET) {
76 i2c_end_transfer(s->bus);
77 }
78
79 s->address = ADDR_RESET;
80 s->iadr = IADR_RESET;
81 s->ifdr = IFDR_RESET;
82 s->i2cr = I2CR_RESET;
83 s->i2sr = I2SR_RESET;
84 s->i2dr_read = I2DR_RESET;
85 s->i2dr_write = I2DR_RESET;
86 }
87
88 static inline void imx_i2c_raise_interrupt(IMXI2CState *s)
89 {
90 /*
91 * raise an interrupt if the device is enabled and it is configured
92 * to generate some interrupts.
93 */
94 if (imx_i2c_is_enabled(s) && imx_i2c_interrupt_is_enabled(s)) {
95 s->i2sr |= I2SR_IIF;
96 qemu_irq_raise(s->irq);
97 }
98 }
99
100 static uint64_t imx_i2c_read(void *opaque, hwaddr offset,
101 unsigned size)
102 {
103 uint16_t value;
104 IMXI2CState *s = IMX_I2C(opaque);
105
106 switch (offset) {
107 case IADR_ADDR:
108 value = s->iadr;
109 break;
110 case IFDR_ADDR:
111 value = s->ifdr;
112 break;
113 case I2CR_ADDR:
114 value = s->i2cr;
115 break;
116 case I2SR_ADDR:
117 value = s->i2sr;
118 break;
119 case I2DR_ADDR:
120 value = s->i2dr_read;
121
122 if (imx_i2c_is_master(s)) {
123 int ret = 0xff;
124
125 if (s->address == ADDR_RESET) {
126 /* something is wrong as the address is not set */
127 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read "
128 "without specifying the slave address\n",
129 TYPE_IMX_I2C, __func__);
130 } else if (s->i2cr & I2CR_MTX) {
131 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read "
132 "but MTX is set\n", TYPE_IMX_I2C, __func__);
133 } else {
134 /* get the next byte */
135 ret = i2c_recv(s->bus);
136
137 if (ret >= 0) {
138 imx_i2c_raise_interrupt(s);
139 } else {
140 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: read failed "
141 "for device 0x%02x\n", TYPE_IMX_I2C,
142 __func__, s->address);
143 ret = 0xff;
144 }
145 }
146
147 s->i2dr_read = ret;
148 } else {
149 qemu_log_mask(LOG_UNIMP, "[%s]%s: slave mode not implemented\n",
150 TYPE_IMX_I2C, __func__);
151 }
152 break;
153 default:
154 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%"
155 HWADDR_PRIx "\n", TYPE_IMX_I2C, __func__, offset);
156 value = 0;
157 break;
158 }
159
160 DPRINTF("read %s [0x%" HWADDR_PRIx "] -> 0x%02x\n",
161 imx_i2c_get_regname(offset), offset, value);
162
163 return (uint64_t)value;
164 }
165
166 static void imx_i2c_write(void *opaque, hwaddr offset,
167 uint64_t value, unsigned size)
168 {
169 IMXI2CState *s = IMX_I2C(opaque);
170
171 DPRINTF("write %s [0x%" HWADDR_PRIx "] <- 0x%02x\n",
172 imx_i2c_get_regname(offset), offset, (int)value);
173
174 value &= 0xff;
175
176 switch (offset) {
177 case IADR_ADDR:
178 s->iadr = value & IADR_MASK;
179 /* i2c_set_slave_address(s->bus, (uint8_t)s->iadr); */
180 break;
181 case IFDR_ADDR:
182 s->ifdr = value & IFDR_MASK;
183 break;
184 case I2CR_ADDR:
185 if (imx_i2c_is_enabled(s) && ((value & I2CR_IEN) == 0)) {
186 /* This is a soft reset. IADR is preserved during soft resets */
187 uint16_t iadr = s->iadr;
188 imx_i2c_reset(DEVICE(s));
189 s->iadr = iadr;
190 } else { /* normal write */
191 s->i2cr = value & I2CR_MASK;
192
193 if (imx_i2c_is_master(s)) {
194 /* set the bus to busy */
195 s->i2sr |= I2SR_IBB;
196 } else { /* slave mode */
197 /* bus is not busy anymore */
198 s->i2sr &= ~I2SR_IBB;
199
200 /*
201 * if we unset the master mode then it ends the ongoing
202 * transfer if any
203 */
204 if (s->address != ADDR_RESET) {
205 i2c_end_transfer(s->bus);
206 s->address = ADDR_RESET;
207 }
208 }
209
210 if (s->i2cr & I2CR_RSTA) { /* Restart */
211 /* if this is a restart then it ends the ongoing transfer */
212 if (s->address != ADDR_RESET) {
213 i2c_end_transfer(s->bus);
214 s->address = ADDR_RESET;
215 s->i2cr &= ~I2CR_RSTA;
216 }
217 }
218 }
219 break;
220 case I2SR_ADDR:
221 /*
222 * if the user writes 0 to IIF then lower the interrupt and
223 * reset the bit
224 */
225 if ((s->i2sr & I2SR_IIF) && !(value & I2SR_IIF)) {
226 s->i2sr &= ~I2SR_IIF;
227 qemu_irq_lower(s->irq);
228 }
229
230 /*
231 * if the user writes 0 to IAL, reset the bit
232 */
233 if ((s->i2sr & I2SR_IAL) && !(value & I2SR_IAL)) {
234 s->i2sr &= ~I2SR_IAL;
235 }
236
237 break;
238 case I2DR_ADDR:
239 /* if the device is not enabled, nothing to do */
240 if (!imx_i2c_is_enabled(s)) {
241 break;
242 }
243
244 s->i2dr_write = value & I2DR_MASK;
245
246 if (imx_i2c_is_master(s)) {
247 /* If this is the first write cycle then it is the slave addr */
248 if (s->address == ADDR_RESET) {
249 if (i2c_start_transfer(s->bus, extract32(s->i2dr_write, 1, 7),
250 extract32(s->i2dr_write, 0, 1))) {
251 /* if non zero is returned, the address is not valid */
252 s->i2sr |= I2SR_RXAK;
253 } else {
254 s->address = s->i2dr_write;
255 s->i2sr &= ~I2SR_RXAK;
256 imx_i2c_raise_interrupt(s);
257 }
258 } else { /* This is a normal data write */
259 if (i2c_send(s->bus, s->i2dr_write)) {
260 /* if the target return non zero then end the transfer */
261 s->i2sr |= I2SR_RXAK;
262 s->address = ADDR_RESET;
263 i2c_end_transfer(s->bus);
264 } else {
265 s->i2sr &= ~I2SR_RXAK;
266 imx_i2c_raise_interrupt(s);
267 }
268 }
269 } else {
270 qemu_log_mask(LOG_UNIMP, "[%s]%s: slave mode not implemented\n",
271 TYPE_IMX_I2C, __func__);
272 }
273 break;
274 default:
275 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%"
276 HWADDR_PRIx "\n", TYPE_IMX_I2C, __func__, offset);
277 break;
278 }
279 }
280
281 static const MemoryRegionOps imx_i2c_ops = {
282 .read = imx_i2c_read,
283 .write = imx_i2c_write,
284 .valid.min_access_size = 1,
285 .valid.max_access_size = 2,
286 .endianness = DEVICE_NATIVE_ENDIAN,
287 };
288
289 static const VMStateDescription imx_i2c_vmstate = {
290 .name = TYPE_IMX_I2C,
291 .version_id = 1,
292 .minimum_version_id = 1,
293 .fields = (VMStateField[]) {
294 VMSTATE_UINT16(address, IMXI2CState),
295 VMSTATE_UINT16(iadr, IMXI2CState),
296 VMSTATE_UINT16(ifdr, IMXI2CState),
297 VMSTATE_UINT16(i2cr, IMXI2CState),
298 VMSTATE_UINT16(i2sr, IMXI2CState),
299 VMSTATE_UINT16(i2dr_read, IMXI2CState),
300 VMSTATE_UINT16(i2dr_write, IMXI2CState),
301 VMSTATE_END_OF_LIST()
302 }
303 };
304
305 static void imx_i2c_realize(DeviceState *dev, Error **errp)
306 {
307 IMXI2CState *s = IMX_I2C(dev);
308
309 memory_region_init_io(&s->iomem, OBJECT(s), &imx_i2c_ops, s, TYPE_IMX_I2C,
310 IMX_I2C_MEM_SIZE);
311 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
312 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
313 s->bus = i2c_init_bus(DEVICE(dev), NULL);
314 }
315
316 static void imx_i2c_class_init(ObjectClass *klass, void *data)
317 {
318 DeviceClass *dc = DEVICE_CLASS(klass);
319
320 dc->vmsd = &imx_i2c_vmstate;
321 dc->reset = imx_i2c_reset;
322 dc->realize = imx_i2c_realize;
323 dc->desc = "i.MX I2C Controller";
324 }
325
326 static const TypeInfo imx_i2c_type_info = {
327 .name = TYPE_IMX_I2C,
328 .parent = TYPE_SYS_BUS_DEVICE,
329 .instance_size = sizeof(IMXI2CState),
330 .class_init = imx_i2c_class_init,
331 };
332
333 static void imx_i2c_register_types(void)
334 {
335 type_register_static(&imx_i2c_type_info);
336 }
337
338 type_init(imx_i2c_register_types)